MPU9250 - MPU9250

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MPU9250

MPU6050.h@15:09f072efa71e, 2018-03-28 (annotated)

Committer:: tyftyftyf
Date:: Wed Mar 28 21:23:40 2018 +0000
Revision:: 15:09f072efa71e
Parent:: 14:057ce8fa00ab

fix build error

Who changed what in which revision?

User	Revision	Line number	New contents of line
garfieldsg	0:662207e34fba	1	//ported from arduino library: https://github.com/jrowberg/i2cdevlib/tree/master/Arduino/MPU6050
garfieldsg	0:662207e34fba	2	//written by szymon gaertig (email: szymon@gaertig.com.pl)
garfieldsg	0:662207e34fba	3	//
garfieldsg	0:662207e34fba	4	//Changelog:
garfieldsg	0:662207e34fba	5	//2013-01-08 - first beta release
garfieldsg	0:662207e34fba	6
garfieldsg	0:662207e34fba	7	// I2Cdev library collection - MPU6050 I2C device class
garfieldsg	0:662207e34fba	8	// Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00)
garfieldsg	0:662207e34fba	9	// 10/3/2011 by Jeff Rowberg <jeff@rowberg.net>
garfieldsg	0:662207e34fba	10	// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib
garfieldsg	0:662207e34fba	11	//
garfieldsg	0:662207e34fba	12	// Changelog:
garfieldsg	0:662207e34fba	13	// ... - ongoing debug release
garfieldsg	0:662207e34fba	14
garfieldsg	0:662207e34fba	15	// NOTE: THIS IS ONLY A PARIAL RELEASE. THIS DEVICE CLASS IS CURRENTLY UNDERGOING ACTIVE
garfieldsg	0:662207e34fba	16	// DEVELOPMENT AND IS STILL MISSING SOME IMPORTANT FEATURES. PLEASE KEEP THIS IN MIND IF
garfieldsg	0:662207e34fba	17	// YOU DECIDE TO USE THIS PARTICULAR CODE FOR ANYTHING.
garfieldsg	0:662207e34fba	18
garfieldsg	0:662207e34fba	19	/* ============================================
garfieldsg	0:662207e34fba	20	I2Cdev device library code is placed under the MIT license
garfieldsg	0:662207e34fba	21	Copyright (c) 2012 Jeff Rowberg
garfieldsg	0:662207e34fba	22
garfieldsg	0:662207e34fba	23	Permission is hereby granted, free of charge, to any person obtaining a copy
garfieldsg	0:662207e34fba	24	of this software and associated documentation files (the "Software"), to deal
garfieldsg	0:662207e34fba	25	in the Software without restriction, including without limitation the rights
garfieldsg	0:662207e34fba	26	to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
garfieldsg	0:662207e34fba	27	copies of the Software, and to permit persons to whom the Software is
garfieldsg	0:662207e34fba	28	furnished to do so, subject to the following conditions:
garfieldsg	0:662207e34fba	29
garfieldsg	0:662207e34fba	30	The above copyright notice and this permission notice shall be included in
garfieldsg	0:662207e34fba	31	all copies or substantial portions of the Software.
garfieldsg	0:662207e34fba	32
garfieldsg	0:662207e34fba	33	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
garfieldsg	0:662207e34fba	34	IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
garfieldsg	0:662207e34fba	35	FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
garfieldsg	0:662207e34fba	36	AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
garfieldsg	0:662207e34fba	37	LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
garfieldsg	0:662207e34fba	38	OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
garfieldsg	0:662207e34fba	39	THE SOFTWARE.
garfieldsg	0:662207e34fba	40	===============================================
garfieldsg	0:662207e34fba	41	*/
garfieldsg	0:662207e34fba	42
garfieldsg	0:662207e34fba	43	#ifndef _MPU6050_H_
garfieldsg	0:662207e34fba	44	#define _MPU6050_H_
garfieldsg	0:662207e34fba	45
tyftyftyf	13:a74f2d622b54	46	#include "mbed.h"
garfieldsg	0:662207e34fba	47	#include "I2Cdev.h"
garfieldsg	0:662207e34fba	48	#include "helper_3dmath.h"
garfieldsg	0:662207e34fba	49
tyftyftyf	13:a74f2d622b54	50
tyftyftyf	13:a74f2d622b54	51	// select MPU9250 or MPU6050
tyftyftyf	13:a74f2d622b54	52	#define MPU9250
tyftyftyf	13:a74f2d622b54	53	//#define MPU6050
tyftyftyf	13:a74f2d622b54	54
tyftyftyf	13:a74f2d622b54	55
tyftyftyf	13:a74f2d622b54	56	#ifdef MPU9250
tyftyftyf	13:a74f2d622b54	57	#include "AK8963.h"
tyftyftyf	13:a74f2d622b54	58	#endif
tyftyftyf	13:a74f2d622b54	59
garfieldsg	0:662207e34fba	60	#define MPU6050_ADDRESS_AD0_LOW 0x68 // address pin low (GND), default for InvenSense evaluation board
garfieldsg	0:662207e34fba	61	#define MPU6050_ADDRESS_AD0_HIGH 0x69 // address pin high (VCC)
garfieldsg	0:662207e34fba	62	#define MPU6050_DEFAULT_ADDRESS MPU6050_ADDRESS_AD0_LOW
garfieldsg	0:662207e34fba	63
garfieldsg	0:662207e34fba	64	#define MPU6050_RA_XG_OFFS_TC 0x00 //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD
garfieldsg	0:662207e34fba	65	#define MPU6050_RA_YG_OFFS_TC 0x01 //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD
garfieldsg	0:662207e34fba	66	#define MPU6050_RA_ZG_OFFS_TC 0x02 //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD
garfieldsg	0:662207e34fba	67	#define MPU6050_RA_X_FINE_GAIN 0x03 //[7:0] X_FINE_GAIN
garfieldsg	0:662207e34fba	68	#define MPU6050_RA_Y_FINE_GAIN 0x04 //[7:0] Y_FINE_GAIN
garfieldsg	0:662207e34fba	69	#define MPU6050_RA_Z_FINE_GAIN 0x05 //[7:0] Z_FINE_GAIN
garfieldsg	0:662207e34fba	70	#define MPU6050_RA_XA_OFFS_H 0x06 //[15:0] XA_OFFS
garfieldsg	0:662207e34fba	71	#define MPU6050_RA_XA_OFFS_L_TC 0x07
garfieldsg	0:662207e34fba	72	#define MPU6050_RA_YA_OFFS_H 0x08 //[15:0] YA_OFFS
garfieldsg	0:662207e34fba	73	#define MPU6050_RA_YA_OFFS_L_TC 0x09
garfieldsg	0:662207e34fba	74	#define MPU6050_RA_ZA_OFFS_H 0x0A //[15:0] ZA_OFFS
garfieldsg	0:662207e34fba	75	#define MPU6050_RA_ZA_OFFS_L_TC 0x0B
garfieldsg	0:662207e34fba	76	#define MPU6050_RA_XG_OFFS_USRH 0x13 //[15:0] XG_OFFS_USR
garfieldsg	0:662207e34fba	77	#define MPU6050_RA_XG_OFFS_USRL 0x14
garfieldsg	0:662207e34fba	78	#define MPU6050_RA_YG_OFFS_USRH 0x15 //[15:0] YG_OFFS_USR
garfieldsg	0:662207e34fba	79	#define MPU6050_RA_YG_OFFS_USRL 0x16
garfieldsg	0:662207e34fba	80	#define MPU6050_RA_ZG_OFFS_USRH 0x17 //[15:0] ZG_OFFS_USR
garfieldsg	0:662207e34fba	81	#define MPU6050_RA_ZG_OFFS_USRL 0x18
garfieldsg	0:662207e34fba	82	#define MPU6050_RA_SMPLRT_DIV 0x19
garfieldsg	0:662207e34fba	83	#define MPU6050_RA_CONFIG 0x1A
garfieldsg	0:662207e34fba	84	#define MPU6050_RA_GYRO_CONFIG 0x1B
garfieldsg	0:662207e34fba	85	#define MPU6050_RA_ACCEL_CONFIG 0x1C
garfieldsg	0:662207e34fba	86	#define MPU6050_RA_FF_THR 0x1D
garfieldsg	0:662207e34fba	87	#define MPU6050_RA_FF_DUR 0x1E
garfieldsg	0:662207e34fba	88	#define MPU6050_RA_MOT_THR 0x1F
garfieldsg	0:662207e34fba	89	#define MPU6050_RA_MOT_DUR 0x20
garfieldsg	0:662207e34fba	90	#define MPU6050_RA_ZRMOT_THR 0x21
garfieldsg	0:662207e34fba	91	#define MPU6050_RA_ZRMOT_DUR 0x22
garfieldsg	0:662207e34fba	92	#define MPU6050_RA_FIFO_EN 0x23
garfieldsg	0:662207e34fba	93	#define MPU6050_RA_I2C_MST_CTRL 0x24
garfieldsg	0:662207e34fba	94	#define MPU6050_RA_I2C_SLV0_ADDR 0x25
garfieldsg	0:662207e34fba	95	#define MPU6050_RA_I2C_SLV0_REG 0x26
garfieldsg	0:662207e34fba	96	#define MPU6050_RA_I2C_SLV0_CTRL 0x27
garfieldsg	0:662207e34fba	97	#define MPU6050_RA_I2C_SLV1_ADDR 0x28
garfieldsg	0:662207e34fba	98	#define MPU6050_RA_I2C_SLV1_REG 0x29
garfieldsg	0:662207e34fba	99	#define MPU6050_RA_I2C_SLV1_CTRL 0x2A
garfieldsg	0:662207e34fba	100	#define MPU6050_RA_I2C_SLV2_ADDR 0x2B
garfieldsg	0:662207e34fba	101	#define MPU6050_RA_I2C_SLV2_REG 0x2C
garfieldsg	0:662207e34fba	102	#define MPU6050_RA_I2C_SLV2_CTRL 0x2D
garfieldsg	0:662207e34fba	103	#define MPU6050_RA_I2C_SLV3_ADDR 0x2E
garfieldsg	0:662207e34fba	104	#define MPU6050_RA_I2C_SLV3_REG 0x2F
garfieldsg	0:662207e34fba	105	#define MPU6050_RA_I2C_SLV3_CTRL 0x30
garfieldsg	0:662207e34fba	106	#define MPU6050_RA_I2C_SLV4_ADDR 0x31
garfieldsg	0:662207e34fba	107	#define MPU6050_RA_I2C_SLV4_REG 0x32
garfieldsg	0:662207e34fba	108	#define MPU6050_RA_I2C_SLV4_DO 0x33
garfieldsg	0:662207e34fba	109	#define MPU6050_RA_I2C_SLV4_CTRL 0x34
garfieldsg	0:662207e34fba	110	#define MPU6050_RA_I2C_SLV4_DI 0x35
garfieldsg	0:662207e34fba	111	#define MPU6050_RA_I2C_MST_STATUS 0x36
garfieldsg	0:662207e34fba	112	#define MPU6050_RA_INT_PIN_CFG 0x37
garfieldsg	0:662207e34fba	113	#define MPU6050_RA_INT_ENABLE 0x38
garfieldsg	0:662207e34fba	114	#define MPU6050_RA_DMP_INT_STATUS 0x39
garfieldsg	0:662207e34fba	115	#define MPU6050_RA_INT_STATUS 0x3A
garfieldsg	0:662207e34fba	116	#define MPU6050_RA_ACCEL_XOUT_H 0x3B
garfieldsg	0:662207e34fba	117	#define MPU6050_RA_ACCEL_XOUT_L 0x3C
garfieldsg	0:662207e34fba	118	#define MPU6050_RA_ACCEL_YOUT_H 0x3D
garfieldsg	0:662207e34fba	119	#define MPU6050_RA_ACCEL_YOUT_L 0x3E
garfieldsg	0:662207e34fba	120	#define MPU6050_RA_ACCEL_ZOUT_H 0x3F
garfieldsg	0:662207e34fba	121	#define MPU6050_RA_ACCEL_ZOUT_L 0x40
garfieldsg	0:662207e34fba	122	#define MPU6050_RA_TEMP_OUT_H 0x41
garfieldsg	0:662207e34fba	123	#define MPU6050_RA_TEMP_OUT_L 0x42
garfieldsg	0:662207e34fba	124	#define MPU6050_RA_GYRO_XOUT_H 0x43
garfieldsg	0:662207e34fba	125	#define MPU6050_RA_GYRO_XOUT_L 0x44
garfieldsg	0:662207e34fba	126	#define MPU6050_RA_GYRO_YOUT_H 0x45
garfieldsg	0:662207e34fba	127	#define MPU6050_RA_GYRO_YOUT_L 0x46
garfieldsg	0:662207e34fba	128	#define MPU6050_RA_GYRO_ZOUT_H 0x47
garfieldsg	0:662207e34fba	129	#define MPU6050_RA_GYRO_ZOUT_L 0x48
garfieldsg	0:662207e34fba	130	#define MPU6050_RA_EXT_SENS_DATA_00 0x49
garfieldsg	0:662207e34fba	131	#define MPU6050_RA_EXT_SENS_DATA_01 0x4A
garfieldsg	0:662207e34fba	132	#define MPU6050_RA_EXT_SENS_DATA_02 0x4B
garfieldsg	0:662207e34fba	133	#define MPU6050_RA_EXT_SENS_DATA_03 0x4C
garfieldsg	0:662207e34fba	134	#define MPU6050_RA_EXT_SENS_DATA_04 0x4D
garfieldsg	0:662207e34fba	135	#define MPU6050_RA_EXT_SENS_DATA_05 0x4E
garfieldsg	0:662207e34fba	136	#define MPU6050_RA_EXT_SENS_DATA_06 0x4F
garfieldsg	0:662207e34fba	137	#define MPU6050_RA_EXT_SENS_DATA_07 0x50
garfieldsg	0:662207e34fba	138	#define MPU6050_RA_EXT_SENS_DATA_08 0x51
garfieldsg	0:662207e34fba	139	#define MPU6050_RA_EXT_SENS_DATA_09 0x52
garfieldsg	0:662207e34fba	140	#define MPU6050_RA_EXT_SENS_DATA_10 0x53
garfieldsg	0:662207e34fba	141	#define MPU6050_RA_EXT_SENS_DATA_11 0x54
garfieldsg	0:662207e34fba	142	#define MPU6050_RA_EXT_SENS_DATA_12 0x55
garfieldsg	0:662207e34fba	143	#define MPU6050_RA_EXT_SENS_DATA_13 0x56
garfieldsg	0:662207e34fba	144	#define MPU6050_RA_EXT_SENS_DATA_14 0x57
garfieldsg	0:662207e34fba	145	#define MPU6050_RA_EXT_SENS_DATA_15 0x58
garfieldsg	0:662207e34fba	146	#define MPU6050_RA_EXT_SENS_DATA_16 0x59
garfieldsg	0:662207e34fba	147	#define MPU6050_RA_EXT_SENS_DATA_17 0x5A
garfieldsg	0:662207e34fba	148	#define MPU6050_RA_EXT_SENS_DATA_18 0x5B
garfieldsg	0:662207e34fba	149	#define MPU6050_RA_EXT_SENS_DATA_19 0x5C
garfieldsg	0:662207e34fba	150	#define MPU6050_RA_EXT_SENS_DATA_20 0x5D
garfieldsg	0:662207e34fba	151	#define MPU6050_RA_EXT_SENS_DATA_21 0x5E
garfieldsg	0:662207e34fba	152	#define MPU6050_RA_EXT_SENS_DATA_22 0x5F
garfieldsg	0:662207e34fba	153	#define MPU6050_RA_EXT_SENS_DATA_23 0x60
garfieldsg	0:662207e34fba	154	#define MPU6050_RA_MOT_DETECT_STATUS 0x61
garfieldsg	0:662207e34fba	155	#define MPU6050_RA_I2C_SLV0_DO 0x63
garfieldsg	0:662207e34fba	156	#define MPU6050_RA_I2C_SLV1_DO 0x64
garfieldsg	0:662207e34fba	157	#define MPU6050_RA_I2C_SLV2_DO 0x65
garfieldsg	0:662207e34fba	158	#define MPU6050_RA_I2C_SLV3_DO 0x66
garfieldsg	0:662207e34fba	159	#define MPU6050_RA_I2C_MST_DELAY_CTRL 0x67
garfieldsg	0:662207e34fba	160	#define MPU6050_RA_SIGNAL_PATH_RESET 0x68
garfieldsg	0:662207e34fba	161	#define MPU6050_RA_MOT_DETECT_CTRL 0x69
garfieldsg	0:662207e34fba	162	#define MPU6050_RA_USER_CTRL 0x6A
garfieldsg	0:662207e34fba	163	#define MPU6050_RA_PWR_MGMT_1 0x6B
garfieldsg	0:662207e34fba	164	#define MPU6050_RA_PWR_MGMT_2 0x6C
garfieldsg	0:662207e34fba	165	#define MPU6050_RA_BANK_SEL 0x6D
garfieldsg	0:662207e34fba	166	#define MPU6050_RA_MEM_START_ADDR 0x6E
garfieldsg	0:662207e34fba	167	#define MPU6050_RA_MEM_R_W 0x6F
garfieldsg	0:662207e34fba	168	#define MPU6050_RA_DMP_CFG_1 0x70
garfieldsg	0:662207e34fba	169	#define MPU6050_RA_DMP_CFG_2 0x71
garfieldsg	0:662207e34fba	170	#define MPU6050_RA_FIFO_COUNTH 0x72
garfieldsg	0:662207e34fba	171	#define MPU6050_RA_FIFO_COUNTL 0x73
garfieldsg	0:662207e34fba	172	#define MPU6050_RA_FIFO_R_W 0x74
garfieldsg	0:662207e34fba	173	#define MPU6050_RA_WHO_AM_I 0x75
garfieldsg	0:662207e34fba	174
garfieldsg	0:662207e34fba	175	#define MPU6050_TC_PWR_MODE_BIT 7
garfieldsg	0:662207e34fba	176	#define MPU6050_TC_OFFSET_BIT 6
garfieldsg	0:662207e34fba	177	#define MPU6050_TC_OFFSET_LENGTH 6
garfieldsg	0:662207e34fba	178	#define MPU6050_TC_OTP_BNK_VLD_BIT 0
garfieldsg	0:662207e34fba	179
garfieldsg	0:662207e34fba	180	#define MPU6050_VDDIO_LEVEL_VLOGIC 0
garfieldsg	0:662207e34fba	181	#define MPU6050_VDDIO_LEVEL_VDD 1
garfieldsg	0:662207e34fba	182
garfieldsg	0:662207e34fba	183	#define MPU6050_CFG_EXT_SYNC_SET_BIT 5
garfieldsg	0:662207e34fba	184	#define MPU6050_CFG_EXT_SYNC_SET_LENGTH 3
garfieldsg	0:662207e34fba	185	#define MPU6050_CFG_DLPF_CFG_BIT 2
garfieldsg	0:662207e34fba	186	#define MPU6050_CFG_DLPF_CFG_LENGTH 3
garfieldsg	0:662207e34fba	187
garfieldsg	0:662207e34fba	188	#define MPU6050_EXT_SYNC_DISABLED 0x0
garfieldsg	0:662207e34fba	189	#define MPU6050_EXT_SYNC_TEMP_OUT_L 0x1
garfieldsg	0:662207e34fba	190	#define MPU6050_EXT_SYNC_GYRO_XOUT_L 0x2
garfieldsg	0:662207e34fba	191	#define MPU6050_EXT_SYNC_GYRO_YOUT_L 0x3
garfieldsg	0:662207e34fba	192	#define MPU6050_EXT_SYNC_GYRO_ZOUT_L 0x4
garfieldsg	0:662207e34fba	193	#define MPU6050_EXT_SYNC_ACCEL_XOUT_L 0x5
garfieldsg	0:662207e34fba	194	#define MPU6050_EXT_SYNC_ACCEL_YOUT_L 0x6
garfieldsg	0:662207e34fba	195	#define MPU6050_EXT_SYNC_ACCEL_ZOUT_L 0x7
garfieldsg	0:662207e34fba	196
garfieldsg	0:662207e34fba	197	#define MPU6050_DLPF_BW_256 0x00
garfieldsg	0:662207e34fba	198	#define MPU6050_DLPF_BW_188 0x01
garfieldsg	0:662207e34fba	199	#define MPU6050_DLPF_BW_98 0x02
garfieldsg	0:662207e34fba	200	#define MPU6050_DLPF_BW_42 0x03
garfieldsg	0:662207e34fba	201	#define MPU6050_DLPF_BW_20 0x04
garfieldsg	0:662207e34fba	202	#define MPU6050_DLPF_BW_10 0x05
garfieldsg	0:662207e34fba	203	#define MPU6050_DLPF_BW_5 0x06
garfieldsg	0:662207e34fba	204
garfieldsg	0:662207e34fba	205	#define MPU6050_GCONFIG_FS_SEL_BIT 4
garfieldsg	0:662207e34fba	206	#define MPU6050_GCONFIG_FS_SEL_LENGTH 2
garfieldsg	0:662207e34fba	207
garfieldsg	0:662207e34fba	208	#define MPU6050_GYRO_FS_250 0x00
garfieldsg	0:662207e34fba	209	#define MPU6050_GYRO_FS_500 0x01
garfieldsg	0:662207e34fba	210	#define MPU6050_GYRO_FS_1000 0x02
garfieldsg	0:662207e34fba	211	#define MPU6050_GYRO_FS_2000 0x03
garfieldsg	0:662207e34fba	212
garfieldsg	0:662207e34fba	213	#define MPU6050_ACONFIG_XA_ST_BIT 7
garfieldsg	0:662207e34fba	214	#define MPU6050_ACONFIG_YA_ST_BIT 6
garfieldsg	0:662207e34fba	215	#define MPU6050_ACONFIG_ZA_ST_BIT 5
garfieldsg	0:662207e34fba	216	#define MPU6050_ACONFIG_AFS_SEL_BIT 4
garfieldsg	0:662207e34fba	217	#define MPU6050_ACONFIG_AFS_SEL_LENGTH 2
garfieldsg	0:662207e34fba	218	#define MPU6050_ACONFIG_ACCEL_HPF_BIT 2
garfieldsg	0:662207e34fba	219	#define MPU6050_ACONFIG_ACCEL_HPF_LENGTH 3
garfieldsg	0:662207e34fba	220
garfieldsg	0:662207e34fba	221	#define MPU6050_ACCEL_FS_2 0x00
garfieldsg	0:662207e34fba	222	#define MPU6050_ACCEL_FS_4 0x01
garfieldsg	0:662207e34fba	223	#define MPU6050_ACCEL_FS_8 0x02
garfieldsg	0:662207e34fba	224	#define MPU6050_ACCEL_FS_16 0x03
garfieldsg	0:662207e34fba	225
garfieldsg	0:662207e34fba	226	#define MPU6050_DHPF_RESET 0x00
garfieldsg	0:662207e34fba	227	#define MPU6050_DHPF_5 0x01
garfieldsg	0:662207e34fba	228	#define MPU6050_DHPF_2P5 0x02
garfieldsg	0:662207e34fba	229	#define MPU6050_DHPF_1P25 0x03
garfieldsg	0:662207e34fba	230	#define MPU6050_DHPF_0P63 0x04
garfieldsg	0:662207e34fba	231	#define MPU6050_DHPF_HOLD 0x07
garfieldsg	0:662207e34fba	232
garfieldsg	0:662207e34fba	233	#define MPU6050_TEMP_FIFO_EN_BIT 7
garfieldsg	0:662207e34fba	234	#define MPU6050_XG_FIFO_EN_BIT 6
garfieldsg	0:662207e34fba	235	#define MPU6050_YG_FIFO_EN_BIT 5
garfieldsg	0:662207e34fba	236	#define MPU6050_ZG_FIFO_EN_BIT 4
garfieldsg	0:662207e34fba	237	#define MPU6050_ACCEL_FIFO_EN_BIT 3
garfieldsg	0:662207e34fba	238	#define MPU6050_SLV2_FIFO_EN_BIT 2
garfieldsg	0:662207e34fba	239	#define MPU6050_SLV1_FIFO_EN_BIT 1
garfieldsg	0:662207e34fba	240	#define MPU6050_SLV0_FIFO_EN_BIT 0
garfieldsg	0:662207e34fba	241
garfieldsg	0:662207e34fba	242	#define MPU6050_MULT_MST_EN_BIT 7
garfieldsg	0:662207e34fba	243	#define MPU6050_WAIT_FOR_ES_BIT 6
garfieldsg	0:662207e34fba	244	#define MPU6050_SLV_3_FIFO_EN_BIT 5
garfieldsg	0:662207e34fba	245	#define MPU6050_I2C_MST_P_NSR_BIT 4
garfieldsg	0:662207e34fba	246	#define MPU6050_I2C_MST_CLK_BIT 3
garfieldsg	0:662207e34fba	247	#define MPU6050_I2C_MST_CLK_LENGTH 4
garfieldsg	0:662207e34fba	248
garfieldsg	0:662207e34fba	249	#define MPU6050_CLOCK_DIV_348 0x0
garfieldsg	0:662207e34fba	250	#define MPU6050_CLOCK_DIV_333 0x1
garfieldsg	0:662207e34fba	251	#define MPU6050_CLOCK_DIV_320 0x2
garfieldsg	0:662207e34fba	252	#define MPU6050_CLOCK_DIV_308 0x3
garfieldsg	0:662207e34fba	253	#define MPU6050_CLOCK_DIV_296 0x4
garfieldsg	0:662207e34fba	254	#define MPU6050_CLOCK_DIV_286 0x5
garfieldsg	0:662207e34fba	255	#define MPU6050_CLOCK_DIV_276 0x6
garfieldsg	0:662207e34fba	256	#define MPU6050_CLOCK_DIV_267 0x7
garfieldsg	0:662207e34fba	257	#define MPU6050_CLOCK_DIV_258 0x8
garfieldsg	0:662207e34fba	258	#define MPU6050_CLOCK_DIV_500 0x9
garfieldsg	0:662207e34fba	259	#define MPU6050_CLOCK_DIV_471 0xA
garfieldsg	0:662207e34fba	260	#define MPU6050_CLOCK_DIV_444 0xB
garfieldsg	0:662207e34fba	261	#define MPU6050_CLOCK_DIV_421 0xC
garfieldsg	0:662207e34fba	262	#define MPU6050_CLOCK_DIV_400 0xD
garfieldsg	0:662207e34fba	263	#define MPU6050_CLOCK_DIV_381 0xE
garfieldsg	0:662207e34fba	264	#define MPU6050_CLOCK_DIV_364 0xF
garfieldsg	0:662207e34fba	265
garfieldsg	0:662207e34fba	266	#define MPU6050_I2C_SLV_RW_BIT 7
garfieldsg	0:662207e34fba	267	#define MPU6050_I2C_SLV_ADDR_BIT 6
garfieldsg	0:662207e34fba	268	#define MPU6050_I2C_SLV_ADDR_LENGTH 7
garfieldsg	0:662207e34fba	269	#define MPU6050_I2C_SLV_EN_BIT 7
garfieldsg	0:662207e34fba	270	#define MPU6050_I2C_SLV_BYTE_SW_BIT 6
garfieldsg	0:662207e34fba	271	#define MPU6050_I2C_SLV_REG_DIS_BIT 5
garfieldsg	0:662207e34fba	272	#define MPU6050_I2C_SLV_GRP_BIT 4
garfieldsg	0:662207e34fba	273	#define MPU6050_I2C_SLV_LEN_BIT 3
garfieldsg	0:662207e34fba	274	#define MPU6050_I2C_SLV_LEN_LENGTH 4
garfieldsg	0:662207e34fba	275
garfieldsg	0:662207e34fba	276	#define MPU6050_I2C_SLV4_RW_BIT 7
garfieldsg	0:662207e34fba	277	#define MPU6050_I2C_SLV4_ADDR_BIT 6
garfieldsg	0:662207e34fba	278	#define MPU6050_I2C_SLV4_ADDR_LENGTH 7
garfieldsg	0:662207e34fba	279	#define MPU6050_I2C_SLV4_EN_BIT 7
garfieldsg	0:662207e34fba	280	#define MPU6050_I2C_SLV4_INT_EN_BIT 6
garfieldsg	0:662207e34fba	281	#define MPU6050_I2C_SLV4_REG_DIS_BIT 5
garfieldsg	0:662207e34fba	282	#define MPU6050_I2C_SLV4_MST_DLY_BIT 4
garfieldsg	0:662207e34fba	283	#define MPU6050_I2C_SLV4_MST_DLY_LENGTH 5
garfieldsg	0:662207e34fba	284
garfieldsg	0:662207e34fba	285	#define MPU6050_MST_PASS_THROUGH_BIT 7
garfieldsg	0:662207e34fba	286	#define MPU6050_MST_I2C_SLV4_DONE_BIT 6
garfieldsg	0:662207e34fba	287	#define MPU6050_MST_I2C_LOST_ARB_BIT 5
garfieldsg	0:662207e34fba	288	#define MPU6050_MST_I2C_SLV4_NACK_BIT 4
garfieldsg	0:662207e34fba	289	#define MPU6050_MST_I2C_SLV3_NACK_BIT 3
garfieldsg	0:662207e34fba	290	#define MPU6050_MST_I2C_SLV2_NACK_BIT 2
garfieldsg	0:662207e34fba	291	#define MPU6050_MST_I2C_SLV1_NACK_BIT 1
garfieldsg	0:662207e34fba	292	#define MPU6050_MST_I2C_SLV0_NACK_BIT 0
garfieldsg	0:662207e34fba	293
garfieldsg	0:662207e34fba	294	#define MPU6050_INTCFG_INT_LEVEL_BIT 7
garfieldsg	0:662207e34fba	295	#define MPU6050_INTCFG_INT_OPEN_BIT 6
garfieldsg	0:662207e34fba	296	#define MPU6050_INTCFG_LATCH_INT_EN_BIT 5
garfieldsg	0:662207e34fba	297	#define MPU6050_INTCFG_INT_RD_CLEAR_BIT 4
garfieldsg	0:662207e34fba	298	#define MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT 3
garfieldsg	0:662207e34fba	299	#define MPU6050_INTCFG_FSYNC_INT_EN_BIT 2
garfieldsg	0:662207e34fba	300	#define MPU6050_INTCFG_I2C_BYPASS_EN_BIT 1
garfieldsg	0:662207e34fba	301	#define MPU6050_INTCFG_CLKOUT_EN_BIT 0
garfieldsg	0:662207e34fba	302
garfieldsg	0:662207e34fba	303	#define MPU6050_INTMODE_ACTIVEHIGH 0x00
garfieldsg	0:662207e34fba	304	#define MPU6050_INTMODE_ACTIVELOW 0x01
garfieldsg	0:662207e34fba	305
garfieldsg	0:662207e34fba	306	#define MPU6050_INTDRV_PUSHPULL 0x00
garfieldsg	0:662207e34fba	307	#define MPU6050_INTDRV_OPENDRAIN 0x01
garfieldsg	0:662207e34fba	308
garfieldsg	0:662207e34fba	309	#define MPU6050_INTLATCH_50USPULSE 0x00
garfieldsg	0:662207e34fba	310	#define MPU6050_INTLATCH_WAITCLEAR 0x01
garfieldsg	0:662207e34fba	311
garfieldsg	0:662207e34fba	312	#define MPU6050_INTCLEAR_STATUSREAD 0x00
garfieldsg	0:662207e34fba	313	#define MPU6050_INTCLEAR_ANYREAD 0x01
garfieldsg	0:662207e34fba	314
garfieldsg	0:662207e34fba	315	#define MPU6050_INTERRUPT_FF_BIT 7
garfieldsg	0:662207e34fba	316	#define MPU6050_INTERRUPT_MOT_BIT 6
garfieldsg	0:662207e34fba	317	#define MPU6050_INTERRUPT_ZMOT_BIT 5
garfieldsg	0:662207e34fba	318	#define MPU6050_INTERRUPT_FIFO_OFLOW_BIT 4
garfieldsg	0:662207e34fba	319	#define MPU6050_INTERRUPT_I2C_MST_INT_BIT 3
garfieldsg	0:662207e34fba	320	#define MPU6050_INTERRUPT_PLL_RDY_INT_BIT 2
garfieldsg	0:662207e34fba	321	#define MPU6050_INTERRUPT_DMP_INT_BIT 1
garfieldsg	0:662207e34fba	322	#define MPU6050_INTERRUPT_DATA_RDY_BIT 0
garfieldsg	0:662207e34fba	323
garfieldsg	0:662207e34fba	324	// TODO: figure out what these actually do
garfieldsg	0:662207e34fba	325	// UMPL source code is not very obivous
garfieldsg	0:662207e34fba	326	#define MPU6050_DMPINT_5_BIT 5
garfieldsg	0:662207e34fba	327	#define MPU6050_DMPINT_4_BIT 4
garfieldsg	0:662207e34fba	328	#define MPU6050_DMPINT_3_BIT 3
garfieldsg	0:662207e34fba	329	#define MPU6050_DMPINT_2_BIT 2
garfieldsg	0:662207e34fba	330	#define MPU6050_DMPINT_1_BIT 1
garfieldsg	0:662207e34fba	331	#define MPU6050_DMPINT_0_BIT 0
garfieldsg	0:662207e34fba	332
garfieldsg	0:662207e34fba	333	#define MPU6050_MOTION_MOT_XNEG_BIT 7
garfieldsg	0:662207e34fba	334	#define MPU6050_MOTION_MOT_XPOS_BIT 6
garfieldsg	0:662207e34fba	335	#define MPU6050_MOTION_MOT_YNEG_BIT 5
garfieldsg	0:662207e34fba	336	#define MPU6050_MOTION_MOT_YPOS_BIT 4
garfieldsg	0:662207e34fba	337	#define MPU6050_MOTION_MOT_ZNEG_BIT 3
garfieldsg	0:662207e34fba	338	#define MPU6050_MOTION_MOT_ZPOS_BIT 2
garfieldsg	0:662207e34fba	339	#define MPU6050_MOTION_MOT_ZRMOT_BIT 0
garfieldsg	0:662207e34fba	340
garfieldsg	0:662207e34fba	341	#define MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT 7
garfieldsg	0:662207e34fba	342	#define MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT 4
garfieldsg	0:662207e34fba	343	#define MPU6050_DELAYCTRL_I2C_SLV3_DLY_EN_BIT 3
garfieldsg	0:662207e34fba	344	#define MPU6050_DELAYCTRL_I2C_SLV2_DLY_EN_BIT 2
garfieldsg	0:662207e34fba	345	#define MPU6050_DELAYCTRL_I2C_SLV1_DLY_EN_BIT 1
garfieldsg	0:662207e34fba	346	#define MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT 0
garfieldsg	0:662207e34fba	347
garfieldsg	0:662207e34fba	348	#define MPU6050_PATHRESET_GYRO_RESET_BIT 2
garfieldsg	0:662207e34fba	349	#define MPU6050_PATHRESET_ACCEL_RESET_BIT 1
garfieldsg	0:662207e34fba	350	#define MPU6050_PATHRESET_TEMP_RESET_BIT 0
garfieldsg	0:662207e34fba	351
garfieldsg	0:662207e34fba	352	#define MPU6050_DETECT_ACCEL_ON_DELAY_BIT 5
garfieldsg	0:662207e34fba	353	#define MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH 2
garfieldsg	0:662207e34fba	354	#define MPU6050_DETECT_FF_COUNT_BIT 3
garfieldsg	0:662207e34fba	355	#define MPU6050_DETECT_FF_COUNT_LENGTH 2
garfieldsg	0:662207e34fba	356	#define MPU6050_DETECT_MOT_COUNT_BIT 1
garfieldsg	0:662207e34fba	357	#define MPU6050_DETECT_MOT_COUNT_LENGTH 2
garfieldsg	0:662207e34fba	358
garfieldsg	0:662207e34fba	359	#define MPU6050_DETECT_DECREMENT_RESET 0x0
garfieldsg	0:662207e34fba	360	#define MPU6050_DETECT_DECREMENT_1 0x1
garfieldsg	0:662207e34fba	361	#define MPU6050_DETECT_DECREMENT_2 0x2
garfieldsg	0:662207e34fba	362	#define MPU6050_DETECT_DECREMENT_4 0x3
garfieldsg	0:662207e34fba	363
garfieldsg	0:662207e34fba	364	#define MPU6050_USERCTRL_DMP_EN_BIT 7
garfieldsg	0:662207e34fba	365	#define MPU6050_USERCTRL_FIFO_EN_BIT 6
garfieldsg	0:662207e34fba	366	#define MPU6050_USERCTRL_I2C_MST_EN_BIT 5
garfieldsg	0:662207e34fba	367	#define MPU6050_USERCTRL_I2C_IF_DIS_BIT 4
garfieldsg	0:662207e34fba	368	#define MPU6050_USERCTRL_DMP_RESET_BIT 3
garfieldsg	0:662207e34fba	369	#define MPU6050_USERCTRL_FIFO_RESET_BIT 2
garfieldsg	0:662207e34fba	370	#define MPU6050_USERCTRL_I2C_MST_RESET_BIT 1
garfieldsg	0:662207e34fba	371	#define MPU6050_USERCTRL_SIG_COND_RESET_BIT 0
garfieldsg	0:662207e34fba	372
garfieldsg	0:662207e34fba	373	#define MPU6050_PWR1_DEVICE_RESET_BIT 7
garfieldsg	0:662207e34fba	374	#define MPU6050_PWR1_SLEEP_BIT 6
garfieldsg	0:662207e34fba	375	#define MPU6050_PWR1_CYCLE_BIT 5
garfieldsg	0:662207e34fba	376	#define MPU6050_PWR1_TEMP_DIS_BIT 3
garfieldsg	0:662207e34fba	377	#define MPU6050_PWR1_CLKSEL_BIT 2
garfieldsg	0:662207e34fba	378	#define MPU6050_PWR1_CLKSEL_LENGTH 3
garfieldsg	0:662207e34fba	379
garfieldsg	0:662207e34fba	380	#define MPU6050_CLOCK_INTERNAL 0x00
garfieldsg	0:662207e34fba	381	#define MPU6050_CLOCK_PLL_XGYRO 0x01
garfieldsg	0:662207e34fba	382	#define MPU6050_CLOCK_PLL_YGYRO 0x02
garfieldsg	0:662207e34fba	383	#define MPU6050_CLOCK_PLL_ZGYRO 0x03
garfieldsg	0:662207e34fba	384	#define MPU6050_CLOCK_PLL_EXT32K 0x04
garfieldsg	0:662207e34fba	385	#define MPU6050_CLOCK_PLL_EXT19M 0x05
garfieldsg	0:662207e34fba	386	#define MPU6050_CLOCK_KEEP_RESET 0x07
garfieldsg	0:662207e34fba	387
garfieldsg	0:662207e34fba	388	#define MPU6050_PWR2_LP_WAKE_CTRL_BIT 7
garfieldsg	0:662207e34fba	389	#define MPU6050_PWR2_LP_WAKE_CTRL_LENGTH 2
garfieldsg	0:662207e34fba	390	#define MPU6050_PWR2_STBY_XA_BIT 5
garfieldsg	0:662207e34fba	391	#define MPU6050_PWR2_STBY_YA_BIT 4
garfieldsg	0:662207e34fba	392	#define MPU6050_PWR2_STBY_ZA_BIT 3
garfieldsg	0:662207e34fba	393	#define MPU6050_PWR2_STBY_XG_BIT 2
garfieldsg	0:662207e34fba	394	#define MPU6050_PWR2_STBY_YG_BIT 1
garfieldsg	0:662207e34fba	395	#define MPU6050_PWR2_STBY_ZG_BIT 0
garfieldsg	0:662207e34fba	396
garfieldsg	0:662207e34fba	397	#define MPU6050_WAKE_FREQ_1P25 0x0
garfieldsg	0:662207e34fba	398	#define MPU6050_WAKE_FREQ_2P5 0x1
garfieldsg	0:662207e34fba	399	#define MPU6050_WAKE_FREQ_5 0x2
garfieldsg	0:662207e34fba	400	#define MPU6050_WAKE_FREQ_10 0x3
garfieldsg	0:662207e34fba	401
garfieldsg	0:662207e34fba	402	#define MPU6050_BANKSEL_PRFTCH_EN_BIT 6
garfieldsg	0:662207e34fba	403	#define MPU6050_BANKSEL_CFG_USER_BANK_BIT 5
garfieldsg	0:662207e34fba	404	#define MPU6050_BANKSEL_MEM_SEL_BIT 4
garfieldsg	0:662207e34fba	405	#define MPU6050_BANKSEL_MEM_SEL_LENGTH 5
garfieldsg	0:662207e34fba	406
garfieldsg	0:662207e34fba	407	#define MPU6050_WHO_AM_I_BIT 6
garfieldsg	0:662207e34fba	408	#define MPU6050_WHO_AM_I_LENGTH 6
garfieldsg	0:662207e34fba	409
garfieldsg	0:662207e34fba	410	#define MPU6050_DMP_MEMORY_BANKS 8
garfieldsg	0:662207e34fba	411	#define MPU6050_DMP_MEMORY_BANK_SIZE 256
garfieldsg	0:662207e34fba	412	#define MPU6050_DMP_MEMORY_CHUNK_SIZE 16
garfieldsg	0:662207e34fba	413
tyftyftyf	15:09f072efa71e	414
tyftyftyf	15:09f072efa71e	415
tyftyftyf	15:09f072efa71e	416	#define MPU60X0_ADDRESS_AD0_LOW 0x68 // address pin low (GND), default for InvenSense evaluation board
tyftyftyf	15:09f072efa71e	417	#define MPU60X0_ADDRESS_AD0_HIGH 0x69 // address pin high (VCC)
tyftyftyf	15:09f072efa71e	418	#define MPU60X0_DEFAULT_ADDRESS MPU60X0_ADDRESS_AD0_LOW
tyftyftyf	15:09f072efa71e	419	#define MPU60X0_DEFAULT_SS_PIN 4
tyftyftyf	15:09f072efa71e	420
tyftyftyf	15:09f072efa71e	421	#define MPU60X0_RA_XG_OFFS_TC 0x00 //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD
tyftyftyf	15:09f072efa71e	422	#define MPU60X0_RA_YG_OFFS_TC 0x01 //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD
tyftyftyf	15:09f072efa71e	423	#define MPU60X0_RA_ZG_OFFS_TC 0x02 //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD
tyftyftyf	15:09f072efa71e	424	#define MPU60X0_RA_X_FINE_GAIN 0x03 //[7:0] X_FINE_GAIN
tyftyftyf	15:09f072efa71e	425	#define MPU60X0_RA_Y_FINE_GAIN 0x04 //[7:0] Y_FINE_GAIN
tyftyftyf	15:09f072efa71e	426	#define MPU60X0_RA_Z_FINE_GAIN 0x05 //[7:0] Z_FINE_GAIN
tyftyftyf	15:09f072efa71e	427	#define MPU60X0_RA_XA_OFFS_H 0x06 //[15:0] XA_OFFS
tyftyftyf	15:09f072efa71e	428	#define MPU60X0_RA_XA_OFFS_L_TC 0x07
tyftyftyf	15:09f072efa71e	429	#define MPU60X0_RA_YA_OFFS_H 0x08 //[15:0] YA_OFFS
tyftyftyf	15:09f072efa71e	430	#define MPU60X0_RA_YA_OFFS_L_TC 0x09
tyftyftyf	15:09f072efa71e	431	#define MPU60X0_RA_ZA_OFFS_H 0x0A //[15:0] ZA_OFFS
tyftyftyf	15:09f072efa71e	432	#define MPU60X0_RA_ZA_OFFS_L_TC 0x0B
tyftyftyf	15:09f072efa71e	433	#define MPU60X0_RA_XG_OFFS_USRH 0x13 //[15:0] XG_OFFS_USR
tyftyftyf	15:09f072efa71e	434	#define MPU60X0_RA_XG_OFFS_USRL 0x14
tyftyftyf	15:09f072efa71e	435	#define MPU60X0_RA_YG_OFFS_USRH 0x15 //[15:0] YG_OFFS_USR
tyftyftyf	15:09f072efa71e	436	#define MPU60X0_RA_YG_OFFS_USRL 0x16
tyftyftyf	15:09f072efa71e	437	#define MPU60X0_RA_ZG_OFFS_USRH 0x17 //[15:0] ZG_OFFS_USR
tyftyftyf	15:09f072efa71e	438	#define MPU60X0_RA_ZG_OFFS_USRL 0x18
tyftyftyf	15:09f072efa71e	439	#define MPU60X0_RA_SMPLRT_DIV 0x19
tyftyftyf	15:09f072efa71e	440	#define MPU60X0_RA_CONFIG 0x1A
tyftyftyf	15:09f072efa71e	441	#define MPU60X0_RA_GYRO_CONFIG 0x1B
tyftyftyf	15:09f072efa71e	442	#define MPU60X0_RA_ACCEL_CONFIG 0x1C
tyftyftyf	15:09f072efa71e	443	#define MPU9250_RA_ACCEL_CONFIG2 0x1D
tyftyftyf	15:09f072efa71e	444	#define MPU60X0_RA_FF_THR 0x1D
tyftyftyf	15:09f072efa71e	445	#define MPU60X0_RA_FF_DUR 0x1E
tyftyftyf	15:09f072efa71e	446	#define MPU60X0_RA_MOT_THR 0x1F
tyftyftyf	15:09f072efa71e	447	#define MPU60X0_RA_MOT_DUR 0x20
tyftyftyf	15:09f072efa71e	448	#define MPU60X0_RA_ZRMOT_THR 0x21
tyftyftyf	15:09f072efa71e	449	#define MPU60X0_RA_ZRMOT_DUR 0x22
tyftyftyf	15:09f072efa71e	450	#define MPU60X0_RA_FIFO_EN 0x23
tyftyftyf	15:09f072efa71e	451	#define MPU60X0_RA_I2C_MST_CTRL 0x24
tyftyftyf	15:09f072efa71e	452	#define MPU60X0_RA_I2C_SLV0_ADDR 0x25
tyftyftyf	15:09f072efa71e	453	#define MPU60X0_RA_I2C_SLV0_REG 0x26
tyftyftyf	15:09f072efa71e	454	#define MPU60X0_RA_I2C_SLV0_CTRL 0x27
tyftyftyf	15:09f072efa71e	455	#define MPU60X0_RA_I2C_SLV1_ADDR 0x28
tyftyftyf	15:09f072efa71e	456	#define MPU60X0_RA_I2C_SLV1_REG 0x29
tyftyftyf	15:09f072efa71e	457	#define MPU60X0_RA_I2C_SLV1_CTRL 0x2A
tyftyftyf	15:09f072efa71e	458	#define MPU60X0_RA_I2C_SLV2_ADDR 0x2B
tyftyftyf	15:09f072efa71e	459	#define MPU60X0_RA_I2C_SLV2_REG 0x2C
tyftyftyf	15:09f072efa71e	460	#define MPU60X0_RA_I2C_SLV2_CTRL 0x2D
tyftyftyf	15:09f072efa71e	461	#define MPU60X0_RA_I2C_SLV3_ADDR 0x2E
tyftyftyf	15:09f072efa71e	462	#define MPU60X0_RA_I2C_SLV3_REG 0x2F
tyftyftyf	15:09f072efa71e	463	#define MPU60X0_RA_I2C_SLV3_CTRL 0x30
tyftyftyf	15:09f072efa71e	464	#define MPU60X0_RA_I2C_SLV4_ADDR 0x31
tyftyftyf	15:09f072efa71e	465	#define MPU60X0_RA_I2C_SLV4_REG 0x32
tyftyftyf	15:09f072efa71e	466	#define MPU60X0_RA_I2C_SLV4_DO 0x33
tyftyftyf	15:09f072efa71e	467	#define MPU60X0_RA_I2C_SLV4_CTRL 0x34
tyftyftyf	15:09f072efa71e	468	#define MPU60X0_RA_I2C_SLV4_DI 0x35
tyftyftyf	15:09f072efa71e	469	#define MPU60X0_RA_I2C_MST_STATUS 0x36
tyftyftyf	15:09f072efa71e	470	#define MPU60X0_RA_INT_PIN_CFG 0x37
tyftyftyf	15:09f072efa71e	471	#define MPU60X0_RA_INT_ENABLE 0x38
tyftyftyf	15:09f072efa71e	472	#define MPU60X0_RA_DMP_INT_STATUS 0x39
tyftyftyf	15:09f072efa71e	473	#define MPU60X0_RA_INT_STATUS 0x3A
tyftyftyf	15:09f072efa71e	474	#define MPU60X0_RA_ACCEL_XOUT_H 0x3B
tyftyftyf	15:09f072efa71e	475	#define MPU60X0_RA_ACCEL_XOUT_L 0x3C
tyftyftyf	15:09f072efa71e	476	#define MPU60X0_RA_ACCEL_YOUT_H 0x3D
tyftyftyf	15:09f072efa71e	477	#define MPU60X0_RA_ACCEL_YOUT_L 0x3E
tyftyftyf	15:09f072efa71e	478	#define MPU60X0_RA_ACCEL_ZOUT_H 0x3F
tyftyftyf	15:09f072efa71e	479	#define MPU60X0_RA_ACCEL_ZOUT_L 0x40
tyftyftyf	15:09f072efa71e	480	#define MPU60X0_RA_TEMP_OUT_H 0x41
tyftyftyf	15:09f072efa71e	481	#define MPU60X0_RA_TEMP_OUT_L 0x42
tyftyftyf	15:09f072efa71e	482	#define MPU60X0_RA_GYRO_XOUT_H 0x43
tyftyftyf	15:09f072efa71e	483	#define MPU60X0_RA_GYRO_XOUT_L 0x44
tyftyftyf	15:09f072efa71e	484	#define MPU60X0_RA_GYRO_YOUT_H 0x45
tyftyftyf	15:09f072efa71e	485	#define MPU60X0_RA_GYRO_YOUT_L 0x46
tyftyftyf	15:09f072efa71e	486	#define MPU60X0_RA_GYRO_ZOUT_H 0x47
tyftyftyf	15:09f072efa71e	487	#define MPU60X0_RA_GYRO_ZOUT_L 0x48
tyftyftyf	15:09f072efa71e	488	#define MPU60X0_RA_EXT_SENS_DATA_00 0x49
tyftyftyf	15:09f072efa71e	489	#define MPU60X0_RA_EXT_SENS_DATA_01 0x4A
tyftyftyf	15:09f072efa71e	490	#define MPU60X0_RA_EXT_SENS_DATA_02 0x4B
tyftyftyf	15:09f072efa71e	491	#define MPU60X0_RA_EXT_SENS_DATA_03 0x4C
tyftyftyf	15:09f072efa71e	492	#define MPU60X0_RA_EXT_SENS_DATA_04 0x4D
tyftyftyf	15:09f072efa71e	493	#define MPU60X0_RA_EXT_SENS_DATA_05 0x4E
tyftyftyf	15:09f072efa71e	494	#define MPU60X0_RA_EXT_SENS_DATA_06 0x4F
tyftyftyf	15:09f072efa71e	495	#define MPU60X0_RA_EXT_SENS_DATA_07 0x50
tyftyftyf	15:09f072efa71e	496	#define MPU60X0_RA_EXT_SENS_DATA_08 0x51
tyftyftyf	15:09f072efa71e	497	#define MPU60X0_RA_EXT_SENS_DATA_09 0x52
tyftyftyf	15:09f072efa71e	498	#define MPU60X0_RA_EXT_SENS_DATA_10 0x53
tyftyftyf	15:09f072efa71e	499	#define MPU60X0_RA_EXT_SENS_DATA_11 0x54
tyftyftyf	15:09f072efa71e	500	#define MPU60X0_RA_EXT_SENS_DATA_12 0x55
tyftyftyf	15:09f072efa71e	501	#define MPU60X0_RA_EXT_SENS_DATA_13 0x56
tyftyftyf	15:09f072efa71e	502	#define MPU60X0_RA_EXT_SENS_DATA_14 0x57
tyftyftyf	15:09f072efa71e	503	#define MPU60X0_RA_EXT_SENS_DATA_15 0x58
tyftyftyf	15:09f072efa71e	504	#define MPU60X0_RA_EXT_SENS_DATA_16 0x59
tyftyftyf	15:09f072efa71e	505	#define MPU60X0_RA_EXT_SENS_DATA_17 0x5A
tyftyftyf	15:09f072efa71e	506	#define MPU60X0_RA_EXT_SENS_DATA_18 0x5B
tyftyftyf	15:09f072efa71e	507	#define MPU60X0_RA_EXT_SENS_DATA_19 0x5C
tyftyftyf	15:09f072efa71e	508	#define MPU60X0_RA_EXT_SENS_DATA_20 0x5D
tyftyftyf	15:09f072efa71e	509	#define MPU60X0_RA_EXT_SENS_DATA_21 0x5E
tyftyftyf	15:09f072efa71e	510	#define MPU60X0_RA_EXT_SENS_DATA_22 0x5F
tyftyftyf	15:09f072efa71e	511	#define MPU60X0_RA_EXT_SENS_DATA_23 0x60
tyftyftyf	15:09f072efa71e	512	#define MPU60X0_RA_MOT_DETECT_STATUS 0x61
tyftyftyf	15:09f072efa71e	513	#define MPU60X0_RA_I2C_SLV0_DO 0x63
tyftyftyf	15:09f072efa71e	514	#define MPU60X0_RA_I2C_SLV1_DO 0x64
tyftyftyf	15:09f072efa71e	515	#define MPU60X0_RA_I2C_SLV2_DO 0x65
tyftyftyf	15:09f072efa71e	516	#define MPU60X0_RA_I2C_SLV3_DO 0x66
tyftyftyf	15:09f072efa71e	517	#define MPU60X0_RA_I2C_MST_DELAY_CTRL 0x67
tyftyftyf	15:09f072efa71e	518	#define MPU60X0_RA_SIGNAL_PATH_RESET 0x68
tyftyftyf	15:09f072efa71e	519	#define MPU60X0_RA_MOT_DETECT_CTRL 0x69
tyftyftyf	15:09f072efa71e	520	#define MPU60X0_RA_USER_CTRL 0x6A
tyftyftyf	15:09f072efa71e	521	#define MPU60X0_RA_PWR_MGMT_1 0x6B
tyftyftyf	15:09f072efa71e	522	#define MPU60X0_RA_PWR_MGMT_2 0x6C
tyftyftyf	15:09f072efa71e	523	#define MPU60X0_RA_BANK_SEL 0x6D
tyftyftyf	15:09f072efa71e	524	#define MPU60X0_RA_MEM_START_ADDR 0x6E
tyftyftyf	15:09f072efa71e	525	#define MPU60X0_RA_MEM_R_W 0x6F
tyftyftyf	15:09f072efa71e	526	#define MPU60X0_RA_DMP_CFG_1 0x70
tyftyftyf	15:09f072efa71e	527	#define MPU60X0_RA_DMP_CFG_2 0x71
tyftyftyf	15:09f072efa71e	528	#define MPU60X0_RA_FIFO_COUNTH 0x72
tyftyftyf	15:09f072efa71e	529	#define MPU60X0_RA_FIFO_COUNTL 0x73
tyftyftyf	15:09f072efa71e	530	#define MPU60X0_RA_FIFO_R_W 0x74
tyftyftyf	15:09f072efa71e	531	#define MPU60X0_RA_WHO_AM_I 0x75
tyftyftyf	15:09f072efa71e	532
tyftyftyf	15:09f072efa71e	533	#define MPU60X0_TC_PWR_MODE_BIT 7
tyftyftyf	15:09f072efa71e	534	#define MPU60X0_TC_OFFSET_BIT 6
tyftyftyf	15:09f072efa71e	535	#define MPU60X0_TC_OFFSET_LENGTH 6
tyftyftyf	15:09f072efa71e	536	#define MPU60X0_TC_OTP_BNK_VLD_BIT 0
tyftyftyf	15:09f072efa71e	537
tyftyftyf	15:09f072efa71e	538	#define MPU60X0_VDDIO_LEVEL_VLOGIC 0
tyftyftyf	15:09f072efa71e	539	#define MPU60X0_VDDIO_LEVEL_VDD 1
tyftyftyf	15:09f072efa71e	540
tyftyftyf	15:09f072efa71e	541	#define MPU60X0_CFG_EXT_SYNC_SET_BIT 5
tyftyftyf	15:09f072efa71e	542	#define MPU60X0_CFG_EXT_SYNC_SET_LENGTH 3
tyftyftyf	15:09f072efa71e	543	#define MPU60X0_CFG_DLPF_CFG_BIT 2
tyftyftyf	15:09f072efa71e	544	#define MPU60X0_CFG_DLPF_CFG_LENGTH 3
tyftyftyf	15:09f072efa71e	545
tyftyftyf	15:09f072efa71e	546	#define MPU60X0_EXT_SYNC_DISABLED 0x0
tyftyftyf	15:09f072efa71e	547	#define MPU60X0_EXT_SYNC_TEMP_OUT_L 0x1
tyftyftyf	15:09f072efa71e	548	#define MPU60X0_EXT_SYNC_GYRO_XOUT_L 0x2
tyftyftyf	15:09f072efa71e	549	#define MPU60X0_EXT_SYNC_GYRO_YOUT_L 0x3
tyftyftyf	15:09f072efa71e	550	#define MPU60X0_EXT_SYNC_GYRO_ZOUT_L 0x4
tyftyftyf	15:09f072efa71e	551	#define MPU60X0_EXT_SYNC_ACCEL_XOUT_L 0x5
tyftyftyf	15:09f072efa71e	552	#define MPU60X0_EXT_SYNC_ACCEL_YOUT_L 0x6
tyftyftyf	15:09f072efa71e	553	#define MPU60X0_EXT_SYNC_ACCEL_ZOUT_L 0x7
tyftyftyf	15:09f072efa71e	554
tyftyftyf	15:09f072efa71e	555	#define MPU60X0_DLPF_BW_256 0x00
tyftyftyf	15:09f072efa71e	556	#define MPU60X0_DLPF_BW_184 0x01
tyftyftyf	15:09f072efa71e	557	#define MPU60X0_DLPF_BW_98 0x02
tyftyftyf	15:09f072efa71e	558	#define MPU60X0_DLPF_BW_42 0x03
tyftyftyf	15:09f072efa71e	559	#define MPU60X0_DLPF_BW_20 0x04
tyftyftyf	15:09f072efa71e	560	#define MPU60X0_DLPF_BW_10 0x05
tyftyftyf	15:09f072efa71e	561	#define MPU60X0_DLPF_BW_5 0x06
tyftyftyf	15:09f072efa71e	562
tyftyftyf	15:09f072efa71e	563	#define MPU60X0_GCONFIG_FS_SEL_BIT 4
tyftyftyf	15:09f072efa71e	564	#define MPU60X0_GCONFIG_FS_SEL_LENGTH 2
tyftyftyf	15:09f072efa71e	565
tyftyftyf	15:09f072efa71e	566	#define MPU60X0_GYRO_FS_250 0x00
tyftyftyf	15:09f072efa71e	567	#define MPU60X0_GYRO_FS_500 0x01
tyftyftyf	15:09f072efa71e	568	#define MPU60X0_GYRO_FS_1000 0x02
tyftyftyf	15:09f072efa71e	569	#define MPU60X0_GYRO_FS_2000 0x03
tyftyftyf	15:09f072efa71e	570
tyftyftyf	15:09f072efa71e	571	#define MPU60X0_ACONFIG_XA_ST_BIT 7
tyftyftyf	15:09f072efa71e	572	#define MPU60X0_ACONFIG_YA_ST_BIT 6
tyftyftyf	15:09f072efa71e	573	#define MPU60X0_ACONFIG_ZA_ST_BIT 5
tyftyftyf	15:09f072efa71e	574	#define MPU60X0_ACONFIG_AFS_SEL_BIT 4
tyftyftyf	15:09f072efa71e	575	#define MPU60X0_ACONFIG_AFS_SEL_LENGTH 2
tyftyftyf	15:09f072efa71e	576	#define MPU60X0_ACONFIG_ACCEL_HPF_BIT 2
tyftyftyf	15:09f072efa71e	577	#define MPU60X0_ACONFIG_ACCEL_HPF_LENGTH 3
tyftyftyf	15:09f072efa71e	578
tyftyftyf	15:09f072efa71e	579	#define MPU60X0_ACCEL_FS_2 0x00
tyftyftyf	15:09f072efa71e	580	#define MPU60X0_ACCEL_FS_4 0x01
tyftyftyf	15:09f072efa71e	581	#define MPU60X0_ACCEL_FS_8 0x02
tyftyftyf	15:09f072efa71e	582	#define MPU60X0_ACCEL_FS_16 0x03
tyftyftyf	15:09f072efa71e	583
tyftyftyf	15:09f072efa71e	584	#define MPU60X0_DHPF_RESET 0x00
tyftyftyf	15:09f072efa71e	585	#define MPU60X0_DHPF_5 0x01
tyftyftyf	15:09f072efa71e	586	#define MPU60X0_DHPF_2P5 0x02
tyftyftyf	15:09f072efa71e	587	#define MPU60X0_DHPF_1P25 0x03
tyftyftyf	15:09f072efa71e	588	#define MPU60X0_DHPF_0P63 0x04
tyftyftyf	15:09f072efa71e	589	#define MPU60X0_DHPF_HOLD 0x07
tyftyftyf	15:09f072efa71e	590
tyftyftyf	15:09f072efa71e	591	#define MPU60X0_TEMP_FIFO_EN_BIT 7
tyftyftyf	15:09f072efa71e	592	#define MPU60X0_XG_FIFO_EN_BIT 6
tyftyftyf	15:09f072efa71e	593	#define MPU60X0_YG_FIFO_EN_BIT 5
tyftyftyf	15:09f072efa71e	594	#define MPU60X0_ZG_FIFO_EN_BIT 4
tyftyftyf	15:09f072efa71e	595	#define MPU60X0_ACCEL_FIFO_EN_BIT 3
tyftyftyf	15:09f072efa71e	596	#define MPU60X0_SLV2_FIFO_EN_BIT 2
tyftyftyf	15:09f072efa71e	597	#define MPU60X0_SLV1_FIFO_EN_BIT 1
tyftyftyf	15:09f072efa71e	598	#define MPU60X0_SLV0_FIFO_EN_BIT 0
tyftyftyf	15:09f072efa71e	599
tyftyftyf	15:09f072efa71e	600	#define MPU60X0_MULT_MST_EN_BIT 7
tyftyftyf	15:09f072efa71e	601	#define MPU60X0_WAIT_FOR_ES_BIT 6
tyftyftyf	15:09f072efa71e	602	#define MPU60X0_SLV_3_FIFO_EN_BIT 5
tyftyftyf	15:09f072efa71e	603	#define MPU60X0_I2C_MST_P_NSR_BIT 4
tyftyftyf	15:09f072efa71e	604	#define MPU60X0_I2C_MST_CLK_BIT 3
tyftyftyf	15:09f072efa71e	605	#define MPU60X0_I2C_MST_CLK_LENGTH 4
tyftyftyf	15:09f072efa71e	606
tyftyftyf	15:09f072efa71e	607	#define MPU60X0_CLOCK_DIV_348 0x0
tyftyftyf	15:09f072efa71e	608	#define MPU60X0_CLOCK_DIV_333 0x1
tyftyftyf	15:09f072efa71e	609	#define MPU60X0_CLOCK_DIV_320 0x2
tyftyftyf	15:09f072efa71e	610	#define MPU60X0_CLOCK_DIV_308 0x3
tyftyftyf	15:09f072efa71e	611	#define MPU60X0_CLOCK_DIV_296 0x4
tyftyftyf	15:09f072efa71e	612	#define MPU60X0_CLOCK_DIV_286 0x5
tyftyftyf	15:09f072efa71e	613	#define MPU60X0_CLOCK_DIV_276 0x6
tyftyftyf	15:09f072efa71e	614	#define MPU60X0_CLOCK_DIV_267 0x7
tyftyftyf	15:09f072efa71e	615	#define MPU60X0_CLOCK_DIV_258 0x8
tyftyftyf	15:09f072efa71e	616	#define MPU60X0_CLOCK_DIV_500 0x9
tyftyftyf	15:09f072efa71e	617	#define MPU60X0_CLOCK_DIV_471 0xA
tyftyftyf	15:09f072efa71e	618	#define MPU60X0_CLOCK_DIV_444 0xB
tyftyftyf	15:09f072efa71e	619	#define MPU60X0_CLOCK_DIV_421 0xC
tyftyftyf	15:09f072efa71e	620	#define MPU60X0_CLOCK_DIV_400 0xD
tyftyftyf	15:09f072efa71e	621	#define MPU60X0_CLOCK_DIV_381 0xE
tyftyftyf	15:09f072efa71e	622	#define MPU60X0_CLOCK_DIV_364 0xF
tyftyftyf	15:09f072efa71e	623
tyftyftyf	15:09f072efa71e	624	#define MPU60X0_I2C_SLV_RW_BIT 7
tyftyftyf	15:09f072efa71e	625	#define MPU60X0_I2C_SLV_ADDR_BIT 6
tyftyftyf	15:09f072efa71e	626	#define MPU60X0_I2C_SLV_ADDR_LENGTH 7
tyftyftyf	15:09f072efa71e	627	#define MPU60X0_I2C_SLV_EN_BIT 7
tyftyftyf	15:09f072efa71e	628	#define MPU60X0_I2C_SLV_BYTE_SW_BIT 6
tyftyftyf	15:09f072efa71e	629	#define MPU60X0_I2C_SLV_REG_DIS_BIT 5
tyftyftyf	15:09f072efa71e	630	#define MPU60X0_I2C_SLV_GRP_BIT 4
tyftyftyf	15:09f072efa71e	631	#define MPU60X0_I2C_SLV_LEN_BIT 3
tyftyftyf	15:09f072efa71e	632	#define MPU60X0_I2C_SLV_LEN_LENGTH 4
tyftyftyf	15:09f072efa71e	633
tyftyftyf	15:09f072efa71e	634	#define MPU60X0_I2C_SLV4_RW_BIT 7
tyftyftyf	15:09f072efa71e	635	#define MPU60X0_I2C_SLV4_ADDR_BIT 6
tyftyftyf	15:09f072efa71e	636	#define MPU60X0_I2C_SLV4_ADDR_LENGTH 7
tyftyftyf	15:09f072efa71e	637	#define MPU60X0_I2C_SLV4_EN_BIT 7
tyftyftyf	15:09f072efa71e	638	#define MPU60X0_I2C_SLV4_INT_EN_BIT 6
tyftyftyf	15:09f072efa71e	639	#define MPU60X0_I2C_SLV4_REG_DIS_BIT 5
tyftyftyf	15:09f072efa71e	640	#define MPU60X0_I2C_SLV4_MST_DLY_BIT 4
tyftyftyf	15:09f072efa71e	641	#define MPU60X0_I2C_SLV4_MST_DLY_LENGTH 5
tyftyftyf	15:09f072efa71e	642
tyftyftyf	15:09f072efa71e	643	#define MPU60X0_MST_PASS_THROUGH_BIT 7
tyftyftyf	15:09f072efa71e	644	#define MPU60X0_MST_I2C_SLV4_DONE_BIT 6
tyftyftyf	15:09f072efa71e	645	#define MPU60X0_MST_I2C_LOST_ARB_BIT 5
tyftyftyf	15:09f072efa71e	646	#define MPU60X0_MST_I2C_SLV4_NACK_BIT 4
tyftyftyf	15:09f072efa71e	647	#define MPU60X0_MST_I2C_SLV3_NACK_BIT 3
tyftyftyf	15:09f072efa71e	648	#define MPU60X0_MST_I2C_SLV2_NACK_BIT 2
tyftyftyf	15:09f072efa71e	649	#define MPU60X0_MST_I2C_SLV1_NACK_BIT 1
tyftyftyf	15:09f072efa71e	650	#define MPU60X0_MST_I2C_SLV0_NACK_BIT 0
tyftyftyf	15:09f072efa71e	651
tyftyftyf	15:09f072efa71e	652	#define MPU60X0_INTCFG_INT_LEVEL_BIT 7
tyftyftyf	15:09f072efa71e	653	#define MPU60X0_INTCFG_INT_OPEN_BIT 6
tyftyftyf	15:09f072efa71e	654	#define MPU60X0_INTCFG_LATCH_INT_EN_BIT 5
tyftyftyf	15:09f072efa71e	655	#define MPU60X0_INTCFG_INT_RD_CLEAR_BIT 4
tyftyftyf	15:09f072efa71e	656	#define MPU60X0_INTCFG_FSYNC_INT_LEVEL_BIT 3
tyftyftyf	15:09f072efa71e	657	#define MPU60X0_INTCFG_FSYNC_INT_EN_BIT 2
tyftyftyf	15:09f072efa71e	658	#define MPU60X0_INTCFG_I2C_BYPASS_EN_BIT 1
tyftyftyf	15:09f072efa71e	659	#define MPU60X0_INTCFG_CLKOUT_EN_BIT 0
tyftyftyf	15:09f072efa71e	660
tyftyftyf	15:09f072efa71e	661	#define MPU60X0_INTMODE_ACTIVEHIGH 0x00
tyftyftyf	15:09f072efa71e	662	#define MPU60X0_INTMODE_ACTIVELOW 0x01
tyftyftyf	15:09f072efa71e	663
tyftyftyf	15:09f072efa71e	664	#define MPU60X0_INTDRV_PUSHPULL 0x00
tyftyftyf	15:09f072efa71e	665	#define MPU60X0_INTDRV_OPENDRAIN 0x01
tyftyftyf	15:09f072efa71e	666
tyftyftyf	15:09f072efa71e	667	#define MPU60X0_INTLATCH_50USPULSE 0x00
tyftyftyf	15:09f072efa71e	668	#define MPU60X0_INTLATCH_WAITCLEAR 0x01
tyftyftyf	15:09f072efa71e	669
tyftyftyf	15:09f072efa71e	670	#define MPU60X0_INTCLEAR_STATUSREAD 0x00
tyftyftyf	15:09f072efa71e	671	#define MPU60X0_INTCLEAR_ANYREAD 0x01
tyftyftyf	15:09f072efa71e	672
tyftyftyf	15:09f072efa71e	673	#define MPU60X0_INTERRUPT_FF_BIT 7
tyftyftyf	15:09f072efa71e	674	#define MPU60X0_INTERRUPT_MOT_BIT 6
tyftyftyf	15:09f072efa71e	675	#define MPU60X0_INTERRUPT_ZMOT_BIT 5
tyftyftyf	15:09f072efa71e	676	#define MPU60X0_INTERRUPT_FIFO_OFLOW_BIT 4
tyftyftyf	15:09f072efa71e	677	#define MPU60X0_INTERRUPT_I2C_MST_INT_BIT 3
tyftyftyf	15:09f072efa71e	678	#define MPU60X0_INTERRUPT_PLL_RDY_INT_BIT 2
tyftyftyf	15:09f072efa71e	679	#define MPU60X0_INTERRUPT_DMP_INT_BIT 1
tyftyftyf	15:09f072efa71e	680	#define MPU60X0_INTERRUPT_DATA_RDY_BIT 0
tyftyftyf	15:09f072efa71e	681
tyftyftyf	15:09f072efa71e	682	#define MPU60X0_INTERRUPT_FF 0x80
tyftyftyf	15:09f072efa71e	683	#define MPU60X0_INTERRUPT_MOT 0x40
tyftyftyf	15:09f072efa71e	684	#define MPU60X0_INTERRUPT_ZMOT 0x20
tyftyftyf	15:09f072efa71e	685	#define MPU60X0_INTERRUPT_FIFO_OFLOW 0x10
tyftyftyf	15:09f072efa71e	686	#define MPU60X0_INTERRUPT_I2C_MST_INT 0x08
tyftyftyf	15:09f072efa71e	687	#define MPU60X0_INTERRUPT_PLL_RDY_INT 0x04
tyftyftyf	15:09f072efa71e	688	#define MPU60X0_INTERRUPT_DMP_INT 0x02
tyftyftyf	15:09f072efa71e	689	#define MPU60X0_INTERRUPT_DATA_RDY 0x01
tyftyftyf	15:09f072efa71e	690
tyftyftyf	15:09f072efa71e	691	// TODO: figure out what these actually do
tyftyftyf	15:09f072efa71e	692	// UMPL source code is not very obivous
tyftyftyf	15:09f072efa71e	693	#define MPU60X0_DMPINT_5_BIT 5
tyftyftyf	15:09f072efa71e	694	#define MPU60X0_DMPINT_4_BIT 4
tyftyftyf	15:09f072efa71e	695	#define MPU60X0_DMPINT_3_BIT 3
tyftyftyf	15:09f072efa71e	696	#define MPU60X0_DMPINT_2_BIT 2
tyftyftyf	15:09f072efa71e	697	#define MPU60X0_DMPINT_1_BIT 1
tyftyftyf	15:09f072efa71e	698	#define MPU60X0_DMPINT_0_BIT 0
tyftyftyf	15:09f072efa71e	699
tyftyftyf	15:09f072efa71e	700	#define MPU60X0_MOTION_MOT_XNEG_BIT 7
tyftyftyf	15:09f072efa71e	701	#define MPU60X0_MOTION_MOT_XPOS_BIT 6
tyftyftyf	15:09f072efa71e	702	#define MPU60X0_MOTION_MOT_YNEG_BIT 5
tyftyftyf	15:09f072efa71e	703	#define MPU60X0_MOTION_MOT_YPOS_BIT 4
tyftyftyf	15:09f072efa71e	704	#define MPU60X0_MOTION_MOT_ZNEG_BIT 3
tyftyftyf	15:09f072efa71e	705	#define MPU60X0_MOTION_MOT_ZPOS_BIT 2
tyftyftyf	15:09f072efa71e	706	#define MPU60X0_MOTION_MOT_ZRMOT_BIT 0
tyftyftyf	15:09f072efa71e	707
tyftyftyf	15:09f072efa71e	708	#define MPU60X0_DELAYCTRL_DELAY_ES_SHADOW_BIT 7
tyftyftyf	15:09f072efa71e	709	#define MPU60X0_DELAYCTRL_I2C_SLV4_DLY_EN_BIT 4
tyftyftyf	15:09f072efa71e	710	#define MPU60X0_DELAYCTRL_I2C_SLV3_DLY_EN_BIT 3
tyftyftyf	15:09f072efa71e	711	#define MPU60X0_DELAYCTRL_I2C_SLV2_DLY_EN_BIT 2
tyftyftyf	15:09f072efa71e	712	#define MPU60X0_DELAYCTRL_I2C_SLV1_DLY_EN_BIT 1
tyftyftyf	15:09f072efa71e	713	#define MPU60X0_DELAYCTRL_I2C_SLV0_DLY_EN_BIT 0
tyftyftyf	15:09f072efa71e	714
tyftyftyf	15:09f072efa71e	715	#define MPU60X0_PATHRESET_GYRO_RESET_BIT 2
tyftyftyf	15:09f072efa71e	716	#define MPU60X0_PATHRESET_ACCEL_RESET_BIT 1
tyftyftyf	15:09f072efa71e	717	#define MPU60X0_PATHRESET_TEMP_RESET_BIT 0
tyftyftyf	15:09f072efa71e	718
tyftyftyf	15:09f072efa71e	719	#define MPU60X0_DETECT_ACCEL_ON_DELAY_BIT 5
tyftyftyf	15:09f072efa71e	720	#define MPU60X0_DETECT_ACCEL_ON_DELAY_LENGTH 2
tyftyftyf	15:09f072efa71e	721	#define MPU60X0_DETECT_FF_COUNT_BIT 3
tyftyftyf	15:09f072efa71e	722	#define MPU60X0_DETECT_FF_COUNT_LENGTH 2
tyftyftyf	15:09f072efa71e	723	#define MPU60X0_DETECT_MOT_COUNT_BIT 1
tyftyftyf	15:09f072efa71e	724	#define MPU60X0_DETECT_MOT_COUNT_LENGTH 2
tyftyftyf	15:09f072efa71e	725
tyftyftyf	15:09f072efa71e	726	#define MPU60X0_DETECT_DECREMENT_RESET 0x0
tyftyftyf	15:09f072efa71e	727	#define MPU60X0_DETECT_DECREMENT_1 0x1
tyftyftyf	15:09f072efa71e	728	#define MPU60X0_DETECT_DECREMENT_2 0x2
tyftyftyf	15:09f072efa71e	729	#define MPU60X0_DETECT_DECREMENT_4 0x3
tyftyftyf	15:09f072efa71e	730
tyftyftyf	15:09f072efa71e	731	#define MPU60X0_USERCTRL_DMP_EN_BIT 7
tyftyftyf	15:09f072efa71e	732	#define MPU60X0_USERCTRL_FIFO_EN_BIT 6
tyftyftyf	15:09f072efa71e	733	#define MPU60X0_USERCTRL_I2C_MST_EN_BIT 5
tyftyftyf	15:09f072efa71e	734	#define MPU60X0_USERCTRL_I2C_IF_DIS_BIT 4
tyftyftyf	15:09f072efa71e	735	#define MPU60X0_USERCTRL_DMP_RESET_BIT 3
tyftyftyf	15:09f072efa71e	736	#define MPU60X0_USERCTRL_FIFO_RESET_BIT 2
tyftyftyf	15:09f072efa71e	737	#define MPU60X0_USERCTRL_I2C_MST_RESET_BIT 1
tyftyftyf	15:09f072efa71e	738	#define MPU60X0_USERCTRL_SIG_COND_RESET_BIT 0
tyftyftyf	15:09f072efa71e	739
tyftyftyf	15:09f072efa71e	740	#define MPU60X0_PWR1_DEVICE_RESET_BIT 7
tyftyftyf	15:09f072efa71e	741	#define MPU60X0_PWR1_SLEEP_BIT 6
tyftyftyf	15:09f072efa71e	742	#define MPU60X0_PWR1_CYCLE_BIT 5
tyftyftyf	15:09f072efa71e	743	#define MPU60X0_PWR1_TEMP_DIS_BIT 3
tyftyftyf	15:09f072efa71e	744	#define MPU60X0_PWR1_CLKSEL_BIT 2
tyftyftyf	15:09f072efa71e	745	#define MPU60X0_PWR1_CLKSEL_LENGTH 3
tyftyftyf	15:09f072efa71e	746
tyftyftyf	15:09f072efa71e	747	#define MPU60X0_CLOCK_INTERNAL 0x00
tyftyftyf	15:09f072efa71e	748	#define MPU60X0_CLOCK_PLL_XGYRO 0x01
tyftyftyf	15:09f072efa71e	749	#define MPU60X0_CLOCK_PLL_YGYRO 0x02
tyftyftyf	15:09f072efa71e	750	#define MPU60X0_CLOCK_PLL_ZGYRO 0x03
tyftyftyf	15:09f072efa71e	751	#define MPU60X0_CLOCK_PLL_EXT32K 0x04
tyftyftyf	15:09f072efa71e	752	#define MPU60X0_CLOCK_PLL_EXT19M 0x05
tyftyftyf	15:09f072efa71e	753	#define MPU60X0_CLOCK_KEEP_RESET 0x07
tyftyftyf	15:09f072efa71e	754
tyftyftyf	15:09f072efa71e	755	#define MPU60X0_PWR2_LP_WAKE_CTRL_BIT 7
tyftyftyf	15:09f072efa71e	756	#define MPU60X0_PWR2_LP_WAKE_CTRL_LENGTH 2
tyftyftyf	15:09f072efa71e	757	#define MPU60X0_PWR2_STBY_XA_BIT 5
tyftyftyf	15:09f072efa71e	758	#define MPU60X0_PWR2_STBY_YA_BIT 4
tyftyftyf	15:09f072efa71e	759	#define MPU60X0_PWR2_STBY_ZA_BIT 3
tyftyftyf	15:09f072efa71e	760	#define MPU60X0_PWR2_STBY_XG_BIT 2
tyftyftyf	15:09f072efa71e	761	#define MPU60X0_PWR2_STBY_YG_BIT 1
tyftyftyf	15:09f072efa71e	762	#define MPU60X0_PWR2_STBY_ZG_BIT 0
tyftyftyf	15:09f072efa71e	763
tyftyftyf	15:09f072efa71e	764	#define MPU60X0_WAKE_FREQ_1P25 0x0
tyftyftyf	15:09f072efa71e	765	#define MPU60X0_WAKE_FREQ_2P5 0x1
tyftyftyf	15:09f072efa71e	766	#define MPU60X0_WAKE_FREQ_5 0x2
tyftyftyf	15:09f072efa71e	767	#define MPU60X0_WAKE_FREQ_10 0x3
tyftyftyf	15:09f072efa71e	768
tyftyftyf	15:09f072efa71e	769	#define MPU60X0_BANKSEL_PRFTCH_EN_BIT 6
tyftyftyf	15:09f072efa71e	770	#define MPU60X0_BANKSEL_CFG_USER_BANK_BIT 5
tyftyftyf	15:09f072efa71e	771	#define MPU60X0_BANKSEL_MEM_SEL_BIT 4
tyftyftyf	15:09f072efa71e	772	#define MPU60X0_BANKSEL_MEM_SEL_LENGTH 5
tyftyftyf	15:09f072efa71e	773
tyftyftyf	15:09f072efa71e	774	#define MPU60X0_WHO_AM_I_BIT 6
tyftyftyf	15:09f072efa71e	775	#define MPU60X0_WHO_AM_I_LENGTH 6
tyftyftyf	15:09f072efa71e	776
tyftyftyf	15:09f072efa71e	777	#define MPU60X0_DMP_MEMORY_BANKS 8
tyftyftyf	15:09f072efa71e	778	#define MPU60X0_DMP_MEMORY_BANK_SIZE 256
tyftyftyf	15:09f072efa71e	779	#define MPU60X0_DMP_MEMORY_CHUNK_SIZE 16
tyftyftyf	15:09f072efa71e	780
tyftyftyf	15:09f072efa71e	781
tyftyftyf	15:09f072efa71e	782	#define I2C_SLV0_EN 0x80
tyftyftyf	15:09f072efa71e	783	#define I2C_SLV4_EN 0x80
tyftyftyf	15:09f072efa71e	784	#define I2C_READ_FLAG 0x80
tyftyftyf	15:09f072efa71e	785	#define SEN_ENABLE 0x00
tyftyftyf	15:09f072efa71e	786	#define I2C_MST_EN 0x20
tyftyftyf	15:09f072efa71e	787	#define I2C_MST_CLK 0x0D
tyftyftyf	15:09f072efa71e	788	#define PWR_RESET 0x80
tyftyftyf	15:09f072efa71e	789
tyftyftyf	15:09f072efa71e	790	#define INT_DISABLE 0x00
tyftyftyf	15:09f072efa71e	791	#define INT_PULSE_50US 0x00
tyftyftyf	15:09f072efa71e	792	#define INT_RAW_RDY_EN 0x01
tyftyftyf	15:09f072efa71e	793
tyftyftyf	14:057ce8fa00ab	794	enum mpu9250_dlpf_bandwidth
tyftyftyf	14:057ce8fa00ab	795	{
tyftyftyf	14:057ce8fa00ab	796	DLPF_BANDWIDTH_184HZ,
tyftyftyf	14:057ce8fa00ab	797	DLPF_BANDWIDTH_92HZ,
tyftyftyf	14:057ce8fa00ab	798	DLPF_BANDWIDTH_41HZ,
tyftyftyf	14:057ce8fa00ab	799	DLPF_BANDWIDTH_20HZ,
tyftyftyf	14:057ce8fa00ab	800	DLPF_BANDWIDTH_10HZ,
tyftyftyf	14:057ce8fa00ab	801	DLPF_BANDWIDTH_5HZ
tyftyftyf	14:057ce8fa00ab	802	};
tyftyftyf	14:057ce8fa00ab	803
garfieldsg	0:662207e34fba	804	// note: DMP code memory blocks defined at end of header file
garfieldsg	0:662207e34fba	805
garfieldsg	0:662207e34fba	806	class MPU6050 {
garfieldsg	0:662207e34fba	807	private:
garfieldsg	0:662207e34fba	808	I2Cdev i2Cdev;
garfieldsg	0:662207e34fba	809	Serial debugSerial;
tyftyftyf	11:9549be34fa7f	810	bool sampling; // flag to indicate whether sampling ticker is running
tyftyftyf	11:9549be34fa7f	811
garfieldsg	0:662207e34fba	812	public:
garfieldsg	0:662207e34fba	813	MPU6050();
tyftyftyf	9:d879deb55ae1	814	MPU6050(MODI2C i2c);
garfieldsg	0:662207e34fba	815	MPU6050(uint8_t address);
tyftyftyf	9:d879deb55ae1	816
tyftyftyf	9:d879deb55ae1	817	void mpu_sample_func();
tyftyftyf	9:d879deb55ae1	818	volatile int16_t ax_cache, ay_cache, az_cache, gx_cache, gy_cache, gz_cache;
tyftyftyf	13:a74f2d622b54	819	#ifdef MPU9250
tyftyftyf	13:a74f2d622b54	820	volatile int16_t hx_cache, hy_cache, hz_cache;
tyftyftyf	13:a74f2d622b54	821	#endif
tyftyftyf	9:d879deb55ae1	822	Ticker mpu_sampling;
tyftyftyf	9:d879deb55ae1	823	char mpu_cmd;
tyftyftyf	13:a74f2d622b54	824	#ifdef MPU9250
tyftyftyf	13:a74f2d622b54	825	uint8_t mpu_buffer[21];
tyftyftyf	13:a74f2d622b54	826	#else
tyftyftyf	9:d879deb55ae1	827	uint8_t mpu_buffer[14];
tyftyftyf	13:a74f2d622b54	828	#endif
tyftyftyf	9:d879deb55ae1	829
tyftyftyf	9:d879deb55ae1	830	void start_sampling();
garfieldsg	0:662207e34fba	831
garfieldsg	0:662207e34fba	832	bool testConnection();
garfieldsg	0:662207e34fba	833
garfieldsg	0:662207e34fba	834	// AUX_VDDIO register
garfieldsg	0:662207e34fba	835	uint8_t getAuxVDDIOLevel();
garfieldsg	0:662207e34fba	836	void setAuxVDDIOLevel(uint8_t level);
garfieldsg	0:662207e34fba	837
garfieldsg	0:662207e34fba	838	// SMPLRT_DIV register
garfieldsg	0:662207e34fba	839	uint8_t getRate();
garfieldsg	0:662207e34fba	840	void setRate(uint8_t rate);
tyftyftyf	11:9549be34fa7f	841
tyftyftyf	11:9549be34fa7f	842	// turn sampling on or off
tyftyftyf	11:9549be34fa7f	843	void sample(bool sampling);
garfieldsg	0:662207e34fba	844
garfieldsg	0:662207e34fba	845	// CONFIG register
garfieldsg	0:662207e34fba	846	uint8_t getExternalFrameSync();
garfieldsg	0:662207e34fba	847	void setExternalFrameSync(uint8_t sync);
garfieldsg	0:662207e34fba	848	uint8_t getDLPFMode();
garfieldsg	0:662207e34fba	849	void setDLPFMode(uint8_t bandwidth);
garfieldsg	0:662207e34fba	850
garfieldsg	0:662207e34fba	851	// GYRO_CONFIG register
garfieldsg	0:662207e34fba	852	uint8_t getFullScaleGyroRange();
garfieldsg	0:662207e34fba	853	void setFullScaleGyroRange(uint8_t range);
garfieldsg	0:662207e34fba	854
garfieldsg	0:662207e34fba	855	// ACCEL_CONFIG register
garfieldsg	0:662207e34fba	856	bool getAccelXSelfTest();
garfieldsg	0:662207e34fba	857	void setAccelXSelfTest(bool enabled);
garfieldsg	0:662207e34fba	858	bool getAccelYSelfTest();
garfieldsg	0:662207e34fba	859	void setAccelYSelfTest(bool enabled);
garfieldsg	0:662207e34fba	860	bool getAccelZSelfTest();
garfieldsg	0:662207e34fba	861	void setAccelZSelfTest(bool enabled);
garfieldsg	0:662207e34fba	862	uint8_t getFullScaleAccelRange();
garfieldsg	0:662207e34fba	863	void setFullScaleAccelRange(uint8_t range);
garfieldsg	0:662207e34fba	864	uint8_t getDHPFMode();
garfieldsg	0:662207e34fba	865	void setDHPFMode(uint8_t mode);
garfieldsg	0:662207e34fba	866
garfieldsg	0:662207e34fba	867	// FF_THR register
garfieldsg	0:662207e34fba	868	uint8_t getFreefallDetectionThreshold();
garfieldsg	0:662207e34fba	869	void setFreefallDetectionThreshold(uint8_t threshold);
garfieldsg	0:662207e34fba	870
garfieldsg	0:662207e34fba	871	// FF_DUR register
garfieldsg	0:662207e34fba	872	uint8_t getFreefallDetectionDuration();
garfieldsg	0:662207e34fba	873	void setFreefallDetectionDuration(uint8_t duration);
garfieldsg	0:662207e34fba	874
garfieldsg	0:662207e34fba	875	// MOT_THR register
garfieldsg	0:662207e34fba	876	uint8_t getMotionDetectionThreshold();
garfieldsg	0:662207e34fba	877	void setMotionDetectionThreshold(uint8_t threshold);
garfieldsg	0:662207e34fba	878
garfieldsg	0:662207e34fba	879	// MOT_DUR register
garfieldsg	0:662207e34fba	880	uint8_t getMotionDetectionDuration();
garfieldsg	0:662207e34fba	881	void setMotionDetectionDuration(uint8_t duration);
garfieldsg	0:662207e34fba	882
garfieldsg	0:662207e34fba	883	// ZRMOT_THR register
garfieldsg	0:662207e34fba	884	uint8_t getZeroMotionDetectionThreshold();
garfieldsg	0:662207e34fba	885	void setZeroMotionDetectionThreshold(uint8_t threshold);
garfieldsg	0:662207e34fba	886
garfieldsg	0:662207e34fba	887	// ZRMOT_DUR register
garfieldsg	0:662207e34fba	888	uint8_t getZeroMotionDetectionDuration();
garfieldsg	0:662207e34fba	889	void setZeroMotionDetectionDuration(uint8_t duration);
garfieldsg	0:662207e34fba	890
garfieldsg	0:662207e34fba	891	// FIFO_EN register
garfieldsg	0:662207e34fba	892	bool getTempFIFOEnabled();
garfieldsg	0:662207e34fba	893	void setTempFIFOEnabled(bool enabled);
garfieldsg	0:662207e34fba	894	bool getXGyroFIFOEnabled();
garfieldsg	0:662207e34fba	895	void setXGyroFIFOEnabled(bool enabled);
garfieldsg	0:662207e34fba	896	bool getYGyroFIFOEnabled();
garfieldsg	0:662207e34fba	897	void setYGyroFIFOEnabled(bool enabled);
garfieldsg	0:662207e34fba	898	bool getZGyroFIFOEnabled();
garfieldsg	0:662207e34fba	899	void setZGyroFIFOEnabled(bool enabled);
garfieldsg	0:662207e34fba	900	bool getAccelFIFOEnabled();
garfieldsg	0:662207e34fba	901	void setAccelFIFOEnabled(bool enabled);
garfieldsg	0:662207e34fba	902	bool getSlave2FIFOEnabled();
garfieldsg	0:662207e34fba	903	void setSlave2FIFOEnabled(bool enabled);
garfieldsg	0:662207e34fba	904	bool getSlave1FIFOEnabled();
garfieldsg	0:662207e34fba	905	void setSlave1FIFOEnabled(bool enabled);
garfieldsg	0:662207e34fba	906	bool getSlave0FIFOEnabled();
garfieldsg	0:662207e34fba	907	void setSlave0FIFOEnabled(bool enabled);
garfieldsg	0:662207e34fba	908
garfieldsg	0:662207e34fba	909	// I2C_MST_CTRL register
garfieldsg	0:662207e34fba	910	bool getMultiMasterEnabled();
garfieldsg	0:662207e34fba	911	void setMultiMasterEnabled(bool enabled);
garfieldsg	0:662207e34fba	912	bool getWaitForExternalSensorEnabled();
garfieldsg	0:662207e34fba	913	void setWaitForExternalSensorEnabled(bool enabled);
garfieldsg	0:662207e34fba	914	bool getSlave3FIFOEnabled();
garfieldsg	0:662207e34fba	915	void setSlave3FIFOEnabled(bool enabled);
garfieldsg	0:662207e34fba	916	bool getSlaveReadWriteTransitionEnabled();
garfieldsg	0:662207e34fba	917	void setSlaveReadWriteTransitionEnabled(bool enabled);
garfieldsg	0:662207e34fba	918	uint8_t getMasterClockSpeed();
garfieldsg	0:662207e34fba	919	void setMasterClockSpeed(uint8_t speed);
garfieldsg	0:662207e34fba	920
garfieldsg	0:662207e34fba	921	// I2C_SLV* registers (Slave 0-3)
garfieldsg	0:662207e34fba	922	uint8_t getSlaveAddress(uint8_t num);
garfieldsg	0:662207e34fba	923	void setSlaveAddress(uint8_t num, uint8_t address);
garfieldsg	0:662207e34fba	924	uint8_t getSlaveRegister(uint8_t num);
garfieldsg	0:662207e34fba	925	void setSlaveRegister(uint8_t num, uint8_t reg);
garfieldsg	0:662207e34fba	926	bool getSlaveEnabled(uint8_t num);
garfieldsg	0:662207e34fba	927	void setSlaveEnabled(uint8_t num, bool enabled);
garfieldsg	0:662207e34fba	928	bool getSlaveWordByteSwap(uint8_t num);
garfieldsg	0:662207e34fba	929	void setSlaveWordByteSwap(uint8_t num, bool enabled);
garfieldsg	0:662207e34fba	930	bool getSlaveWriteMode(uint8_t num);
garfieldsg	0:662207e34fba	931	void setSlaveWriteMode(uint8_t num, bool mode);
garfieldsg	0:662207e34fba	932	bool getSlaveWordGroupOffset(uint8_t num);
garfieldsg	0:662207e34fba	933	void setSlaveWordGroupOffset(uint8_t num, bool enabled);
garfieldsg	0:662207e34fba	934	uint8_t getSlaveDataLength(uint8_t num);
garfieldsg	0:662207e34fba	935	void setSlaveDataLength(uint8_t num, uint8_t length);
garfieldsg	0:662207e34fba	936
garfieldsg	0:662207e34fba	937	// I2C_SLV* registers (Slave 4)
garfieldsg	0:662207e34fba	938	uint8_t getSlave4Address();
garfieldsg	0:662207e34fba	939	void setSlave4Address(uint8_t address);
garfieldsg	0:662207e34fba	940	uint8_t getSlave4Register();
garfieldsg	0:662207e34fba	941	void setSlave4Register(uint8_t reg);
garfieldsg	0:662207e34fba	942	void setSlave4OutputByte(uint8_t data);
garfieldsg	0:662207e34fba	943	bool getSlave4Enabled();
garfieldsg	0:662207e34fba	944	void setSlave4Enabled(bool enabled);
garfieldsg	0:662207e34fba	945	bool getSlave4InterruptEnabled();
garfieldsg	0:662207e34fba	946	void setSlave4InterruptEnabled(bool enabled);
garfieldsg	0:662207e34fba	947	bool getSlave4WriteMode();
garfieldsg	0:662207e34fba	948	void setSlave4WriteMode(bool mode);
garfieldsg	0:662207e34fba	949	uint8_t getSlave4MasterDelay();
garfieldsg	0:662207e34fba	950	void setSlave4MasterDelay(uint8_t delay);
garfieldsg	0:662207e34fba	951	uint8_t getSlate4InputByte();
garfieldsg	0:662207e34fba	952
garfieldsg	0:662207e34fba	953	// I2C_MST_STATUS register
garfieldsg	0:662207e34fba	954	bool getPassthroughStatus();
garfieldsg	0:662207e34fba	955	bool getSlave4IsDone();
garfieldsg	0:662207e34fba	956	bool getLostArbitration();
garfieldsg	0:662207e34fba	957	bool getSlave4Nack();
garfieldsg	0:662207e34fba	958	bool getSlave3Nack();
garfieldsg	0:662207e34fba	959	bool getSlave2Nack();
garfieldsg	0:662207e34fba	960	bool getSlave1Nack();
garfieldsg	0:662207e34fba	961	bool getSlave0Nack();
garfieldsg	0:662207e34fba	962
garfieldsg	0:662207e34fba	963	// INT_PIN_CFG register
garfieldsg	0:662207e34fba	964	bool getInterruptMode();
garfieldsg	0:662207e34fba	965	void setInterruptMode(bool mode);
garfieldsg	0:662207e34fba	966	bool getInterruptDrive();
garfieldsg	0:662207e34fba	967	void setInterruptDrive(bool drive);
garfieldsg	0:662207e34fba	968	bool getInterruptLatch();
garfieldsg	0:662207e34fba	969	void setInterruptLatch(bool latch);
garfieldsg	0:662207e34fba	970	bool getInterruptLatchClear();
garfieldsg	0:662207e34fba	971	void setInterruptLatchClear(bool clear);
garfieldsg	0:662207e34fba	972	bool getFSyncInterruptLevel();
garfieldsg	0:662207e34fba	973	void setFSyncInterruptLevel(bool level);
garfieldsg	0:662207e34fba	974	bool getFSyncInterruptEnabled();
garfieldsg	0:662207e34fba	975	void setFSyncInterruptEnabled(bool enabled);
garfieldsg	0:662207e34fba	976	bool getI2CBypassEnabled();
garfieldsg	0:662207e34fba	977	void setI2CBypassEnabled(bool enabled);
garfieldsg	0:662207e34fba	978	bool getClockOutputEnabled();
garfieldsg	0:662207e34fba	979	void setClockOutputEnabled(bool enabled);
garfieldsg	0:662207e34fba	980
garfieldsg	0:662207e34fba	981	// INT_ENABLE register
garfieldsg	0:662207e34fba	982	uint8_t getIntEnabled();
garfieldsg	0:662207e34fba	983	void setIntEnabled(uint8_t enabled);
garfieldsg	0:662207e34fba	984	bool getIntFreefallEnabled();
garfieldsg	0:662207e34fba	985	void setIntFreefallEnabled(bool enabled);
garfieldsg	0:662207e34fba	986	bool getIntMotionEnabled();
garfieldsg	0:662207e34fba	987	void setIntMotionEnabled(bool enabled);
garfieldsg	0:662207e34fba	988	bool getIntZeroMotionEnabled();
garfieldsg	0:662207e34fba	989	void setIntZeroMotionEnabled(bool enabled);
garfieldsg	0:662207e34fba	990	bool getIntFIFOBufferOverflowEnabled();
garfieldsg	0:662207e34fba	991	void setIntFIFOBufferOverflowEnabled(bool enabled);
garfieldsg	0:662207e34fba	992	bool getIntI2CMasterEnabled();
garfieldsg	0:662207e34fba	993	void setIntI2CMasterEnabled(bool enabled);
garfieldsg	0:662207e34fba	994	bool getIntDataReadyEnabled();
garfieldsg	0:662207e34fba	995	void setIntDataReadyEnabled(bool enabled);
garfieldsg	0:662207e34fba	996
garfieldsg	0:662207e34fba	997	// INT_STATUS register
garfieldsg	0:662207e34fba	998	uint8_t getIntStatus();
garfieldsg	0:662207e34fba	999	bool getIntFreefallStatus();
garfieldsg	0:662207e34fba	1000	bool getIntMotionStatus();
garfieldsg	0:662207e34fba	1001	bool getIntZeroMotionStatus();
garfieldsg	0:662207e34fba	1002	bool getIntFIFOBufferOverflowStatus();
garfieldsg	0:662207e34fba	1003	bool getIntI2CMasterStatus();
garfieldsg	0:662207e34fba	1004	bool getIntDataReadyStatus();
garfieldsg	0:662207e34fba	1005
garfieldsg	0:662207e34fba	1006	// ACCEL_OUT_ registers
garfieldsg	0:662207e34fba	1007	void getMotion9(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz, int16_t* mx, int16_t* my, int16_t* mz);
garfieldsg	0:662207e34fba	1008	void getMotion6(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz);
garfieldsg	0:662207e34fba	1009	void getAcceleration(int16_t* x, int16_t* y, int16_t* z);
garfieldsg	0:662207e34fba	1010	int16_t getAccelerationX();
garfieldsg	0:662207e34fba	1011	int16_t getAccelerationY();
garfieldsg	0:662207e34fba	1012	int16_t getAccelerationZ();
garfieldsg	0:662207e34fba	1013
garfieldsg	0:662207e34fba	1014	// TEMP_OUT_* registers
garfieldsg	0:662207e34fba	1015	int16_t getTemperature();
garfieldsg	0:662207e34fba	1016
garfieldsg	0:662207e34fba	1017	// GYRO_OUT_ registers
garfieldsg	0:662207e34fba	1018	void getRotation(int16_t* x, int16_t* y, int16_t* z);
garfieldsg	0:662207e34fba	1019	int16_t getRotationX();
garfieldsg	0:662207e34fba	1020	int16_t getRotationY();
garfieldsg	0:662207e34fba	1021	int16_t getRotationZ();
garfieldsg	0:662207e34fba	1022
garfieldsg	0:662207e34fba	1023	// EXT_SENS_DATA_* registers
garfieldsg	0:662207e34fba	1024	uint8_t getExternalSensorByte(int position);
garfieldsg	0:662207e34fba	1025	uint16_t getExternalSensorWord(int position);
garfieldsg	0:662207e34fba	1026	uint32_t getExternalSensorDWord(int position);
garfieldsg	0:662207e34fba	1027
garfieldsg	0:662207e34fba	1028	// MOT_DETECT_STATUS register
garfieldsg	0:662207e34fba	1029	bool getXNegMotionDetected();
garfieldsg	0:662207e34fba	1030	bool getXPosMotionDetected();
garfieldsg	0:662207e34fba	1031	bool getYNegMotionDetected();
garfieldsg	0:662207e34fba	1032	bool getYPosMotionDetected();
garfieldsg	0:662207e34fba	1033	bool getZNegMotionDetected();
garfieldsg	0:662207e34fba	1034	bool getZPosMotionDetected();
garfieldsg	0:662207e34fba	1035	bool getZeroMotionDetected();
garfieldsg	0:662207e34fba	1036
garfieldsg	0:662207e34fba	1037	// I2C_SLV*_DO register
garfieldsg	0:662207e34fba	1038	void setSlaveOutputByte(uint8_t num, uint8_t data);
garfieldsg	0:662207e34fba	1039
garfieldsg	0:662207e34fba	1040	// I2C_MST_DELAY_CTRL register
garfieldsg	0:662207e34fba	1041	bool getExternalShadowDelayEnabled();
garfieldsg	0:662207e34fba	1042	void setExternalShadowDelayEnabled(bool enabled);
garfieldsg	0:662207e34fba	1043	bool getSlaveDelayEnabled(uint8_t num);
garfieldsg	0:662207e34fba	1044	void setSlaveDelayEnabled(uint8_t num, bool enabled);
garfieldsg	0:662207e34fba	1045
garfieldsg	0:662207e34fba	1046	// SIGNAL_PATH_RESET register
garfieldsg	0:662207e34fba	1047	void resetGyroscopePath();
garfieldsg	0:662207e34fba	1048	void resetAccelerometerPath();
garfieldsg	0:662207e34fba	1049	void resetTemperaturePath();
garfieldsg	0:662207e34fba	1050
garfieldsg	0:662207e34fba	1051	// MOT_DETECT_CTRL register
garfieldsg	0:662207e34fba	1052	uint8_t getAccelerometerPowerOnDelay();
garfieldsg	0:662207e34fba	1053	void setAccelerometerPowerOnDelay(uint8_t delay);
garfieldsg	0:662207e34fba	1054	uint8_t getFreefallDetectionCounterDecrement();
garfieldsg	0:662207e34fba	1055	void setFreefallDetectionCounterDecrement(uint8_t decrement);
garfieldsg	0:662207e34fba	1056	uint8_t getMotionDetectionCounterDecrement();
garfieldsg	0:662207e34fba	1057	void setMotionDetectionCounterDecrement(uint8_t decrement);
garfieldsg	0:662207e34fba	1058
garfieldsg	0:662207e34fba	1059	// USER_CTRL register
garfieldsg	0:662207e34fba	1060	bool getFIFOEnabled();
garfieldsg	0:662207e34fba	1061	void setFIFOEnabled(bool enabled);
garfieldsg	0:662207e34fba	1062	bool getI2CMasterModeEnabled();
garfieldsg	0:662207e34fba	1063	void setI2CMasterModeEnabled(bool enabled);
garfieldsg	0:662207e34fba	1064	void switchSPIEnabled(bool enabled);
garfieldsg	0:662207e34fba	1065	void resetFIFO();
garfieldsg	0:662207e34fba	1066	void resetI2CMaster();
garfieldsg	0:662207e34fba	1067	void resetSensors();
garfieldsg	0:662207e34fba	1068
garfieldsg	0:662207e34fba	1069	// PWR_MGMT_1 register
garfieldsg	0:662207e34fba	1070	void reset();
garfieldsg	0:662207e34fba	1071	bool getSleepEnabled();
garfieldsg	0:662207e34fba	1072	void setSleepEnabled(bool enabled);
garfieldsg	0:662207e34fba	1073	bool getWakeCycleEnabled();
garfieldsg	0:662207e34fba	1074	void setWakeCycleEnabled(bool enabled);
garfieldsg	0:662207e34fba	1075	bool getTempSensorEnabled();
garfieldsg	0:662207e34fba	1076	void setTempSensorEnabled(bool enabled);
garfieldsg	0:662207e34fba	1077	uint8_t getClockSource();
garfieldsg	0:662207e34fba	1078	void setClockSource(uint8_t source);
garfieldsg	0:662207e34fba	1079
garfieldsg	0:662207e34fba	1080	// PWR_MGMT_2 register
garfieldsg	0:662207e34fba	1081	uint8_t getWakeFrequency();
garfieldsg	0:662207e34fba	1082	void setWakeFrequency(uint8_t frequency);
garfieldsg	0:662207e34fba	1083	bool getStandbyXAccelEnabled();
garfieldsg	0:662207e34fba	1084	void setStandbyXAccelEnabled(bool enabled);
garfieldsg	0:662207e34fba	1085	bool getStandbyYAccelEnabled();
garfieldsg	0:662207e34fba	1086	void setStandbyYAccelEnabled(bool enabled);
garfieldsg	0:662207e34fba	1087	bool getStandbyZAccelEnabled();
garfieldsg	0:662207e34fba	1088	void setStandbyZAccelEnabled(bool enabled);
garfieldsg	0:662207e34fba	1089	bool getStandbyXGyroEnabled();
garfieldsg	0:662207e34fba	1090	void setStandbyXGyroEnabled(bool enabled);
garfieldsg	0:662207e34fba	1091	bool getStandbyYGyroEnabled();
garfieldsg	0:662207e34fba	1092	void setStandbyYGyroEnabled(bool enabled);
garfieldsg	0:662207e34fba	1093	bool getStandbyZGyroEnabled();
garfieldsg	0:662207e34fba	1094	void setStandbyZGyroEnabled(bool enabled);
garfieldsg	0:662207e34fba	1095
garfieldsg	0:662207e34fba	1096	// FIFO_COUNT_* registers
garfieldsg	0:662207e34fba	1097	uint16_t getFIFOCount();
garfieldsg	0:662207e34fba	1098
garfieldsg	0:662207e34fba	1099	// FIFO_R_W register
garfieldsg	0:662207e34fba	1100	uint8_t getFIFOByte();
garfieldsg	0:662207e34fba	1101	void setFIFOByte(uint8_t data);
garfieldsg	0:662207e34fba	1102	void getFIFOBytes(uint8_t *data, uint8_t length);
garfieldsg	0:662207e34fba	1103
garfieldsg	0:662207e34fba	1104	// WHO_AM_I register
garfieldsg	0:662207e34fba	1105	uint8_t getDeviceID();
garfieldsg	0:662207e34fba	1106	void setDeviceID(uint8_t id);
garfieldsg	0:662207e34fba	1107
garfieldsg	0:662207e34fba	1108	// ======== UNDOCUMENTED/DMP REGISTERS/METHODS ========
garfieldsg	0:662207e34fba	1109
garfieldsg	0:662207e34fba	1110	// XG_OFFS_TC register
garfieldsg	0:662207e34fba	1111	uint8_t getOTPBankValid();
garfieldsg	0:662207e34fba	1112	void setOTPBankValid(bool enabled);
garfieldsg	0:662207e34fba	1113	int8_t getXGyroOffset();
garfieldsg	0:662207e34fba	1114	void setXGyroOffset(int8_t offset);
garfieldsg	0:662207e34fba	1115
garfieldsg	0:662207e34fba	1116	// YG_OFFS_TC register
garfieldsg	0:662207e34fba	1117	int8_t getYGyroOffset();
garfieldsg	0:662207e34fba	1118	void setYGyroOffset(int8_t offset);
garfieldsg	0:662207e34fba	1119
garfieldsg	0:662207e34fba	1120	// ZG_OFFS_TC register
garfieldsg	0:662207e34fba	1121	int8_t getZGyroOffset();
garfieldsg	0:662207e34fba	1122	void setZGyroOffset(int8_t offset);
garfieldsg	0:662207e34fba	1123
garfieldsg	0:662207e34fba	1124	// X_FINE_GAIN register
garfieldsg	0:662207e34fba	1125	int8_t getXFineGain();
garfieldsg	0:662207e34fba	1126	void setXFineGain(int8_t gain);
garfieldsg	0:662207e34fba	1127
garfieldsg	0:662207e34fba	1128	// Y_FINE_GAIN register
garfieldsg	0:662207e34fba	1129	int8_t getYFineGain();
garfieldsg	0:662207e34fba	1130	void setYFineGain(int8_t gain);
garfieldsg	0:662207e34fba	1131
garfieldsg	0:662207e34fba	1132	// Z_FINE_GAIN register
garfieldsg	0:662207e34fba	1133	int8_t getZFineGain();
garfieldsg	0:662207e34fba	1134	void setZFineGain(int8_t gain);
garfieldsg	0:662207e34fba	1135
garfieldsg	0:662207e34fba	1136	// XA_OFFS_* registers
garfieldsg	0:662207e34fba	1137	int16_t getXAccelOffset();
garfieldsg	0:662207e34fba	1138	void setXAccelOffset(int16_t offset);
garfieldsg	0:662207e34fba	1139
garfieldsg	0:662207e34fba	1140	// YA_OFFS_* register
garfieldsg	0:662207e34fba	1141	int16_t getYAccelOffset();
garfieldsg	0:662207e34fba	1142	void setYAccelOffset(int16_t offset);
garfieldsg	0:662207e34fba	1143
garfieldsg	0:662207e34fba	1144	// ZA_OFFS_* register
garfieldsg	0:662207e34fba	1145	int16_t getZAccelOffset();
garfieldsg	0:662207e34fba	1146	void setZAccelOffset(int16_t offset);
garfieldsg	0:662207e34fba	1147
garfieldsg	0:662207e34fba	1148	// XG_OFFS_USR* registers
garfieldsg	0:662207e34fba	1149	int16_t getXGyroOffsetUser();
garfieldsg	0:662207e34fba	1150	void setXGyroOffsetUser(int16_t offset);
garfieldsg	0:662207e34fba	1151
garfieldsg	0:662207e34fba	1152	// YG_OFFS_USR* register
garfieldsg	0:662207e34fba	1153	int16_t getYGyroOffsetUser();
garfieldsg	0:662207e34fba	1154	void setYGyroOffsetUser(int16_t offset);
garfieldsg	0:662207e34fba	1155
garfieldsg	0:662207e34fba	1156	// ZG_OFFS_USR* register
garfieldsg	0:662207e34fba	1157	int16_t getZGyroOffsetUser();
garfieldsg	0:662207e34fba	1158	void setZGyroOffsetUser(int16_t offset);
garfieldsg	0:662207e34fba	1159
garfieldsg	0:662207e34fba	1160	// INT_ENABLE register (DMP functions)
garfieldsg	0:662207e34fba	1161	bool getIntPLLReadyEnabled();
garfieldsg	0:662207e34fba	1162	void setIntPLLReadyEnabled(bool enabled);
garfieldsg	0:662207e34fba	1163	bool getIntDMPEnabled();
garfieldsg	0:662207e34fba	1164	void setIntDMPEnabled(bool enabled);
garfieldsg	0:662207e34fba	1165
garfieldsg	0:662207e34fba	1166	// DMP_INT_STATUS
garfieldsg	0:662207e34fba	1167	bool getDMPInt5Status();
garfieldsg	0:662207e34fba	1168	bool getDMPInt4Status();
garfieldsg	0:662207e34fba	1169	bool getDMPInt3Status();
garfieldsg	0:662207e34fba	1170	bool getDMPInt2Status();
garfieldsg	0:662207e34fba	1171	bool getDMPInt1Status();
garfieldsg	0:662207e34fba	1172	bool getDMPInt0Status();
garfieldsg	0:662207e34fba	1173
garfieldsg	0:662207e34fba	1174	// INT_STATUS register (DMP functions)
garfieldsg	0:662207e34fba	1175	bool getIntPLLReadyStatus();
garfieldsg	0:662207e34fba	1176	bool getIntDMPStatus();
garfieldsg	0:662207e34fba	1177
garfieldsg	0:662207e34fba	1178	// USER_CTRL register (DMP functions)
garfieldsg	0:662207e34fba	1179	bool getDMPEnabled();
garfieldsg	0:662207e34fba	1180	void setDMPEnabled(bool enabled);
garfieldsg	0:662207e34fba	1181	void resetDMP();
garfieldsg	0:662207e34fba	1182
garfieldsg	0:662207e34fba	1183	// BANK_SEL register
garfieldsg	0:662207e34fba	1184	void setMemoryBank(uint8_t bank, bool prefetchEnabled=false, bool userBank=false);
garfieldsg	0:662207e34fba	1185
garfieldsg	0:662207e34fba	1186	// MEM_START_ADDR register
garfieldsg	0:662207e34fba	1187	void setMemoryStartAddress(uint8_t address);
garfieldsg	0:662207e34fba	1188
garfieldsg	0:662207e34fba	1189	// MEM_R_W register
garfieldsg	0:662207e34fba	1190	uint8_t readMemoryByte();
garfieldsg	0:662207e34fba	1191	void writeMemoryByte(uint8_t data);
garfieldsg	0:662207e34fba	1192	void readMemoryBlock(uint8_t *data, uint16_t dataSize, uint8_t bank=0, uint8_t address=0);
garfieldsg	0:662207e34fba	1193	bool writeMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank=0, uint8_t address=0, bool verify=true, bool useProgMem=false);
garfieldsg	0:662207e34fba	1194	bool writeProgMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank=0, uint8_t address=0, bool verify=true);
garfieldsg	0:662207e34fba	1195
garfieldsg	0:662207e34fba	1196	bool writeDMPConfigurationSet(const uint8_t *data, uint16_t dataSize, bool useProgMem=false);
garfieldsg	0:662207e34fba	1197	bool writeProgDMPConfigurationSet(const uint8_t *data, uint16_t dataSize);
garfieldsg	0:662207e34fba	1198
garfieldsg	0:662207e34fba	1199	// DMP_CFG_1 register
garfieldsg	0:662207e34fba	1200	uint8_t getDMPConfig1();
garfieldsg	0:662207e34fba	1201	void setDMPConfig1(uint8_t config);
garfieldsg	0:662207e34fba	1202
garfieldsg	0:662207e34fba	1203	// DMP_CFG_2 register
garfieldsg	0:662207e34fba	1204	uint8_t getDMPConfig2();
garfieldsg	0:662207e34fba	1205	void setDMPConfig2(uint8_t config);
tyftyftyf	12:e32a6beb0a41	1206
tyftyftyf	12:e32a6beb0a41	1207	void initialize();
tyftyftyf	13:a74f2d622b54	1208
tyftyftyf	13:a74f2d622b54	1209	#ifdef MPU9250
tyftyftyf	12:e32a6beb0a41	1210	void initialize9250();
tyftyftyf	12:e32a6beb0a41	1211	void initialize9250MasterMode();
tyftyftyf	12:e32a6beb0a41	1212	void get9250Motion9Counts(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz, int16_t* hx, int16_t* hy, int16_t* hz);
tyftyftyf	12:e32a6beb0a41	1213	void get9250Motion9(float* ax, float* ay, float* az, float* gx, float* gy, float* gz, float* hx, float* hy, float* hz);
tyftyftyf	12:e32a6beb0a41	1214	void get9250AccelCounts(int16_t* ax, int16_t* ay, int16_t* az);
tyftyftyf	12:e32a6beb0a41	1215	void get9250GyroCounts(int16_t* gx, int16_t* gy, int16_t* gz);
tyftyftyf	12:e32a6beb0a41	1216	void get9250MagCounts(int16_t* hx, int16_t* hy, int16_t* hz);
tyftyftyf	12:e32a6beb0a41	1217	void get9250TempCounts(int16_t* t);
tyftyftyf	12:e32a6beb0a41	1218	int setFilt9250(mpu9250_dlpf_bandwidth bandwidth, uint8_t SRD);
tyftyftyf	12:e32a6beb0a41	1219	int enableInt9250(bool enable);
tyftyftyf	12:e32a6beb0a41	1220	void readAKRegisters(uint8_t subAddress, uint8_t count, uint8_t* dest);
tyftyftyf	12:e32a6beb0a41	1221	bool writeAKRegister(uint8_t subAddress, uint8_t data);
tyftyftyf	12:e32a6beb0a41	1222	bool writeRegister(uint8_t subAddress, uint8_t data);
tyftyftyf	12:e32a6beb0a41	1223	void readRegister(uint8_t subAddress, uint8_t count, uint8_t* dest);
tyftyftyf	15:09f072efa71e	1224	void setStandbyDisable();
tyftyftyf	13:a74f2d622b54	1225	#endif
garfieldsg	0:662207e34fba	1226
garfieldsg	0:662207e34fba	1227	// special methods for MotionApps 2.0 implementation
garfieldsg	0:662207e34fba	1228	#ifdef MPU6050_INCLUDE_DMP_MOTIONAPPS20
garfieldsg	0:662207e34fba	1229	uint8_t *dmpPacketBuffer;
garfieldsg	0:662207e34fba	1230	uint16_t dmpPacketSize;
garfieldsg	0:662207e34fba	1231
garfieldsg	0:662207e34fba	1232	uint8_t dmpInitialize();
garfieldsg	0:662207e34fba	1233	bool dmpPacketAvailable();
garfieldsg	0:662207e34fba	1234
garfieldsg	0:662207e34fba	1235	uint8_t dmpSetFIFORate(uint8_t fifoRate);
garfieldsg	0:662207e34fba	1236	uint8_t dmpGetFIFORate();
garfieldsg	0:662207e34fba	1237	uint8_t dmpGetSampleStepSizeMS();
garfieldsg	0:662207e34fba	1238	uint8_t dmpGetSampleFrequency();
garfieldsg	0:662207e34fba	1239	int32_t dmpDecodeTemperature(int8_t tempReg);
garfieldsg	0:662207e34fba	1240
garfieldsg	0:662207e34fba	1241	// Register callbacks after a packet of FIFO data is processed
garfieldsg	0:662207e34fba	1242	//uint8_t dmpRegisterFIFORateProcess(inv_obj_func func, int16_t priority);
garfieldsg	0:662207e34fba	1243	//uint8_t dmpUnregisterFIFORateProcess(inv_obj_func func);
garfieldsg	0:662207e34fba	1244	uint8_t dmpRunFIFORateProcesses();
garfieldsg	0:662207e34fba	1245
garfieldsg	0:662207e34fba	1246	// Setup FIFO for various output
garfieldsg	0:662207e34fba	1247	uint8_t dmpSendQuaternion(uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1248	uint8_t dmpSendGyro(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1249	uint8_t dmpSendAccel(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1250	uint8_t dmpSendLinearAccel(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1251	uint8_t dmpSendLinearAccelInWorld(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1252	uint8_t dmpSendControlData(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1253	uint8_t dmpSendSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1254	uint8_t dmpSendExternalSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1255	uint8_t dmpSendGravity(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1256	uint8_t dmpSendPacketNumber(uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1257	uint8_t dmpSendQuantizedAccel(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1258	uint8_t dmpSendEIS(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1259
garfieldsg	0:662207e34fba	1260	// Get Fixed Point data from FIFO
garfieldsg	0:662207e34fba	1261	uint8_t dmpGetAccel(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1262	uint8_t dmpGetAccel(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1263	uint8_t dmpGetAccel(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1264	uint8_t dmpGetQuaternion(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1265	uint8_t dmpGetQuaternion(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1266	uint8_t dmpGetQuaternion(Quaternion q, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1267	uint8_t dmpGet6AxisQuaternion(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1268	uint8_t dmpGet6AxisQuaternion(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1269	uint8_t dmpGet6AxisQuaternion(Quaternion q, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1270	uint8_t dmpGetRelativeQuaternion(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1271	uint8_t dmpGetRelativeQuaternion(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1272	uint8_t dmpGetRelativeQuaternion(Quaternion data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1273	uint8_t dmpGetGyro(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1274	uint8_t dmpGetGyro(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1275	uint8_t dmpGetGyro(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1276	uint8_t dmpSetLinearAccelFilterCoefficient(float coef);
garfieldsg	0:662207e34fba	1277	uint8_t dmpGetLinearAccel(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1278	uint8_t dmpGetLinearAccel(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1279	uint8_t dmpGetLinearAccel(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1280	uint8_t dmpGetLinearAccel(VectorInt16 v, VectorInt16 vRaw, VectorFloat *gravity);
garfieldsg	0:662207e34fba	1281	uint8_t dmpGetLinearAccelInWorld(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1282	uint8_t dmpGetLinearAccelInWorld(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1283	uint8_t dmpGetLinearAccelInWorld(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1284	uint8_t dmpGetLinearAccelInWorld(VectorInt16 v, VectorInt16 vReal, Quaternion *q);
garfieldsg	0:662207e34fba	1285	uint8_t dmpGetGyroAndAccelSensor(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1286	uint8_t dmpGetGyroAndAccelSensor(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1287	uint8_t dmpGetGyroAndAccelSensor(VectorInt16 g, VectorInt16 a, const uint8_t* packet=0);
garfieldsg	0:662207e34fba	1288	uint8_t dmpGetGyroSensor(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1289	uint8_t dmpGetGyroSensor(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1290	uint8_t dmpGetGyroSensor(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1291	uint8_t dmpGetControlData(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1292	uint8_t dmpGetTemperature(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1293	uint8_t dmpGetGravity(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1294	uint8_t dmpGetGravity(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1295	uint8_t dmpGetGravity(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1296	uint8_t dmpGetGravity(VectorFloat v, Quaternion q);
garfieldsg	0:662207e34fba	1297	uint8_t dmpGetUnquantizedAccel(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1298	uint8_t dmpGetUnquantizedAccel(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1299	uint8_t dmpGetUnquantizedAccel(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1300	uint8_t dmpGetQuantizedAccel(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1301	uint8_t dmpGetQuantizedAccel(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1302	uint8_t dmpGetQuantizedAccel(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1303	uint8_t dmpGetExternalSensorData(int32_t data, uint16_t size, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1304	uint8_t dmpGetEIS(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1305
garfieldsg	0:662207e34fba	1306	uint8_t dmpGetEuler(float data, Quaternion q);
garfieldsg	0:662207e34fba	1307	uint8_t dmpGetYawPitchRoll(float data, Quaternion q, VectorFloat *gravity);
garfieldsg	0:662207e34fba	1308
garfieldsg	0:662207e34fba	1309	// Get Floating Point data from FIFO
garfieldsg	0:662207e34fba	1310	uint8_t dmpGetAccelFloat(float data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1311	uint8_t dmpGetQuaternionFloat(float data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1312
garfieldsg	0:662207e34fba	1313	uint8_t dmpProcessFIFOPacket(const unsigned char *dmpData);
garfieldsg	0:662207e34fba	1314	uint8_t dmpReadAndProcessFIFOPacket(uint8_t numPackets, uint8_t *processed=NULL);
garfieldsg	0:662207e34fba	1315
garfieldsg	0:662207e34fba	1316	uint8_t dmpSetFIFOProcessedCallback(void (*func) (void));
garfieldsg	0:662207e34fba	1317
garfieldsg	0:662207e34fba	1318	uint8_t dmpInitFIFOParam();
garfieldsg	0:662207e34fba	1319	uint8_t dmpCloseFIFO();
garfieldsg	0:662207e34fba	1320	uint8_t dmpSetGyroDataSource(uint8_t source);
garfieldsg	0:662207e34fba	1321	uint8_t dmpDecodeQuantizedAccel();
garfieldsg	0:662207e34fba	1322	uint32_t dmpGetGyroSumOfSquare();
garfieldsg	0:662207e34fba	1323	uint32_t dmpGetAccelSumOfSquare();
garfieldsg	0:662207e34fba	1324	void dmpOverrideQuaternion(long *q);
garfieldsg	0:662207e34fba	1325	uint16_t dmpGetFIFOPacketSize();
garfieldsg	0:662207e34fba	1326	#endif
garfieldsg	0:662207e34fba	1327
garfieldsg	0:662207e34fba	1328	// special methods for MotionApps 4.1 implementation
garfieldsg	0:662207e34fba	1329	#ifdef MPU6050_INCLUDE_DMP_MOTIONAPPS41
garfieldsg	0:662207e34fba	1330	uint8_t *dmpPacketBuffer;
garfieldsg	0:662207e34fba	1331	uint16_t dmpPacketSize;
garfieldsg	0:662207e34fba	1332
garfieldsg	0:662207e34fba	1333	uint8_t dmpInitialize();
garfieldsg	0:662207e34fba	1334	bool dmpPacketAvailable();
garfieldsg	0:662207e34fba	1335
garfieldsg	0:662207e34fba	1336	uint8_t dmpSetFIFORate(uint8_t fifoRate);
garfieldsg	0:662207e34fba	1337	uint8_t dmpGetFIFORate();
garfieldsg	0:662207e34fba	1338	uint8_t dmpGetSampleStepSizeMS();
garfieldsg	0:662207e34fba	1339	uint8_t dmpGetSampleFrequency();
garfieldsg	0:662207e34fba	1340	int32_t dmpDecodeTemperature(int8_t tempReg);
garfieldsg	0:662207e34fba	1341
garfieldsg	0:662207e34fba	1342	// Register callbacks after a packet of FIFO data is processed
garfieldsg	0:662207e34fba	1343	//uint8_t dmpRegisterFIFORateProcess(inv_obj_func func, int16_t priority);
garfieldsg	0:662207e34fba	1344	//uint8_t dmpUnregisterFIFORateProcess(inv_obj_func func);
garfieldsg	0:662207e34fba	1345	uint8_t dmpRunFIFORateProcesses();
garfieldsg	0:662207e34fba	1346
garfieldsg	0:662207e34fba	1347	// Setup FIFO for various output
garfieldsg	0:662207e34fba	1348	uint8_t dmpSendQuaternion(uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1349	uint8_t dmpSendGyro(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1350	uint8_t dmpSendAccel(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1351	uint8_t dmpSendLinearAccel(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1352	uint8_t dmpSendLinearAccelInWorld(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1353	uint8_t dmpSendControlData(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1354	uint8_t dmpSendSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1355	uint8_t dmpSendExternalSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1356	uint8_t dmpSendGravity(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1357	uint8_t dmpSendPacketNumber(uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1358	uint8_t dmpSendQuantizedAccel(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1359	uint8_t dmpSendEIS(uint_fast16_t elements, uint_fast16_t accuracy);
garfieldsg	0:662207e34fba	1360
garfieldsg	0:662207e34fba	1361	// Get Fixed Point data from FIFO
garfieldsg	0:662207e34fba	1362	uint8_t dmpGetAccel(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1363	uint8_t dmpGetAccel(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1364	uint8_t dmpGetAccel(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1365	uint8_t dmpGetQuaternion(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1366	uint8_t dmpGetQuaternion(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1367	uint8_t dmpGetQuaternion(Quaternion q, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1368	uint8_t dmpGet6AxisQuaternion(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1369	uint8_t dmpGet6AxisQuaternion(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1370	uint8_t dmpGet6AxisQuaternion(Quaternion q, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1371	uint8_t dmpGetRelativeQuaternion(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1372	uint8_t dmpGetRelativeQuaternion(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1373	uint8_t dmpGetRelativeQuaternion(Quaternion data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1374	uint8_t dmpGetGyro(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1375	uint8_t dmpGetGyro(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1376	uint8_t dmpGetGyro(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1377	uint8_t dmpGetMag(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1378	uint8_t dmpSetLinearAccelFilterCoefficient(float coef);
garfieldsg	0:662207e34fba	1379	uint8_t dmpGetLinearAccel(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1380	uint8_t dmpGetLinearAccel(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1381	uint8_t dmpGetLinearAccel(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1382	uint8_t dmpGetLinearAccel(VectorInt16 v, VectorInt16 vRaw, VectorFloat *gravity);
garfieldsg	0:662207e34fba	1383	uint8_t dmpGetLinearAccelInWorld(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1384	uint8_t dmpGetLinearAccelInWorld(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1385	uint8_t dmpGetLinearAccelInWorld(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1386	uint8_t dmpGetLinearAccelInWorld(VectorInt16 v, VectorInt16 vReal, Quaternion *q);
garfieldsg	0:662207e34fba	1387	uint8_t dmpGetGyroAndAccelSensor(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1388	uint8_t dmpGetGyroAndAccelSensor(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1389	uint8_t dmpGetGyroAndAccelSensor(VectorInt16 g, VectorInt16 a, const uint8_t* packet=0);
garfieldsg	0:662207e34fba	1390	uint8_t dmpGetGyroSensor(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1391	uint8_t dmpGetGyroSensor(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1392	uint8_t dmpGetGyroSensor(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1393	uint8_t dmpGetControlData(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1394	uint8_t dmpGetTemperature(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1395	uint8_t dmpGetGravity(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1396	uint8_t dmpGetGravity(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1397	uint8_t dmpGetGravity(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1398	uint8_t dmpGetGravity(VectorFloat v, Quaternion q);
garfieldsg	0:662207e34fba	1399	uint8_t dmpGetUnquantizedAccel(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1400	uint8_t dmpGetUnquantizedAccel(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1401	uint8_t dmpGetUnquantizedAccel(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1402	uint8_t dmpGetQuantizedAccel(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1403	uint8_t dmpGetQuantizedAccel(int16_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1404	uint8_t dmpGetQuantizedAccel(VectorInt16 v, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1405	uint8_t dmpGetExternalSensorData(int32_t data, uint16_t size, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1406	uint8_t dmpGetEIS(int32_t data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1407
garfieldsg	0:662207e34fba	1408	uint8_t dmpGetEuler(float data, Quaternion q);
garfieldsg	0:662207e34fba	1409	uint8_t dmpGetYawPitchRoll(float data, Quaternion q, VectorFloat *gravity);
garfieldsg	0:662207e34fba	1410
garfieldsg	0:662207e34fba	1411	// Get Floating Point data from FIFO
garfieldsg	0:662207e34fba	1412	uint8_t dmpGetAccelFloat(float data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1413	uint8_t dmpGetQuaternionFloat(float data, const uint8_t packet=0);
garfieldsg	0:662207e34fba	1414
garfieldsg	0:662207e34fba	1415	uint8_t dmpProcessFIFOPacket(const unsigned char *dmpData);
garfieldsg	0:662207e34fba	1416	uint8_t dmpReadAndProcessFIFOPacket(uint8_t numPackets, uint8_t *processed=NULL);
garfieldsg	0:662207e34fba	1417
garfieldsg	0:662207e34fba	1418	uint8_t dmpSetFIFOProcessedCallback(void (*func) (void));
garfieldsg	0:662207e34fba	1419
garfieldsg	0:662207e34fba	1420	uint8_t dmpInitFIFOParam();
garfieldsg	0:662207e34fba	1421	uint8_t dmpCloseFIFO();
garfieldsg	0:662207e34fba	1422	uint8_t dmpSetGyroDataSource(uint8_t source);
garfieldsg	0:662207e34fba	1423	uint8_t dmpDecodeQuantizedAccel();
garfieldsg	0:662207e34fba	1424	uint32_t dmpGetGyroSumOfSquare();
garfieldsg	0:662207e34fba	1425	uint32_t dmpGetAccelSumOfSquare();
garfieldsg	0:662207e34fba	1426	void dmpOverrideQuaternion(long *q);
garfieldsg	0:662207e34fba	1427	uint16_t dmpGetFIFOPacketSize();
garfieldsg	0:662207e34fba	1428	#endif
garfieldsg	0:662207e34fba	1429
garfieldsg	0:662207e34fba	1430	private:
garfieldsg	0:662207e34fba	1431	uint8_t devAddr;
tyftyftyf	13:a74f2d622b54	1432	#ifdef MPU9250
tyftyftyf	13:a74f2d622b54	1433	uint8_t buffer[21];
tyftyftyf	13:a74f2d622b54	1434	#else
garfieldsg	0:662207e34fba	1435	uint8_t buffer[14];
tyftyftyf	13:a74f2d622b54	1436	#endif
tyftyftyf	12:e32a6beb0a41	1437	uint8_t magDevAddr;
tyftyftyf	15:09f072efa71e	1438
tyftyftyf	15:09f072efa71e	1439	#ifdef MPU9250
tyftyftyf	15:09f072efa71e	1440	// transformation matrix
tyftyftyf	15:09f072efa71e	1441	/* transform the accel and gyro axes to match the magnetometer axes */
tyftyftyf	15:09f072efa71e	1442	int16_t tX[3];// = {0, 1, 0};
tyftyftyf	15:09f072efa71e	1443	int16_t tY[3];// = {1, 0, 0};
tyftyftyf	15:09f072efa71e	1444	int16_t tZ[3];// = {0, 0, 1}; //was -1 transformation is done within lib.
tyftyftyf	15:09f072efa71e	1445	#endif
garfieldsg	0:662207e34fba	1446	};
garfieldsg	0:662207e34fba	1447
garfieldsg	0:662207e34fba	1448	#endif /* _MPU6050_H_ */

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Type:	Library
Created:	28 Mar 2018
Imports:	7
Forks:	0
Commits:	23
Dependents:	1
Dependencies:	0
Followers:	2

MPU6050.h@15:09f072efa71e, 2018-03-28 (annotated)

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