Tsungta Wu / Mbed OS mbed_SPIS_multiByte_example_SOG

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Dependencies:   NNN50_WIFI_API

Fork of mbed_SPIS_multiByte_example_SOG by Sog Yang

spi_api_multibyte.h@7:0ea5460e0de3, 2017-06-21 (annotated)

Committer:
tsungta
Date:
Wed Jun 21 08:54:26 2017 +0000
Revision:
7:0ea5460e0de3
Parent:
5:6a1155885fc9 
Add TCP send function

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tsungta 0:b7415ae44dac 1
tsungta 0:b7415ae44dac 2 /** \addtogroup hal */
tsungta 0:b7415ae44dac 3 /** @{*/
tsungta 0:b7415ae44dac 4 /* mbed Microcontroller Library
tsungta 0:b7415ae44dac 5 * Copyright (c) 2006-2013 ARM Limited
tsungta 0:b7415ae44dac 6 *
tsungta 0:b7415ae44dac 7 * Licensed under the Apache License, Version 2.0 (the "License");
tsungta 0:b7415ae44dac 8 * you may not use this file except in compliance with the License.
tsungta 0:b7415ae44dac 9 * You may obtain a copy of the License at
tsungta 0:b7415ae44dac 10 *
tsungta 0:b7415ae44dac 11 * http://www.apache.org/licenses/LICENSE-2.0
tsungta 0:b7415ae44dac 12 *
tsungta 0:b7415ae44dac 13 * Unless required by applicable law or agreed to in writing, software
tsungta 0:b7415ae44dac 14 * distributed under the License is distributed on an "AS IS" BASIS,
tsungta 0:b7415ae44dac 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
tsungta 0:b7415ae44dac 16 * See the License for the specific language governing permissions and
tsungta 0:b7415ae44dac 17 * limitations under the License.
tsungta 0:b7415ae44dac 18 */
tsungta 0:b7415ae44dac 19 #ifndef MBED_SPI_API_MULTIBYTE_H
tsungta 0:b7415ae44dac 20 #define MBED_SPI_API_MULTIBYTE_H
tsungta 0:b7415ae44dac 21
tsungta 0:b7415ae44dac 22 #include "device.h"
tsungta 0:b7415ae44dac 23 #include "hal/dma_api.h"
tsungta 0:b7415ae44dac 24 #include "hal/buffer.h"
tsungta 0:b7415ae44dac 25
tsungta 0:b7415ae44dac 26 #if DEVICE_SPI
tsungta 0:b7415ae44dac 27
tsungta 0:b7415ae44dac 28 #define SPI_EVENT_ERROR (1 << 1)
tsungta 0:b7415ae44dac 29 #define SPI_EVENT_COMPLETE (1 << 2)
tsungta 0:b7415ae44dac 30 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
tsungta 0:b7415ae44dac 31 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
tsungta 0:b7415ae44dac 32
tsungta 0:b7415ae44dac 33 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
tsungta 0:b7415ae44dac 34
tsungta 0:b7415ae44dac 35 #define SPI_FILL_WORD (0xFFFF)
tsungta 0:b7415ae44dac 36
tsungta 0:b7415ae44dac 37 #if DEVICE_SPI_ASYNCH
tsungta 0:b7415ae44dac 38 /** Asynch SPI HAL structure
tsungta 0:b7415ae44dac 39 */
tsungta 0:b7415ae44dac 40 typedef struct {
tsungta 0:b7415ae44dac 41 struct spi_s spi; /**< Target specific SPI structure */
tsungta 0:b7415ae44dac 42 struct buffer_s tx_buff; /**< Tx buffer */
tsungta 0:b7415ae44dac 43 struct buffer_s rx_buff; /**< Rx buffer */
tsungta 0:b7415ae44dac 44 } spi_mb_t;
tsungta 0:b7415ae44dac 45
tsungta 0:b7415ae44dac 46 #else
tsungta 0:b7415ae44dac 47 /** Non-asynch SPI HAL structure
tsungta 0:b7415ae44dac 48 */
tsungta 0:b7415ae44dac 49 typedef struct spi_s spi_mb_t;
tsungta 0:b7415ae44dac 50
tsungta 0:b7415ae44dac 51 #endif
tsungta 0:b7415ae44dac 52
sog_yang 5:6a1155885fc9 53
tsungta 0:b7415ae44dac 54 #ifdef __cplusplus
tsungta 0:b7415ae44dac 55 extern "C" {
tsungta 0:b7415ae44dac 56 #endif
tsungta 0:b7415ae44dac 57
sog_yang 5:6a1155885fc9 58
tsungta 0:b7415ae44dac 59 /**
tsungta 0:b7415ae44dac 60 * \defgroup hal_GeneralSPI SPI Configuration Functions
tsungta 0:b7415ae44dac 61 * @{
tsungta 0:b7415ae44dac 62 */
tsungta 0:b7415ae44dac 63
tsungta 0:b7415ae44dac 64 /** Initialize the SPI peripheral
tsungta 0:b7415ae44dac 65 *
tsungta 0:b7415ae44dac 66 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
tsungta 0:b7415ae44dac 67 * @param[out] obj The SPI object to initialize
tsungta 0:b7415ae44dac 68 * @param[in] mosi The pin to use for MOSI
tsungta 0:b7415ae44dac 69 * @param[in] miso The pin to use for MISO
tsungta 0:b7415ae44dac 70 * @param[in] sclk The pin to use for SCLK
tsungta 0:b7415ae44dac 71 * @param[in] ssel The pin to use for SSEL
tsungta 0:b7415ae44dac 72 */
tsungta 0:b7415ae44dac 73 void spi_init_multibyte(spi_mb_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
tsungta 0:b7415ae44dac 74
tsungta 0:b7415ae44dac 75 /** Release a SPI object
tsungta 0:b7415ae44dac 76 *
tsungta 0:b7415ae44dac 77 * TODO: spi_free is currently unimplemented
tsungta 0:b7415ae44dac 78 * This will require reference counting at the C++ level to be safe
tsungta 0:b7415ae44dac 79 *
tsungta 0:b7415ae44dac 80 * Return the pins owned by the SPI object to their reset state
tsungta 0:b7415ae44dac 81 * Disable the SPI peripheral
tsungta 0:b7415ae44dac 82 * Disable the SPI clock
tsungta 0:b7415ae44dac 83 * @param[in] obj The SPI object to deinitialize
tsungta 0:b7415ae44dac 84 */
tsungta 0:b7415ae44dac 85 void spi_free_multibyte(spi_mb_t *obj);
tsungta 0:b7415ae44dac 86
tsungta 0:b7415ae44dac 87 /** Configure the SPI format
tsungta 0:b7415ae44dac 88 *
tsungta 0:b7415ae44dac 89 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
tsungta 0:b7415ae44dac 90 * The default bit order is MSB.
tsungta 0:b7415ae44dac 91 * @param[in,out] obj The SPI object to configure
tsungta 0:b7415ae44dac 92 * @param[in] bits The number of bits per frame
tsungta 0:b7415ae44dac 93 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
tsungta 0:b7415ae44dac 94 * @param[in] slave Zero for master mode or non-zero for slave mode
tsungta 0:b7415ae44dac 95 */
tsungta 0:b7415ae44dac 96 void spi_format_multibyte(spi_mb_t *obj, int bits, int mode, int slave);
tsungta 0:b7415ae44dac 97
tsungta 0:b7415ae44dac 98 /** Set the SPI baud rate
tsungta 0:b7415ae44dac 99 *
tsungta 0:b7415ae44dac 100 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
tsungta 0:b7415ae44dac 101 * Configures the SPI peripheral's baud rate
tsungta 0:b7415ae44dac 102 * @param[in,out] obj The SPI object to configure
tsungta 0:b7415ae44dac 103 * @param[in] hz The baud rate in Hz
tsungta 0:b7415ae44dac 104 */
tsungta 0:b7415ae44dac 105 void spi_frequency_multibyte(spi_mb_t *obj, int hz);
tsungta 0:b7415ae44dac 106
tsungta 0:b7415ae44dac 107 /**@}*/
tsungta 0:b7415ae44dac 108 /**
tsungta 0:b7415ae44dac 109 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
tsungta 0:b7415ae44dac 110 * @{
tsungta 0:b7415ae44dac 111 */
tsungta 0:b7415ae44dac 112
tsungta 0:b7415ae44dac 113 /** Write a byte out in master mode and receive a value
tsungta 0:b7415ae44dac 114 *
tsungta 0:b7415ae44dac 115 * @param[in] obj The SPI peripheral to use for sending
tsungta 0:b7415ae44dac 116 * @param[in] value The value to send
tsungta 0:b7415ae44dac 117 * @return Returns the value received during send
tsungta 0:b7415ae44dac 118 */
tsungta 0:b7415ae44dac 119 int spi_master_write_multibyte(spi_mb_t *obj, int value);
tsungta 0:b7415ae44dac 120
tsungta 0:b7415ae44dac 121 /** Check if a value is available to read
tsungta 0:b7415ae44dac 122 *
tsungta 0:b7415ae44dac 123 * @param[in] obj The SPI peripheral to check
tsungta 0:b7415ae44dac 124 * @return non-zero if a value is available
tsungta 0:b7415ae44dac 125 */
tsungta 2:c520d7c7739d 126 int spi_slave_receive_multibyte(spi_mb_t *obj, int bytes);
tsungta 0:b7415ae44dac 127
tsungta 0:b7415ae44dac 128 /** Get a received value out of the SPI receive buffer in slave mode
tsungta 0:b7415ae44dac 129 *
tsungta 0:b7415ae44dac 130 * Blocks until a value is available
tsungta 0:b7415ae44dac 131 * @param[in] obj The SPI peripheral to read
tsungta 0:b7415ae44dac 132 * @return The value received
tsungta 0:b7415ae44dac 133 */
tsungta 0:b7415ae44dac 134 int spi_slave_read_multibyte(spi_mb_t *obj);
tsungta 0:b7415ae44dac 135
sog_yang 5:6a1155885fc9 136 bool get_spi_slave_readable(spi_mb_t *obj);
sog_yang 5:6a1155885fc9 137
tsungta 0:b7415ae44dac 138 /** Write a value to the SPI peripheral in slave mode
tsungta 0:b7415ae44dac 139 *
tsungta 0:b7415ae44dac 140 * Blocks until the SPI peripheral can be written to
tsungta 0:b7415ae44dac 141 * @param[in] obj The SPI peripheral to write
tsungta 0:b7415ae44dac 142 * @param[in] value The value to write
tsungta 0:b7415ae44dac 143 */
tsungta 2:c520d7c7739d 144 void spi_slave_write_multibyte(spi_mb_t *obj, uint8_t *value, int bytes);
tsungta 0:b7415ae44dac 145
tsungta 0:b7415ae44dac 146 /** Checks if the specified SPI peripheral is in use
tsungta 0:b7415ae44dac 147 *
tsungta 0:b7415ae44dac 148 * @param[in] obj The SPI peripheral to check
tsungta 0:b7415ae44dac 149 * @return non-zero if the peripheral is currently transmitting
tsungta 0:b7415ae44dac 150 */
tsungta 0:b7415ae44dac 151 int spi_busy_multibyte(spi_mb_t *obj);
tsungta 0:b7415ae44dac 152
tsungta 0:b7415ae44dac 153 /** Get the module number
tsungta 0:b7415ae44dac 154 *
tsungta 0:b7415ae44dac 155 * @param[in] obj The SPI peripheral to check
tsungta 0:b7415ae44dac 156 * @return The module number
tsungta 0:b7415ae44dac 157 */
tsungta 0:b7415ae44dac 158 uint8_t spi_get_module_multibyte(spi_mb_t *obj);
tsungta 0:b7415ae44dac 159
tsungta 0:b7415ae44dac 160 /**@}*/
tsungta 0:b7415ae44dac 161
tsungta 0:b7415ae44dac 162 #if DEVICE_SPI_ASYNCH
tsungta 0:b7415ae44dac 163 /**
tsungta 0:b7415ae44dac 164 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
tsungta 0:b7415ae44dac 165 * @{
tsungta 0:b7415ae44dac 166 */
tsungta 0:b7415ae44dac 167
tsungta 0:b7415ae44dac 168 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
tsungta 0:b7415ae44dac 169 *
tsungta 0:b7415ae44dac 170 * @param[in] obj The SPI object that holds the transfer information
tsungta 0:b7415ae44dac 171 * @param[in] tx The transmit buffer
tsungta 0:b7415ae44dac 172 * @param[in] tx_length The number of bytes to transmit
tsungta 0:b7415ae44dac 173 * @param[in] rx The receive buffer
tsungta 0:b7415ae44dac 174 * @param[in] rx_length The number of bytes to receive
tsungta 0:b7415ae44dac 175 * @param[in] bit_width The bit width of buffer words
tsungta 0:b7415ae44dac 176 * @param[in] event The logical OR of events to be registered
tsungta 0:b7415ae44dac 177 * @param[in] handler SPI interrupt handler
tsungta 0:b7415ae44dac 178 * @param[in] hint A suggestion for how to use DMA with this transfer
tsungta 0:b7415ae44dac 179 */
tsungta 0:b7415ae44dac 180 void spi_master_transfer_multibyte(spi_mb_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
tsungta 0:b7415ae44dac 181
tsungta 0:b7415ae44dac 182 /** The asynchronous IRQ handler
tsungta 0:b7415ae44dac 183 *
tsungta 0:b7415ae44dac 184 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
tsungta 0:b7415ae44dac 185 * conditions, such as buffer overflows or transfer complete.
tsungta 0:b7415ae44dac 186 * @param[in] obj The SPI object that holds the transfer information
tsungta 0:b7415ae44dac 187 * @return Event flags if a transfer termination condition was met; otherwise 0.
tsungta 0:b7415ae44dac 188 */
tsungta 0:b7415ae44dac 189 uint32_t spi_irq_handler_asynch_multibyte(spi_mb_t *obj);
tsungta 0:b7415ae44dac 190
tsungta 0:b7415ae44dac 191 /** Attempts to determine if the SPI peripheral is already in use
tsungta 0:b7415ae44dac 192 *
tsungta 0:b7415ae44dac 193 * If a temporary DMA channel has been allocated, peripheral is in use.
tsungta 0:b7415ae44dac 194 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
tsungta 0:b7415ae44dac 195 * channel were allocated.
tsungta 0:b7415ae44dac 196 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
tsungta 0:b7415ae44dac 197 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
tsungta 0:b7415ae44dac 198 * there are any bytes in the FIFOs.
tsungta 0:b7415ae44dac 199 * @param[in] obj The SPI object to check for activity
tsungta 0:b7415ae44dac 200 * @return Non-zero if the SPI port is active or zero if it is not.
tsungta 0:b7415ae44dac 201 */
tsungta 0:b7415ae44dac 202 uint8_t spi_active_multibyte(spi_mb_t *obj);
tsungta 0:b7415ae44dac 203
tsungta 0:b7415ae44dac 204 /** Abort an SPI transfer
tsungta 0:b7415ae44dac 205 *
tsungta 0:b7415ae44dac 206 * @param obj The SPI peripheral to stop
tsungta 0:b7415ae44dac 207 */
tsungta 0:b7415ae44dac 208 void spi_abort_asynch_multibyte(spi_mb_t *obj);
tsungta 0:b7415ae44dac 209
tsungta 0:b7415ae44dac 210
sog_yang 5:6a1155885fc9 211
tsungta 0:b7415ae44dac 212 #endif
tsungta 0:b7415ae44dac 213
tsungta 0:b7415ae44dac 214 /**@}*/
tsungta 0:b7415ae44dac 215
tsungta 0:b7415ae44dac 216 #ifdef __cplusplus
tsungta 0:b7415ae44dac 217 }
tsungta 0:b7415ae44dac 218 #endif // __cplusplus
tsungta 0:b7415ae44dac 219
tsungta 0:b7415ae44dac 220 #endif // SPI_DEVICE
tsungta 0:b7415ae44dac 221
tsungta 0:b7415ae44dac 222 #endif // MBED_SPI_API_H
tsungta 0:b7415ae44dac 223
tsungta 0:b7415ae44dac 224 /** @}*/