This has been tested with 128D EVB SPI connection is shown as following D3 -> 128D EVB pin 82 D4 -> 128D EVB pin 12 D5 -> 128D EVB pin 39

Committer:
tsungta
Date:
Mon Nov 06 06:07:02 2017 +0000
Revision:
0:01dbd5035212
first commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tsungta 0:01dbd5035212 1 {
tsungta 0:01dbd5035212 2 "config": {
tsungta 0:01dbd5035212 3 "lf_clock_rc_calib_timer_interval": {
tsungta 0:01dbd5035212 4 "value": 16,
tsungta 0:01dbd5035212 5 "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL"
tsungta 0:01dbd5035212 6 },
tsungta 0:01dbd5035212 7 "lf_clock_rc_calib_mode_config": {
tsungta 0:01dbd5035212 8 "value": 0,
tsungta 0:01dbd5035212 9 "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG"
tsungta 0:01dbd5035212 10 },
tsungta 0:01dbd5035212 11 "uart_hwfc": {
tsungta 0:01dbd5035212 12 "help": "Value: 1 for enable, 0 for disable",
tsungta 0:01dbd5035212 13 "value": 0,
tsungta 0:01dbd5035212 14 "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
tsungta 0:01dbd5035212 15 }
tsungta 0:01dbd5035212 16 }
tsungta 0:01dbd5035212 17 }