Ken Todotani
Memory to Memory DMA demo from CMSIS example. This demo execute 1000 times of 32 word memory to memory DMA (copy), and also measures number of dummy loop execution during DMA cylcles. Line 56 of "DMA_M2M.c" can change DMA source. where; 1)static : source is SRAM 2)const : source is Flash ROM
Revision 0:692bf16d1455, committed 2010-11-14
- Comitter:
- todotani
- Date:
- Sun Nov 14 03:26:04 2010 +0000
- Commit message:
- 2010/11/14
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/CMSIS_Lib/lpc17xx_clkpwr.c Sun Nov 14 03:26:04 2010 +0000
@@ -0,0 +1,338 @@
+/***********************************************************************//**
+ * @file lpc17xx_clkpwr.c
+ * @brief Contains all functions support for Clock and Power Control
+ * firmware library on LPC17xx
+ * @version 3.0
+ * @date 18. June. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup CLKPWR
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_clkpwr.h"
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup CLKPWR_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief Set value of each Peripheral Clock Selection
+ * @param[in] ClkType Peripheral Clock Selection of each type,
+ * should be one of the following:
+ * - CLKPWR_PCLKSEL_WDT : WDT
+ - CLKPWR_PCLKSEL_TIMER0 : Timer 0
+ - CLKPWR_PCLKSEL_TIMER1 : Timer 1
+ - CLKPWR_PCLKSEL_UART0 : UART 0
+ - CLKPWR_PCLKSEL_UART1 : UART 1
+ - CLKPWR_PCLKSEL_PWM1 : PWM 1
+ - CLKPWR_PCLKSEL_I2C0 : I2C 0
+ - CLKPWR_PCLKSEL_SPI : SPI
+ - CLKPWR_PCLKSEL_SSP1 : SSP 1
+ - CLKPWR_PCLKSEL_DAC : DAC
+ - CLKPWR_PCLKSEL_ADC : ADC
+ - CLKPWR_PCLKSEL_CAN1 : CAN 1
+ - CLKPWR_PCLKSEL_CAN2 : CAN 2
+ - CLKPWR_PCLKSEL_ACF : ACF
+ - CLKPWR_PCLKSEL_QEI : QEI
+ - CLKPWR_PCLKSEL_PCB : PCB
+ - CLKPWR_PCLKSEL_I2C1 : I2C 1
+ - CLKPWR_PCLKSEL_SSP0 : SSP 0
+ - CLKPWR_PCLKSEL_TIMER2 : Timer 2
+ - CLKPWR_PCLKSEL_TIMER3 : Timer 3
+ - CLKPWR_PCLKSEL_UART2 : UART 2
+ - CLKPWR_PCLKSEL_UART3 : UART 3
+ - CLKPWR_PCLKSEL_I2C2 : I2C 2
+ - CLKPWR_PCLKSEL_I2S : I2S
+ - CLKPWR_PCLKSEL_RIT : RIT
+ - CLKPWR_PCLKSEL_SYSCON : SYSCON
+ - CLKPWR_PCLKSEL_MC : MC
+
+ * @param[in] DivVal Value of divider, should be:
+ * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
+ * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
+ * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
+ *
+ * @return none
+ **********************************************************************/
+void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
+{
+ uint32_t bitpos;
+
+ bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
+
+ /* PCLKSEL0 selected */
+ if (ClkType < 32)
+ {
+ /* Clear two bit at bit position */
+ LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
+
+ /* Set two selected bit */
+ LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
+ }
+ /* PCLKSEL1 selected */
+ else
+ {
+ /* Clear two bit at bit position */
+ LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
+
+ /* Set two selected bit */
+ LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Get current value of each Peripheral Clock Selection
+ * @param[in] ClkType Peripheral Clock Selection of each type,
+ * should be one of the following:
+ * - CLKPWR_PCLKSEL_WDT : WDT
+ - CLKPWR_PCLKSEL_TIMER0 : Timer 0
+ - CLKPWR_PCLKSEL_TIMER1 : Timer 1
+ - CLKPWR_PCLKSEL_UART0 : UART 0
+ - CLKPWR_PCLKSEL_UART1 : UART 1
+ - CLKPWR_PCLKSEL_PWM1 : PWM 1
+ - CLKPWR_PCLKSEL_I2C0 : I2C 0
+ - CLKPWR_PCLKSEL_SPI : SPI
+ - CLKPWR_PCLKSEL_SSP1 : SSP 1
+ - CLKPWR_PCLKSEL_DAC : DAC
+ - CLKPWR_PCLKSEL_ADC : ADC
+ - CLKPWR_PCLKSEL_CAN1 : CAN 1
+ - CLKPWR_PCLKSEL_CAN2 : CAN 2
+ - CLKPWR_PCLKSEL_ACF : ACF
+ - CLKPWR_PCLKSEL_QEI : QEI
+ - CLKPWR_PCLKSEL_PCB : PCB
+ - CLKPWR_PCLKSEL_I2C1 : I2C 1
+ - CLKPWR_PCLKSEL_SSP0 : SSP 0
+ - CLKPWR_PCLKSEL_TIMER2 : Timer 2
+ - CLKPWR_PCLKSEL_TIMER3 : Timer 3
+ - CLKPWR_PCLKSEL_UART2 : UART 2
+ - CLKPWR_PCLKSEL_UART3 : UART 3
+ - CLKPWR_PCLKSEL_I2C2 : I2C 2
+ - CLKPWR_PCLKSEL_I2S : I2S
+ - CLKPWR_PCLKSEL_RIT : RIT
+ - CLKPWR_PCLKSEL_SYSCON : SYSCON
+ - CLKPWR_PCLKSEL_MC : MC
+
+ * @return Value of Selected Peripheral Clock Selection
+ **********************************************************************/
+uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
+{
+ uint32_t bitpos, retval;
+
+ if (ClkType < 32)
+ {
+ bitpos = ClkType;
+ retval = LPC_SC->PCLKSEL0;
+ }
+ else
+ {
+ bitpos = ClkType - 32;
+ retval = LPC_SC->PCLKSEL1;
+ }
+
+ retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
+ return retval;
+}
+
+
+
+/*********************************************************************//**
+ * @brief Get current value of each Peripheral Clock
+ * @param[in] ClkType Peripheral Clock Selection of each type,
+ * should be one of the following:
+ * - CLKPWR_PCLKSEL_WDT : WDT
+ - CLKPWR_PCLKSEL_TIMER0 : Timer 0
+ - CLKPWR_PCLKSEL_TIMER1 : Timer 1
+ - CLKPWR_PCLKSEL_UART0 : UART 0
+ - CLKPWR_PCLKSEL_UART1 : UART 1
+ - CLKPWR_PCLKSEL_PWM1 : PWM 1
+ - CLKPWR_PCLKSEL_I2C0 : I2C 0
+ - CLKPWR_PCLKSEL_SPI : SPI
+ - CLKPWR_PCLKSEL_SSP1 : SSP 1
+ - CLKPWR_PCLKSEL_DAC : DAC
+ - CLKPWR_PCLKSEL_ADC : ADC
+ - CLKPWR_PCLKSEL_CAN1 : CAN 1
+ - CLKPWR_PCLKSEL_CAN2 : CAN 2
+ - CLKPWR_PCLKSEL_ACF : ACF
+ - CLKPWR_PCLKSEL_QEI : QEI
+ - CLKPWR_PCLKSEL_PCB : PCB
+ - CLKPWR_PCLKSEL_I2C1 : I2C 1
+ - CLKPWR_PCLKSEL_SSP0 : SSP 0
+ - CLKPWR_PCLKSEL_TIMER2 : Timer 2
+ - CLKPWR_PCLKSEL_TIMER3 : Timer 3
+ - CLKPWR_PCLKSEL_UART2 : UART 2
+ - CLKPWR_PCLKSEL_UART3 : UART 3
+ - CLKPWR_PCLKSEL_I2C2 : I2C 2
+ - CLKPWR_PCLKSEL_I2S : I2S
+ - CLKPWR_PCLKSEL_RIT : RIT
+ - CLKPWR_PCLKSEL_SYSCON : SYSCON
+ - CLKPWR_PCLKSEL_MC : MC
+
+ * @return Value of Selected Peripheral Clock
+ **********************************************************************/
+uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
+{
+ uint32_t retval, div;
+
+ retval = SystemCoreClock;
+ div = CLKPWR_GetPCLKSEL(ClkType);
+
+ switch (div)
+ {
+ case 0:
+ div = 4;
+ break;
+
+ case 1:
+ div = 1;
+ break;
+
+ case 2:
+ div = 2;
+ break;
+
+ case 3:
+ div = 8;
+ break;
+ }
+ retval /= div;
+
+ return retval;
+}
+
+
+
+/*********************************************************************//**
+ * @brief Configure power supply for each peripheral according to NewState
+ * @param[in] PPType Type of peripheral used to enable power,
+ * should be one of the following:
+ * - CLKPWR_PCONP_PCTIM0 : Timer 0
+ - CLKPWR_PCONP_PCTIM1 : Timer 1
+ - CLKPWR_PCONP_PCUART0 : UART 0
+ - CLKPWR_PCONP_PCUART1 : UART 1
+ - CLKPWR_PCONP_PCPWM1 : PWM 1
+ - CLKPWR_PCONP_PCI2C0 : I2C 0
+ - CLKPWR_PCONP_PCSPI : SPI
+ - CLKPWR_PCONP_PCRTC : RTC
+ - CLKPWR_PCONP_PCSSP1 : SSP 1
+ - CLKPWR_PCONP_PCAD : ADC
+ - CLKPWR_PCONP_PCAN1 : CAN 1
+ - CLKPWR_PCONP_PCAN2 : CAN 2
+ - CLKPWR_PCONP_PCGPIO : GPIO
+ - CLKPWR_PCONP_PCRIT : RIT
+ - CLKPWR_PCONP_PCMC : MC
+ - CLKPWR_PCONP_PCQEI : QEI
+ - CLKPWR_PCONP_PCI2C1 : I2C 1
+ - CLKPWR_PCONP_PCSSP0 : SSP 0
+ - CLKPWR_PCONP_PCTIM2 : Timer 2
+ - CLKPWR_PCONP_PCTIM3 : Timer 3
+ - CLKPWR_PCONP_PCUART2 : UART 2
+ - CLKPWR_PCONP_PCUART3 : UART 3
+ - CLKPWR_PCONP_PCI2C2 : I2C 2
+ - CLKPWR_PCONP_PCI2S : I2S
+ - CLKPWR_PCONP_PCGPDMA : GPDMA
+ - CLKPWR_PCONP_PCENET : Ethernet
+ - CLKPWR_PCONP_PCUSB : USB
+ *
+ * @param[in] NewState New state of Peripheral Power, should be:
+ * - ENABLE : Enable power for this peripheral
+ * - DISABLE : Disable power for this peripheral
+ *
+ * @return none
+ **********************************************************************/
+void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
+{
+ if (NewState == ENABLE)
+ {
+ LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK;
+ }
+ else if (NewState == DISABLE)
+ {
+ LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void CLKPWR_Sleep(void)
+{
+ LPC_SC->PCON = 0x00;
+ /* Sleep Mode*/
+ __WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void CLKPWR_DeepSleep(void)
+{
+ /* Deep-Sleep Mode, set SLEEPDEEP bit */
+ SCB->SCR = 0x4;
+ LPC_SC->PCON = 0x8;
+ /* Deep Sleep Mode*/
+ __WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void CLKPWR_PowerDown(void)
+{
+ /* Deep-Sleep Mode, set SLEEPDEEP bit */
+ SCB->SCR = 0x4;
+ LPC_SC->PCON = 0x09;
+ /* Power Down Mode*/
+ __WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void CLKPWR_DeepPowerDown(void)
+{
+ /* Deep-Sleep Mode, set SLEEPDEEP bit */
+ SCB->SCR = 0x4;
+ LPC_SC->PCON = 0x03;
+ /* Deep Power Down Mode*/
+ __WFI();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/CMSIS_Lib/lpc17xx_clkpwr.h Sun Nov 14 03:26:04 2010 +0000
@@ -0,0 +1,394 @@
+/***********************************************************************//**
+ * @file lpc17xx_clkpwr.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for Clock and Power Control firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CLKPWR CLKPWR
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_CLKPWR_H_
+#define LPC17XX_CLKPWR_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
+ * @{
+ */
+
+/**********************************************************************
+ * Peripheral Clock Selection Definitions
+ **********************************************************************/
+/** Peripheral clock divider bit position for WDT */
+#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
+/** Peripheral clock divider bit position for TIMER0 */
+#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
+/** Peripheral clock divider bit position for TIMER1 */
+#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
+/** Peripheral clock divider bit position for UART0 */
+#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
+/** Peripheral clock divider bit position for UART1 */
+#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
+/** Peripheral clock divider bit position for PWM1 */
+#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
+/** Peripheral clock divider bit position for I2C0 */
+#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
+/** Peripheral clock divider bit position for SPI */
+#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
+/** Peripheral clock divider bit position for SSP1 */
+#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
+/** Peripheral clock divider bit position for DAC */
+#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
+/** Peripheral clock divider bit position for ADC */
+#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
+/** Peripheral clock divider bit position for CAN1 */
+#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
+/** Peripheral clock divider bit position for CAN2 */
+#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
+/** Peripheral clock divider bit position for ACF */
+#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
+/** Peripheral clock divider bit position for QEI */
+#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
+/** Peripheral clock divider bit position for PCB */
+#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
+/** Peripheral clock divider bit position for I2C1 */
+#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
+/** Peripheral clock divider bit position for SSP0 */
+#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
+/** Peripheral clock divider bit position for TIMER2 */
+#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
+/** Peripheral clock divider bit position for TIMER3 */
+#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
+/** Peripheral clock divider bit position for UART2 */
+#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
+/** Peripheral clock divider bit position for UART3 */
+#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
+/** Peripheral clock divider bit position for I2C2 */
+#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
+/** Peripheral clock divider bit position for I2S */
+#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
+/** Peripheral clock divider bit position for RIT */
+#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
+/** Peripheral clock divider bit position for SYSCON */
+#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
+/** Peripheral clock divider bit position for MC */
+#define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
+
+/** Macro for Peripheral Clock Selection register bit values
+ * Note: When CCLK_DIV_8, Peripheral�s clock is selected to
+ * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
+ * when �11�selects PCLK_xyz = CCLK/6 */
+/* Peripheral clock divider is set to 4 from CCLK */
+#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
+/** Peripheral clock divider is the same with CCLK */
+#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
+/** Peripheral clock divider is set to 2 from CCLK */
+#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
+
+
+/********************************************************************
+* Power Control for Peripherals Definitions
+**********************************************************************/
+/** Timer/Counter 0 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
+/* Timer/Counter 1 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
+/** UART0 power/clock control bit */
+#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
+/** UART1 power/clock control bit */
+#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
+/** PWM1 power/clock control bit */
+#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
+/** The I2C0 interface power/clock control bit */
+#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
+/** The SPI interface power/clock control bit */
+#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
+/** The RTC power/clock control bit */
+#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
+/** The SSP1 interface power/clock control bit */
+#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
+/** A/D converter 0 (ADC0) power/clock control bit */
+#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
+/** CAN Controller 1 power/clock control bit */
+#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
+/** CAN Controller 2 power/clock control bit */
+#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
+/** GPIO power/clock control bit */
+#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
+/** Repetitive Interrupt Timer power/clock control bit */
+#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
+/** Motor Control PWM */
+#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
+/** Quadrature Encoder Interface power/clock control bit */
+#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
+/** The I2C1 interface power/clock control bit */
+#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
+/** The SSP0 interface power/clock control bit */
+#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
+/** Timer 2 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
+/** Timer 3 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
+/** UART 2 power/clock control bit */
+#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
+/** UART 3 power/clock control bit */
+#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
+/** I2C interface 2 power/clock control bit */
+#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
+/** I2S interface power/clock control bit*/
+#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
+/** GP DMA function power/clock control bit*/
+#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
+/** Ethernet block power/clock control bit*/
+#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
+/** USB interface power/clock control bit*/
+#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
+
+
+/**
+ * @}
+ */
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Clock Source Select Register
+ **********************************************************************/
+/** Internal RC oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
+/** Main oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
+/** RTC oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
+/** Clock source selection bit mask */
+#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for Clock Output Configuration Register
+ **********************************************************************/
+/* Clock Output Configuration register definition */
+/** Selects the CPU clock as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
+/** Selects the main oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
+/** Selects the Internal RC oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
+/** Selects the USB clock as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
+/** Selects the RTC oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
+/** Integer value to divide the output clock by, minus one */
+#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
+/** CLKOUT enable control */
+#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
+/** CLKOUT activity indication */
+#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
+/** Clock source selection bit mask */
+#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Control Register
+ **********************************************************************/
+/** PLL 0 control enable */
+#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
+/** PLL 0 control connect */
+#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
+/** PLL 0 control bit mask */
+#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Configuration Register
+ **********************************************************************/
+/** PLL 0 Configuration MSEL field */
+#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
+/** PLL 0 Configuration NSEL field */
+#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
+/** PLL 0 Configuration bit mask */
+#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
+
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Status Register
+ **********************************************************************/
+/** PLL 0 MSEL value */
+#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
+/** PLL NSEL get value */
+#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
+/** PLL status enable bit */
+#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
+/** PLL status Connect bit */
+#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
+/** PLL status lock */
+#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Feed Register
+ **********************************************************************/
+/** PLL0 Feed bit mask */
+#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Control Register
+ **********************************************************************/
+/** USB PLL control enable */
+#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
+/** USB PLL control connect */
+#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
+/** USB PLL control bit mask */
+#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Configuration Register
+ **********************************************************************/
+/** USB PLL MSEL set value */
+#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
+/** USB PLL PSEL set value */
+#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
+/** USB PLL configuration bit mask */
+#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Status Register
+ **********************************************************************/
+/** USB PLL MSEL get value */
+#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
+/** USB PLL PSEL get value */
+#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
+/** USB PLL status enable bit */
+#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
+/** USB PLL status Connect bit */
+#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
+/** USB PLL status lock */
+#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Feed Register
+ **********************************************************************/
+/** PLL1 Feed bit mask */
+#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for CPU Clock Configuration Register
+ **********************************************************************/
+/** CPU Clock configuration bit mask */
+#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for USB Clock Configuration Register
+ **********************************************************************/
+/** USB Clock Configuration bit mask */
+#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for IRC Trim Register
+ **********************************************************************/
+/** IRC Trim bit mask */
+#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for Peripheral Clock Selection Register 0 and 1
+ **********************************************************************/
+/** Peripheral Clock Selection 0 mask bit */
+#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
+/** Peripheral Clock Selection 1 mask bit */
+#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
+/** Macro to set peripheral clock of each type
+ * p: position of two bits that hold divider of peripheral clock
+ * n: value of divider of peripheral clock to be set */
+#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
+/** Macro to mask peripheral clock of each type */
+#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
+/** Macro to get peripheral clock of each type */
+#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
+
+/*********************************************************************//**
+ * Macro defines for Power Mode Control Register
+ **********************************************************************/
+/** Power mode control bit 0 */
+#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
+/** Power mode control bit 1 */
+#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
+/** Brown-Out Reduced Power Mode */
+#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
+/** Brown-Out Global Disable */
+#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
+/** Brown Out Reset Disable */
+#define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
+/** Sleep Mode entry flag */
+#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
+/** Deep Sleep entry flag */
+#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
+/** Power-down entry flag */
+#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
+/** Deep Power-down entry flag */
+#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
+
+/*********************************************************************//**
+ * Macro defines for Power Control for Peripheral Register
+ **********************************************************************/
+/** Power Control for Peripherals bit mask */
+#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
+ * @{
+ */
+
+void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
+uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
+uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
+void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
+void CLKPWR_Sleep(void);
+void CLKPWR_DeepSleep(void);
+void CLKPWR_PowerDown(void);
+void CLKPWR_DeepPowerDown(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_CLKPWR_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/CMSIS_Lib/lpc17xx_gpdma.c Sun Nov 14 03:26:04 2010 +0000
@@ -0,0 +1,446 @@
+/***********************************************************************//**
+ * @file lpc17xx_gpdma.c
+ * @brief Contains all functions support for GPDMA firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup GPDMA
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_gpdma.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#include "lpc17xx_libcfg.h"
+
+#ifdef _GPDMA
+
+
+/* Private Variables ---------------------------------------------------------- */
+/** @defgroup GPDMA_Private_Variables GPDMA Private Variables
+ * @{
+ */
+
+/**
+ * @brief Lookup Table of Connection Type matched with
+ * Peripheral Data (FIFO) register base address
+ */
+#ifdef __IAR_SYSTEMS_ICC__
+volatile const void *GPDMA_LUTPerAddr[] = {
+ (&LPC_SSP0->DR), // SSP0 Tx
+ (&LPC_SSP0->DR), // SSP0 Rx
+ (&LPC_SSP1->DR), // SSP1 Tx
+ (&LPC_SSP1->DR), // SSP1 Rx
+ (&LPC_ADC->ADGDR), // ADC
+ (&LPC_I2S->I2STXFIFO), // I2S Tx
+ (&LPC_I2S->I2SRXFIFO), // I2S Rx
+ (&LPC_DAC->DACR), // DAC
+ (&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx
+ (&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx
+ (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
+ (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
+ (&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx
+ (&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx
+ (&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx
+ (&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx
+ (&LPC_TIM0->MR0), // MAT0.0
+ (&LPC_TIM0->MR1), // MAT0.1
+ (&LPC_TIM1->MR0), // MAT1.0
+ (&LPC_TIM1->MR1), // MAT1.1
+ (&LPC_TIM2->MR0), // MAT2.0
+ (&LPC_TIM2->MR1), // MAT2.1
+ (&LPC_TIM3->MR0), // MAT3.0
+ (&LPC_TIM3->MR1), // MAT3.1
+};
+#else
+const uint32_t GPDMA_LUTPerAddr[] = {
+ ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx
+ ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx
+ ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx
+ ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx
+ ((uint32_t)&LPC_ADC->ADGDR), // ADC
+ ((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx
+ ((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx
+ ((uint32_t)&LPC_DAC->DACR), // DAC
+ ((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx
+ ((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx
+ ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
+ ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
+ ((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx
+ ((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx
+ ((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx
+ ((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx
+ ((uint32_t)&LPC_TIM0->MR0), // MAT0.0
+ ((uint32_t)&LPC_TIM0->MR1), // MAT0.1
+ ((uint32_t)&LPC_TIM1->MR0), // MAT1.0
+ ((uint32_t)&LPC_TIM1->MR1), // MAT1.1
+ ((uint32_t)&LPC_TIM2->MR0), // MAT2.0
+ ((uint32_t)&LPC_TIM2->MR1), // MAT2.1
+ ((uint32_t)&LPC_TIM3->MR0), // MAT3.0
+ ((uint32_t)&LPC_TIM3->MR1), // MAT3.1
+};
+#endif
+/**
+ * @brief Lookup Table of GPDMA Channel Number matched with
+ * GPDMA channel pointer
+ */
+const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
+ LPC_GPDMACH0, // GPDMA Channel 0
+ LPC_GPDMACH1, // GPDMA Channel 1
+ LPC_GPDMACH2, // GPDMA Channel 2
+ LPC_GPDMACH3, // GPDMA Channel 3
+ LPC_GPDMACH4, // GPDMA Channel 4
+ LPC_GPDMACH5, // GPDMA Channel 5
+ LPC_GPDMACH6, // GPDMA Channel 6
+ LPC_GPDMACH7, // GPDMA Channel 7
+};
+/**
+ * @brief Optimized Peripheral Source and Destination burst size
+ */
+const uint8_t GPDMA_LUTPerBurst[] = {
+ GPDMA_BSIZE_4, // SSP0 Tx
+ GPDMA_BSIZE_4, // SSP0 Rx
+ GPDMA_BSIZE_4, // SSP1 Tx
+ GPDMA_BSIZE_4, // SSP1 Rx
+ GPDMA_BSIZE_4, // ADC
+ GPDMA_BSIZE_32, // I2S channel 0
+ GPDMA_BSIZE_32, // I2S channel 1
+ GPDMA_BSIZE_1, // DAC
+ GPDMA_BSIZE_1, // UART0 Tx
+ GPDMA_BSIZE_1, // UART0 Rx
+ GPDMA_BSIZE_1, // UART1 Tx
+ GPDMA_BSIZE_1, // UART1 Rx
+ GPDMA_BSIZE_1, // UART2 Tx
+ GPDMA_BSIZE_1, // UART2 Rx
+ GPDMA_BSIZE_1, // UART3 Tx
+ GPDMA_BSIZE_1, // UART3 Rx
+ GPDMA_BSIZE_1, // MAT0.0
+ GPDMA_BSIZE_1, // MAT0.1
+ GPDMA_BSIZE_1, // MAT1.0
+ GPDMA_BSIZE_1, // MAT1.1
+ GPDMA_BSIZE_1, // MAT2.0
+ GPDMA_BSIZE_1, // MAT2.1
+ GPDMA_BSIZE_1, // MAT3.0
+ GPDMA_BSIZE_1, // MAT3.1
+};
+/**
+ * @brief Optimized Peripheral Source and Destination transfer width
+ */
+const uint8_t GPDMA_LUTPerWid[] = {
+ GPDMA_WIDTH_BYTE, // SSP0 Tx
+ GPDMA_WIDTH_BYTE, // SSP0 Rx
+ GPDMA_WIDTH_BYTE, // SSP1 Tx
+ GPDMA_WIDTH_BYTE, // SSP1 Rx
+ GPDMA_WIDTH_WORD, // ADC
+ GPDMA_WIDTH_WORD, // I2S channel 0
+ GPDMA_WIDTH_WORD, // I2S channel 1
+ GPDMA_WIDTH_BYTE, // DAC
+ GPDMA_WIDTH_BYTE, // UART0 Tx
+ GPDMA_WIDTH_BYTE, // UART0 Rx
+ GPDMA_WIDTH_BYTE, // UART1 Tx
+ GPDMA_WIDTH_BYTE, // UART1 Rx
+ GPDMA_WIDTH_BYTE, // UART2 Tx
+ GPDMA_WIDTH_BYTE, // UART2 Rx
+ GPDMA_WIDTH_BYTE, // UART3 Tx
+ GPDMA_WIDTH_BYTE, // UART3 Rx
+ GPDMA_WIDTH_WORD, // MAT0.0
+ GPDMA_WIDTH_WORD, // MAT0.1
+ GPDMA_WIDTH_WORD, // MAT1.0
+ GPDMA_WIDTH_WORD, // MAT1.1
+ GPDMA_WIDTH_WORD, // MAT2.0
+ GPDMA_WIDTH_WORD, // MAT2.1
+ GPDMA_WIDTH_WORD, // MAT3.0
+ GPDMA_WIDTH_WORD, // MAT3.1
+};
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup GPDMA_Public_Functions
+ * @{
+ */
+
+/********************************************************************//**
+ * @brief Initialize GPDMA controller
+ * @param None
+ * @return None
+ *********************************************************************/
+void GPDMA_Init(void)
+{
+ /* Enable GPDMA clock */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);
+
+ // Reset all channel configuration register
+ LPC_GPDMACH0->DMACCConfig = 0;
+ LPC_GPDMACH1->DMACCConfig = 0;
+ LPC_GPDMACH2->DMACCConfig = 0;
+ LPC_GPDMACH3->DMACCConfig = 0;
+ LPC_GPDMACH4->DMACCConfig = 0;
+ LPC_GPDMACH5->DMACCConfig = 0;
+ LPC_GPDMACH6->DMACCConfig = 0;
+ LPC_GPDMACH7->DMACCConfig = 0;
+
+ /* Clear all DMA interrupt and error flag */
+ LPC_GPDMA->DMACIntTCClear = 0xFF;
+ LPC_GPDMA->DMACIntErrClr = 0xFF;
+}
+
+/********************************************************************//**
+ * @brief Setup GPDMA channel peripheral according to the specified
+ * parameters in the GPDMAChannelConfig.
+ * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
+ * structure that contains the configuration
+ * information for the specified GPDMA channel peripheral.
+ * @return ERROR if selected channel is enabled before
+ * or SUCCESS if channel is configured successfully
+ *********************************************************************/
+Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
+{
+ LPC_GPDMACH_TypeDef *pDMAch;
+ uint32_t tmp1, tmp2;
+
+ if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
+ // This channel is enabled, return ERROR, need to release this channel first
+ return ERROR;
+ }
+
+ // Get Channel pointer
+ pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
+
+ // Reset the Interrupt status
+ LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
+ LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
+
+ // Clear DMA configure
+ pDMAch->DMACCControl = 0x00;
+ pDMAch->DMACCConfig = 0x00;
+
+ /* Assign Linker List Item value */
+ pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI;
+
+ /* Set value to Channel Control Registers */
+ switch (GPDMAChannelConfig->TransferType)
+ {
+ // Memory to memory
+ case GPDMA_TRANSFERTYPE_M2M:
+ // Assign physical source and destination address
+ pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
+ pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
+ pDMAch->DMACCControl
+ = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
+ | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
+ | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
+ | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
+ | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
+ | GPDMA_DMACCxControl_SI \
+ | GPDMA_DMACCxControl_DI \
+ | GPDMA_DMACCxControl_I;
+ break;
+ // Memory to peripheral
+ case GPDMA_TRANSFERTYPE_M2P:
+ // Assign physical source
+ pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
+ // Assign peripheral destination address
+ pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
+ pDMAch->DMACCControl
+ = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
+ | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_SI \
+ | GPDMA_DMACCxControl_I;
+ break;
+ // Peripheral to memory
+ case GPDMA_TRANSFERTYPE_P2M:
+ // Assign peripheral source address
+ pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
+ // Assign memory destination address
+ pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
+ pDMAch->DMACCControl
+ = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
+ | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_DI \
+ | GPDMA_DMACCxControl_I;
+ break;
+ // Peripheral to peripheral
+ case GPDMA_TRANSFERTYPE_P2P:
+ // Assign peripheral source address
+ pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
+ // Assign peripheral destination address
+ pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
+ pDMAch->DMACCControl
+ = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
+ | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_I;
+ break;
+ // Do not support any more transfer type, return ERROR
+ default:
+ return ERROR;
+ }
+
+ /* Re-Configure DMA Request Select for source peripheral */
+ if (GPDMAChannelConfig->SrcConn > 15)
+ {
+ DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16));
+ } else {
+ DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn - 8));
+ }
+
+ /* Re-Configure DMA Request Select for Destination peripheral */
+ if (GPDMAChannelConfig->DstConn > 15)
+ {
+ DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16));
+ } else {
+ DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn - 8));
+ }
+
+ /* Enable DMA channels, little endian */
+ LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E;
+ while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E));
+
+ // Calculate absolute value for Connection number
+ tmp1 = GPDMAChannelConfig->SrcConn;
+ tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
+ tmp2 = GPDMAChannelConfig->DstConn;
+ tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
+
+ // Configure DMA Channel, enable Error Counter and Terminate counter
+ pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
+ | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
+ | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
+ | GPDMA_DMACCxConfig_DestPeripheral(tmp2);
+
+ return SUCCESS;
+}
+
+
+/*********************************************************************//**
+ * @brief Enable/Disable DMA channel
+ * @param[in] channelNum GPDMA channel, should be in range from 0 to 7
+ * @param[in] NewState New State of this command, should be:
+ * - ENABLE.
+ * - DISABLE.
+ * @return None
+ **********************************************************************/
+void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
+{
+ LPC_GPDMACH_TypeDef *pDMAch;
+
+ // Get Channel pointer
+ pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
+
+ if (NewState == ENABLE) {
+ pDMAch->DMACCConfig |= GPDMA_DMACCxConfig_E;
+ } else {
+ pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E;
+ }
+}
+/*********************************************************************//**
+ * @brief Check if corresponding channel does have an active interrupt
+ * request or not
+ * @param[in] type type of status, should be:
+ * - GPDMA_STAT_INT: GPDMA Interrupt Status
+ * - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status
+ * - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status
+ * - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status
+ * - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status
+ * - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status
+ * @param[in] channel GPDMA channel, should be in range from 0 to 7
+ * @return IntStatus status of DMA channel interrupt after masking
+ * Should be:
+ * - SET: the corresponding channel has no active interrupt request
+ * - RESET: the corresponding channel does have an active interrupt request
+ **********************************************************************/
+IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
+{
+ CHECK_PARAM(PARAM_GPDMA_STAT(type));
+ CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
+
+ switch (type)
+ {
+ case GPDMA_STAT_INT: //check status of DMA channel interrupts
+ if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel)))
+ return SET;
+ return RESET;
+ case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
+ if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel))
+ return SET;
+ return RESET;
+ case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
+ if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel))
+ return SET;
+ return RESET;
+ case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
+ if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel))
+ return SET;
+ return RESET;
+ case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
+ if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel))
+ return SET;
+ return RESET;
+ default: //check enable status for DMA channels
+ if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel))
+ return SET;
+ return RESET;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Clear one or more interrupt requests on DMA channels
+ * @param[in] type type of interrupt request, should be:
+ * - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear
+ * - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear
+ * @param[in] channel GPDMA channel, should be in range from 0 to 7
+ * @return None
+ **********************************************************************/
+void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
+{
+ CHECK_PARAM(PARAM_GPDMA_STATCLR(type));
+ CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
+
+ if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
+ LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel);
+ else // clear the error interrupt request
+ LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel);
+}
+
+/**
+ * @}
+ */
+
+#endif /* _GPDMA */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/CMSIS_Lib/lpc17xx_gpdma.h Sun Nov 14 03:26:04 2010 +0000
@@ -0,0 +1,420 @@
+/***********************************************************************//**
+ * @file lpc17xx_gpdma.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for GPDMA firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup GPDMA GPDMA
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_GPDMA_H_
+#define LPC17XX_GPDMA_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
+ * @{
+ */
+
+/** Peripheral declaration */
+#define DMAREQSEL (*(__IO uint32_t *) ( 0x4000C1C4))
+
+/** DMA Connection number definitions */
+#define GPDMA_CONN_SSP0_Tx ((0UL)) /**< SSP0 Tx */
+#define GPDMA_CONN_SSP0_Rx ((1UL)) /**< SSP0 Rx */
+#define GPDMA_CONN_SSP1_Tx ((2UL)) /**< SSP1 Tx */
+#define GPDMA_CONN_SSP1_Rx ((3UL)) /**< SSP1 Rx */
+#define GPDMA_CONN_ADC ((4UL)) /**< ADC */
+#define GPDMA_CONN_I2S_Channel_0 ((5UL)) /**< I2S channel 0 */
+#define GPDMA_CONN_I2S_Channel_1 ((6UL)) /**< I2S channel 1 */
+#define GPDMA_CONN_DAC ((7UL)) /**< DAC */
+#define GPDMA_CONN_UART0_Tx ((8UL)) /**< UART0 Tx */
+#define GPDMA_CONN_UART0_Rx ((9UL)) /**< UART0 Rx */
+#define GPDMA_CONN_UART1_Tx ((10UL)) /**< UART1 Tx */
+#define GPDMA_CONN_UART1_Rx ((11UL)) /**< UART1 Rx */
+#define GPDMA_CONN_UART2_Tx ((12UL)) /**< UART2 Tx */
+#define GPDMA_CONN_UART2_Rx ((13UL)) /**< UART2 Rx */
+#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
+#define GPDMA_CONN_UART3_Rx ((15UL)) /**< UART3 Rx */
+#define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */
+#define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */
+#define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */
+#define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */
+#define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */
+#define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */
+#define GPDMA_CONN_MAT3_0 ((22UL)) /**< MAT3.0 */
+#define GPDMA_CONN_MAT3_1 ((23UL)) /**< MAT3.1 */
+
+/** GPDMA Transfer type definitions */
+#define GPDMA_TRANSFERTYPE_M2M ((0UL)) /**< Memory to memory - DMA control */
+#define GPDMA_TRANSFERTYPE_M2P ((1UL)) /**< Memory to peripheral - DMA control */
+#define GPDMA_TRANSFERTYPE_P2M ((2UL)) /**< Peripheral to memory - DMA control */
+#define GPDMA_TRANSFERTYPE_P2P ((3UL)) /**< Source peripheral to destination peripheral - DMA control */
+
+/** Burst size in Source and Destination definitions */
+#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
+#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
+#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
+#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
+#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
+#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
+#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
+#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
+
+/** Width in Source transfer width and Destination transfer width definitions */
+#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
+#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
+#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
+
+/** DMA Request Select Mode definitions */
+#define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */
+#define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Status register
+ **********************************************************************/
+#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Terminal Count Request Status register
+ **********************************************************************/
+#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Terminal Count Request Clear register
+ **********************************************************************/
+#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Error Status register
+ **********************************************************************/
+#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Error Clear register
+ **********************************************************************/
+#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Raw Interrupt Terminal Count Status register
+ **********************************************************************/
+#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Raw Error Interrupt Status register
+ **********************************************************************/
+#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Enabled Channel register
+ **********************************************************************/
+#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Burst Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Single Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Last Burst Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Last Single Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Configuration register
+ **********************************************************************/
+#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
+#define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/
+#define GPDMA_DMACConfig_BITMASK ((0x03))
+
+/*********************************************************************//**
+ * Macro defines for DMA Synchronization register
+ **********************************************************************/
+#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSync_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Request Select register
+ **********************************************************************/
+#define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
+#define GPDMA_DMAReqSel_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Channel Linked List Item registers
+ **********************************************************************/
+/** DMA Channel Linked List Item registers bit mask*/
+#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
+
+/*********************************************************************//**
+ * Macro defines for DMA channel control registers
+ **********************************************************************/
+#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/
+#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/
+#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/
+#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/
+#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/
+#define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/
+#define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/
+#define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/
+#define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/
+#define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/
+#define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */
+/** DMA channel control registers bit mask */
+#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Channel Configuration registers
+ **********************************************************************/
+#define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/
+#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/
+#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/
+#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/
+#define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/
+#define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/
+#define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/
+#define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/
+#define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/
+/** DMA Channel Configuration registers bit mask */
+#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macros check GPDMA channel */
+#define PARAM_GPDMA_CHANNEL(n) ((n>=0) && (n<=7))
+
+/* Macros check GPDMA connection type */
+#define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
+|| (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
+|| (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \
+|| (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \
+|| (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
+|| (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
+|| (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
+|| (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
+|| (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
+|| (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
+|| (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
+|| (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
+
+/* Macros check GPDMA burst size type */
+#define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
+|| (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
+|| (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
+|| (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
+
+/* Macros check GPDMA width type */
+#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
+|| (n==GPDMA_WIDTH_WORD))
+
+/* Macros check GPDMA status type */
+#define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
+|| (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
+|| (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
+
+/* Macros check GPDMA transfer type */
+#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \
+||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P))
+
+/* Macros check GPDMA state clear type */
+#define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
+
+/* Macros check GPDMA request select type */
+#define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER))
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Types GPDMA Public Types
+ * @{
+ */
+
+/**
+ * @brief GPDMA Status enumeration
+ */
+typedef enum {
+ GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
+ GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
+ GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
+ GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
+ GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
+ GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
+} GPDMA_Status_Type;
+
+/**
+ * @brief GPDMA Interrupt clear status enumeration
+ */
+typedef enum{
+ GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
+ GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
+}GPDMA_StateClear_Type;
+
+/**
+ * @brief GPDMA Channel configuration structure type definition
+ */
+typedef struct {
+ uint32_t ChannelNum; /**< DMA channel number, should be in
+ range from 0 to 7.
+ Note: DMA channel 0 has the highest priority
+ and DMA channel 7 the lowest priority.
+ */
+ uint32_t TransferSize; /**< Length/Size of transfer */
+ uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
+ uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
+ uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
+ uint32_t TransferType; /**< Transfer Type, should be one of the following:
+ - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
+ - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
+ - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
+ - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
+ */
+ uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
+ following:
+ - GPDMA_CONN_SSP0_Tx: SSP0, Tx
+ - GPDMA_CONN_SSP0_Rx: SSP0, Rx
+ - GPDMA_CONN_SSP1_Tx: SSP1, Tx
+ - GPDMA_CONN_SSP1_Rx: SSP1, Rx
+ - GPDMA_CONN_ADC: ADC
+ - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
+ - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
+ - GPDMA_CONN_DAC: DAC
+ - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
+ - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
+ - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
+ - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
+ - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
+ - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
+ - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
+ - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
+ */
+ uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
+ following:
+ - GPDMA_CONN_SSP0_Tx: SSP0, Tx
+ - GPDMA_CONN_SSP0_Rx: SSP0, Rx
+ - GPDMA_CONN_SSP1_Tx: SSP1, Tx
+ - GPDMA_CONN_SSP1_Rx: SSP1, Rx
+ - GPDMA_CONN_ADC: ADC
+ - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
+ - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
+ - GPDMA_CONN_DAC: DAC
+ - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
+ - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
+ - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
+ - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
+ - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
+ - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
+ - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
+ - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
+ */
+ uint32_t DMALLI; /**< Linker List Item structure data address
+ if there's no Linker List, set as '0'
+ */
+} GPDMA_Channel_CFG_Type;
+
+/**
+ * @brief GPDMA Linker List Item structure type definition
+ */
+typedef struct {
+ uint32_t SrcAddr; /**< Source Address */
+ uint32_t DstAddr; /**< Destination address */
+ uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
+ uint32_t Control; /**< GPDMA Control of this LLI */
+} GPDMA_LLI_Type;
+
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
+ * @{
+ */
+
+void GPDMA_Init(void);
+//Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs);
+Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
+IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
+void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
+void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
+//void GPDMA_IntHandler(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_GPDMA_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/CMSIS_Lib/lpc17xx_libcfg.h Sun Nov 14 03:26:04 2010 +0000 @@ -0,0 +1,143 @@ +/***********************************************************************//** + * @file lpc17xx_libcfg.h + * @purpose Library configuration file + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +#ifndef LPC17XX_LIBCFG_H_ +#define LPC17XX_LIBCFG_H_ + +#include "lpc_types.h" + + +/************************** DEBUG MODE DEFINITIONS *********************************/ +/* Un-comment the line below to compile the library in DEBUG mode, this will expanse + the "CHECK_PARAM" macro in the FW library code */ + +#define DEBUG + + +/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/ + +/* Comment the line below to disable the specific peripheral inclusion */ + +/* DEBUG_FRAMWORK ------------------------------ */ +#define _DBGFWK + +/* GPIO ------------------------------- */ +//#define _GPIO + +/* EXTI ------------------------------- */ +//#define _EXTI + +/* UART ------------------------------- */ +#define _UART +#define _UART0 +//#define _UART1 +//#define _UART2 +//#define _UART3 + +/* SPI ------------------------------- */ +//#define _SPI + +/* SSP ------------------------------- */ +//#define _SSP +//#define _SSP0 +//#define _SSP1 + +/* SYSTICK --------------------------- */ +//#define _SYSTICK + +/* I2C ------------------------------- */ +//#define _I2C +//#define _I2C0 +//#define _I2C1 +//#define _I2C2 + +/* TIMER ------------------------------- */ +//#define _TIM + +/* WDT ------------------------------- */ +//#define _WDT + + +/* GPDMA ------------------------------- */ +#define _GPDMA + + +/* DAC ------------------------------- */ +//#define _DAC + +/* DAC ------------------------------- */ +//#define _ADC + + +/* PWM ------------------------------- */ +//#define _PWM +//#define _PWM1 + +/* RTC ------------------------------- */ +//#define _RTC + +/* I2S ------------------------------- */ +//#define _I2S + +/* USB device ------------------------------- */ +//#define _USBDEV +//#define _USB_DMA + +/* QEI ------------------------------- */ +//#define _QEI + +/* MCPWM ------------------------------- */ +//#define _MCPWM + +/* CAN--------------------------------*/ +//#define _CAN + +/* RIT ------------------------------- */ +//#define _RIT + +/* EMAC ------------------------------ */ +//#define _EMAC + +/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/ + +#ifdef DEBUG +/******************************************************************************* +* @brief The CHECK_PARAM macro is used for function's parameters check. +* It is used only if the library is compiled in DEBUG mode. +* @param[in] expr - If expr is false, it calls check_failed() function +* which reports the name of the source file and the source +* line number of the call that failed. +* - If expr is true, it returns no value. +* @return None +*******************************************************************************/ +#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) +#else +#define CHECK_PARAM(expr) +#endif /* DEBUG */ + + + +/************************** GLOBAL/PUBLIC FUNCTION DECLARATION *********************************/ + +#ifdef DEBUG +void check_failed(uint8_t *file, uint32_t line); +#endif + + +#endif /* LPC17XX_LIBCFG_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/CMSIS_Lib/lpc_types.h Sun Nov 14 03:26:04 2010 +0000
@@ -0,0 +1,196 @@
+/***********************************************************************//**
+ * @file lpc_types.h
+ * @brief Contains the NXP ABL typedefs for C standard types.
+ * It is intended to be used in ISO C conforming development
+ * environments and checks for this insofar as it is possible
+ * to do so.
+ * @version 1.0
+ * @date 27 Jul. 2008
+ * @author wellsk
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Type group ----------------------------------------------------------- */
+/** @defgroup LPC_Types LPC_Types
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC_TYPES_H
+#define LPC_TYPES_H
+
+/* Includes ------------------------------------------------------------------- */
+#include <stdint.h>
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/**
+ * @brief Boolean Type definition
+ */
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum
+{
+ NONE_BLOCKING = 0, /**< None Blocking type */
+ BLOCKING, /**< Blocking type */
+} TRANSFER_BLOCK_Type;
+
+
+/** Pointer to Function returning Void (any number of parameters) */
+typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+typedef int32_t(*PFI)();
+
+/**
+ * @}
+ */
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros
+ * @{
+ */
+
+/* _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/* Set bit macro */
+#define _BIT(n) (1<<n)
+
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f,v) (v<<f)
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off. When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void*) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+/**
+ * @}
+ */
+
+
+/* Old Type Definition compatibility ------------------------------------------ */
+/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/** SMA type for character type */
+typedef char CHAR;
+
+/** SMA type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** SMA type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** SMA type for 16 bit unsigned value */
+typedef uint16_t UNS_16;
+
+/** SMA type for 16 bit signed value */
+typedef int16_t INT_16;
+
+/** SMA type for 32 bit unsigned value */
+typedef uint32_t UNS_32;
+
+/** SMA type for 32 bit signed value */
+typedef int32_t INT_32;
+
+/** SMA type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** SMA type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+/** 32 bit boolean type */
+typedef Bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef Bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef Bool BOOL_8;
+
+/**
+ * @}
+ */
+
+
+#endif /* LPC_TYPES_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/DMA_M2M.c Sun Nov 14 03:26:04 2010 +0000
@@ -0,0 +1,239 @@
+/***********************************************************************//**
+ * @file flash_2_ram.c
+ * @purpose This example used to test GPDMA function by transferring
+ * data from flash to ram memory
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ *
+ * Adupted for mebed
+ * and modified for insturction execution test during DMA
+ * by Todotani 14 Nov. 2010
+ *---------------------------------------------------------------------
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+#include "lpc17xx_gpdma.h"
+#include "lpc17xx_libcfg.h"
+#include "mbed.h"
+#include "GetTickCount.h"
+
+/* Example group ----------------------------------------------------------- */
+/** @defgroup GPDMA_Flash_2_Ram_Test Flash_2_Ram_Test
+ * @ingroup GPDMA_Examples
+ * @{
+ */
+
+/************************** PRIVATE DEFINTIONS*************************/
+#define DMA_SIZE 32 /** DMA transfer size */
+#define DMA_CYCLES 1000
+
+/************************** PRIVATE VARIABLES *************************/
+uint8_t menu[]=
+ "********************************************************************************\n\r"
+ "Hello NXP Semiconductors \n\r"
+ "GPDMA demo \n\r"
+ "\t - MCU: LPC1768(mbed) \n\r"
+ "\t - Core: ARM CORTEX-M3 \n\r"
+ "\t - Communicate via: UART0 - 9600 bps \n\r"
+ "This example used to test GPDMA function by transfer data from Flash \n\r"
+ "to RAM memory\n\r"
+ "********************************************************************************\n\r";
+uint8_t menu2[] = "Demo terminated! \n\r";
+uint8_t err_menu[] = "Buffer Check fail!\n\r";
+uint8_t compl_menu[] = "Buffer Check success!\n\r\n\r";
+
+//DMAScr_Buffer will be burn into flash when compile
+static uint32_t DMASrc_Buffer[DMA_SIZE]=
+{
+ 0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
+ 0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
+ 0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
+ 0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40,
+ 0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
+ 0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
+ 0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
+ 0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40
+};
+
+uint32_t DMADest_Buffer[DMA_SIZE];
+//uint32_t *DMADest_Buffer = (uint32_t *)0x2007C000; //LPC_AHBRAM0_BASE;
+
+volatile uint32_t TC_count = 0;
+uint32_t loop = 0;
+GPDMA_Channel_CFG_Type GPDMACfg;
+
+Serial pc(USBTX, USBRX);
+
+
+/*-------------------------MAIN FUNCTION------------------------------*/
+extern "C" void DMA_IRQHandler (void); // extern "C" required for mbed
+
+void Buffer_Init(void);
+void Buffer_Verify(void);
+void SetupDMA(void);
+
+
+/*----------------- INTERRUPT SERVICE ROUTINES --------------------------*/
+/*********************************************************************//**
+ * @brief GPDMA interrupt handler sub-routine
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void DMA_IRQHandler (void)
+{
+ // check GPDMA interrupt on channel 0
+ if (GPDMA_IntGetStatus(GPDMA_STAT_INT, 0)) { //check interrupt status on channel 0
+ // Check counter terminal status
+ if(GPDMA_IntGetStatus(GPDMA_STAT_INTTC, 0)) {
+ // Clear terminate counter Interrupt pending
+ GPDMA_ClearIntPending (GPDMA_STATCLR_INTTC, 0);
+
+ if (++TC_count < DMA_CYCLES) {
+ // Setup channel with given parameter
+ GPDMA_Setup(&GPDMACfg);
+ // Run DMA again
+ GPDMA_ChannelCmd(0, ENABLE);
+ return;
+ } else {
+ /* DMA run predetermined cycles */
+ int elapsedTime = GetTickCount();
+ Buffer_Verify();
+ pc.printf("%s", compl_menu);
+ pc.printf("DMA %d cycles, %d loop executions\n\r", TC_count, loop);
+ pc.printf("Elapsed time %d ms\n\r\n\r", elapsedTime);
+
+ while(1); // Halt program
+ }
+ }
+
+ if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, 0)){
+ // Clear error counter Interrupt pending
+ GPDMA_ClearIntPending (GPDMA_STATCLR_INTERR, 0);
+ pc.printf("DMA Error detected.\n\r");
+ while(1); // Halt program
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Verify buffer
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void Buffer_Verify(void)
+{
+ uint8_t i;
+ uint32_t *src_addr = (uint32_t *)DMASrc_Buffer;
+ uint32_t *dest_addr = (uint32_t *)DMADest_Buffer;
+
+ for ( i = 0; i < DMA_SIZE; i++ )
+ {
+ if ( *src_addr++ != *dest_addr++ )
+ {
+ pc.printf("Verrify Error!.\n\r");
+ }
+ }
+}
+
+
+/*-------------------------MAIN FUNCTION--------------------------------*/
+/*********************************************************************//**
+ * @brief c_entry: Main program body
+ * @param[in] None
+ * @return int
+ **********************************************************************/
+int c_entry(void)
+{
+ pc.baud(9600);
+
+ // print welcome screen
+ pc.printf("%s", menu);
+
+ /* Disable GPDMA interrupt */
+ NVIC_DisableIRQ(DMA_IRQn);
+ /* preemption = 1, sub-priority = 1 */
+ NVIC_SetPriority(DMA_IRQn, ((0x01<<3)|0x01));
+
+ /* Initialize GPDMA controller */
+ GPDMA_Init();
+
+ // Setup GPDMA channel --------------------------------
+ // channel 0
+ GPDMACfg.ChannelNum = 0;
+ // Source memory
+ GPDMACfg.SrcMemAddr = (uint32_t)DMASrc_Buffer;
+ // Destination memory
+ GPDMACfg.DstMemAddr = (uint32_t)DMADest_Buffer;
+ // Transfer size
+ GPDMACfg.TransferSize = DMA_SIZE;
+ // Transfer width
+ GPDMACfg.TransferWidth = GPDMA_WIDTH_WORD;
+ // Transfer type
+ GPDMACfg.TransferType = GPDMA_TRANSFERTYPE_M2M;
+ // Source connection - unused
+ GPDMACfg.SrcConn = 0;
+ // Destination connection - unused
+ GPDMACfg.DstConn = 0;
+ // Linker List Item - unused
+ GPDMACfg.DMALLI = 0;
+ // Setup channel with given parameter
+ GPDMA_Setup(&GPDMACfg);
+
+ /* Enable GPDMA interrupt */
+ NVIC_EnableIRQ(DMA_IRQn);
+
+ pc.printf("Start transfer...\n\r");
+ GetTickCount_Start();
+
+ // Enable GPDMA channel 0
+ GPDMA_ChannelCmd(0, ENABLE);
+
+ /* Wait for GPDMA processing complete */
+ while (1) {
+ loop++;
+ }
+
+ return 1;
+}
+
+/* With ARM and GHS toolsets, the entry point is main() - this will
+ allow the linker to generate wrapper code to setup stacks, allocate
+ heap area, and initialize and copy code and data segments. For GNU
+ toolsets, the entry point is through __start() in the crt0_gnu.asm
+ file, and that startup code will setup stacks and data */
+int main(void) {
+ return c_entry();
+}
+
+#ifdef DEBUG
+/*******************************************************************************
+ * @brief Reports the name of the source file and the source line number
+ * where the CHECK_PARAM error has occurred.
+ * @param[in] file Pointer to the source file name
+ * @param[in] line assert_param error line source number
+ * @return None
+ *******************************************************************************/
+void check_failed(uint8_t *file, uint32_t line) {
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+ /* Infinite loop */
+ while (1)
+ ;
+}
+#endif
+
+/*
+ * @}
+ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/GetTickCount/GetTickCount.cpp Sun Nov 14 03:26:04 2010 +0000
@@ -0,0 +1,5 @@
+volatile unsigned int TickCount;
+
+extern "C" void SysTick_Handler (void) {
+ TickCount += 1;
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/GetTickCount/GetTickCount.h Sun Nov 14 03:26:04 2010 +0000
@@ -0,0 +1,31 @@
+/* mbed GetTickCount Library
+ * Copyright (c) 2010 Michael Wei
+ */
+
+//shouldn't have to include, but fixes weird problems with defines
+#include "LPC1768/LPC17xx.h"
+
+#ifndef MBED_TICKCOUNT_H
+#define MBED_TICKCOUNT_H
+extern volatile unsigned int TickCount;
+
+inline void GetTickCount_Start(void) {
+ //CMSIS SYSTICK Config
+ SysTick_Config(SystemCoreClock / 1000); /* Generate interrupt every 1 ms */
+}
+
+inline void GetTickCount_Stop(void) {
+ SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (0<<SYSTICK_ENABLE) | (0<<SYSTICK_TICKINT); /* Disable SysTick IRQ and SysTick Timer */
+}
+
+inline void GetTickCount_Reset(void) {
+ SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (0<<SYSTICK_ENABLE) | (0<<SYSTICK_TICKINT); /* Disable SysTick IRQ and SysTick Timer */
+ TickCount = 0;
+ SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
+}
+
+inline unsigned int GetTickCount(void)
+{
+ return TickCount;
+}
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed.bld Sun Nov 14 03:26:04 2010 +0000 @@ -0,0 +1,1 @@ +http://mbed.org/users/mbed_official/code/mbed/builds/e2ac27c8e93e