Ken Todotani / Mbed 2 deprecated DMA_M2M

Memory to Memory DMA demo from CMSIS example. This demo execute 1000 times of 32 word memory to memory DMA (copy), and also measures number of dummy loop execution during DMA cylcles. Line 56 of "DMA_M2M.c" can change DMA source. where; 1)static : source is SRAM 2)const : source is Flash ROM

Dependencies:   mbed

CMSIS_Lib/lpc17xx_gpdma.c@0:692bf16d1455, 2010-11-14 (annotated)

Committer:
todotani
Date:
Sun Nov 14 03:26:04 2010 +0000
Revision:
0:692bf16d1455
2010/11/14

Who changed what in which revision?

UserRevisionLine numberNew contents of line
todotani 0:692bf16d1455 1 /***********************************************************************//**
todotani 0:692bf16d1455 2 * @file lpc17xx_gpdma.c
todotani 0:692bf16d1455 3 * @brief Contains all functions support for GPDMA firmware library on LPC17xx
todotani 0:692bf16d1455 4 * @version 2.0
todotani 0:692bf16d1455 5 * @date 21. May. 2010
todotani 0:692bf16d1455 6 * @author NXP MCU SW Application Team
todotani 0:692bf16d1455 7 **************************************************************************
todotani 0:692bf16d1455 8 * Software that is described herein is for illustrative purposes only
todotani 0:692bf16d1455 9 * which provides customers with programming information regarding the
todotani 0:692bf16d1455 10 * products. This software is supplied "AS IS" without any warranties.
todotani 0:692bf16d1455 11 * NXP Semiconductors assumes no responsibility or liability for the
todotani 0:692bf16d1455 12 * use of the software, conveys no license or title under any patent,
todotani 0:692bf16d1455 13 * copyright, or mask work right to the product. NXP Semiconductors
todotani 0:692bf16d1455 14 * reserves the right to make changes in the software without
todotani 0:692bf16d1455 15 * notification. NXP Semiconductors also make no representation or
todotani 0:692bf16d1455 16 * warranty that such application will be suitable for the specified
todotani 0:692bf16d1455 17 * use without further testing or modification.
todotani 0:692bf16d1455 18 **********************************************************************/
todotani 0:692bf16d1455 19
todotani 0:692bf16d1455 20 /* Peripheral group ----------------------------------------------------------- */
todotani 0:692bf16d1455 21 /** @addtogroup GPDMA
todotani 0:692bf16d1455 22 * @{
todotani 0:692bf16d1455 23 */
todotani 0:692bf16d1455 24
todotani 0:692bf16d1455 25 /* Includes ------------------------------------------------------------------- */
todotani 0:692bf16d1455 26 #include "lpc17xx_gpdma.h"
todotani 0:692bf16d1455 27 #include "lpc17xx_clkpwr.h"
todotani 0:692bf16d1455 28
todotani 0:692bf16d1455 29 /* If this source file built with example, the LPC17xx FW library configuration
todotani 0:692bf16d1455 30 * file in each example directory ("lpc17xx_libcfg.h") must be included,
todotani 0:692bf16d1455 31 * otherwise the default FW library configuration file must be included instead
todotani 0:692bf16d1455 32 */
todotani 0:692bf16d1455 33 #include "lpc17xx_libcfg.h"
todotani 0:692bf16d1455 34
todotani 0:692bf16d1455 35 #ifdef _GPDMA
todotani 0:692bf16d1455 36
todotani 0:692bf16d1455 37
todotani 0:692bf16d1455 38 /* Private Variables ---------------------------------------------------------- */
todotani 0:692bf16d1455 39 /** @defgroup GPDMA_Private_Variables GPDMA Private Variables
todotani 0:692bf16d1455 40 * @{
todotani 0:692bf16d1455 41 */
todotani 0:692bf16d1455 42
todotani 0:692bf16d1455 43 /**
todotani 0:692bf16d1455 44 * @brief Lookup Table of Connection Type matched with
todotani 0:692bf16d1455 45 * Peripheral Data (FIFO) register base address
todotani 0:692bf16d1455 46 */
todotani 0:692bf16d1455 47 #ifdef __IAR_SYSTEMS_ICC__
todotani 0:692bf16d1455 48 volatile const void *GPDMA_LUTPerAddr[] = {
todotani 0:692bf16d1455 49 (&LPC_SSP0->DR), // SSP0 Tx
todotani 0:692bf16d1455 50 (&LPC_SSP0->DR), // SSP0 Rx
todotani 0:692bf16d1455 51 (&LPC_SSP1->DR), // SSP1 Tx
todotani 0:692bf16d1455 52 (&LPC_SSP1->DR), // SSP1 Rx
todotani 0:692bf16d1455 53 (&LPC_ADC->ADGDR), // ADC
todotani 0:692bf16d1455 54 (&LPC_I2S->I2STXFIFO), // I2S Tx
todotani 0:692bf16d1455 55 (&LPC_I2S->I2SRXFIFO), // I2S Rx
todotani 0:692bf16d1455 56 (&LPC_DAC->DACR), // DAC
todotani 0:692bf16d1455 57 (&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx
todotani 0:692bf16d1455 58 (&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx
todotani 0:692bf16d1455 59 (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
todotani 0:692bf16d1455 60 (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
todotani 0:692bf16d1455 61 (&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx
todotani 0:692bf16d1455 62 (&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx
todotani 0:692bf16d1455 63 (&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx
todotani 0:692bf16d1455 64 (&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx
todotani 0:692bf16d1455 65 (&LPC_TIM0->MR0), // MAT0.0
todotani 0:692bf16d1455 66 (&LPC_TIM0->MR1), // MAT0.1
todotani 0:692bf16d1455 67 (&LPC_TIM1->MR0), // MAT1.0
todotani 0:692bf16d1455 68 (&LPC_TIM1->MR1), // MAT1.1
todotani 0:692bf16d1455 69 (&LPC_TIM2->MR0), // MAT2.0
todotani 0:692bf16d1455 70 (&LPC_TIM2->MR1), // MAT2.1
todotani 0:692bf16d1455 71 (&LPC_TIM3->MR0), // MAT3.0
todotani 0:692bf16d1455 72 (&LPC_TIM3->MR1), // MAT3.1
todotani 0:692bf16d1455 73 };
todotani 0:692bf16d1455 74 #else
todotani 0:692bf16d1455 75 const uint32_t GPDMA_LUTPerAddr[] = {
todotani 0:692bf16d1455 76 ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx
todotani 0:692bf16d1455 77 ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx
todotani 0:692bf16d1455 78 ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx
todotani 0:692bf16d1455 79 ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx
todotani 0:692bf16d1455 80 ((uint32_t)&LPC_ADC->ADGDR), // ADC
todotani 0:692bf16d1455 81 ((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx
todotani 0:692bf16d1455 82 ((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx
todotani 0:692bf16d1455 83 ((uint32_t)&LPC_DAC->DACR), // DAC
todotani 0:692bf16d1455 84 ((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx
todotani 0:692bf16d1455 85 ((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx
todotani 0:692bf16d1455 86 ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
todotani 0:692bf16d1455 87 ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
todotani 0:692bf16d1455 88 ((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx
todotani 0:692bf16d1455 89 ((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx
todotani 0:692bf16d1455 90 ((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx
todotani 0:692bf16d1455 91 ((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx
todotani 0:692bf16d1455 92 ((uint32_t)&LPC_TIM0->MR0), // MAT0.0
todotani 0:692bf16d1455 93 ((uint32_t)&LPC_TIM0->MR1), // MAT0.1
todotani 0:692bf16d1455 94 ((uint32_t)&LPC_TIM1->MR0), // MAT1.0
todotani 0:692bf16d1455 95 ((uint32_t)&LPC_TIM1->MR1), // MAT1.1
todotani 0:692bf16d1455 96 ((uint32_t)&LPC_TIM2->MR0), // MAT2.0
todotani 0:692bf16d1455 97 ((uint32_t)&LPC_TIM2->MR1), // MAT2.1
todotani 0:692bf16d1455 98 ((uint32_t)&LPC_TIM3->MR0), // MAT3.0
todotani 0:692bf16d1455 99 ((uint32_t)&LPC_TIM3->MR1), // MAT3.1
todotani 0:692bf16d1455 100 };
todotani 0:692bf16d1455 101 #endif
todotani 0:692bf16d1455 102 /**
todotani 0:692bf16d1455 103 * @brief Lookup Table of GPDMA Channel Number matched with
todotani 0:692bf16d1455 104 * GPDMA channel pointer
todotani 0:692bf16d1455 105 */
todotani 0:692bf16d1455 106 const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
todotani 0:692bf16d1455 107 LPC_GPDMACH0, // GPDMA Channel 0
todotani 0:692bf16d1455 108 LPC_GPDMACH1, // GPDMA Channel 1
todotani 0:692bf16d1455 109 LPC_GPDMACH2, // GPDMA Channel 2
todotani 0:692bf16d1455 110 LPC_GPDMACH3, // GPDMA Channel 3
todotani 0:692bf16d1455 111 LPC_GPDMACH4, // GPDMA Channel 4
todotani 0:692bf16d1455 112 LPC_GPDMACH5, // GPDMA Channel 5
todotani 0:692bf16d1455 113 LPC_GPDMACH6, // GPDMA Channel 6
todotani 0:692bf16d1455 114 LPC_GPDMACH7, // GPDMA Channel 7
todotani 0:692bf16d1455 115 };
todotani 0:692bf16d1455 116 /**
todotani 0:692bf16d1455 117 * @brief Optimized Peripheral Source and Destination burst size
todotani 0:692bf16d1455 118 */
todotani 0:692bf16d1455 119 const uint8_t GPDMA_LUTPerBurst[] = {
todotani 0:692bf16d1455 120 GPDMA_BSIZE_4, // SSP0 Tx
todotani 0:692bf16d1455 121 GPDMA_BSIZE_4, // SSP0 Rx
todotani 0:692bf16d1455 122 GPDMA_BSIZE_4, // SSP1 Tx
todotani 0:692bf16d1455 123 GPDMA_BSIZE_4, // SSP1 Rx
todotani 0:692bf16d1455 124 GPDMA_BSIZE_4, // ADC
todotani 0:692bf16d1455 125 GPDMA_BSIZE_32, // I2S channel 0
todotani 0:692bf16d1455 126 GPDMA_BSIZE_32, // I2S channel 1
todotani 0:692bf16d1455 127 GPDMA_BSIZE_1, // DAC
todotani 0:692bf16d1455 128 GPDMA_BSIZE_1, // UART0 Tx
todotani 0:692bf16d1455 129 GPDMA_BSIZE_1, // UART0 Rx
todotani 0:692bf16d1455 130 GPDMA_BSIZE_1, // UART1 Tx
todotani 0:692bf16d1455 131 GPDMA_BSIZE_1, // UART1 Rx
todotani 0:692bf16d1455 132 GPDMA_BSIZE_1, // UART2 Tx
todotani 0:692bf16d1455 133 GPDMA_BSIZE_1, // UART2 Rx
todotani 0:692bf16d1455 134 GPDMA_BSIZE_1, // UART3 Tx
todotani 0:692bf16d1455 135 GPDMA_BSIZE_1, // UART3 Rx
todotani 0:692bf16d1455 136 GPDMA_BSIZE_1, // MAT0.0
todotani 0:692bf16d1455 137 GPDMA_BSIZE_1, // MAT0.1
todotani 0:692bf16d1455 138 GPDMA_BSIZE_1, // MAT1.0
todotani 0:692bf16d1455 139 GPDMA_BSIZE_1, // MAT1.1
todotani 0:692bf16d1455 140 GPDMA_BSIZE_1, // MAT2.0
todotani 0:692bf16d1455 141 GPDMA_BSIZE_1, // MAT2.1
todotani 0:692bf16d1455 142 GPDMA_BSIZE_1, // MAT3.0
todotani 0:692bf16d1455 143 GPDMA_BSIZE_1, // MAT3.1
todotani 0:692bf16d1455 144 };
todotani 0:692bf16d1455 145 /**
todotani 0:692bf16d1455 146 * @brief Optimized Peripheral Source and Destination transfer width
todotani 0:692bf16d1455 147 */
todotani 0:692bf16d1455 148 const uint8_t GPDMA_LUTPerWid[] = {
todotani 0:692bf16d1455 149 GPDMA_WIDTH_BYTE, // SSP0 Tx
todotani 0:692bf16d1455 150 GPDMA_WIDTH_BYTE, // SSP0 Rx
todotani 0:692bf16d1455 151 GPDMA_WIDTH_BYTE, // SSP1 Tx
todotani 0:692bf16d1455 152 GPDMA_WIDTH_BYTE, // SSP1 Rx
todotani 0:692bf16d1455 153 GPDMA_WIDTH_WORD, // ADC
todotani 0:692bf16d1455 154 GPDMA_WIDTH_WORD, // I2S channel 0
todotani 0:692bf16d1455 155 GPDMA_WIDTH_WORD, // I2S channel 1
todotani 0:692bf16d1455 156 GPDMA_WIDTH_BYTE, // DAC
todotani 0:692bf16d1455 157 GPDMA_WIDTH_BYTE, // UART0 Tx
todotani 0:692bf16d1455 158 GPDMA_WIDTH_BYTE, // UART0 Rx
todotani 0:692bf16d1455 159 GPDMA_WIDTH_BYTE, // UART1 Tx
todotani 0:692bf16d1455 160 GPDMA_WIDTH_BYTE, // UART1 Rx
todotani 0:692bf16d1455 161 GPDMA_WIDTH_BYTE, // UART2 Tx
todotani 0:692bf16d1455 162 GPDMA_WIDTH_BYTE, // UART2 Rx
todotani 0:692bf16d1455 163 GPDMA_WIDTH_BYTE, // UART3 Tx
todotani 0:692bf16d1455 164 GPDMA_WIDTH_BYTE, // UART3 Rx
todotani 0:692bf16d1455 165 GPDMA_WIDTH_WORD, // MAT0.0
todotani 0:692bf16d1455 166 GPDMA_WIDTH_WORD, // MAT0.1
todotani 0:692bf16d1455 167 GPDMA_WIDTH_WORD, // MAT1.0
todotani 0:692bf16d1455 168 GPDMA_WIDTH_WORD, // MAT1.1
todotani 0:692bf16d1455 169 GPDMA_WIDTH_WORD, // MAT2.0
todotani 0:692bf16d1455 170 GPDMA_WIDTH_WORD, // MAT2.1
todotani 0:692bf16d1455 171 GPDMA_WIDTH_WORD, // MAT3.0
todotani 0:692bf16d1455 172 GPDMA_WIDTH_WORD, // MAT3.1
todotani 0:692bf16d1455 173 };
todotani 0:692bf16d1455 174
todotani 0:692bf16d1455 175 /**
todotani 0:692bf16d1455 176 * @}
todotani 0:692bf16d1455 177 */
todotani 0:692bf16d1455 178
todotani 0:692bf16d1455 179 /* Public Functions ----------------------------------------------------------- */
todotani 0:692bf16d1455 180 /** @addtogroup GPDMA_Public_Functions
todotani 0:692bf16d1455 181 * @{
todotani 0:692bf16d1455 182 */
todotani 0:692bf16d1455 183
todotani 0:692bf16d1455 184 /********************************************************************//**
todotani 0:692bf16d1455 185 * @brief Initialize GPDMA controller
todotani 0:692bf16d1455 186 * @param None
todotani 0:692bf16d1455 187 * @return None
todotani 0:692bf16d1455 188 *********************************************************************/
todotani 0:692bf16d1455 189 void GPDMA_Init(void)
todotani 0:692bf16d1455 190 {
todotani 0:692bf16d1455 191 /* Enable GPDMA clock */
todotani 0:692bf16d1455 192 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);
todotani 0:692bf16d1455 193
todotani 0:692bf16d1455 194 // Reset all channel configuration register
todotani 0:692bf16d1455 195 LPC_GPDMACH0->DMACCConfig = 0;
todotani 0:692bf16d1455 196 LPC_GPDMACH1->DMACCConfig = 0;
todotani 0:692bf16d1455 197 LPC_GPDMACH2->DMACCConfig = 0;
todotani 0:692bf16d1455 198 LPC_GPDMACH3->DMACCConfig = 0;
todotani 0:692bf16d1455 199 LPC_GPDMACH4->DMACCConfig = 0;
todotani 0:692bf16d1455 200 LPC_GPDMACH5->DMACCConfig = 0;
todotani 0:692bf16d1455 201 LPC_GPDMACH6->DMACCConfig = 0;
todotani 0:692bf16d1455 202 LPC_GPDMACH7->DMACCConfig = 0;
todotani 0:692bf16d1455 203
todotani 0:692bf16d1455 204 /* Clear all DMA interrupt and error flag */
todotani 0:692bf16d1455 205 LPC_GPDMA->DMACIntTCClear = 0xFF;
todotani 0:692bf16d1455 206 LPC_GPDMA->DMACIntErrClr = 0xFF;
todotani 0:692bf16d1455 207 }
todotani 0:692bf16d1455 208
todotani 0:692bf16d1455 209 /********************************************************************//**
todotani 0:692bf16d1455 210 * @brief Setup GPDMA channel peripheral according to the specified
todotani 0:692bf16d1455 211 * parameters in the GPDMAChannelConfig.
todotani 0:692bf16d1455 212 * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
todotani 0:692bf16d1455 213 * structure that contains the configuration
todotani 0:692bf16d1455 214 * information for the specified GPDMA channel peripheral.
todotani 0:692bf16d1455 215 * @return ERROR if selected channel is enabled before
todotani 0:692bf16d1455 216 * or SUCCESS if channel is configured successfully
todotani 0:692bf16d1455 217 *********************************************************************/
todotani 0:692bf16d1455 218 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
todotani 0:692bf16d1455 219 {
todotani 0:692bf16d1455 220 LPC_GPDMACH_TypeDef *pDMAch;
todotani 0:692bf16d1455 221 uint32_t tmp1, tmp2;
todotani 0:692bf16d1455 222
todotani 0:692bf16d1455 223 if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
todotani 0:692bf16d1455 224 // This channel is enabled, return ERROR, need to release this channel first
todotani 0:692bf16d1455 225 return ERROR;
todotani 0:692bf16d1455 226 }
todotani 0:692bf16d1455 227
todotani 0:692bf16d1455 228 // Get Channel pointer
todotani 0:692bf16d1455 229 pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
todotani 0:692bf16d1455 230
todotani 0:692bf16d1455 231 // Reset the Interrupt status
todotani 0:692bf16d1455 232 LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
todotani 0:692bf16d1455 233 LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
todotani 0:692bf16d1455 234
todotani 0:692bf16d1455 235 // Clear DMA configure
todotani 0:692bf16d1455 236 pDMAch->DMACCControl = 0x00;
todotani 0:692bf16d1455 237 pDMAch->DMACCConfig = 0x00;
todotani 0:692bf16d1455 238
todotani 0:692bf16d1455 239 /* Assign Linker List Item value */
todotani 0:692bf16d1455 240 pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI;
todotani 0:692bf16d1455 241
todotani 0:692bf16d1455 242 /* Set value to Channel Control Registers */
todotani 0:692bf16d1455 243 switch (GPDMAChannelConfig->TransferType)
todotani 0:692bf16d1455 244 {
todotani 0:692bf16d1455 245 // Memory to memory
todotani 0:692bf16d1455 246 case GPDMA_TRANSFERTYPE_M2M:
todotani 0:692bf16d1455 247 // Assign physical source and destination address
todotani 0:692bf16d1455 248 pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
todotani 0:692bf16d1455 249 pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
todotani 0:692bf16d1455 250 pDMAch->DMACCControl
todotani 0:692bf16d1455 251 = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
todotani 0:692bf16d1455 252 | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
todotani 0:692bf16d1455 253 | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
todotani 0:692bf16d1455 254 | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
todotani 0:692bf16d1455 255 | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
todotani 0:692bf16d1455 256 | GPDMA_DMACCxControl_SI \
todotani 0:692bf16d1455 257 | GPDMA_DMACCxControl_DI \
todotani 0:692bf16d1455 258 | GPDMA_DMACCxControl_I;
todotani 0:692bf16d1455 259 break;
todotani 0:692bf16d1455 260 // Memory to peripheral
todotani 0:692bf16d1455 261 case GPDMA_TRANSFERTYPE_M2P:
todotani 0:692bf16d1455 262 // Assign physical source
todotani 0:692bf16d1455 263 pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
todotani 0:692bf16d1455 264 // Assign peripheral destination address
todotani 0:692bf16d1455 265 pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
todotani 0:692bf16d1455 266 pDMAch->DMACCControl
todotani 0:692bf16d1455 267 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
todotani 0:692bf16d1455 268 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
todotani 0:692bf16d1455 269 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
todotani 0:692bf16d1455 270 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
todotani 0:692bf16d1455 271 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
todotani 0:692bf16d1455 272 | GPDMA_DMACCxControl_SI \
todotani 0:692bf16d1455 273 | GPDMA_DMACCxControl_I;
todotani 0:692bf16d1455 274 break;
todotani 0:692bf16d1455 275 // Peripheral to memory
todotani 0:692bf16d1455 276 case GPDMA_TRANSFERTYPE_P2M:
todotani 0:692bf16d1455 277 // Assign peripheral source address
todotani 0:692bf16d1455 278 pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
todotani 0:692bf16d1455 279 // Assign memory destination address
todotani 0:692bf16d1455 280 pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
todotani 0:692bf16d1455 281 pDMAch->DMACCControl
todotani 0:692bf16d1455 282 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
todotani 0:692bf16d1455 283 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
todotani 0:692bf16d1455 284 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
todotani 0:692bf16d1455 285 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
todotani 0:692bf16d1455 286 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
todotani 0:692bf16d1455 287 | GPDMA_DMACCxControl_DI \
todotani 0:692bf16d1455 288 | GPDMA_DMACCxControl_I;
todotani 0:692bf16d1455 289 break;
todotani 0:692bf16d1455 290 // Peripheral to peripheral
todotani 0:692bf16d1455 291 case GPDMA_TRANSFERTYPE_P2P:
todotani 0:692bf16d1455 292 // Assign peripheral source address
todotani 0:692bf16d1455 293 pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
todotani 0:692bf16d1455 294 // Assign peripheral destination address
todotani 0:692bf16d1455 295 pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
todotani 0:692bf16d1455 296 pDMAch->DMACCControl
todotani 0:692bf16d1455 297 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
todotani 0:692bf16d1455 298 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
todotani 0:692bf16d1455 299 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
todotani 0:692bf16d1455 300 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
todotani 0:692bf16d1455 301 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
todotani 0:692bf16d1455 302 | GPDMA_DMACCxControl_I;
todotani 0:692bf16d1455 303 break;
todotani 0:692bf16d1455 304 // Do not support any more transfer type, return ERROR
todotani 0:692bf16d1455 305 default:
todotani 0:692bf16d1455 306 return ERROR;
todotani 0:692bf16d1455 307 }
todotani 0:692bf16d1455 308
todotani 0:692bf16d1455 309 /* Re-Configure DMA Request Select for source peripheral */
todotani 0:692bf16d1455 310 if (GPDMAChannelConfig->SrcConn > 15)
todotani 0:692bf16d1455 311 {
todotani 0:692bf16d1455 312 DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16));
todotani 0:692bf16d1455 313 } else {
todotani 0:692bf16d1455 314 DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn - 8));
todotani 0:692bf16d1455 315 }
todotani 0:692bf16d1455 316
todotani 0:692bf16d1455 317 /* Re-Configure DMA Request Select for Destination peripheral */
todotani 0:692bf16d1455 318 if (GPDMAChannelConfig->DstConn > 15)
todotani 0:692bf16d1455 319 {
todotani 0:692bf16d1455 320 DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16));
todotani 0:692bf16d1455 321 } else {
todotani 0:692bf16d1455 322 DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn - 8));
todotani 0:692bf16d1455 323 }
todotani 0:692bf16d1455 324
todotani 0:692bf16d1455 325 /* Enable DMA channels, little endian */
todotani 0:692bf16d1455 326 LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E;
todotani 0:692bf16d1455 327 while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E));
todotani 0:692bf16d1455 328
todotani 0:692bf16d1455 329 // Calculate absolute value for Connection number
todotani 0:692bf16d1455 330 tmp1 = GPDMAChannelConfig->SrcConn;
todotani 0:692bf16d1455 331 tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
todotani 0:692bf16d1455 332 tmp2 = GPDMAChannelConfig->DstConn;
todotani 0:692bf16d1455 333 tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
todotani 0:692bf16d1455 334
todotani 0:692bf16d1455 335 // Configure DMA Channel, enable Error Counter and Terminate counter
todotani 0:692bf16d1455 336 pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
todotani 0:692bf16d1455 337 | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
todotani 0:692bf16d1455 338 | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
todotani 0:692bf16d1455 339 | GPDMA_DMACCxConfig_DestPeripheral(tmp2);
todotani 0:692bf16d1455 340
todotani 0:692bf16d1455 341 return SUCCESS;
todotani 0:692bf16d1455 342 }
todotani 0:692bf16d1455 343
todotani 0:692bf16d1455 344
todotani 0:692bf16d1455 345 /*********************************************************************//**
todotani 0:692bf16d1455 346 * @brief Enable/Disable DMA channel
todotani 0:692bf16d1455 347 * @param[in] channelNum GPDMA channel, should be in range from 0 to 7
todotani 0:692bf16d1455 348 * @param[in] NewState New State of this command, should be:
todotani 0:692bf16d1455 349 * - ENABLE.
todotani 0:692bf16d1455 350 * - DISABLE.
todotani 0:692bf16d1455 351 * @return None
todotani 0:692bf16d1455 352 **********************************************************************/
todotani 0:692bf16d1455 353 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
todotani 0:692bf16d1455 354 {
todotani 0:692bf16d1455 355 LPC_GPDMACH_TypeDef *pDMAch;
todotani 0:692bf16d1455 356
todotani 0:692bf16d1455 357 // Get Channel pointer
todotani 0:692bf16d1455 358 pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
todotani 0:692bf16d1455 359
todotani 0:692bf16d1455 360 if (NewState == ENABLE) {
todotani 0:692bf16d1455 361 pDMAch->DMACCConfig |= GPDMA_DMACCxConfig_E;
todotani 0:692bf16d1455 362 } else {
todotani 0:692bf16d1455 363 pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E;
todotani 0:692bf16d1455 364 }
todotani 0:692bf16d1455 365 }
todotani 0:692bf16d1455 366 /*********************************************************************//**
todotani 0:692bf16d1455 367 * @brief Check if corresponding channel does have an active interrupt
todotani 0:692bf16d1455 368 * request or not
todotani 0:692bf16d1455 369 * @param[in] type type of status, should be:
todotani 0:692bf16d1455 370 * - GPDMA_STAT_INT: GPDMA Interrupt Status
todotani 0:692bf16d1455 371 * - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status
todotani 0:692bf16d1455 372 * - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status
todotani 0:692bf16d1455 373 * - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status
todotani 0:692bf16d1455 374 * - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status
todotani 0:692bf16d1455 375 * - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status
todotani 0:692bf16d1455 376 * @param[in] channel GPDMA channel, should be in range from 0 to 7
todotani 0:692bf16d1455 377 * @return IntStatus status of DMA channel interrupt after masking
todotani 0:692bf16d1455 378 * Should be:
todotani 0:692bf16d1455 379 * - SET: the corresponding channel has no active interrupt request
todotani 0:692bf16d1455 380 * - RESET: the corresponding channel does have an active interrupt request
todotani 0:692bf16d1455 381 **********************************************************************/
todotani 0:692bf16d1455 382 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
todotani 0:692bf16d1455 383 {
todotani 0:692bf16d1455 384 CHECK_PARAM(PARAM_GPDMA_STAT(type));
todotani 0:692bf16d1455 385 CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
todotani 0:692bf16d1455 386
todotani 0:692bf16d1455 387 switch (type)
todotani 0:692bf16d1455 388 {
todotani 0:692bf16d1455 389 case GPDMA_STAT_INT: //check status of DMA channel interrupts
todotani 0:692bf16d1455 390 if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel)))
todotani 0:692bf16d1455 391 return SET;
todotani 0:692bf16d1455 392 return RESET;
todotani 0:692bf16d1455 393 case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
todotani 0:692bf16d1455 394 if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel))
todotani 0:692bf16d1455 395 return SET;
todotani 0:692bf16d1455 396 return RESET;
todotani 0:692bf16d1455 397 case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
todotani 0:692bf16d1455 398 if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel))
todotani 0:692bf16d1455 399 return SET;
todotani 0:692bf16d1455 400 return RESET;
todotani 0:692bf16d1455 401 case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
todotani 0:692bf16d1455 402 if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel))
todotani 0:692bf16d1455 403 return SET;
todotani 0:692bf16d1455 404 return RESET;
todotani 0:692bf16d1455 405 case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
todotani 0:692bf16d1455 406 if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel))
todotani 0:692bf16d1455 407 return SET;
todotani 0:692bf16d1455 408 return RESET;
todotani 0:692bf16d1455 409 default: //check enable status for DMA channels
todotani 0:692bf16d1455 410 if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel))
todotani 0:692bf16d1455 411 return SET;
todotani 0:692bf16d1455 412 return RESET;
todotani 0:692bf16d1455 413 }
todotani 0:692bf16d1455 414 }
todotani 0:692bf16d1455 415
todotani 0:692bf16d1455 416 /*********************************************************************//**
todotani 0:692bf16d1455 417 * @brief Clear one or more interrupt requests on DMA channels
todotani 0:692bf16d1455 418 * @param[in] type type of interrupt request, should be:
todotani 0:692bf16d1455 419 * - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear
todotani 0:692bf16d1455 420 * - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear
todotani 0:692bf16d1455 421 * @param[in] channel GPDMA channel, should be in range from 0 to 7
todotani 0:692bf16d1455 422 * @return None
todotani 0:692bf16d1455 423 **********************************************************************/
todotani 0:692bf16d1455 424 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
todotani 0:692bf16d1455 425 {
todotani 0:692bf16d1455 426 CHECK_PARAM(PARAM_GPDMA_STATCLR(type));
todotani 0:692bf16d1455 427 CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
todotani 0:692bf16d1455 428
todotani 0:692bf16d1455 429 if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
todotani 0:692bf16d1455 430 LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel);
todotani 0:692bf16d1455 431 else // clear the error interrupt request
todotani 0:692bf16d1455 432 LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel);
todotani 0:692bf16d1455 433 }
todotani 0:692bf16d1455 434
todotani 0:692bf16d1455 435 /**
todotani 0:692bf16d1455 436 * @}
todotani 0:692bf16d1455 437 */
todotani 0:692bf16d1455 438
todotani 0:692bf16d1455 439 #endif /* _GPDMA */
todotani 0:692bf16d1455 440
todotani 0:692bf16d1455 441 /**
todotani 0:692bf16d1455 442 * @}
todotani 0:692bf16d1455 443 */
todotani 0:692bf16d1455 444
todotani 0:692bf16d1455 445 /* --------------------------------- End Of File ------------------------------ */
todotani 0:692bf16d1455 446