Timothy Mulrooney / LMiC

first test

Dependents:   LoRaWAN-lmic-app_tjm

Fork of LMiC by Semtech

radio.cpp@7:29058a7ccf23, 2016-02-25 (annotated)

Committer:
tmulrooney
Date:
Thu Feb 25 21:28:23 2016 +0000
Revision:
7:29058a7ccf23
Parent:
6:eed5fd627a2b 
first successful join

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:62d1edcc13d1 1 /*******************************************************************************
mluis 1:d3b7bde3995c 2 * Copyright (c) 2014-2015 IBM Corporation.
mluis 0:62d1edcc13d1 3 * All rights reserved. This program and the accompanying materials
mluis 0:62d1edcc13d1 4 * are made available under the terms of the Eclipse Public License v1.0
mluis 0:62d1edcc13d1 5 * which accompanies this distribution, and is available at
mluis 0:62d1edcc13d1 6 * http://www.eclipse.org/legal/epl-v10.html
mluis 0:62d1edcc13d1 7 *
mluis 0:62d1edcc13d1 8 * Contributors:
mluis 0:62d1edcc13d1 9 * IBM Zurich Research Lab - initial API, implementation and documentation
mluis 0:62d1edcc13d1 10 * Semtech Apps Team - Modified to support the MBED sx1276 driver
mluis 0:62d1edcc13d1 11 * library.
mluis 0:62d1edcc13d1 12 * Possibility to use original or Semtech's MBED
mluis 0:62d1edcc13d1 13 * radio driver. The selection is done by setting
mluis 0:62d1edcc13d1 14 * USE_SMTC_RADIO_DRIVER preprocessing directive
mluis 0:62d1edcc13d1 15 * in lmic.h
mluis 0:62d1edcc13d1 16 *******************************************************************************/
mluis 1:d3b7bde3995c 17
mluis 0:62d1edcc13d1 18 #include "lmic.h"
tmulrooney 5:464c1f2d6cbb 19 #include "debug.h"
mluis 0:62d1edcc13d1 20
mluis 0:62d1edcc13d1 21 #if USE_SMTC_RADIO_DRIVER
tmulrooney 5:464c1f2d6cbb 22 #include "sx1272-hal.h"
mluis 0:62d1edcc13d1 23
mluis 0:62d1edcc13d1 24 /*!
mluis 1:d3b7bde3995c 25 * Syncword for lora networks
mluis 0:62d1edcc13d1 26 */
mluis 1:d3b7bde3995c 27 #define LORA_MAC_SYNCWORD 0x34
mluis 0:62d1edcc13d1 28
mluis 0:62d1edcc13d1 29 /*
mluis 0:62d1edcc13d1 30 * Callback functions prototypes
mluis 0:62d1edcc13d1 31 */
mluis 0:62d1edcc13d1 32 /*!
mluis 0:62d1edcc13d1 33 * @brief Function to be executed on Radio Tx Done event
mluis 0:62d1edcc13d1 34 */
mluis 0:62d1edcc13d1 35 void OnTxDone( void );
mluis 0:62d1edcc13d1 36
mluis 0:62d1edcc13d1 37 /*!
mluis 0:62d1edcc13d1 38 * @brief Function to be executed on Radio Rx Done event
mluis 0:62d1edcc13d1 39 */
mluis 0:62d1edcc13d1 40 void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr );
mluis 0:62d1edcc13d1 41
mluis 0:62d1edcc13d1 42 /*!
mluis 0:62d1edcc13d1 43 * @brief Function executed on Radio Tx Timeout event
mluis 0:62d1edcc13d1 44 */
mluis 0:62d1edcc13d1 45 void OnTxTimeout( void );
mluis 0:62d1edcc13d1 46
mluis 0:62d1edcc13d1 47 /*!
mluis 0:62d1edcc13d1 48 * @brief Function executed on Radio Rx Timeout event
mluis 0:62d1edcc13d1 49 */
mluis 0:62d1edcc13d1 50 void OnRxTimeout( void );
mluis 0:62d1edcc13d1 51
mluis 0:62d1edcc13d1 52 /*!
mluis 0:62d1edcc13d1 53 * @brief Function executed on Radio Rx Error event
mluis 0:62d1edcc13d1 54 */
mluis 0:62d1edcc13d1 55 void OnRxError( void );
mluis 0:62d1edcc13d1 56
mluis 0:62d1edcc13d1 57 /*!
mluis 0:62d1edcc13d1 58 * @brief Function executed on Radio Fhss Change Channel event
mluis 0:62d1edcc13d1 59 */
mluis 0:62d1edcc13d1 60 void OnFhssChangeChannel( uint8_t channelIndex );
mluis 0:62d1edcc13d1 61
mluis 0:62d1edcc13d1 62 /*!
mluis 0:62d1edcc13d1 63 * @brief Function executed on CAD Done event
mluis 0:62d1edcc13d1 64 */
mluis 0:62d1edcc13d1 65 void OnCadDone( void );
mluis 0:62d1edcc13d1 66
mluis 3:519c71d29a06 67 /*!
mluis 3:519c71d29a06 68 * Radio events function pointer
mluis 3:519c71d29a06 69 */
mluis 3:519c71d29a06 70 static RadioEvents_t RadioEvents;
mluis 3:519c71d29a06 71
mluis 0:62d1edcc13d1 72 /*
mluis 0:62d1edcc13d1 73 * Radio object declraration
mluis 0:62d1edcc13d1 74 */
tmulrooney 5:464c1f2d6cbb 75 //SX1272MB1xAS Radio( NULL );
tmulrooney 5:464c1f2d6cbb 76 SX1272MB1xAS *Radio;
mluis 0:62d1edcc13d1 77
mluis 0:62d1edcc13d1 78 static const u2_t LORA_RXDONE_FIXUP[] = {
mluis 0:62d1edcc13d1 79 [FSK] = us2osticks(0), // ( 0 ticks)
mluis 0:62d1edcc13d1 80 [SF7] = us2osticks(0), // ( 0 ticks)
mluis 0:62d1edcc13d1 81 [SF8] = us2osticks(1648), // ( 54 ticks)
mluis 0:62d1edcc13d1 82 [SF9] = us2osticks(3265), // ( 107 ticks)
mluis 0:62d1edcc13d1 83 [SF10] = us2osticks(7049), // ( 231 ticks)
mluis 0:62d1edcc13d1 84 [SF11] = us2osticks(13641), // ( 447 ticks)
mluis 0:62d1edcc13d1 85 [SF12] = us2osticks(31189), // (1022 ticks)
mluis 0:62d1edcc13d1 86 };
mluis 0:62d1edcc13d1 87
mluis 0:62d1edcc13d1 88 void OnTxDone( void )
mluis 0:62d1edcc13d1 89 {
tmulrooney 5:464c1f2d6cbb 90 debug("OnTxDone enter\r\n");
mluis 0:62d1edcc13d1 91 ostime_t now = os_getTime( );
mluis 0:62d1edcc13d1 92 // save exact tx time
mluis 1:d3b7bde3995c 93 LMIC.txend = now - us2osticks( RADIO_WAKEUP_TIME ); // TXDONE FIXUP
mluis 0:62d1edcc13d1 94
mluis 0:62d1edcc13d1 95 // go from stanby to sleep
tmulrooney 5:464c1f2d6cbb 96 Radio->Sleep( );
mluis 0:62d1edcc13d1 97 // run os job (use preset func ptr)
mluis 0:62d1edcc13d1 98 os_setCallback( &LMIC.osjob, LMIC.osjob.func );
mluis 0:62d1edcc13d1 99 }
mluis 0:62d1edcc13d1 100
mluis 0:62d1edcc13d1 101 void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr )
mluis 0:62d1edcc13d1 102 {
tmulrooney 5:464c1f2d6cbb 103 debug("OnRxDone enter\r\n");
mluis 0:62d1edcc13d1 104 ostime_t now = os_getTime( );
mluis 0:62d1edcc13d1 105 // save exact rx time
mluis 1:d3b7bde3995c 106 if( getBw( LMIC.rps ) == BW125 )
mluis 1:d3b7bde3995c 107 {
mluis 1:d3b7bde3995c 108 now -= LORA_RXDONE_FIXUP[getSf( LMIC.rps )];
mluis 1:d3b7bde3995c 109 }
mluis 1:d3b7bde3995c 110 LMIC.rxtime = now;
mluis 0:62d1edcc13d1 111 // read the PDU and inform the MAC that we received something
mluis 0:62d1edcc13d1 112 LMIC.dataLen = size;
mluis 0:62d1edcc13d1 113 // now read the FIFO
mluis 0:62d1edcc13d1 114 memcpy( LMIC.frame, payload, size );
mluis 0:62d1edcc13d1 115 // read rx quality parameters
mluis 1:d3b7bde3995c 116 LMIC.snr = snr; // SNR [dB] * 4
mluis 1:d3b7bde3995c 117 LMIC.rssi = rssi; // RSSI [dBm] (-196...+63)
mluis 0:62d1edcc13d1 118
mluis 0:62d1edcc13d1 119 // go from stanby to sleep
tmulrooney 5:464c1f2d6cbb 120 Radio->Sleep( );
mluis 0:62d1edcc13d1 121 // run os job (use preset func ptr)
mluis 0:62d1edcc13d1 122 os_setCallback( &LMIC.osjob, LMIC.osjob.func );
mluis 0:62d1edcc13d1 123 }
mluis 0:62d1edcc13d1 124
mluis 0:62d1edcc13d1 125 void OnTxTimeout( void )
mluis 0:62d1edcc13d1 126 {
tmulrooney 5:464c1f2d6cbb 127 debug("OnTxTimeout enter\r\n");
tmulrooney 5:464c1f2d6cbb 128 ostime_t now = os_getTime( );
mluis 0:62d1edcc13d1 129
mluis 0:62d1edcc13d1 130 // indicate error
mluis 1:d3b7bde3995c 131 LMIC.dataLen = 0;
mluis 1:d3b7bde3995c 132
mluis 0:62d1edcc13d1 133 // go from stanby to sleep
tmulrooney 5:464c1f2d6cbb 134 Radio->Sleep( );
mluis 0:62d1edcc13d1 135 // run os job (use preset func ptr)
mluis 0:62d1edcc13d1 136 os_setCallback( &LMIC.osjob, LMIC.osjob.func );
mluis 0:62d1edcc13d1 137 }
mluis 0:62d1edcc13d1 138
mluis 0:62d1edcc13d1 139 void OnRxTimeout( void )
mluis 0:62d1edcc13d1 140 {
tmulrooney 5:464c1f2d6cbb 141 debug("OnRxTimeout enter\r\n");
tmulrooney 5:464c1f2d6cbb 142 ostime_t now = os_getTime( );
mluis 0:62d1edcc13d1 143 // indicate timeout
mluis 0:62d1edcc13d1 144 LMIC.dataLen = 0;
mluis 0:62d1edcc13d1 145
mluis 0:62d1edcc13d1 146 // go from stanby to sleep
tmulrooney 5:464c1f2d6cbb 147 Radio->Sleep( );
mluis 0:62d1edcc13d1 148 // run os job (use preset func ptr)
mluis 0:62d1edcc13d1 149 os_setCallback( &LMIC.osjob, LMIC.osjob.func );
mluis 0:62d1edcc13d1 150 }
mluis 0:62d1edcc13d1 151
mluis 0:62d1edcc13d1 152 void OnRxError( void )
mluis 0:62d1edcc13d1 153 {
tmulrooney 5:464c1f2d6cbb 154 debug("OnRxError enter\r\n");
mluis 0:62d1edcc13d1 155 ostime_t now = os_getTime( );
mluis 0:62d1edcc13d1 156
mluis 0:62d1edcc13d1 157 // indicate error
mluis 0:62d1edcc13d1 158 LMIC.dataLen = 0;
mluis 0:62d1edcc13d1 159
mluis 0:62d1edcc13d1 160 // go from stanby to sleep
tmulrooney 5:464c1f2d6cbb 161 Radio->Sleep( );
mluis 0:62d1edcc13d1 162 // run os job (use preset func ptr)
mluis 0:62d1edcc13d1 163 os_setCallback( &LMIC.osjob, LMIC.osjob.func );
mluis 0:62d1edcc13d1 164 }
mluis 0:62d1edcc13d1 165
mluis 0:62d1edcc13d1 166 /*!
mluis 0:62d1edcc13d1 167 * LMIC API implementation
mluis 0:62d1edcc13d1 168 */
mluis 0:62d1edcc13d1 169 // RADIO STATE
mluis 0:62d1edcc13d1 170 // (initialized by radio_init( ), used by radio_rand1( ))
mluis 0:62d1edcc13d1 171 static u1_t randbuf[16];
mluis 0:62d1edcc13d1 172
mluis 0:62d1edcc13d1 173 // get random seed from wideband noise rssi
mluis 0:62d1edcc13d1 174 void radio_init( void )
mluis 0:62d1edcc13d1 175 {
tmulrooney 6:eed5fd627a2b 176 debug("radio_init1 enter\r\n");
tmulrooney 6:eed5fd627a2b 177 Radio = new SX1272MB1xAS(NULL);
tmulrooney 6:eed5fd627a2b 178 hal_disableIRQs( );
mluis 3:519c71d29a06 179
mluis 3:519c71d29a06 180 // Initialize Radio driver
mluis 3:519c71d29a06 181 RadioEvents.TxDone = OnTxDone;
mluis 3:519c71d29a06 182 RadioEvents.RxDone = OnRxDone;
mluis 3:519c71d29a06 183 RadioEvents.RxError = OnRxError;
mluis 3:519c71d29a06 184 RadioEvents.TxTimeout = OnTxTimeout;
mluis 3:519c71d29a06 185 RadioEvents.RxTimeout = OnRxTimeout;
tmulrooney 5:464c1f2d6cbb 186 Radio->Init( &RadioEvents );
mluis 0:62d1edcc13d1 187
mluis 0:62d1edcc13d1 188 // seed 15-byte randomness via noise rssi
mluis 0:62d1edcc13d1 189 // Set LoRa modem ON
tmulrooney 5:464c1f2d6cbb 190 Radio->SetModem( MODEM_LORA );
mluis 0:62d1edcc13d1 191 // Disable LoRa modem interrupts
tmulrooney 5:464c1f2d6cbb 192 Radio->Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:62d1edcc13d1 193 RFLR_IRQFLAGS_RXDONE |
mluis 0:62d1edcc13d1 194 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:62d1edcc13d1 195 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:62d1edcc13d1 196 RFLR_IRQFLAGS_TXDONE |
mluis 0:62d1edcc13d1 197 RFLR_IRQFLAGS_CADDONE |
mluis 0:62d1edcc13d1 198 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:62d1edcc13d1 199 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:62d1edcc13d1 200
mluis 0:62d1edcc13d1 201 // Set radio in continuous reception
tmulrooney 5:464c1f2d6cbb 202 Radio->Rx( 0 );
mluis 0:62d1edcc13d1 203
mluis 0:62d1edcc13d1 204 for( int i = 1; i < 16; i++ )
mluis 0:62d1edcc13d1 205 {
mluis 0:62d1edcc13d1 206 for( int j = 0; j < 8; j++ )
mluis 0:62d1edcc13d1 207 {
mluis 0:62d1edcc13d1 208 u1_t b; // wait for two non-identical subsequent least-significant bits
tmulrooney 5:464c1f2d6cbb 209 while( ( b = Radio->Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) == ( Radio->Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) );
mluis 0:62d1edcc13d1 210 randbuf[i] = ( randbuf[i] << 1 ) | b;
mluis 0:62d1edcc13d1 211 }
mluis 0:62d1edcc13d1 212 }
mluis 0:62d1edcc13d1 213 randbuf[0] = 16; // set initial index
mluis 0:62d1edcc13d1 214
mluis 0:62d1edcc13d1 215 // Change LoRa modem SyncWord
tmulrooney 5:464c1f2d6cbb 216 Radio->Write( REG_LR_SYNCWORD, LORA_MAC_SYNCWORD );
mluis 0:62d1edcc13d1 217
tmulrooney 5:464c1f2d6cbb 218 Radio->Sleep( );
mluis 0:62d1edcc13d1 219
mluis 0:62d1edcc13d1 220 hal_enableIRQs( );
tmulrooney 5:464c1f2d6cbb 221 debug("radio_init exit\r\n");
mluis 0:62d1edcc13d1 222 }
mluis 0:62d1edcc13d1 223
mluis 0:62d1edcc13d1 224 // return next random byte derived from seed buffer
mluis 0:62d1edcc13d1 225 // (buf[0] holds index of next byte to be returned)
mluis 0:62d1edcc13d1 226 u1_t radio_rand1( void )
mluis 0:62d1edcc13d1 227 {
tmulrooney 5:464c1f2d6cbb 228 debug("radio_rand1 enter\r\n");
mluis 0:62d1edcc13d1 229 u1_t i = randbuf[0];
mluis 0:62d1edcc13d1 230 ASSERT( i != 0 );
mluis 0:62d1edcc13d1 231 if( i == 16 )
mluis 0:62d1edcc13d1 232 {
mluis 0:62d1edcc13d1 233 os_aes( AES_ENC, randbuf, 16 ); // encrypt seed with any key
mluis 0:62d1edcc13d1 234 i = 0;
mluis 0:62d1edcc13d1 235 }
mluis 0:62d1edcc13d1 236 u1_t v = randbuf[i++];
mluis 0:62d1edcc13d1 237 randbuf[0] = i;
mluis 0:62d1edcc13d1 238 return v;
mluis 0:62d1edcc13d1 239 }
mluis 0:62d1edcc13d1 240
mluis 0:62d1edcc13d1 241 void os_radio( u1_t mode )
mluis 0:62d1edcc13d1 242 {
tmulrooney 7:29058a7ccf23 243 //debug_val("os_radio enter ",mode);
mluis 0:62d1edcc13d1 244 hal_disableIRQs( );
mluis 0:62d1edcc13d1 245 switch( mode )
mluis 0:62d1edcc13d1 246 {
mluis 0:62d1edcc13d1 247 case RADIO_RST:
mluis 0:62d1edcc13d1 248 // put radio to sleep
tmulrooney 5:464c1f2d6cbb 249 Radio->Sleep( );
mluis 0:62d1edcc13d1 250 break;
mluis 0:62d1edcc13d1 251
mluis 0:62d1edcc13d1 252 case RADIO_TX:
mluis 0:62d1edcc13d1 253 // transmit frame now
mluis 0:62d1edcc13d1 254 //ASSERT( Radio.GetState( ) == IDLE );
mluis 0:62d1edcc13d1 255
tmulrooney 5:464c1f2d6cbb 256 Radio->SetChannel( LMIC.freq );
mluis 0:62d1edcc13d1 257 if( getSf( LMIC.rps ) == FSK )
mluis 0:62d1edcc13d1 258 { // FSK modem
tmulrooney 5:464c1f2d6cbb 259 Radio->SetTxConfig( MODEM_FSK, LMIC.txpow, 25e3, 0, 50e3, 0, 5, false, true, 0, 0, false, 3e6 );
mluis 0:62d1edcc13d1 260 }
mluis 0:62d1edcc13d1 261 else
mluis 0:62d1edcc13d1 262 { // LoRa modem
mluis 0:62d1edcc13d1 263
tmulrooney 5:464c1f2d6cbb 264 Radio->SetTxConfig( MODEM_LORA, LMIC.txpow, 0, getBw( LMIC.rps ), getSf( LMIC.rps ) + 6, getCr( LMIC.rps ) + 1, 8, getIh( LMIC.rps ) ? true : false, ( getNocrc( LMIC.rps ) == 0 ) ? true : false, 0, 0, false, 3e6 );
mluis 0:62d1edcc13d1 265 }
mluis 0:62d1edcc13d1 266
mluis 0:62d1edcc13d1 267 //starttx( ); // buf=LMIC.frame, len=LMIC.dataLen
tmulrooney 5:464c1f2d6cbb 268 Radio->Send( LMIC.frame, LMIC.dataLen );
mluis 0:62d1edcc13d1 269 break;
mluis 0:62d1edcc13d1 270
mluis 0:62d1edcc13d1 271 case RADIO_RX:
mluis 0:62d1edcc13d1 272 // receive frame now (exactly at rxtime)
mluis 0:62d1edcc13d1 273 //ASSERT( Radio.GetState( ) == IDLE );
mluis 0:62d1edcc13d1 274
tmulrooney 5:464c1f2d6cbb 275 Radio->SetChannel( LMIC.freq );
mluis 0:62d1edcc13d1 276 if( getSf( LMIC.rps ) == FSK )
mluis 0:62d1edcc13d1 277 { // FSK modem
mluis 0:62d1edcc13d1 278 //Radio.SetRxConfig( MODEM_FSK, 50e3, 50e3, 0, 83.333e3, 5, 0, false, 0, true, 0, 0, false, false );
tmulrooney 5:464c1f2d6cbb 279 Radio->SetRxConfig( MODEM_FSK, 50e3, 50e3, 0, 83.333e3, 5, 0, false, 0, true, 0, 0, false, true );
mluis 0:62d1edcc13d1 280 }
mluis 0:62d1edcc13d1 281 else
mluis 0:62d1edcc13d1 282 { // LoRa modem
mluis 1:d3b7bde3995c 283 if( ( getSf( LMIC.rps ) <= SF9 ) && ( LMIC.rxsyms < 8 ) )
mluis 1:d3b7bde3995c 284 {
tmulrooney 5:464c1f2d6cbb 285 Radio->SetRxConfig( MODEM_LORA, getBw( LMIC.rps ), getSf( LMIC.rps ) + 6, getCr( LMIC.rps ) + 1, 0, 8, LMIC.rxsyms + 3, getIh( LMIC.rps ) ? true : false, getIh( LMIC.rps ), ( getNocrc( LMIC.rps ) == 0 ) ? true : false, 0, 0, true, false );
mluis 1:d3b7bde3995c 286 }
mluis 1:d3b7bde3995c 287 else
mluis 1:d3b7bde3995c 288 {
tmulrooney 5:464c1f2d6cbb 289 Radio->SetRxConfig( MODEM_LORA, getBw( LMIC.rps ), getSf( LMIC.rps ) + 6, getCr( LMIC.rps ) + 1, 0, 8, LMIC.rxsyms, getIh( LMIC.rps ) ? true : false, getIh( LMIC.rps ), ( getNocrc( LMIC.rps ) == 0 ) ? true : false, 0, 0, true, false );
mluis 1:d3b7bde3995c 290 }
mluis 0:62d1edcc13d1 291 }
mluis 0:62d1edcc13d1 292
mluis 0:62d1edcc13d1 293 // now instruct the radio to receive
mluis 0:62d1edcc13d1 294 hal_waitUntil( LMIC.rxtime ); // busy wait until exact rx time
mluis 0:62d1edcc13d1 295
mluis 0:62d1edcc13d1 296 //startrx( RXMODE_SINGLE ); // buf = LMIC.frame, time = LMIC.rxtime, timeout=LMIC.rxsyms
mluis 0:62d1edcc13d1 297 if( getSf( LMIC.rps ) == FSK )
mluis 0:62d1edcc13d1 298 { // FSK modem
tmulrooney 5:464c1f2d6cbb 299 Radio->Rx( 50e3 ); // Max Rx window 50 ms
mluis 0:62d1edcc13d1 300 }
mluis 0:62d1edcc13d1 301 else
mluis 0:62d1edcc13d1 302 { // LoRa modem
tmulrooney 5:464c1f2d6cbb 303 Radio->Rx( 3e6 ); // Max Rx window 3 seconds
mluis 0:62d1edcc13d1 304 }
mluis 0:62d1edcc13d1 305 break;
mluis 0:62d1edcc13d1 306
mluis 0:62d1edcc13d1 307 case RADIO_RXON:
mluis 0:62d1edcc13d1 308 // start scanning for beacon now
mluis 0:62d1edcc13d1 309
mluis 0:62d1edcc13d1 310 //ASSERT( Radio.GetState( ) == IDLE );
mluis 0:62d1edcc13d1 311
tmulrooney 5:464c1f2d6cbb 312 Radio->SetChannel( LMIC.freq );
mluis 0:62d1edcc13d1 313 if( getSf( LMIC.rps ) == FSK )
mluis 0:62d1edcc13d1 314 { // FSK modem
tmulrooney 5:464c1f2d6cbb 315 Radio->SetRxConfig( MODEM_FSK, 50e3, 50e3, 0, 83.333e3, 5, 0, false, 0, true, 0, 0, false, true );
mluis 0:62d1edcc13d1 316 }
mluis 0:62d1edcc13d1 317 else
mluis 0:62d1edcc13d1 318 { // LoRa modem
tmulrooney 5:464c1f2d6cbb 319 Radio->SetRxConfig( MODEM_LORA, getBw( LMIC.rps ), getSf( LMIC.rps ) + 6, getCr( LMIC.rps ) + 1, 0, 8, LMIC.rxsyms, getIh( LMIC.rps ) ? true : false, getIh( LMIC.rps ), ( getNocrc( LMIC.rps ) == 0 ) ? true : false, 0, 0, true, true );
mluis 0:62d1edcc13d1 320 }
mluis 0:62d1edcc13d1 321
mluis 1:d3b7bde3995c 322 //startrx( RXMODE_SCAN ); // buf = LMIC.frame
tmulrooney 5:464c1f2d6cbb 323 Radio->Rx( 0 );
mluis 0:62d1edcc13d1 324 break;
mluis 0:62d1edcc13d1 325 }
mluis 0:62d1edcc13d1 326 hal_enableIRQs( );
mluis 0:62d1edcc13d1 327 }
mluis 0:62d1edcc13d1 328
mluis 0:62d1edcc13d1 329 #else
mluis 0:62d1edcc13d1 330
mluis 0:62d1edcc13d1 331 // ----------------------------------------
mluis 0:62d1edcc13d1 332 // Registers Mapping
mluis 0:62d1edcc13d1 333 #define RegFifo 0x00 // common
mluis 0:62d1edcc13d1 334 #define RegOpMode 0x01 // common
mluis 0:62d1edcc13d1 335 #define FSKRegBitrateMsb 0x02
mluis 0:62d1edcc13d1 336 #define FSKRegBitrateLsb 0x03
mluis 0:62d1edcc13d1 337 #define FSKRegFdevMsb 0x04
mluis 0:62d1edcc13d1 338 #define FSKRegFdevLsb 0x05
mluis 0:62d1edcc13d1 339 #define RegFrfMsb 0x06 // common
mluis 0:62d1edcc13d1 340 #define RegFrfMid 0x07 // common
mluis 0:62d1edcc13d1 341 #define RegFrfLsb 0x08 // common
mluis 0:62d1edcc13d1 342 #define RegPaConfig 0x09 // common
mluis 0:62d1edcc13d1 343 #define RegPaRamp 0x0A // common
mluis 0:62d1edcc13d1 344 #define RegOcp 0x0B // common
mluis 0:62d1edcc13d1 345 #define RegLna 0x0C // common
mluis 0:62d1edcc13d1 346 #define FSKRegRxConfig 0x0D
mluis 0:62d1edcc13d1 347 #define LORARegFifoAddrPtr 0x0D
mluis 0:62d1edcc13d1 348 #define FSKRegRssiConfig 0x0E
mluis 0:62d1edcc13d1 349 #define LORARegFifoTxBaseAddr 0x0E
mluis 0:62d1edcc13d1 350 #define FSKRegRssiCollision 0x0F
mluis 0:62d1edcc13d1 351 #define LORARegFifoRxBaseAddr 0x0F
mluis 0:62d1edcc13d1 352 #define FSKRegRssiThresh 0x10
mluis 0:62d1edcc13d1 353 #define LORARegFifoRxCurrentAddr 0x10
mluis 0:62d1edcc13d1 354 #define FSKRegRssiValue 0x11
mluis 0:62d1edcc13d1 355 #define LORARegIrqFlagsMask 0x11
mluis 0:62d1edcc13d1 356 #define FSKRegRxBw 0x12
mluis 0:62d1edcc13d1 357 #define LORARegIrqFlags 0x12
mluis 0:62d1edcc13d1 358 #define FSKRegAfcBw 0x13
mluis 0:62d1edcc13d1 359 #define LORARegRxNbBytes 0x13
mluis 0:62d1edcc13d1 360 #define FSKRegOokPeak 0x14
mluis 0:62d1edcc13d1 361 #define LORARegRxHeaderCntValueMsb 0x14
mluis 0:62d1edcc13d1 362 #define FSKRegOokFix 0x15
mluis 0:62d1edcc13d1 363 #define LORARegRxHeaderCntValueLsb 0x15
mluis 0:62d1edcc13d1 364 #define FSKRegOokAvg 0x16
mluis 0:62d1edcc13d1 365 #define LORARegRxPacketCntValueMsb 0x16
mluis 0:62d1edcc13d1 366 #define LORARegRxpacketCntValueLsb 0x17
mluis 0:62d1edcc13d1 367 #define LORARegModemStat 0x18
mluis 0:62d1edcc13d1 368 #define LORARegPktSnrValue 0x19
mluis 0:62d1edcc13d1 369 #define FSKRegAfcFei 0x1A
mluis 0:62d1edcc13d1 370 #define LORARegPktRssiValue 0x1A
mluis 0:62d1edcc13d1 371 #define FSKRegAfcMsb 0x1B
mluis 0:62d1edcc13d1 372 #define LORARegRssiValue 0x1B
mluis 0:62d1edcc13d1 373 #define FSKRegAfcLsb 0x1C
mluis 0:62d1edcc13d1 374 #define LORARegHopChannel 0x1C
mluis 0:62d1edcc13d1 375 #define FSKRegFeiMsb 0x1D
mluis 0:62d1edcc13d1 376 #define LORARegModemConfig1 0x1D
mluis 0:62d1edcc13d1 377 #define FSKRegFeiLsb 0x1E
mluis 0:62d1edcc13d1 378 #define LORARegModemConfig2 0x1E
mluis 0:62d1edcc13d1 379 #define FSKRegPreambleDetect 0x1F
mluis 0:62d1edcc13d1 380 #define LORARegSymbTimeoutLsb 0x1F
mluis 0:62d1edcc13d1 381 #define FSKRegRxTimeout1 0x20
mluis 0:62d1edcc13d1 382 #define LORARegPreambleMsb 0x20
mluis 0:62d1edcc13d1 383 #define FSKRegRxTimeout2 0x21
mluis 0:62d1edcc13d1 384 #define LORARegPreambleLsb 0x21
mluis 0:62d1edcc13d1 385 #define FSKRegRxTimeout3 0x22
mluis 0:62d1edcc13d1 386 #define LORARegPayloadLength 0x22
mluis 0:62d1edcc13d1 387 #define FSKRegRxDelay 0x23
mluis 0:62d1edcc13d1 388 #define LORARegPayloadMaxLength 0x23
mluis 0:62d1edcc13d1 389 #define FSKRegOsc 0x24
mluis 0:62d1edcc13d1 390 #define LORARegHopPeriod 0x24
mluis 0:62d1edcc13d1 391 #define FSKRegPreambleMsb 0x25
mluis 0:62d1edcc13d1 392 #define LORARegFifoRxByteAddr 0x25
mluis 0:62d1edcc13d1 393 #define LORARegModemConfig3 0x26
mluis 0:62d1edcc13d1 394 #define FSKRegPreambleLsb 0x26
mluis 0:62d1edcc13d1 395 #define FSKRegSyncConfig 0x27
mluis 0:62d1edcc13d1 396 #define LORARegFeiMsb 0x28
mluis 0:62d1edcc13d1 397 #define FSKRegSyncValue1 0x28
mluis 0:62d1edcc13d1 398 #define LORAFeiMib 0x29
mluis 0:62d1edcc13d1 399 #define FSKRegSyncValue2 0x29
mluis 0:62d1edcc13d1 400 #define LORARegFeiLsb 0x2A
mluis 0:62d1edcc13d1 401 #define FSKRegSyncValue3 0x2A
mluis 0:62d1edcc13d1 402 #define FSKRegSyncValue4 0x2B
mluis 0:62d1edcc13d1 403 #define LORARegRssiWideband 0x2C
mluis 0:62d1edcc13d1 404 #define FSKRegSyncValue5 0x2C
mluis 0:62d1edcc13d1 405 #define FSKRegSyncValue6 0x2D
mluis 0:62d1edcc13d1 406 #define FSKRegSyncValue7 0x2E
mluis 0:62d1edcc13d1 407 #define FSKRegSyncValue8 0x2F
mluis 0:62d1edcc13d1 408 #define FSKRegPacketConfig1 0x30
mluis 0:62d1edcc13d1 409 #define FSKRegPacketConfig2 0x31
mluis 0:62d1edcc13d1 410 #define LORARegDetectOptimize 0x31
mluis 0:62d1edcc13d1 411 #define FSKRegPayloadLength 0x32
mluis 0:62d1edcc13d1 412 #define FSKRegNodeAdrs 0x33
mluis 0:62d1edcc13d1 413 #define LORARegInvertIQ 0x33
mluis 0:62d1edcc13d1 414 #define FSKRegBroadcastAdrs 0x34
mluis 0:62d1edcc13d1 415 #define FSKRegFifoThresh 0x35
mluis 0:62d1edcc13d1 416 #define FSKRegSeqConfig1 0x36
mluis 0:62d1edcc13d1 417 #define FSKRegSeqConfig2 0x37
mluis 0:62d1edcc13d1 418 #define LORARegDetectionThreshold 0x37
mluis 0:62d1edcc13d1 419 #define FSKRegTimerResol 0x38
mluis 0:62d1edcc13d1 420 #define FSKRegTimer1Coef 0x39
mluis 0:62d1edcc13d1 421 #define LORARegSyncWord 0x39
mluis 0:62d1edcc13d1 422 #define FSKRegTimer2Coef 0x3A
mluis 0:62d1edcc13d1 423 #define FSKRegImageCal 0x3B
mluis 0:62d1edcc13d1 424 #define FSKRegTemp 0x3C
mluis 0:62d1edcc13d1 425 #define FSKRegLowBat 0x3D
mluis 0:62d1edcc13d1 426 #define FSKRegIrqFlags1 0x3E
mluis 0:62d1edcc13d1 427 #define FSKRegIrqFlags2 0x3F
mluis 0:62d1edcc13d1 428 #define RegDioMapping1 0x40 // common
mluis 0:62d1edcc13d1 429 #define RegDioMapping2 0x41 // common
mluis 0:62d1edcc13d1 430 #define RegVersion 0x42 // common
mluis 0:62d1edcc13d1 431 // #define RegAgcRef 0x43 // common
mluis 0:62d1edcc13d1 432 // #define RegAgcThresh1 0x44 // common
mluis 0:62d1edcc13d1 433 // #define RegAgcThresh2 0x45 // common
mluis 0:62d1edcc13d1 434 // #define RegAgcThresh3 0x46 // common
mluis 0:62d1edcc13d1 435 // #define RegPllHop 0x4B // common
mluis 0:62d1edcc13d1 436 // #define RegTcxo 0x58 // common
mluis 0:62d1edcc13d1 437 #define RegPaDac 0x5A // common
mluis 0:62d1edcc13d1 438 // #define RegPll 0x5C // common
mluis 0:62d1edcc13d1 439 // #define RegPllLowPn 0x5E // common
mluis 0:62d1edcc13d1 440 // #define RegFormerTemp 0x6C // common
mluis 0:62d1edcc13d1 441 // #define RegBitRateFrac 0x70 // common
mluis 0:62d1edcc13d1 442
mluis 0:62d1edcc13d1 443 // ----------------------------------------
mluis 0:62d1edcc13d1 444 // spread factors and mode for RegModemConfig2
mluis 0:62d1edcc13d1 445 #define SX1272_MC2_FSK 0x00
mluis 0:62d1edcc13d1 446 #define SX1272_MC2_SF7 0x70
mluis 0:62d1edcc13d1 447 #define SX1272_MC2_SF8 0x80
mluis 0:62d1edcc13d1 448 #define SX1272_MC2_SF9 0x90
mluis 0:62d1edcc13d1 449 #define SX1272_MC2_SF10 0xA0
mluis 0:62d1edcc13d1 450 #define SX1272_MC2_SF11 0xB0
mluis 0:62d1edcc13d1 451 #define SX1272_MC2_SF12 0xC0
mluis 0:62d1edcc13d1 452 // bandwidth for RegModemConfig1
mluis 0:62d1edcc13d1 453 #define SX1272_MC1_BW_125 0x00
mluis 0:62d1edcc13d1 454 #define SX1272_MC1_BW_250 0x40
mluis 0:62d1edcc13d1 455 #define SX1272_MC1_BW_500 0x80
mluis 0:62d1edcc13d1 456 // coding rate for RegModemConfig1
mluis 0:62d1edcc13d1 457 #define SX1272_MC1_CR_4_5 0x08
mluis 0:62d1edcc13d1 458 #define SX1272_MC1_CR_4_6 0x10
mluis 0:62d1edcc13d1 459 #define SX1272_MC1_CR_4_7 0x18
mluis 0:62d1edcc13d1 460 #define SX1272_MC1_CR_4_8 0x20
mluis 0:62d1edcc13d1 461 #define SX1272_MC1_IMPLICIT_HEADER_MODE_ON 0x04 // required for receive
mluis 0:62d1edcc13d1 462 #define SX1272_MC1_RX_PAYLOAD_CRCON 0x02
mluis 0:62d1edcc13d1 463 #define SX1272_MC1_LOW_DATA_RATE_OPTIMIZE 0x01 // mandated for SF11 and SF12
mluis 0:62d1edcc13d1 464 // transmit power configuration for RegPaConfig
mluis 0:62d1edcc13d1 465 #define SX1272_PAC_PA_SELECT_PA_BOOST 0x80
mluis 0:62d1edcc13d1 466 #define SX1272_PAC_PA_SELECT_RFIO_PIN 0x00
mluis 0:62d1edcc13d1 467
mluis 0:62d1edcc13d1 468
mluis 0:62d1edcc13d1 469 // sx1276 RegModemConfig1
mluis 0:62d1edcc13d1 470 #define SX1276_MC1_BW_125 0x70
mluis 0:62d1edcc13d1 471 #define SX1276_MC1_BW_250 0x80
mluis 0:62d1edcc13d1 472 #define SX1276_MC1_BW_500 0x90
mluis 0:62d1edcc13d1 473 #define SX1276_MC1_CR_4_5 0x02
mluis 0:62d1edcc13d1 474 #define SX1276_MC1_CR_4_6 0x04
mluis 0:62d1edcc13d1 475 #define SX1276_MC1_CR_4_7 0x06
mluis 0:62d1edcc13d1 476 #define SX1276_MC1_CR_4_8 0x08
mluis 0:62d1edcc13d1 477
mluis 0:62d1edcc13d1 478 #define SX1276_MC1_IMPLICIT_HEADER_MODE_ON 0x01
mluis 0:62d1edcc13d1 479
mluis 0:62d1edcc13d1 480 // sx1276 RegModemConfig2
mluis 0:62d1edcc13d1 481 #define SX1276_MC2_RX_PAYLOAD_CRCON 0x04
mluis 0:62d1edcc13d1 482
mluis 0:62d1edcc13d1 483 // sx1276 RegModemConfig3
mluis 0:62d1edcc13d1 484 #define SX1276_MC3_LOW_DATA_RATE_OPTIMIZE 0x08
mluis 0:62d1edcc13d1 485 #define SX1276_MC3_AGCAUTO 0x04
mluis 0:62d1edcc13d1 486
mluis 0:62d1edcc13d1 487 // preamble for lora networks (nibbles swapped)
mluis 1:d3b7bde3995c 488 #define LORA_MAC_PREAMBLE 0x34
mluis 0:62d1edcc13d1 489
mluis 0:62d1edcc13d1 490 #define RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG1 0x0A
mluis 0:62d1edcc13d1 491 #ifdef CFG_sx1276_radio
mluis 0:62d1edcc13d1 492 #define RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG2 0x70
mluis 0:62d1edcc13d1 493 #elif CFG_sx1272_radio
mluis 0:62d1edcc13d1 494 #define RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG2 0x74
mluis 0:62d1edcc13d1 495 #endif
mluis 0:62d1edcc13d1 496
mluis 0:62d1edcc13d1 497
mluis 0:62d1edcc13d1 498
mluis 0:62d1edcc13d1 499 // ----------------------------------------
mluis 0:62d1edcc13d1 500 // Constants for radio registers
mluis 0:62d1edcc13d1 501 #define OPMODE_LORA 0x80
mluis 0:62d1edcc13d1 502 #define OPMODE_MASK 0x07
mluis 0:62d1edcc13d1 503 #define OPMODE_SLEEP 0x00
mluis 0:62d1edcc13d1 504 #define OPMODE_STANDBY 0x01
mluis 0:62d1edcc13d1 505 #define OPMODE_FSTX 0x02
mluis 0:62d1edcc13d1 506 #define OPMODE_TX 0x03
mluis 0:62d1edcc13d1 507 #define OPMODE_FSRX 0x04
mluis 0:62d1edcc13d1 508 #define OPMODE_RX 0x05
mluis 0:62d1edcc13d1 509 #define OPMODE_RX_SINGLE 0x06
mluis 0:62d1edcc13d1 510 #define OPMODE_CAD 0x07
mluis 0:62d1edcc13d1 511
mluis 0:62d1edcc13d1 512 // ----------------------------------------
mluis 0:62d1edcc13d1 513 // Bits masking the corresponding IRQs from the radio
mluis 0:62d1edcc13d1 514 #define IRQ_LORA_RXTOUT_MASK 0x80
mluis 0:62d1edcc13d1 515 #define IRQ_LORA_RXDONE_MASK 0x40
mluis 0:62d1edcc13d1 516 #define IRQ_LORA_CRCERR_MASK 0x20
mluis 0:62d1edcc13d1 517 #define IRQ_LORA_HEADER_MASK 0x10
mluis 0:62d1edcc13d1 518 #define IRQ_LORA_TXDONE_MASK 0x08
mluis 0:62d1edcc13d1 519 #define IRQ_LORA_CDDONE_MASK 0x04
mluis 0:62d1edcc13d1 520 #define IRQ_LORA_FHSSCH_MASK 0x02
mluis 0:62d1edcc13d1 521 #define IRQ_LORA_CDDETD_MASK 0x01
mluis 0:62d1edcc13d1 522
mluis 0:62d1edcc13d1 523 #define IRQ_FSK1_MODEREADY_MASK 0x80
mluis 0:62d1edcc13d1 524 #define IRQ_FSK1_RXREADY_MASK 0x40
mluis 0:62d1edcc13d1 525 #define IRQ_FSK1_TXREADY_MASK 0x20
mluis 0:62d1edcc13d1 526 #define IRQ_FSK1_PLLLOCK_MASK 0x10
mluis 0:62d1edcc13d1 527 #define IRQ_FSK1_RSSI_MASK 0x08
mluis 0:62d1edcc13d1 528 #define IRQ_FSK1_TIMEOUT_MASK 0x04
mluis 0:62d1edcc13d1 529 #define IRQ_FSK1_PREAMBLEDETECT_MASK 0x02
mluis 0:62d1edcc13d1 530 #define IRQ_FSK1_SYNCADDRESSMATCH_MASK 0x01
mluis 0:62d1edcc13d1 531 #define IRQ_FSK2_FIFOFULL_MASK 0x80
mluis 0:62d1edcc13d1 532 #define IRQ_FSK2_FIFOEMPTY_MASK 0x40
mluis 0:62d1edcc13d1 533 #define IRQ_FSK2_FIFOLEVEL_MASK 0x20
mluis 0:62d1edcc13d1 534 #define IRQ_FSK2_FIFOOVERRUN_MASK 0x10
mluis 0:62d1edcc13d1 535 #define IRQ_FSK2_PACKETSENT_MASK 0x08
mluis 0:62d1edcc13d1 536 #define IRQ_FSK2_PAYLOADREADY_MASK 0x04
mluis 0:62d1edcc13d1 537 #define IRQ_FSK2_CRCOK_MASK 0x02
mluis 0:62d1edcc13d1 538 #define IRQ_FSK2_LOWBAT_MASK 0x01
mluis 0:62d1edcc13d1 539
mluis 0:62d1edcc13d1 540 // ----------------------------------------
mluis 0:62d1edcc13d1 541 // DIO function mappings D0D1D2D3
mluis 0:62d1edcc13d1 542 #define MAP_DIO0_LORA_RXDONE 0x00 // 00------
mluis 0:62d1edcc13d1 543 #define MAP_DIO0_LORA_TXDONE 0x40 // 01------
mluis 0:62d1edcc13d1 544 #define MAP_DIO1_LORA_RXTOUT 0x00 // --00----
mluis 0:62d1edcc13d1 545 #define MAP_DIO1_LORA_NOP 0x30 // --11----
mluis 0:62d1edcc13d1 546 #define MAP_DIO2_LORA_NOP 0xC0 // ----11--
mluis 0:62d1edcc13d1 547
mluis 0:62d1edcc13d1 548 #define MAP_DIO0_FSK_READY 0x00 // 00------ (packet sent / payload ready)
mluis 0:62d1edcc13d1 549 #define MAP_DIO1_FSK_NOP 0x30 // --11----
mluis 0:62d1edcc13d1 550 #define MAP_DIO2_FSK_TXNOP 0x04 // ----01--
mluis 0:62d1edcc13d1 551 #define MAP_DIO2_FSK_TIMEOUT 0x08 // ----10--
mluis 0:62d1edcc13d1 552
mluis 0:62d1edcc13d1 553
mluis 0:62d1edcc13d1 554 // FSK IMAGECAL defines
mluis 0:62d1edcc13d1 555 #define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F
mluis 0:62d1edcc13d1 556 #define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80
mluis 0:62d1edcc13d1 557 #define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default
mluis 0:62d1edcc13d1 558
mluis 0:62d1edcc13d1 559 #define RF_IMAGECAL_IMAGECAL_MASK 0xBF
mluis 0:62d1edcc13d1 560 #define RF_IMAGECAL_IMAGECAL_START 0x40
mluis 0:62d1edcc13d1 561
mluis 0:62d1edcc13d1 562 #define RF_IMAGECAL_IMAGECAL_RUNNING 0x20
mluis 0:62d1edcc13d1 563 #define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default
mluis 0:62d1edcc13d1 564
mluis 0:62d1edcc13d1 565
mluis 0:62d1edcc13d1 566 // RADIO STATE
mluis 0:62d1edcc13d1 567 // (initialized by radio_init(), used by radio_rand1())
mluis 0:62d1edcc13d1 568 static u1_t randbuf[16];
mluis 0:62d1edcc13d1 569
mluis 0:62d1edcc13d1 570
mluis 0:62d1edcc13d1 571 #ifdef CFG_sx1276_radio
mluis 0:62d1edcc13d1 572 #define LNA_RX_GAIN (0x20|0x1)
mluis 0:62d1edcc13d1 573 #elif CFG_sx1272_radio
mluis 0:62d1edcc13d1 574 #define LNA_RX_GAIN (0x20|0x03)
mluis 0:62d1edcc13d1 575 #else
mluis 0:62d1edcc13d1 576 #error Missing CFG_sx1272_radio/CFG_sx1276_radio
mluis 0:62d1edcc13d1 577 #endif
mluis 0:62d1edcc13d1 578
mluis 1:d3b7bde3995c 579 #define RADIO_DBG
mluis 1:d3b7bde3995c 580 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 581 DigitalOut txStateIo( PB_8 );
mluis 1:d3b7bde3995c 582 DigitalOut rxStateIo( PB_9 );
mluis 1:d3b7bde3995c 583 #endif
mluis 1:d3b7bde3995c 584
tmulrooney 5:464c1f2d6cbb 585 static void writeReg (u1_t addr, u1_t data )
tmulrooney 5:464c1f2d6cbb 586 {
tmulrooney 5:464c1f2d6cbb 587 debug("writeReg enter 0x%02X 0x%02X\r\n",addr,data);
mluis 0:62d1edcc13d1 588 hal_pin_nss(0);
mluis 0:62d1edcc13d1 589 hal_spi(addr | 0x80);
mluis 0:62d1edcc13d1 590 hal_spi(data);
mluis 0:62d1edcc13d1 591 hal_pin_nss(1);
mluis 0:62d1edcc13d1 592 }
mluis 0:62d1edcc13d1 593
tmulrooney 5:464c1f2d6cbb 594 static u1_t readReg (u1_t addr)
tmulrooney 5:464c1f2d6cbb 595 {
mluis 0:62d1edcc13d1 596 hal_pin_nss(0);
mluis 0:62d1edcc13d1 597 hal_spi(addr & 0x7F);
mluis 0:62d1edcc13d1 598 u1_t val = hal_spi(0x00);
mluis 0:62d1edcc13d1 599 hal_pin_nss(1);
tmulrooney 5:464c1f2d6cbb 600 debug("readReg exit 0x%02X 0x%02X\r\n",addr,val);
mluis 0:62d1edcc13d1 601 return val;
mluis 0:62d1edcc13d1 602 }
mluis 0:62d1edcc13d1 603
tmulrooney 5:464c1f2d6cbb 604 static void writeBuf (u1_t addr, xref2u1_t buf, u1_t len)
tmulrooney 5:464c1f2d6cbb 605 {
tmulrooney 5:464c1f2d6cbb 606 debug("writeBuf enter 0x%02X\r\n",addr);
mluis 0:62d1edcc13d1 607 hal_pin_nss(0);
mluis 0:62d1edcc13d1 608 hal_spi(addr | 0x80);
tmulrooney 5:464c1f2d6cbb 609 for (u1_t i=0; i<len; i++)
tmulrooney 5:464c1f2d6cbb 610 {
tmulrooney 5:464c1f2d6cbb 611 debug(" 0x%02X\r\n",buf[i]);
mluis 0:62d1edcc13d1 612 hal_spi(buf[i]);
mluis 0:62d1edcc13d1 613 }
mluis 0:62d1edcc13d1 614 hal_pin_nss(1);
tmulrooney 5:464c1f2d6cbb 615 debug("\r\n");
mluis 0:62d1edcc13d1 616 }
mluis 0:62d1edcc13d1 617
tmulrooney 5:464c1f2d6cbb 618 static void readBuf (u1_t addr, xref2u1_t buf, u1_t len)
tmulrooney 5:464c1f2d6cbb 619 {
tmulrooney 5:464c1f2d6cbb 620 debug("readBuf enter 0x%02X\r\n",addr);
mluis 0:62d1edcc13d1 621 hal_pin_nss(0);
mluis 0:62d1edcc13d1 622 hal_spi(addr & 0x7F);
mluis 0:62d1edcc13d1 623 for (u1_t i=0; i<len; i++) {
mluis 0:62d1edcc13d1 624 buf[i] = hal_spi(0x00);
tmulrooney 5:464c1f2d6cbb 625 debug(" 0x%02X\r\n",buf[i]);
mluis 0:62d1edcc13d1 626 }
mluis 0:62d1edcc13d1 627 hal_pin_nss(1);
tmulrooney 5:464c1f2d6cbb 628 debug("\r\n");
mluis 0:62d1edcc13d1 629 }
mluis 0:62d1edcc13d1 630
tmulrooney 5:464c1f2d6cbb 631 static void opmode (u1_t mode)
tmulrooney 5:464c1f2d6cbb 632 {
tmulrooney 5:464c1f2d6cbb 633 debug("opmode enter %d\r\n",mode);
mluis 0:62d1edcc13d1 634 writeReg(RegOpMode, (readReg(RegOpMode) & ~OPMODE_MASK) | mode);
mluis 0:62d1edcc13d1 635 }
mluis 0:62d1edcc13d1 636
tmulrooney 5:464c1f2d6cbb 637 static void opmodeLora()
tmulrooney 5:464c1f2d6cbb 638 {
tmulrooney 5:464c1f2d6cbb 639 debug("opmodeLora enter\r\n");
tmulrooney 5:464c1f2d6cbb 640 u1_t u = OPMODE_LORA;
mluis 0:62d1edcc13d1 641 #ifdef CFG_sx1276_radio
mluis 0:62d1edcc13d1 642 u |= 0x8; // TBD: sx1276 high freq
mluis 0:62d1edcc13d1 643 #endif
mluis 0:62d1edcc13d1 644 writeReg(RegOpMode, u);
mluis 0:62d1edcc13d1 645 }
mluis 0:62d1edcc13d1 646
tmulrooney 5:464c1f2d6cbb 647 static void opmodeFSK()
tmulrooney 5:464c1f2d6cbb 648 {
tmulrooney 5:464c1f2d6cbb 649 debug("opmodeFSK enter\r\n");
mluis 0:62d1edcc13d1 650 u1_t u = 0;
mluis 0:62d1edcc13d1 651 #ifdef CFG_sx1276_radio
mluis 0:62d1edcc13d1 652 u |= 0x8; // TBD: sx1276 high freq
mluis 0:62d1edcc13d1 653 #endif
mluis 0:62d1edcc13d1 654 writeReg(RegOpMode, u);
mluis 0:62d1edcc13d1 655 }
mluis 0:62d1edcc13d1 656
mluis 0:62d1edcc13d1 657 // configure LoRa modem (cfg1, cfg2)
tmulrooney 5:464c1f2d6cbb 658 static void configLoraModem ()
tmulrooney 5:464c1f2d6cbb 659 {
tmulrooney 5:464c1f2d6cbb 660 debug("configLoraModem enter\r\n");
mluis 0:62d1edcc13d1 661 sf_t sf = getSf(LMIC.rps);
mluis 0:62d1edcc13d1 662
mluis 0:62d1edcc13d1 663 #ifdef CFG_sx1276_radio
mluis 1:d3b7bde3995c 664 u1_t mc1 = 0, mc2 = 0, mc3 = 0;
mluis 0:62d1edcc13d1 665
mluis 1:d3b7bde3995c 666 switch (getBw(LMIC.rps)) {
mluis 1:d3b7bde3995c 667 case BW125: mc1 |= SX1276_MC1_BW_125; break;
mluis 1:d3b7bde3995c 668 case BW250: mc1 |= SX1276_MC1_BW_250; break;
mluis 1:d3b7bde3995c 669 case BW500: mc1 |= SX1276_MC1_BW_500; break;
mluis 1:d3b7bde3995c 670 default:
mluis 1:d3b7bde3995c 671 ASSERT(0);
mluis 1:d3b7bde3995c 672 }
mluis 1:d3b7bde3995c 673 switch( getCr(LMIC.rps) ) {
mluis 1:d3b7bde3995c 674 case CR_4_5: mc1 |= SX1276_MC1_CR_4_5; break;
mluis 1:d3b7bde3995c 675 case CR_4_6: mc1 |= SX1276_MC1_CR_4_6; break;
mluis 1:d3b7bde3995c 676 case CR_4_7: mc1 |= SX1276_MC1_CR_4_7; break;
mluis 1:d3b7bde3995c 677 case CR_4_8: mc1 |= SX1276_MC1_CR_4_8; break;
mluis 1:d3b7bde3995c 678 default:
mluis 1:d3b7bde3995c 679 ASSERT(0);
mluis 1:d3b7bde3995c 680 }
mluis 0:62d1edcc13d1 681
mluis 1:d3b7bde3995c 682 if (getIh(LMIC.rps)) {
mluis 1:d3b7bde3995c 683 mc1 |= SX1276_MC1_IMPLICIT_HEADER_MODE_ON;
mluis 1:d3b7bde3995c 684 writeReg(LORARegPayloadLength, getIh(LMIC.rps)); // required length
mluis 1:d3b7bde3995c 685 }
mluis 1:d3b7bde3995c 686 // set ModemConfig1
mluis 1:d3b7bde3995c 687 writeReg(LORARegModemConfig1, mc1);
mluis 0:62d1edcc13d1 688
mluis 1:d3b7bde3995c 689 mc2 = (SX1272_MC2_SF7 + ((sf-1)<<4));
mluis 1:d3b7bde3995c 690 if (getNocrc(LMIC.rps) == 0) {
mluis 1:d3b7bde3995c 691 mc2 |= SX1276_MC2_RX_PAYLOAD_CRCON;
mluis 1:d3b7bde3995c 692 }
mluis 1:d3b7bde3995c 693 writeReg(LORARegModemConfig2, mc2);
mluis 1:d3b7bde3995c 694
mluis 1:d3b7bde3995c 695 mc3 = SX1276_MC3_AGCAUTO;
mluis 1:d3b7bde3995c 696 if ((sf == SF11 || sf == SF12) && getBw(LMIC.rps) == BW125) {
mluis 1:d3b7bde3995c 697 mc3 |= SX1276_MC3_LOW_DATA_RATE_OPTIMIZE;
mluis 1:d3b7bde3995c 698 }
mluis 1:d3b7bde3995c 699 writeReg(LORARegModemConfig3, mc3);
mluis 0:62d1edcc13d1 700 #elif CFG_sx1272_radio
mluis 1:d3b7bde3995c 701 u1_t mc1 = (getBw(LMIC.rps)<<6);
mluis 0:62d1edcc13d1 702
mluis 1:d3b7bde3995c 703 switch( getCr(LMIC.rps) ) {
mluis 1:d3b7bde3995c 704 case CR_4_5: mc1 |= SX1272_MC1_CR_4_5; break;
mluis 1:d3b7bde3995c 705 case CR_4_6: mc1 |= SX1272_MC1_CR_4_6; break;
mluis 1:d3b7bde3995c 706 case CR_4_7: mc1 |= SX1272_MC1_CR_4_7; break;
mluis 1:d3b7bde3995c 707 case CR_4_8: mc1 |= SX1272_MC1_CR_4_8; break;
mluis 1:d3b7bde3995c 708 }
mluis 1:d3b7bde3995c 709
mluis 1:d3b7bde3995c 710 if ((sf == SF11 || sf == SF12) && getBw(LMIC.rps) == BW125) {
mluis 1:d3b7bde3995c 711 mc1 |= SX1272_MC1_LOW_DATA_RATE_OPTIMIZE;
mluis 1:d3b7bde3995c 712 }
mluis 1:d3b7bde3995c 713
mluis 1:d3b7bde3995c 714 if (getNocrc(LMIC.rps) == 0) {
mluis 1:d3b7bde3995c 715 mc1 |= SX1272_MC1_RX_PAYLOAD_CRCON;
mluis 1:d3b7bde3995c 716 }
mluis 1:d3b7bde3995c 717
mluis 1:d3b7bde3995c 718 if (getIh(LMIC.rps)) {
mluis 1:d3b7bde3995c 719 mc1 |= SX1272_MC1_IMPLICIT_HEADER_MODE_ON;
mluis 1:d3b7bde3995c 720 writeReg(LORARegPayloadLength, getIh(LMIC.rps)); // required length
mluis 1:d3b7bde3995c 721 }
mluis 1:d3b7bde3995c 722 // set ModemConfig1
mluis 1:d3b7bde3995c 723 writeReg(LORARegModemConfig1, mc1);
mluis 1:d3b7bde3995c 724
mluis 1:d3b7bde3995c 725 // set ModemConfig2 (sf, AgcAutoOn=1 SymbTimeoutHi=00)
mluis 1:d3b7bde3995c 726 writeReg(LORARegModemConfig2, (SX1272_MC2_SF7 + ((sf-1)<<4)) | 0x04);
mluis 0:62d1edcc13d1 727 #else
mluis 0:62d1edcc13d1 728 #error Missing CFG_sx1272_radio/CFG_sx1276_radio
mluis 0:62d1edcc13d1 729 #endif /* CFG_sx1272_radio */
mluis 0:62d1edcc13d1 730 }
mluis 0:62d1edcc13d1 731
tmulrooney 5:464c1f2d6cbb 732 static void configChannel ()
tmulrooney 5:464c1f2d6cbb 733 {
mluis 0:62d1edcc13d1 734 // set frequency: FQ = (FRF * 32 Mhz) / (2 ^ 19)
mluis 0:62d1edcc13d1 735 u8_t frf = ((u8_t)LMIC.freq << 19) / 32000000;
tmulrooney 5:464c1f2d6cbb 736 debug("configChannel enter %d %lld\r\n",LMIC.freq, frf);
mluis 0:62d1edcc13d1 737 writeReg(RegFrfMsb, (u1_t)(frf>>16));
mluis 0:62d1edcc13d1 738 writeReg(RegFrfMid, (u1_t)(frf>> 8));
mluis 0:62d1edcc13d1 739 writeReg(RegFrfLsb, (u1_t)(frf>> 0));
mluis 0:62d1edcc13d1 740 }
mluis 0:62d1edcc13d1 741
mluis 0:62d1edcc13d1 742
mluis 0:62d1edcc13d1 743
tmulrooney 5:464c1f2d6cbb 744 static void configPower ()
tmulrooney 5:464c1f2d6cbb 745 {
tmulrooney 5:464c1f2d6cbb 746 debug("configPower enter\r\n");
mluis 0:62d1edcc13d1 747 #ifdef CFG_sx1276_radio
mluis 0:62d1edcc13d1 748 // no boost used for now
mluis 0:62d1edcc13d1 749 s1_t pw = (s1_t)LMIC.txpow;
mluis 1:d3b7bde3995c 750 if(pw >= 17) {
mluis 1:d3b7bde3995c 751 pw = 15;
mluis 1:d3b7bde3995c 752 } else if(pw < 2) {
mluis 1:d3b7bde3995c 753 pw = 2;
mluis 0:62d1edcc13d1 754 }
mluis 0:62d1edcc13d1 755 // check board type for BOOST pin
mluis 1:d3b7bde3995c 756 writeReg(RegPaConfig, (u1_t)(0x80|(pw&0xf)));
mluis 0:62d1edcc13d1 757 writeReg(RegPaDac, readReg(RegPaDac)|0x4);
mluis 0:62d1edcc13d1 758
mluis 0:62d1edcc13d1 759 #elif CFG_sx1272_radio
mluis 0:62d1edcc13d1 760 // set PA config (2-17 dBm using PA_BOOST)
mluis 0:62d1edcc13d1 761 s1_t pw = (s1_t)LMIC.txpow;
mluis 0:62d1edcc13d1 762 if(pw > 17) {
mluis 1:d3b7bde3995c 763 pw = 17;
mluis 0:62d1edcc13d1 764 } else if(pw < 2) {
mluis 1:d3b7bde3995c 765 pw = 2;
mluis 0:62d1edcc13d1 766 }
mluis 0:62d1edcc13d1 767 writeReg(RegPaConfig, (u1_t)(0x80|(pw-2)));
mluis 0:62d1edcc13d1 768 #else
mluis 0:62d1edcc13d1 769 #error Missing CFG_sx1272_radio/CFG_sx1276_radio
mluis 0:62d1edcc13d1 770 #endif /* CFG_sx1272_radio */
mluis 0:62d1edcc13d1 771 }
mluis 0:62d1edcc13d1 772
tmulrooney 5:464c1f2d6cbb 773 static void txfsk ()
tmulrooney 5:464c1f2d6cbb 774 {
tmulrooney 7:29058a7ccf23 775 debug_str("txfsk enter\r\n");
mluis 0:62d1edcc13d1 776 // select FSK modem (from sleep mode)
mluis 0:62d1edcc13d1 777 writeReg(RegOpMode, 0x10); // FSK, BT=0.5
mluis 0:62d1edcc13d1 778 ASSERT(readReg(RegOpMode) == 0x10);
mluis 0:62d1edcc13d1 779 // enter standby mode (required for FIFO loading))
mluis 0:62d1edcc13d1 780 opmode(OPMODE_STANDBY);
mluis 1:d3b7bde3995c 781 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 782 txStateIo = 0;
mluis 1:d3b7bde3995c 783 rxStateIo = 0;
mluis 1:d3b7bde3995c 784 #endif
mluis 0:62d1edcc13d1 785 // set bitrate
mluis 0:62d1edcc13d1 786 writeReg(FSKRegBitrateMsb, 0x02); // 50kbps
mluis 0:62d1edcc13d1 787 writeReg(FSKRegBitrateLsb, 0x80);
mluis 0:62d1edcc13d1 788 // set frequency deviation
mluis 0:62d1edcc13d1 789 writeReg(FSKRegFdevMsb, 0x01); // +/- 25kHz
mluis 0:62d1edcc13d1 790 writeReg(FSKRegFdevLsb, 0x99);
mluis 0:62d1edcc13d1 791 // frame and packet handler settings
mluis 0:62d1edcc13d1 792 writeReg(FSKRegPreambleMsb, 0x00);
mluis 0:62d1edcc13d1 793 writeReg(FSKRegPreambleLsb, 0x05);
mluis 0:62d1edcc13d1 794 writeReg(FSKRegSyncConfig, 0x12);
mluis 0:62d1edcc13d1 795 writeReg(FSKRegPacketConfig1, 0xD0);
mluis 0:62d1edcc13d1 796 writeReg(FSKRegPacketConfig2, 0x40);
mluis 0:62d1edcc13d1 797 writeReg(FSKRegSyncValue1, 0xC1);
mluis 0:62d1edcc13d1 798 writeReg(FSKRegSyncValue2, 0x94);
mluis 0:62d1edcc13d1 799 writeReg(FSKRegSyncValue3, 0xC1);
mluis 0:62d1edcc13d1 800 // configure frequency
mluis 0:62d1edcc13d1 801 configChannel();
mluis 0:62d1edcc13d1 802 // configure output power
mluis 0:62d1edcc13d1 803 configPower();
mluis 0:62d1edcc13d1 804
mluis 0:62d1edcc13d1 805 // set the IRQ mapping DIO0=PacketSent DIO1=NOP DIO2=NOP
mluis 0:62d1edcc13d1 806 writeReg(RegDioMapping1, MAP_DIO0_FSK_READY|MAP_DIO1_FSK_NOP|MAP_DIO2_FSK_TXNOP);
mluis 0:62d1edcc13d1 807
mluis 0:62d1edcc13d1 808 // initialize the payload size and address pointers
mluis 0:62d1edcc13d1 809 writeReg(FSKRegPayloadLength, LMIC.dataLen+1); // (insert length byte into payload))
mluis 0:62d1edcc13d1 810
mluis 0:62d1edcc13d1 811 // download length byte and buffer to the radio FIFO
mluis 0:62d1edcc13d1 812 writeReg(RegFifo, LMIC.dataLen);
mluis 0:62d1edcc13d1 813 writeBuf(RegFifo, LMIC.frame, LMIC.dataLen);
mluis 0:62d1edcc13d1 814
mluis 0:62d1edcc13d1 815 // enable antenna switch for TX
mluis 0:62d1edcc13d1 816 hal_pin_rxtx(1);
mluis 0:62d1edcc13d1 817
mluis 0:62d1edcc13d1 818 // now we actually start the transmission
mluis 0:62d1edcc13d1 819 opmode(OPMODE_TX);
mluis 1:d3b7bde3995c 820 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 821 txStateIo = 1;
mluis 1:d3b7bde3995c 822 #endif
mluis 0:62d1edcc13d1 823 }
mluis 0:62d1edcc13d1 824
tmulrooney 5:464c1f2d6cbb 825 static void txlora ()
tmulrooney 5:464c1f2d6cbb 826 {
tmulrooney 7:29058a7ccf23 827 debug_str("txlora enter\r\n");
mluis 0:62d1edcc13d1 828 // select LoRa modem (from sleep mode)
mluis 0:62d1edcc13d1 829 //writeReg(RegOpMode, OPMODE_LORA);
mluis 0:62d1edcc13d1 830 opmodeLora();
mluis 0:62d1edcc13d1 831 ASSERT((readReg(RegOpMode) & OPMODE_LORA) != 0);
mluis 0:62d1edcc13d1 832
mluis 0:62d1edcc13d1 833 // enter standby mode (required for FIFO loading))
mluis 0:62d1edcc13d1 834 opmode(OPMODE_STANDBY);
mluis 1:d3b7bde3995c 835 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 836 txStateIo = 0;
mluis 1:d3b7bde3995c 837 rxStateIo = 0;
mluis 1:d3b7bde3995c 838 #endif
mluis 0:62d1edcc13d1 839 // configure LoRa modem (cfg1, cfg2)
mluis 0:62d1edcc13d1 840 configLoraModem();
mluis 0:62d1edcc13d1 841 // configure frequency
mluis 0:62d1edcc13d1 842 configChannel();
mluis 0:62d1edcc13d1 843 // configure output power
mluis 0:62d1edcc13d1 844 writeReg(RegPaRamp, (readReg(RegPaRamp) & 0xF0) | 0x08); // set PA ramp-up time 50 uSec
mluis 0:62d1edcc13d1 845 configPower();
mluis 0:62d1edcc13d1 846 // set sync word
mluis 0:62d1edcc13d1 847 writeReg(LORARegSyncWord, LORA_MAC_PREAMBLE);
mluis 0:62d1edcc13d1 848
mluis 0:62d1edcc13d1 849 // set the IRQ mapping DIO0=TxDone DIO1=NOP DIO2=NOP
mluis 0:62d1edcc13d1 850 writeReg(RegDioMapping1, MAP_DIO0_LORA_TXDONE|MAP_DIO1_LORA_NOP|MAP_DIO2_LORA_NOP);
mluis 0:62d1edcc13d1 851 // clear all radio IRQ flags
mluis 0:62d1edcc13d1 852 writeReg(LORARegIrqFlags, 0xFF);
mluis 0:62d1edcc13d1 853 // mask all IRQs but TxDone
mluis 0:62d1edcc13d1 854 writeReg(LORARegIrqFlagsMask, ~IRQ_LORA_TXDONE_MASK);
mluis 0:62d1edcc13d1 855
mluis 0:62d1edcc13d1 856 // initialize the payload size and address pointers
mluis 0:62d1edcc13d1 857 writeReg(LORARegFifoTxBaseAddr, 0x00);
mluis 0:62d1edcc13d1 858 writeReg(LORARegFifoAddrPtr, 0x00);
mluis 0:62d1edcc13d1 859 writeReg(LORARegPayloadLength, LMIC.dataLen);
mluis 0:62d1edcc13d1 860
mluis 0:62d1edcc13d1 861 // download buffer to the radio FIFO
mluis 0:62d1edcc13d1 862 writeBuf(RegFifo, LMIC.frame, LMIC.dataLen);
mluis 0:62d1edcc13d1 863
mluis 0:62d1edcc13d1 864 // enable antenna switch for TX
mluis 0:62d1edcc13d1 865 hal_pin_rxtx(1);
mluis 0:62d1edcc13d1 866
mluis 0:62d1edcc13d1 867 // now we actually start the transmission
mluis 0:62d1edcc13d1 868 opmode(OPMODE_TX);
mluis 0:62d1edcc13d1 869 }
mluis 0:62d1edcc13d1 870
mluis 0:62d1edcc13d1 871 // start transmitter (buf=LMIC.frame, len=LMIC.dataLen)
tmulrooney 5:464c1f2d6cbb 872 static void starttx ()
tmulrooney 5:464c1f2d6cbb 873 {
tmulrooney 7:29058a7ccf23 874 debug_str("starttx enter\r\n");
mluis 0:62d1edcc13d1 875 ASSERT( (readReg(RegOpMode) & OPMODE_MASK) == OPMODE_SLEEP );
mluis 0:62d1edcc13d1 876 if(getSf(LMIC.rps) == FSK) { // FSK modem
mluis 0:62d1edcc13d1 877 txfsk();
mluis 0:62d1edcc13d1 878 } else { // LoRa modem
mluis 0:62d1edcc13d1 879 txlora();
mluis 0:62d1edcc13d1 880 }
mluis 0:62d1edcc13d1 881 // the radio will go back to STANDBY mode as soon as the TX is finished
mluis 0:62d1edcc13d1 882 // the corresponding IRQ will inform us about completion.
mluis 0:62d1edcc13d1 883 }
mluis 0:62d1edcc13d1 884
mluis 0:62d1edcc13d1 885 enum { RXMODE_SINGLE, RXMODE_SCAN, RXMODE_RSSI };
mluis 0:62d1edcc13d1 886
mluis 0:62d1edcc13d1 887 static const u1_t rxlorairqmask[] = {
mluis 0:62d1edcc13d1 888 [RXMODE_SINGLE] = IRQ_LORA_RXDONE_MASK|IRQ_LORA_RXTOUT_MASK,
mluis 0:62d1edcc13d1 889 [RXMODE_SCAN] = IRQ_LORA_RXDONE_MASK,
mluis 0:62d1edcc13d1 890 [RXMODE_RSSI] = 0x00,
mluis 0:62d1edcc13d1 891 };
mluis 0:62d1edcc13d1 892
mluis 0:62d1edcc13d1 893 // start LoRa receiver (time=LMIC.rxtime, timeout=LMIC.rxsyms, result=LMIC.frame[LMIC.dataLen])
tmulrooney 5:464c1f2d6cbb 894 static void rxlora (u1_t rxmode)
tmulrooney 5:464c1f2d6cbb 895 {
tmulrooney 7:29058a7ccf23 896 debug_str("rxlora enter\r\n");
mluis 0:62d1edcc13d1 897 // select LoRa modem (from sleep mode)
mluis 0:62d1edcc13d1 898 opmodeLora();
mluis 0:62d1edcc13d1 899 ASSERT((readReg(RegOpMode) & OPMODE_LORA) != 0);
mluis 0:62d1edcc13d1 900 // enter standby mode (warm up))
mluis 0:62d1edcc13d1 901 opmode(OPMODE_STANDBY);
mluis 1:d3b7bde3995c 902 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 903 txStateIo = 0;
mluis 1:d3b7bde3995c 904 rxStateIo = 0;
mluis 1:d3b7bde3995c 905 #endif
mluis 0:62d1edcc13d1 906 // don't use MAC settings at startup
mluis 0:62d1edcc13d1 907 if(rxmode == RXMODE_RSSI) { // use fixed settings for rssi scan
mluis 0:62d1edcc13d1 908 writeReg(LORARegModemConfig1, RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG1);
mluis 0:62d1edcc13d1 909 writeReg(LORARegModemConfig2, RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG2);
mluis 0:62d1edcc13d1 910 } else { // single or continuous rx mode
mluis 0:62d1edcc13d1 911 // configure LoRa modem (cfg1, cfg2)
mluis 0:62d1edcc13d1 912 configLoraModem();
mluis 0:62d1edcc13d1 913 // configure frequency
mluis 0:62d1edcc13d1 914 configChannel();
mluis 0:62d1edcc13d1 915 }
mluis 0:62d1edcc13d1 916 // set LNA gain
mluis 0:62d1edcc13d1 917 writeReg(RegLna, LNA_RX_GAIN);
mluis 0:62d1edcc13d1 918 // set max payload size
mluis 0:62d1edcc13d1 919 writeReg(LORARegPayloadMaxLength, 64);
mluis 0:62d1edcc13d1 920 // use inverted I/Q signal (prevent mote-to-mote communication)
mluis 0:62d1edcc13d1 921 writeReg(LORARegInvertIQ, readReg(LORARegInvertIQ)|(1<<6));
mluis 0:62d1edcc13d1 922 // set symbol timeout (for single rx)
mluis 0:62d1edcc13d1 923 writeReg(LORARegSymbTimeoutLsb, LMIC.rxsyms);
mluis 0:62d1edcc13d1 924 // set sync word
mluis 0:62d1edcc13d1 925 writeReg(LORARegSyncWord, LORA_MAC_PREAMBLE);
mluis 0:62d1edcc13d1 926
mluis 0:62d1edcc13d1 927 // configure DIO mapping DIO0=RxDone DIO1=RxTout DIO2=NOP
mluis 0:62d1edcc13d1 928 writeReg(RegDioMapping1, MAP_DIO0_LORA_RXDONE|MAP_DIO1_LORA_RXTOUT|MAP_DIO2_LORA_NOP);
mluis 0:62d1edcc13d1 929 // clear all radio IRQ flags
mluis 0:62d1edcc13d1 930 writeReg(LORARegIrqFlags, 0xFF);
mluis 0:62d1edcc13d1 931 // enable required radio IRQs
mluis 0:62d1edcc13d1 932 writeReg(LORARegIrqFlagsMask, ~rxlorairqmask[rxmode]);
mluis 0:62d1edcc13d1 933
mluis 0:62d1edcc13d1 934 // enable antenna switch for RX
mluis 0:62d1edcc13d1 935 hal_pin_rxtx(0);
mluis 0:62d1edcc13d1 936
mluis 0:62d1edcc13d1 937 // now instruct the radio to receive
mluis 0:62d1edcc13d1 938 if (rxmode == RXMODE_SINGLE) { // single rx
mluis 0:62d1edcc13d1 939 hal_waitUntil(LMIC.rxtime); // busy wait until exact rx time
mluis 1:d3b7bde3995c 940 opmode(OPMODE_RX_SINGLE);
mluis 1:d3b7bde3995c 941 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 942 rxStateIo = 1;
mluis 1:d3b7bde3995c 943 #endif
mluis 0:62d1edcc13d1 944 } else { // continous rx (scan or rssi)
mluis 1:d3b7bde3995c 945 opmode(OPMODE_RX);
mluis 1:d3b7bde3995c 946 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 947 rxStateIo = 1;
mluis 1:d3b7bde3995c 948 #endif
mluis 0:62d1edcc13d1 949 }
mluis 0:62d1edcc13d1 950 }
mluis 0:62d1edcc13d1 951
tmulrooney 5:464c1f2d6cbb 952 static void rxfsk (u1_t rxmode)
tmulrooney 5:464c1f2d6cbb 953 {
tmulrooney 7:29058a7ccf23 954 debug_str("rxfsk enter\r\n");
mluis 0:62d1edcc13d1 955 // only single rx (no continuous scanning, no noise sampling)
mluis 0:62d1edcc13d1 956 ASSERT( rxmode == RXMODE_SINGLE );
mluis 0:62d1edcc13d1 957 // select FSK modem (from sleep mode)
mluis 0:62d1edcc13d1 958 //writeReg(RegOpMode, 0x00); // (not LoRa)
mluis 0:62d1edcc13d1 959 opmodeFSK();
mluis 0:62d1edcc13d1 960 ASSERT((readReg(RegOpMode) & OPMODE_LORA) == 0);
mluis 0:62d1edcc13d1 961 // enter standby mode (warm up))
mluis 0:62d1edcc13d1 962 opmode(OPMODE_STANDBY);
mluis 1:d3b7bde3995c 963 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 964 txStateIo = 0;
mluis 1:d3b7bde3995c 965 rxStateIo = 0;
mluis 1:d3b7bde3995c 966 #endif
mluis 0:62d1edcc13d1 967 // configure frequency
mluis 0:62d1edcc13d1 968 configChannel();
mluis 0:62d1edcc13d1 969 // set LNA gain
mluis 0:62d1edcc13d1 970 //writeReg(RegLna, 0x20|0x03); // max gain, boost enable
mluis 0:62d1edcc13d1 971 writeReg(RegLna, LNA_RX_GAIN);
mluis 0:62d1edcc13d1 972 // configure receiver
mluis 0:62d1edcc13d1 973 writeReg(FSKRegRxConfig, 0x1E); // AFC auto, AGC, trigger on preamble?!?
mluis 0:62d1edcc13d1 974 // set receiver bandwidth
mluis 0:62d1edcc13d1 975 writeReg(FSKRegRxBw, 0x0B); // 50kHz SSb
mluis 0:62d1edcc13d1 976 // set AFC bandwidth
mluis 0:62d1edcc13d1 977 writeReg(FSKRegAfcBw, 0x12); // 83.3kHz SSB
mluis 0:62d1edcc13d1 978 // set preamble detection
mluis 0:62d1edcc13d1 979 writeReg(FSKRegPreambleDetect, 0xAA); // enable, 2 bytes, 10 chip errors
mluis 0:62d1edcc13d1 980 // set sync config
mluis 0:62d1edcc13d1 981 writeReg(FSKRegSyncConfig, 0x12); // no auto restart, preamble 0xAA, enable, fill FIFO, 3 bytes sync
mluis 0:62d1edcc13d1 982 // set packet config
mluis 0:62d1edcc13d1 983 writeReg(FSKRegPacketConfig1, 0xD8); // var-length, whitening, crc, no auto-clear, no adr filter
mluis 0:62d1edcc13d1 984 writeReg(FSKRegPacketConfig2, 0x40); // packet mode
mluis 0:62d1edcc13d1 985 // set sync value
mluis 0:62d1edcc13d1 986 writeReg(FSKRegSyncValue1, 0xC1);
mluis 0:62d1edcc13d1 987 writeReg(FSKRegSyncValue2, 0x94);
mluis 0:62d1edcc13d1 988 writeReg(FSKRegSyncValue3, 0xC1);
mluis 0:62d1edcc13d1 989 // set preamble timeout
mluis 0:62d1edcc13d1 990 writeReg(FSKRegRxTimeout2, 0xFF);//(LMIC.rxsyms+1)/2);
mluis 0:62d1edcc13d1 991 // set bitrate
mluis 0:62d1edcc13d1 992 writeReg(FSKRegBitrateMsb, 0x02); // 50kbps
mluis 0:62d1edcc13d1 993 writeReg(FSKRegBitrateLsb, 0x80);
mluis 0:62d1edcc13d1 994 // set frequency deviation
mluis 0:62d1edcc13d1 995 writeReg(FSKRegFdevMsb, 0x01); // +/- 25kHz
mluis 0:62d1edcc13d1 996 writeReg(FSKRegFdevLsb, 0x99);
mluis 0:62d1edcc13d1 997
mluis 0:62d1edcc13d1 998 // configure DIO mapping DIO0=PayloadReady DIO1=NOP DIO2=TimeOut
mluis 0:62d1edcc13d1 999 writeReg(RegDioMapping1, MAP_DIO0_FSK_READY|MAP_DIO1_FSK_NOP|MAP_DIO2_FSK_TIMEOUT);
mluis 0:62d1edcc13d1 1000
mluis 0:62d1edcc13d1 1001 // enable antenna switch for RX
mluis 0:62d1edcc13d1 1002 hal_pin_rxtx(0);
mluis 0:62d1edcc13d1 1003
mluis 0:62d1edcc13d1 1004 // now instruct the radio to receive
mluis 0:62d1edcc13d1 1005 hal_waitUntil(LMIC.rxtime); // busy wait until exact rx time
mluis 0:62d1edcc13d1 1006 opmode(OPMODE_RX); // no single rx mode available in FSK
mluis 1:d3b7bde3995c 1007 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 1008 rxStateIo = 1;
mluis 1:d3b7bde3995c 1009 #endif
mluis 0:62d1edcc13d1 1010 }
mluis 0:62d1edcc13d1 1011
tmulrooney 5:464c1f2d6cbb 1012 static void startrx (u1_t rxmode)
tmulrooney 5:464c1f2d6cbb 1013 {
tmulrooney 7:29058a7ccf23 1014 debug_str("startrx enter\r\n");
mluis 0:62d1edcc13d1 1015 ASSERT( (readReg(RegOpMode) & OPMODE_MASK) == OPMODE_SLEEP );
mluis 0:62d1edcc13d1 1016 if(getSf(LMIC.rps) == FSK) { // FSK modem
mluis 0:62d1edcc13d1 1017 rxfsk(rxmode);
mluis 0:62d1edcc13d1 1018 } else { // LoRa modem
mluis 0:62d1edcc13d1 1019 rxlora(rxmode);
mluis 0:62d1edcc13d1 1020 }
mluis 0:62d1edcc13d1 1021 // the radio will go back to STANDBY mode as soon as the RX is finished
mluis 0:62d1edcc13d1 1022 // or timed out, and the corresponding IRQ will inform us about completion.
mluis 0:62d1edcc13d1 1023 }
mluis 0:62d1edcc13d1 1024
mluis 0:62d1edcc13d1 1025 // get random seed from wideband noise rssi
tmulrooney 5:464c1f2d6cbb 1026 void radio_init ()
tmulrooney 5:464c1f2d6cbb 1027 {
tmulrooney 5:464c1f2d6cbb 1028 debug("radio_init2 enter\r\n");
tmulrooney 5:464c1f2d6cbb 1029 Radio = new SX1272MB1xAS(NULL);
mluis 0:62d1edcc13d1 1030 hal_disableIRQs();
mluis 0:62d1edcc13d1 1031
mluis 0:62d1edcc13d1 1032 // manually reset radio
mluis 0:62d1edcc13d1 1033 #ifdef CFG_sx1276_radio
mluis 0:62d1edcc13d1 1034 hal_pin_rst(0); // drive RST pin low
mluis 0:62d1edcc13d1 1035 #else
mluis 0:62d1edcc13d1 1036 hal_pin_rst(1); // drive RST pin high
mluis 0:62d1edcc13d1 1037 #endif
mluis 0:62d1edcc13d1 1038 hal_waitUntil(os_getTime()+ms2osticks(1)); // wait >100us
mluis 0:62d1edcc13d1 1039 hal_pin_rst(2); // configure RST pin floating!
mluis 0:62d1edcc13d1 1040 hal_waitUntil(os_getTime()+ms2osticks(5)); // wait 5ms
mluis 0:62d1edcc13d1 1041
mluis 0:62d1edcc13d1 1042 opmode(OPMODE_SLEEP);
mluis 1:d3b7bde3995c 1043 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 1044 txStateIo = 0;
mluis 1:d3b7bde3995c 1045 rxStateIo = 0;
mluis 1:d3b7bde3995c 1046 #endif
mluis 0:62d1edcc13d1 1047 // some sanity checks, e.g., read version number
mluis 0:62d1edcc13d1 1048 u1_t v = readReg(RegVersion);
mluis 0:62d1edcc13d1 1049 #ifdef CFG_sx1276_radio
mluis 0:62d1edcc13d1 1050 ASSERT(v == 0x12 );
mluis 0:62d1edcc13d1 1051 #elif CFG_sx1272_radio
mluis 0:62d1edcc13d1 1052 ASSERT(v == 0x22);
mluis 0:62d1edcc13d1 1053 #else
mluis 0:62d1edcc13d1 1054 #error Missing CFG_sx1272_radio/CFG_sx1276_radio
mluis 0:62d1edcc13d1 1055 #endif
mluis 0:62d1edcc13d1 1056 // seed 15-byte randomness via noise rssi
mluis 0:62d1edcc13d1 1057 rxlora(RXMODE_RSSI);
mluis 0:62d1edcc13d1 1058 while( (readReg(RegOpMode) & OPMODE_MASK) != OPMODE_RX ); // continuous rx
mluis 0:62d1edcc13d1 1059 for(int i=1; i<16; i++) {
mluis 0:62d1edcc13d1 1060 for(int j=0; j<8; j++) {
mluis 0:62d1edcc13d1 1061 u1_t b; // wait for two non-identical subsequent least-significant bits
mluis 0:62d1edcc13d1 1062 while( (b = readReg(LORARegRssiWideband) & 0x01) == (readReg(LORARegRssiWideband) & 0x01) );
mluis 0:62d1edcc13d1 1063 randbuf[i] = (randbuf[i] << 1) | b;
mluis 0:62d1edcc13d1 1064 }
mluis 0:62d1edcc13d1 1065 }
mluis 0:62d1edcc13d1 1066 randbuf[0] = 16; // set initial index
mluis 0:62d1edcc13d1 1067
mluis 1:d3b7bde3995c 1068 #ifdef CFG_sx1276mb1_board
mluis 0:62d1edcc13d1 1069 // chain calibration
mluis 0:62d1edcc13d1 1070 writeReg(RegPaConfig, 0);
mluis 0:62d1edcc13d1 1071
mluis 0:62d1edcc13d1 1072 // Launch Rx chain calibration for LF band
mluis 0:62d1edcc13d1 1073 writeReg(FSKRegImageCal, (readReg(FSKRegImageCal) & RF_IMAGECAL_IMAGECAL_MASK)|RF_IMAGECAL_IMAGECAL_START);
mluis 0:62d1edcc13d1 1074 while((readReg(FSKRegImageCal)&RF_IMAGECAL_IMAGECAL_RUNNING) == RF_IMAGECAL_IMAGECAL_RUNNING){ ; }
mluis 0:62d1edcc13d1 1075
mluis 0:62d1edcc13d1 1076 // Sets a Frequency in HF band
mluis 0:62d1edcc13d1 1077 u4_t frf = 868000000;
mluis 0:62d1edcc13d1 1078 writeReg(RegFrfMsb, (u1_t)(frf>>16));
mluis 0:62d1edcc13d1 1079 writeReg(RegFrfMid, (u1_t)(frf>> 8));
mluis 0:62d1edcc13d1 1080 writeReg(RegFrfLsb, (u1_t)(frf>> 0));
mluis 0:62d1edcc13d1 1081
mluis 0:62d1edcc13d1 1082 // Launch Rx chain calibration for HF band
mluis 0:62d1edcc13d1 1083 writeReg(FSKRegImageCal, (readReg(FSKRegImageCal) & RF_IMAGECAL_IMAGECAL_MASK)|RF_IMAGECAL_IMAGECAL_START);
mluis 0:62d1edcc13d1 1084 while((readReg(FSKRegImageCal) & RF_IMAGECAL_IMAGECAL_RUNNING) == RF_IMAGECAL_IMAGECAL_RUNNING) { ; }
mluis 1:d3b7bde3995c 1085 #endif /* CFG_sx1276mb1_board */
mluis 0:62d1edcc13d1 1086
mluis 0:62d1edcc13d1 1087 opmode(OPMODE_SLEEP);
mluis 1:d3b7bde3995c 1088 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 1089 txStateIo = 0;
mluis 1:d3b7bde3995c 1090 rxStateIo = 0;
mluis 1:d3b7bde3995c 1091 #endif
mluis 0:62d1edcc13d1 1092 hal_enableIRQs();
mluis 0:62d1edcc13d1 1093 }
mluis 0:62d1edcc13d1 1094
mluis 0:62d1edcc13d1 1095 // return next random byte derived from seed buffer
mluis 0:62d1edcc13d1 1096 // (buf[0] holds index of next byte to be returned)
tmulrooney 5:464c1f2d6cbb 1097 u1_t radio_rand1 ()
tmulrooney 5:464c1f2d6cbb 1098 {
tmulrooney 5:464c1f2d6cbb 1099 debug("radio_rand1 enter\r\n");
mluis 0:62d1edcc13d1 1100 u1_t i = randbuf[0];
mluis 0:62d1edcc13d1 1101 ASSERT( i != 0 );
mluis 0:62d1edcc13d1 1102 if( i==16 ) {
mluis 0:62d1edcc13d1 1103 os_aes(AES_ENC, randbuf, 16); // encrypt seed with any key
mluis 0:62d1edcc13d1 1104 i = 0;
mluis 0:62d1edcc13d1 1105 }
mluis 0:62d1edcc13d1 1106 u1_t v = randbuf[i++];
mluis 0:62d1edcc13d1 1107 randbuf[0] = i;
mluis 0:62d1edcc13d1 1108 return v;
mluis 0:62d1edcc13d1 1109 }
mluis 0:62d1edcc13d1 1110
tmulrooney 5:464c1f2d6cbb 1111 u1_t radio_rssi ()
tmulrooney 5:464c1f2d6cbb 1112 {
tmulrooney 5:464c1f2d6cbb 1113 debug("radio_rssi enter\r\n");
mluis 0:62d1edcc13d1 1114 hal_disableIRQs();
mluis 0:62d1edcc13d1 1115 u1_t r = readReg(LORARegRssiValue);
mluis 0:62d1edcc13d1 1116 hal_enableIRQs();
mluis 0:62d1edcc13d1 1117 return r;
mluis 0:62d1edcc13d1 1118 }
mluis 0:62d1edcc13d1 1119
mluis 0:62d1edcc13d1 1120 static const u2_t LORA_RXDONE_FIXUP[] = {
mluis 0:62d1edcc13d1 1121 [FSK] = us2osticks(0), // ( 0 ticks)
mluis 0:62d1edcc13d1 1122 [SF7] = us2osticks(0), // ( 0 ticks)
mluis 0:62d1edcc13d1 1123 [SF8] = us2osticks(1648), // ( 54 ticks)
mluis 0:62d1edcc13d1 1124 [SF9] = us2osticks(3265), // ( 107 ticks)
mluis 0:62d1edcc13d1 1125 [SF10] = us2osticks(7049), // ( 231 ticks)
mluis 0:62d1edcc13d1 1126 [SF11] = us2osticks(13641), // ( 447 ticks)
mluis 0:62d1edcc13d1 1127 [SF12] = us2osticks(31189), // (1022 ticks)
mluis 0:62d1edcc13d1 1128 };
mluis 0:62d1edcc13d1 1129
mluis 0:62d1edcc13d1 1130 // called by hal ext IRQ handler
mluis 0:62d1edcc13d1 1131 // (radio goes to stanby mode after tx/rx operations)
tmulrooney 5:464c1f2d6cbb 1132 void radio_irq_handler (u1_t dio)
tmulrooney 5:464c1f2d6cbb 1133 {
tmulrooney 7:29058a7ccf23 1134 debug_val("radio_irq_handler enter %d\r\n",dio);
mluis 0:62d1edcc13d1 1135 ostime_t now = os_getTime();
mluis 0:62d1edcc13d1 1136 if( (readReg(RegOpMode) & OPMODE_LORA) != 0) { // LORA modem
mluis 1:d3b7bde3995c 1137 u1_t flags = readReg(LORARegIrqFlags);
mluis 1:d3b7bde3995c 1138 if( flags & IRQ_LORA_TXDONE_MASK ) {
mluis 1:d3b7bde3995c 1139 // save exact tx time
mluis 1:d3b7bde3995c 1140 LMIC.txend = now - us2osticks(43); // TXDONE FIXUP
mluis 1:d3b7bde3995c 1141 } else if( flags & IRQ_LORA_RXDONE_MASK ) {
mluis 1:d3b7bde3995c 1142 // save exact rx time
mluis 1:d3b7bde3995c 1143 if(getBw(LMIC.rps) == BW125) {
mluis 1:d3b7bde3995c 1144 now -= LORA_RXDONE_FIXUP[getSf(LMIC.rps)];
mluis 1:d3b7bde3995c 1145 }
mluis 1:d3b7bde3995c 1146 LMIC.rxtime = now;
mluis 1:d3b7bde3995c 1147 // read the PDU and inform the MAC that we received something
mluis 1:d3b7bde3995c 1148 LMIC.dataLen = (readReg(LORARegModemConfig1) & SX1272_MC1_IMPLICIT_HEADER_MODE_ON) ?
mluis 1:d3b7bde3995c 1149 readReg(LORARegPayloadLength) : readReg(LORARegRxNbBytes);
mluis 1:d3b7bde3995c 1150 // set FIFO read address pointer
mluis 1:d3b7bde3995c 1151 writeReg(LORARegFifoAddrPtr, readReg(LORARegFifoRxCurrentAddr));
mluis 1:d3b7bde3995c 1152 // now read the FIFO
mluis 1:d3b7bde3995c 1153 readBuf(RegFifo, LMIC.frame, LMIC.dataLen);
mluis 1:d3b7bde3995c 1154 // read rx quality parameters
mluis 1:d3b7bde3995c 1155 LMIC.snr = readReg(LORARegPktSnrValue); // SNR [dB] * 4
mluis 1:d3b7bde3995c 1156 LMIC.rssi = readReg(LORARegPktRssiValue) - 125 + 64; // RSSI [dBm] (-196...+63)
mluis 1:d3b7bde3995c 1157 } else if( flags & IRQ_LORA_RXTOUT_MASK ) {
mluis 1:d3b7bde3995c 1158 // indicate timeout
mluis 1:d3b7bde3995c 1159 LMIC.dataLen = 0;
mluis 1:d3b7bde3995c 1160 }
mluis 0:62d1edcc13d1 1161 // mask all radio IRQs
mluis 0:62d1edcc13d1 1162 writeReg(LORARegIrqFlagsMask, 0xFF);
mluis 0:62d1edcc13d1 1163 // clear radio IRQ flags
mluis 0:62d1edcc13d1 1164 writeReg(LORARegIrqFlags, 0xFF);
mluis 0:62d1edcc13d1 1165 } else { // FSK modem
mluis 1:d3b7bde3995c 1166 u1_t flags1 = readReg(FSKRegIrqFlags1);
mluis 1:d3b7bde3995c 1167 u1_t flags2 = readReg(FSKRegIrqFlags2);
mluis 1:d3b7bde3995c 1168 if( flags2 & IRQ_FSK2_PACKETSENT_MASK ) {
mluis 1:d3b7bde3995c 1169 // save exact tx time
mluis 1:d3b7bde3995c 1170 LMIC.txend = now;
mluis 0:62d1edcc13d1 1171 } else if( flags2 & IRQ_FSK2_PAYLOADREADY_MASK ) {
mluis 1:d3b7bde3995c 1172 // save exact rx time
mluis 1:d3b7bde3995c 1173 LMIC.rxtime = now;
mluis 1:d3b7bde3995c 1174 // read the PDU and inform the MAC that we received something
mluis 1:d3b7bde3995c 1175 LMIC.dataLen = readReg(FSKRegPayloadLength);
mluis 1:d3b7bde3995c 1176 // now read the FIFO
mluis 1:d3b7bde3995c 1177 readBuf(RegFifo, LMIC.frame, LMIC.dataLen);
mluis 1:d3b7bde3995c 1178 // read rx quality parameters
mluis 1:d3b7bde3995c 1179 LMIC.snr = 0; // determine snr
mluis 1:d3b7bde3995c 1180 LMIC.rssi = 0; // determine rssi
mluis 1:d3b7bde3995c 1181 } else if( flags1 & IRQ_FSK1_TIMEOUT_MASK ) {
mluis 1:d3b7bde3995c 1182 // indicate timeout
mluis 1:d3b7bde3995c 1183 LMIC.dataLen = 0;
mluis 1:d3b7bde3995c 1184 } else {
mluis 0:62d1edcc13d1 1185 while(1);
mluis 0:62d1edcc13d1 1186 }
mluis 0:62d1edcc13d1 1187 }
mluis 0:62d1edcc13d1 1188 // go from stanby to sleep
mluis 0:62d1edcc13d1 1189 opmode(OPMODE_SLEEP);
mluis 1:d3b7bde3995c 1190 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 1191 txStateIo = 0;
mluis 1:d3b7bde3995c 1192 rxStateIo = 0;
mluis 1:d3b7bde3995c 1193 #endif
mluis 0:62d1edcc13d1 1194 // run os job (use preset func ptr)
mluis 0:62d1edcc13d1 1195 os_setCallback(&LMIC.osjob, LMIC.osjob.func);
mluis 0:62d1edcc13d1 1196 }
mluis 0:62d1edcc13d1 1197
tmulrooney 5:464c1f2d6cbb 1198 void os_radio (u1_t mode)
tmulrooney 5:464c1f2d6cbb 1199 {
tmulrooney 7:29058a7ccf23 1200 //debug("os_radio enter\r\n");
tmulrooney 7:29058a7ccf23 1201 // hal_disableIRQs();
mluis 0:62d1edcc13d1 1202 switch (mode) {
mluis 0:62d1edcc13d1 1203 case RADIO_RST:
mluis 0:62d1edcc13d1 1204 // put radio to sleep
mluis 0:62d1edcc13d1 1205 opmode(OPMODE_SLEEP);
mluis 1:d3b7bde3995c 1206 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 1207 txStateIo = 0;
mluis 1:d3b7bde3995c 1208 rxStateIo = 0;
mluis 1:d3b7bde3995c 1209 #endif
mluis 0:62d1edcc13d1 1210 break;
mluis 0:62d1edcc13d1 1211
mluis 0:62d1edcc13d1 1212 case RADIO_TX:
mluis 1:d3b7bde3995c 1213 // transmit frame now
mluis 0:62d1edcc13d1 1214 starttx(); // buf=LMIC.frame, len=LMIC.dataLen
mluis 1:d3b7bde3995c 1215 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 1216 txStateIo = 1;
mluis 1:d3b7bde3995c 1217 #endif
mluis 0:62d1edcc13d1 1218 break;
mluis 0:62d1edcc13d1 1219
mluis 0:62d1edcc13d1 1220 case RADIO_RX:
mluis 1:d3b7bde3995c 1221 // receive frame now (exactly at rxtime)
mluis 0:62d1edcc13d1 1222 startrx(RXMODE_SINGLE); // buf=LMIC.frame, time=LMIC.rxtime, timeout=LMIC.rxsyms
mluis 1:d3b7bde3995c 1223 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 1224 rxStateIo = 1;
mluis 1:d3b7bde3995c 1225 #endif
mluis 0:62d1edcc13d1 1226 break;
mluis 0:62d1edcc13d1 1227
mluis 0:62d1edcc13d1 1228 case RADIO_RXON:
mluis 0:62d1edcc13d1 1229 // start scanning for beacon now
mluis 0:62d1edcc13d1 1230 startrx(RXMODE_SCAN); // buf=LMIC.frame
mluis 1:d3b7bde3995c 1231 #if defined(RADIO_DBG)
mluis 1:d3b7bde3995c 1232 rxStateIo = 1;
mluis 1:d3b7bde3995c 1233 #endif
mluis 0:62d1edcc13d1 1234 break;
mluis 0:62d1edcc13d1 1235 }
mluis 0:62d1edcc13d1 1236 hal_enableIRQs();
mluis 0:62d1edcc13d1 1237 }
mluis 0:62d1edcc13d1 1238
mluis 0:62d1edcc13d1 1239 #endif // USE_SMTC_RADIO_DRIVER