It is only writing and initialization.

Dependents:   ov7670_dma_nucleo_f4 NUCLEO-F446RE_testDCMI

Committer:
tmnt
Date:
Fri Apr 29 13:37:13 2016 +0000
Revision:
0:754d49cac336
Add OV7670_SCCB library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tmnt 0:754d49cac336 1
tmnt 0:754d49cac336 2
tmnt 0:754d49cac336 3 #include "mbed.h"
tmnt 0:754d49cac336 4
tmnt 0:754d49cac336 5
tmnt 0:754d49cac336 6 class ov7670_sccb
tmnt 0:754d49cac336 7 {
tmnt 0:754d49cac336 8
tmnt 0:754d49cac336 9 DigitalOut SDA;
tmnt 0:754d49cac336 10 DigitalOut SCL;
tmnt 0:754d49cac336 11
tmnt 0:754d49cac336 12 public:
tmnt 0:754d49cac336 13 ov7670_sccb(PinName _SDA,PinName _SCL);
tmnt 0:754d49cac336 14
tmnt 0:754d49cac336 15 void I2cstart(void);
tmnt 0:754d49cac336 16 void I2cstop(void);
tmnt 0:754d49cac336 17 void I2cout(unsigned char datar);
tmnt 0:754d49cac336 18 void c(unsigned char adrs,unsigned char datak);
tmnt 0:754d49cac336 19 void cam_init();
tmnt 0:754d49cac336 20
tmnt 0:754d49cac336 21 };
tmnt 0:754d49cac336 22
tmnt 0:754d49cac336 23
tmnt 0:754d49cac336 24 #define REG_COM1 0x04 /* Control 1 */
tmnt 0:754d49cac336 25 #define REG_COM6 0x0f /* Control 6 */
tmnt 0:754d49cac336 26 #define REG_AECH 0x10 /* More bits of AEC value */
tmnt 0:754d49cac336 27 #define REG_CLKRC 0x11 /* Clocl control */
tmnt 0:754d49cac336 28 #define CLK_EXT 0x40 /* Use external clock directly */
tmnt 0:754d49cac336 29 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
tmnt 0:754d49cac336 30 #define REG_COM7 0x12 /* Control 7 */
tmnt 0:754d49cac336 31 #define COM7_RESET 0x80 /* Register reset */
tmnt 0:754d49cac336 32 #define COM7_FMT_MASK 0x38
tmnt 0:754d49cac336 33 #define COM7_FMT_VGA 0x00
tmnt 0:754d49cac336 34 #define COM7_FMT_CIF 0x20 /* CIF format */
tmnt 0:754d49cac336 35 #define COM7_FMT_QVGA 0x10 /* QVGA format */
tmnt 0:754d49cac336 36 #define COM7_FMT_QCIF 0x08 /* QCIF format */
tmnt 0:754d49cac336 37 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
tmnt 0:754d49cac336 38 #define COM7_YUV 0x00 /* YUV */
tmnt 0:754d49cac336 39 #define COM7_BAYER 0x01 /* Bayer format */
tmnt 0:754d49cac336 40 #define COM7_PBAYER 0x05 /* "Processed bayer" */
tmnt 0:754d49cac336 41 #define REG_COM8 0x13 /* Control 8 */
tmnt 0:754d49cac336 42 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
tmnt 0:754d49cac336 43 #define REG_TSLB 0x3a /* lots of stuff */
tmnt 0:754d49cac336 44 #define REG_COM15 0x40 /* Control 15 */
tmnt 0:754d49cac336 45 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
tmnt 0:754d49cac336 46 #define COM15_R01FE 0x80 /* 01 to FE */
tmnt 0:754d49cac336 47 #define COM15_R00FF 0xc0 /* 00 to FF */
tmnt 0:754d49cac336 48 #define COM15_RGB565 0x10 /* RGB565 output */
tmnt 0:754d49cac336 49 #define COM15_RGB555 0x30 /* RGB555 output */
tmnt 0:754d49cac336 50 #define REG_COM16 0x41 /* Control 16 */
tmnt 0:754d49cac336 51 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
tmnt 0:754d49cac336 52 #define REG_COM17 0x42 /* Control 17 */
tmnt 0:754d49cac336 53 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
tmnt 0:754d49cac336 54 #define COM17_CBAR 0x08 /* DSP Color bar */
tmnt 0:754d49cac336 55 #define REG_CMATRIX_BASE 0x4f
tmnt 0:754d49cac336 56 #define CMATRIX_LEN 6
tmnt 0:754d49cac336 57 #define REG_CMATRIX_SIGN 0x58
tmnt 0:754d49cac336 58 #define REG_BRIGHT 0x55 /* Brightness */
tmnt 0:754d49cac336 59 #define REG_CONTRAS 0x56 /* Contrast control */
tmnt 0:754d49cac336 60
tmnt 0:754d49cac336 61 #define REG_GFIX 0x69 /* Fix gain control */
tmnt 0:754d49cac336 62
tmnt 0:754d49cac336 63 #define REG_REG76 0x76 /* OV's name */
tmnt 0:754d49cac336 64 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
tmnt 0:754d49cac336 65 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
tmnt 0:754d49cac336 66
tmnt 0:754d49cac336 67 #define REG_RGB444 0x8c /* RGB 444 control */
tmnt 0:754d49cac336 68 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
tmnt 0:754d49cac336 69 #define R444_RGBX 0x01 /* Empty nibble at end */
tmnt 0:754d49cac336 70
tmnt 0:754d49cac336 71 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
tmnt 0:754d49cac336 72 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
tmnt 0:754d49cac336 73
tmnt 0:754d49cac336 74 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
tmnt 0:754d49cac336 75 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
tmnt 0:754d49cac336 76 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
tmnt 0:754d49cac336 77 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
tmnt 0:754d49cac336 78 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
tmnt 0:754d49cac336 79 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
tmnt 0:754d49cac336 80 #define REG_BD60MAX 0xab /* 60hz banding step limit */