Tom Kreyche / Mbed 2 deprecated ADXL362_buffer

ADXL362 Deep FIFO Buffer

main.cpp@0:73eaa4d98d25, 2013-10-15 (annotated)

Committer:
tkreyche
Date:
Tue Oct 15 04:46:39 2013 +0000
Revision:
0:73eaa4d98d25
v1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tkreyche 0:73eaa4d98d25 1 #include "mbed.h"
tkreyche 0:73eaa4d98d25 2
tkreyche 0:73eaa4d98d25 3 // ACC Registers
tkreyche 0:73eaa4d98d25 4 #define ID0 0x00
tkreyche 0:73eaa4d98d25 5 #define STATUS 0x0b
tkreyche 0:73eaa4d98d25 6 #define FIFO_EL 0x0c
tkreyche 0:73eaa4d98d25 7 #define FIFO_EH 0x0d
tkreyche 0:73eaa4d98d25 8 #define RESET 0x1f
tkreyche 0:73eaa4d98d25 9 #define FIFO_CTL 0x28
tkreyche 0:73eaa4d98d25 10 #define FIFO_SAM 0x29
tkreyche 0:73eaa4d98d25 11 #define INTMAP1 0x2a
tkreyche 0:73eaa4d98d25 12 #define INTMAP2 0x2b
tkreyche 0:73eaa4d98d25 13 #define FILTER_CTL 0x2c
tkreyche 0:73eaa4d98d25 14 #define POWER_CTL 0x2d
tkreyche 0:73eaa4d98d25 15
tkreyche 0:73eaa4d98d25 16 #define WR_SPI 0x0a
tkreyche 0:73eaa4d98d25 17 #define RD_SPI 0x0b
tkreyche 0:73eaa4d98d25 18 #define RD_FIFO 0x0d
tkreyche 0:73eaa4d98d25 19 #define DOWN 0
tkreyche 0:73eaa4d98d25 20 #define UP 1
tkreyche 0:73eaa4d98d25 21
tkreyche 0:73eaa4d98d25 22 #define SAMPLE_SET 128
tkreyche 0:73eaa4d98d25 23
tkreyche 0:73eaa4d98d25 24 // function definitions
tkreyche 0:73eaa4d98d25 25 void drSub();
tkreyche 0:73eaa4d98d25 26 uint8_t ACC_ReadReg( uint8_t reg );
tkreyche 0:73eaa4d98d25 27 void ACC_WriteReg( uint8_t reg, uint8_t reg );
tkreyche 0:73eaa4d98d25 28 uint32_t drFlag;
tkreyche 0:73eaa4d98d25 29 void ACC_GetXYZ12( int16_t *x, int16_t *y, int16_t *z);
tkreyche 0:73eaa4d98d25 30 void ACC_GetXYZ8( int8_t *x, int8_t *y, int8_t *z);
tkreyche 0:73eaa4d98d25 31 void ACC_GetFIFO(uint8_t *x, uint32_t samples);
tkreyche 0:73eaa4d98d25 32 int16_t convertFIFOdata(uint8_t h, uint8_t l);
tkreyche 0:73eaa4d98d25 33
tkreyche 0:73eaa4d98d25 34 // mbed hardware config
tkreyche 0:73eaa4d98d25 35 SPI spi(p11, p12, p13); // mosi, miso, sclk
tkreyche 0:73eaa4d98d25 36 DigitalOut cs(p14);
tkreyche 0:73eaa4d98d25 37 InterruptIn dr(p15);
tkreyche 0:73eaa4d98d25 38 Serial pc(USBTX, USBRX); // tx, rx
tkreyche 0:73eaa4d98d25 39
tkreyche 0:73eaa4d98d25 40
tkreyche 0:73eaa4d98d25 41 int main()
tkreyche 0:73eaa4d98d25 42 {
tkreyche 0:73eaa4d98d25 43 // local variables
tkreyche 0:73eaa4d98d25 44 uint8_t reg;
tkreyche 0:73eaa4d98d25 45
tkreyche 0:73eaa4d98d25 46 int8_t x8 = 0;
tkreyche 0:73eaa4d98d25 47 int8_t y8 = 0;
tkreyche 0:73eaa4d98d25 48 int8_t z8 = 0;
tkreyche 0:73eaa4d98d25 49
tkreyche 0:73eaa4d98d25 50 int16_t x12 = 0;
tkreyche 0:73eaa4d98d25 51 int16_t y12 = 0;
tkreyche 0:73eaa4d98d25 52 int16_t z12 = 0;
tkreyche 0:73eaa4d98d25 53
tkreyche 0:73eaa4d98d25 54 //uint8_t fl;
tkreyche 0:73eaa4d98d25 55 //uint8_t fh;
tkreyche 0:73eaa4d98d25 56 //uint32_t fb;
tkreyche 0:73eaa4d98d25 57
tkreyche 0:73eaa4d98d25 58 uint8_t xyz[1020]; // 6 bytes per 3x sample set
tkreyche 0:73eaa4d98d25 59 for (uint32_t i = 0; i < 1020; i++) xyz[i] = 0;
tkreyche 0:73eaa4d98d25 60
tkreyche 0:73eaa4d98d25 61 // mbed serial port config
tkreyche 0:73eaa4d98d25 62 pc.baud(115200);
tkreyche 0:73eaa4d98d25 63
tkreyche 0:73eaa4d98d25 64 // mbed spi config
tkreyche 0:73eaa4d98d25 65 // spi 8 bits, mode 0, 1 MHz for adxl362
tkreyche 0:73eaa4d98d25 66 spi.format(8,0);
tkreyche 0:73eaa4d98d25 67 // 5 MHz, max for acc - works fine
tkreyche 0:73eaa4d98d25 68 spi.frequency(5000000);
tkreyche 0:73eaa4d98d25 69
tkreyche 0:73eaa4d98d25 70 // mbed interrupt config
tkreyche 0:73eaa4d98d25 71 drFlag = 0;
tkreyche 0:73eaa4d98d25 72 dr.mode(PullDown);
tkreyche 0:73eaa4d98d25 73 dr.rise(&drSub);
tkreyche 0:73eaa4d98d25 74 __disable_irq();
tkreyche 0:73eaa4d98d25 75
tkreyche 0:73eaa4d98d25 76 // reset the adxl362
tkreyche 0:73eaa4d98d25 77 wait_ms(100);
tkreyche 0:73eaa4d98d25 78 ACC_WriteReg(RESET, 0x52);
tkreyche 0:73eaa4d98d25 79 wait_ms(100);
tkreyche 0:73eaa4d98d25 80
tkreyche 0:73eaa4d98d25 81 /*
tkreyche 0:73eaa4d98d25 82 // read adxl362 registers
tkreyche 0:73eaa4d98d25 83 printf("\r\n");
tkreyche 0:73eaa4d98d25 84 // read id register
tkreyche 0:73eaa4d98d25 85 reg = ACC_ReadReg(ID0);
tkreyche 0:73eaa4d98d25 86 pc.printf("ID0 = 0x%X\r\n", reg);
tkreyche 0:73eaa4d98d25 87 reg = ACC_ReadReg(FILTER_CTL);
tkreyche 0:73eaa4d98d25 88 pc.printf("FILTER_CTL = 0x%X\r\n", reg);
tkreyche 0:73eaa4d98d25 89 */
tkreyche 0:73eaa4d98d25 90
tkreyche 0:73eaa4d98d25 91 // set FIFO
tkreyche 0:73eaa4d98d25 92 ACC_WriteReg(FIFO_CTL,0x0A); // stream mode, AH bit
tkreyche 0:73eaa4d98d25 93 //ACC_WriteReg(FIFO_CTL,0x02); // stream mode, no AH bit
tkreyche 0:73eaa4d98d25 94 reg = ACC_ReadReg(FIFO_CTL);
tkreyche 0:73eaa4d98d25 95 pc.printf("FIFO_CTL = 0x%X\r\n", reg);
tkreyche 0:73eaa4d98d25 96
tkreyche 0:73eaa4d98d25 97 //ACC_WriteReg(FIFO_SAM,0xFF); // fifo depth
tkreyche 0:73eaa4d98d25 98 ACC_WriteReg(FIFO_SAM,SAMPLE_SET * 3); // fifo depth
tkreyche 0:73eaa4d98d25 99 reg = ACC_ReadReg(FIFO_SAM);
tkreyche 0:73eaa4d98d25 100 pc.printf("FIFO_SAM = 0x%X\r\n", reg);
tkreyche 0:73eaa4d98d25 101
tkreyche 0:73eaa4d98d25 102 // set adxl362 to 4g range, 25Hz
tkreyche 0:73eaa4d98d25 103 //ACC_WriteReg(FILTER_CTL,0x51);
tkreyche 0:73eaa4d98d25 104 // 2g, 25Hz
tkreyche 0:73eaa4d98d25 105 ACC_WriteReg(FILTER_CTL,0x11);
tkreyche 0:73eaa4d98d25 106 reg = ACC_ReadReg(FILTER_CTL);
tkreyche 0:73eaa4d98d25 107 printf("FILTER_CTL = 0x%X\r\n", reg);
tkreyche 0:73eaa4d98d25 108
tkreyche 0:73eaa4d98d25 109 // map adxl362 interrupts
tkreyche 0:73eaa4d98d25 110 //ACC_WriteReg(INTMAP1,0x01); //data ready
tkreyche 0:73eaa4d98d25 111 ACC_WriteReg(INTMAP1,0x04); //watermark
tkreyche 0:73eaa4d98d25 112 reg = ACC_ReadReg(INTMAP1);
tkreyche 0:73eaa4d98d25 113 pc.printf("INTMAP1 = 0x%X\r\n", reg);
tkreyche 0:73eaa4d98d25 114
tkreyche 0:73eaa4d98d25 115 // set adxl362 to measurement mode, ultralow noise
tkreyche 0:73eaa4d98d25 116 ACC_WriteReg(POWER_CTL,0x22);
tkreyche 0:73eaa4d98d25 117 reg = ACC_ReadReg(POWER_CTL);
tkreyche 0:73eaa4d98d25 118 pc.printf("POWER_CTL = 0x%X\r\n", reg);
tkreyche 0:73eaa4d98d25 119
tkreyche 0:73eaa4d98d25 120
tkreyche 0:73eaa4d98d25 121 // start continuous processing adxl362 data
tkreyche 0:73eaa4d98d25 122 __enable_irq();
tkreyche 0:73eaa4d98d25 123
tkreyche 0:73eaa4d98d25 124 uint64_t j = 0;
tkreyche 0:73eaa4d98d25 125
tkreyche 0:73eaa4d98d25 126 while(1) {
tkreyche 0:73eaa4d98d25 127
tkreyche 0:73eaa4d98d25 128 if(drFlag == 1) {
tkreyche 0:73eaa4d98d25 129
tkreyche 0:73eaa4d98d25 130
tkreyche 0:73eaa4d98d25 131 //fl = ACC_ReadReg(FIFO_EL);
tkreyche 0:73eaa4d98d25 132 //fh = ACC_ReadReg(FIFO_EH);
tkreyche 0:73eaa4d98d25 133 //fb = (fh << 8) | fl;
tkreyche 0:73eaa4d98d25 134 //pc.printf("\r\n%04X\r\n", fb);
tkreyche 0:73eaa4d98d25 135
tkreyche 0:73eaa4d98d25 136 ACC_GetFIFO(&xyz[0],SAMPLE_SET);
tkreyche 0:73eaa4d98d25 137
tkreyche 0:73eaa4d98d25 138 pc.printf("--%u------------------------------------------------------------\r\n", j);
tkreyche 0:73eaa4d98d25 139
tkreyche 0:73eaa4d98d25 140 for (uint32_t i = 0; i < SAMPLE_SET * 6; i+=6) {
tkreyche 0:73eaa4d98d25 141
tkreyche 0:73eaa4d98d25 142 // useful use for testing
tkreyche 0:73eaa4d98d25 143 /*
tkreyche 0:73eaa4d98d25 144 uint8_t xAddr = (xyz[i+1] & 0xC0) >> 6;
tkreyche 0:73eaa4d98d25 145 uint8_t yAddr = (xyz[i+3] & 0xC0) >> 6;
tkreyche 0:73eaa4d98d25 146 uint8_t zAddr = (xyz[i+5] & 0xC0) >> 6;
tkreyche 0:73eaa4d98d25 147 pc.printf("%u %02x %02x %02x\r\n", j, xAddr, yAddr, zAddr);
tkreyche 0:73eaa4d98d25 148 */
tkreyche 0:73eaa4d98d25 149
tkreyche 0:73eaa4d98d25 150 int16_t x = convertFIFOdata(xyz[i+1], xyz[i]);
tkreyche 0:73eaa4d98d25 151 int16_t y = convertFIFOdata(xyz[i+3], xyz[i+2]);
tkreyche 0:73eaa4d98d25 152 int16_t z = convertFIFOdata(xyz[i+5], xyz[i+4]);
tkreyche 0:73eaa4d98d25 153
tkreyche 0:73eaa4d98d25 154 pc.printf("%+05d %+05d %+05d\r\n",x,y,z);
tkreyche 0:73eaa4d98d25 155 j++;
tkreyche 0:73eaa4d98d25 156 drFlag = 0;
tkreyche 0:73eaa4d98d25 157 }
tkreyche 0:73eaa4d98d25 158 }
tkreyche 0:73eaa4d98d25 159
tkreyche 0:73eaa4d98d25 160 if(drFlag == 8) {
tkreyche 0:73eaa4d98d25 161 ACC_GetXYZ8(&x8, &y8, &z8);
tkreyche 0:73eaa4d98d25 162 pc.printf("%+04d %+04d %+04d\r\n", x8,y8,z8);
tkreyche 0:73eaa4d98d25 163 drFlag = 0;
tkreyche 0:73eaa4d98d25 164 }
tkreyche 0:73eaa4d98d25 165
tkreyche 0:73eaa4d98d25 166 else if(drFlag == 12) {
tkreyche 0:73eaa4d98d25 167 ACC_GetXYZ12(&x12, &y12, &z12);
tkreyche 0:73eaa4d98d25 168 pc.printf ("%+05d %+05d %+05d\r\n",x12, y12, z12);
tkreyche 0:73eaa4d98d25 169 //pc.printf("%04X, %04X, %04X\r\n", x12, y12, z12);
tkreyche 0:73eaa4d98d25 170 drFlag = 0;
tkreyche 0:73eaa4d98d25 171 }
tkreyche 0:73eaa4d98d25 172
tkreyche 0:73eaa4d98d25 173 }
tkreyche 0:73eaa4d98d25 174 }
tkreyche 0:73eaa4d98d25 175
tkreyche 0:73eaa4d98d25 176 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 177 // convert fifo sample to unsigned int
tkreyche 0:73eaa4d98d25 178 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 179 int16_t convertFIFOdata(uint8_t hiByte, uint8_t loByte)
tkreyche 0:73eaa4d98d25 180 {
tkreyche 0:73eaa4d98d25 181 /*
tkreyche 0:73eaa4d98d25 182 //mask off type bits
tkreyche 0:73eaa4d98d25 183 uint16_t x = ((h & 0x3F) << 8);
tkreyche 0:73eaa4d98d25 184 // combine low byte
tkreyche 0:73eaa4d98d25 185 x = x | l;
tkreyche 0:73eaa4d98d25 186 // get sign bits, copy into B15, B14, combine
tkreyche 0:73eaa4d98d25 187 x = ((x & 0x3000) << 2) | x;
tkreyche 0:73eaa4d98d25 188 int16_t y = x;
tkreyche 0:73eaa4d98d25 189 return (y);
tkreyche 0:73eaa4d98d25 190 */
tkreyche 0:73eaa4d98d25 191 //mask off id bits, combine low byte
tkreyche 0:73eaa4d98d25 192 int16_t x = ((hiByte & 0x3F) << 8) | loByte;
tkreyche 0:73eaa4d98d25 193 // get sign bits, copy into B15, B14, combine
tkreyche 0:73eaa4d98d25 194 x = ((x & 0x3000) << 2) | x;
tkreyche 0:73eaa4d98d25 195 return(x);
tkreyche 0:73eaa4d98d25 196 }
tkreyche 0:73eaa4d98d25 197
tkreyche 0:73eaa4d98d25 198
tkreyche 0:73eaa4d98d25 199 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 200 // read FIFO
tkreyche 0:73eaa4d98d25 201 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 202
tkreyche 0:73eaa4d98d25 203 void ACC_GetFIFO(uint8_t *x, uint32_t samples)
tkreyche 0:73eaa4d98d25 204 {
tkreyche 0:73eaa4d98d25 205 cs = DOWN;
tkreyche 0:73eaa4d98d25 206 spi.write(RD_FIFO);
tkreyche 0:73eaa4d98d25 207 for(int i = 0; i < samples * 6; i++) {
tkreyche 0:73eaa4d98d25 208 *x = spi.write(0x00);
tkreyche 0:73eaa4d98d25 209 x++;
tkreyche 0:73eaa4d98d25 210 }
tkreyche 0:73eaa4d98d25 211
tkreyche 0:73eaa4d98d25 212 cs = UP;
tkreyche 0:73eaa4d98d25 213 }
tkreyche 0:73eaa4d98d25 214
tkreyche 0:73eaa4d98d25 215 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 216 // read 8-bit x,y,z data
tkreyche 0:73eaa4d98d25 217 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 218
tkreyche 0:73eaa4d98d25 219 void ACC_GetXYZ8(int8_t* x, int8_t* y, int8_t* z)
tkreyche 0:73eaa4d98d25 220 {
tkreyche 0:73eaa4d98d25 221
tkreyche 0:73eaa4d98d25 222 cs = DOWN;
tkreyche 0:73eaa4d98d25 223 spi.write(RD_SPI);
tkreyche 0:73eaa4d98d25 224 spi.write(0x08);
tkreyche 0:73eaa4d98d25 225
tkreyche 0:73eaa4d98d25 226 *x = spi.write(0x00);
tkreyche 0:73eaa4d98d25 227 *y = spi.write(0x00);
tkreyche 0:73eaa4d98d25 228 *z = spi.write(0x00);
tkreyche 0:73eaa4d98d25 229
tkreyche 0:73eaa4d98d25 230 cs = UP;
tkreyche 0:73eaa4d98d25 231 }
tkreyche 0:73eaa4d98d25 232
tkreyche 0:73eaa4d98d25 233 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 234 // read 12-bit x,y,z data
tkreyche 0:73eaa4d98d25 235 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 236
tkreyche 0:73eaa4d98d25 237 void ACC_GetXYZ12(int16_t* x, int16_t* y, int16_t* z)
tkreyche 0:73eaa4d98d25 238 {
tkreyche 0:73eaa4d98d25 239 int16_t xyzVal[6] = {0, 0, 0, 0, 0, 0};
tkreyche 0:73eaa4d98d25 240
tkreyche 0:73eaa4d98d25 241 cs = DOWN;
tkreyche 0:73eaa4d98d25 242 spi.write(RD_SPI);
tkreyche 0:73eaa4d98d25 243 spi.write(0x0E);
tkreyche 0:73eaa4d98d25 244
tkreyche 0:73eaa4d98d25 245 for (uint32_t i = 0; i < 6; i++) {
tkreyche 0:73eaa4d98d25 246 xyzVal[i] = spi.write(0x00);
tkreyche 0:73eaa4d98d25 247 }
tkreyche 0:73eaa4d98d25 248
tkreyche 0:73eaa4d98d25 249 *x = (xyzVal[1] << 8) + xyzVal[0];
tkreyche 0:73eaa4d98d25 250 *y = (xyzVal[3] << 8) + xyzVal[2];
tkreyche 0:73eaa4d98d25 251 *z = (xyzVal[5] << 8) + xyzVal[4];
tkreyche 0:73eaa4d98d25 252
tkreyche 0:73eaa4d98d25 253 cs = UP;
tkreyche 0:73eaa4d98d25 254 }
tkreyche 0:73eaa4d98d25 255
tkreyche 0:73eaa4d98d25 256 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 257 // read ACC 8-bit registers
tkreyche 0:73eaa4d98d25 258 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 259
tkreyche 0:73eaa4d98d25 260 uint8_t ACC_ReadReg( uint8_t reg )
tkreyche 0:73eaa4d98d25 261 {
tkreyche 0:73eaa4d98d25 262 cs = DOWN;
tkreyche 0:73eaa4d98d25 263 spi.write(RD_SPI);
tkreyche 0:73eaa4d98d25 264 spi.write(reg);
tkreyche 0:73eaa4d98d25 265 uint8_t val = spi.write(0x00);
tkreyche 0:73eaa4d98d25 266 cs = UP;
tkreyche 0:73eaa4d98d25 267 return (val);
tkreyche 0:73eaa4d98d25 268 }
tkreyche 0:73eaa4d98d25 269
tkreyche 0:73eaa4d98d25 270 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 271 // write ACC 8-bit register
tkreyche 0:73eaa4d98d25 272 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 273
tkreyche 0:73eaa4d98d25 274 void ACC_WriteReg( uint8_t reg, uint8_t cmd )
tkreyche 0:73eaa4d98d25 275 {
tkreyche 0:73eaa4d98d25 276 cs = DOWN;
tkreyche 0:73eaa4d98d25 277 spi.write(WR_SPI);
tkreyche 0:73eaa4d98d25 278 spi.write(reg);
tkreyche 0:73eaa4d98d25 279 spi.write(cmd);
tkreyche 0:73eaa4d98d25 280 cs = UP;
tkreyche 0:73eaa4d98d25 281 }
tkreyche 0:73eaa4d98d25 282
tkreyche 0:73eaa4d98d25 283 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 284 // Handle data ready interrupt
tkreyche 0:73eaa4d98d25 285 // just sets data ready flag
tkreyche 0:73eaa4d98d25 286 ////////////////////////////////////////////////////////////////////////////////////
tkreyche 0:73eaa4d98d25 287
tkreyche 0:73eaa4d98d25 288 void drSub()
tkreyche 0:73eaa4d98d25 289 {
tkreyche 0:73eaa4d98d25 290 drFlag = 1;
tkreyche 0:73eaa4d98d25 291 //drFlag = 8;
tkreyche 0:73eaa4d98d25 292 //drFlag = 12;
tkreyche 0:73eaa4d98d25 293 }