Keisha Brathwaite / KBrat-SSD645-HW-8_1_SLCD

KBrat-SSD645-HW-8_1_SLCD

Fork of SLCD by Erik -

LCDconfig.h@1:1579bcd31410, 2014-01-20 (annotated)

Committer:
star297
Date:
Mon Jan 20 21:08:32 2014 +0000
Revision:
1:1579bcd31410
Child:
3:f70873bc6121
added functions

Who changed what in which revision?

UserRevisionLine numberNew contents of line
star297 1:1579bcd31410 1 #ifndef __LCDConfig_H_
star297 1:1579bcd31410 2 #define __LCDConfig_H_
star297 1:1579bcd31410 3
star297 1:1579bcd31410 4 #include "FRDM-s401.h" // 4x7 segdisplay
star297 1:1579bcd31410 5
star297 1:1579bcd31410 6
star297 1:1579bcd31410 7 #if 1 // VREF to VLL1
star297 1:1579bcd31410 8 /* Following configuration is used for LCD default initialization */
star297 1:1579bcd31410 9 #define _LCDRVEN (1) //
star297 1:1579bcd31410 10 #define _LCDRVTRIM (8) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
star297 1:1579bcd31410 11 #define _LCDCPSEL (1) // charge pump select 0 or 1
star297 1:1579bcd31410 12 #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
star297 1:1579bcd31410 13 #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
star297 1:1579bcd31410 14 #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock
star297 1:1579bcd31410 15
star297 1:1579bcd31410 16 #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms
star297 1:1579bcd31410 17 #define _LCDSUPPLY (1)
star297 1:1579bcd31410 18 #define _LCDHREF (0) // 0 or 1
star297 1:1579bcd31410 19 #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock
star297 1:1579bcd31410 20 #define _LCDLCK (1) //Any number between 0 and 7
star297 1:1579bcd31410 21 #define _LCDBLINKRATE (3) //Any number between 0 and 7
star297 1:1579bcd31410 22
star297 1:1579bcd31410 23
star297 1:1579bcd31410 24 #else //VLL3 to VDD internally
star297 1:1579bcd31410 25 /* Following configuration is used for LCD default initialization */
star297 1:1579bcd31410 26 #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock
star297 1:1579bcd31410 27 #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock
star297 1:1579bcd31410 28 #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms
star297 1:1579bcd31410 29 #define _LCDSUPPLY (0)
star297 1:1579bcd31410 30 #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
star297 1:1579bcd31410 31 #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
star297 1:1579bcd31410 32 #define _LCDRVTRIM (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
star297 1:1579bcd31410 33 #define _LCDHREF (0) // 0 or 1
star297 1:1579bcd31410 34 #define _LCDCPSEL (1) // 0 or 1
star297 1:1579bcd31410 35 #define _LCDRVEN (0) //
star297 1:1579bcd31410 36 #define _LCDBLINKRATE (3) //Any number between 0 and 7
star297 1:1579bcd31410 37 #define _LCDLCK (0) //Any number between 0 and 7
star297 1:1579bcd31410 38
star297 1:1579bcd31410 39 #endif
star297 1:1579bcd31410 40
star297 1:1579bcd31410 41
star297 1:1579bcd31410 42
star297 1:1579bcd31410 43
star297 1:1579bcd31410 44 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 0 ~|~|~|~|~|~|~|~|~|~|~|~|~*/
star297 1:1579bcd31410 45 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
star297 1:1579bcd31410 46 #define _LCDINTENABLE (1)
star297 1:1579bcd31410 47
star297 1:1579bcd31410 48 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 1 ~|~|~|~|~|~|~|~|~|~|~|~|~|*/
star297 1:1579bcd31410 49 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
star297 1:1579bcd31410 50 #define _LCDFRAMEINTERRUPT (0) //0 Disable Frame Frequency Interrupt
star297 1:1579bcd31410 51 //1 Enable an LCD interrupt that coincides with the LCD frame frequency
star297 1:1579bcd31410 52 #define _LCDFULLCPLDIRIVE (0) // 0 GPIO shared with the LCD. Inputs levels and internal pullup reference to VDD
star297 1:1579bcd31410 53 // 1 If VSUPPLY=11and RVEN=0. Inputs levels and internal pullup reference to VLL3
star297 1:1579bcd31410 54 #define _LCDWAITMODE (0) // 0 Allows the LCD driver and charge pump to continue running during wait mode
star297 1:1579bcd31410 55 // 1 Disable the LCD when the MCU goes into wait mode
star297 1:1579bcd31410 56 #define _LCDSTOPMODE (0) // 0 Allows the LCD driver and charge pump to continue running during stop2 or stop3
star297 1:1579bcd31410 57
star297 1:1579bcd31410 58 // 1 Disable the LCD when and charge pump when the MCU goes into stop2 or stop3
star297 1:1579bcd31410 59
star297 1:1579bcd31410 60 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Voltage Supply Register ~|~|~|~|~|~|~|~|~|~|~|~*/
star297 1:1579bcd31410 61 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
star297 1:1579bcd31410 62 #define _LCDHIGHREF (0) //0 Divide input VIREG=1.0v
star297 1:1579bcd31410 63 //1 Do not divide the input VIREG=1.67v
star297 1:1579bcd31410 64 #define _LCDBBYPASS (0) //Determines whether the internal LCD op amp buffer is bypassed
star297 1:1579bcd31410 65 //0 Buffered mode
star297 1:1579bcd31410 66 //1 Unbuffered mode
star297 1:1579bcd31410 67
star297 1:1579bcd31410 68 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Regulated Voltage Control |~|~|~|~|~|~|~|~|~|~*/
star297 1:1579bcd31410 69 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
star297 1:1579bcd31410 70 #define _LCDCONTRAST (1) //Contrast by software 0 -- Disable 1-- Enable
star297 1:1579bcd31410 71 #define _LVLCONTRAST (0) //Any number between 0 and 15, if the number is bigger the glass get darker
star297 1:1579bcd31410 72
star297 1:1579bcd31410 73 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Blink Control Register ~|~|~|~|~|~|~|~|~|~|~|~*/
star297 1:1579bcd31410 74 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
star297 1:1579bcd31410 75 #define _LCDBLINKCONTROL (0) //0 Disable blink mode
star297 1:1579bcd31410 76 //1 Enable blink mode
star297 1:1579bcd31410 77 #define _LCDALTMODE (0) //0 Normal display
star297 1:1579bcd31410 78 //1 Alternate display for 4 backplanes or less the LCD backplane sequencer changes to otuput an alternate display
star297 1:1579bcd31410 79 #define _LCDBLANKDISP (0) //0 Do not blank display
star297 1:1579bcd31410 80 //1 Blank display if you put it in 0 the text before blank is manteined
star297 1:1579bcd31410 81 #define _LCDBLINKMODE (0) //0 Display blank during the blink period
star297 1:1579bcd31410 82 //1 Display alternate displat during blink period (Ignored if duty is 5 or greater)
star297 1:1579bcd31410 83
star297 1:1579bcd31410 84
star297 1:1579bcd31410 85 //Calculated values
star297 1:1579bcd31410 86 #define _LCDUSEDPINS (_LCDFRONTPLANES + _LCDBACKPLANES)
star297 1:1579bcd31410 87 #define _LCDDUTY (_LCDBACKPLANES-1) //Any number between 0 and 7
star297 1:1579bcd31410 88 #define LCD_WF_BASE LCD->WF8B[0]
star297 1:1579bcd31410 89
star297 1:1579bcd31410 90 // General definitions used by the LCD library
star297 1:1579bcd31410 91 #define SymbolON(LCDn,bit) *((uint8 *)&LCD_WF_BASE + LCDn) |= (1<<(bit))
star297 1:1579bcd31410 92 #define SymbolOFF(LCDn,bit) *((uint8 *)&LCD_WF_BASE + LCDn) &= ~(1<<(bit))
star297 1:1579bcd31410 93 #define LCD_WF(x) *((uint8 *)&LCD_WF_BASE + x)
star297 1:1579bcd31410 94
star297 1:1579bcd31410 95 /*LCD Fault Detections Consts*/
star297 1:1579bcd31410 96 #define FP_TYPE 0x00 // pin is a Front Plane
star297 1:1579bcd31410 97 #define BP_TYPE 0x80 // pin is Back Plane
star297 1:1579bcd31410 98
star297 1:1579bcd31410 99 // Fault Detect Preescaler Options
star297 1:1579bcd31410 100 #define FDPRS_1 0
star297 1:1579bcd31410 101 #define FDPRS_2 1
star297 1:1579bcd31410 102 #define FDPRS_4 2
star297 1:1579bcd31410 103 #define FDPRS_8 3
star297 1:1579bcd31410 104 #define FDPRS_16 4
star297 1:1579bcd31410 105 #define FDPRS_32 5
star297 1:1579bcd31410 106 #define FDPRS_64 6
star297 1:1579bcd31410 107 #define FDPRS_128 7
star297 1:1579bcd31410 108
star297 1:1579bcd31410 109 // Fault Detect Sample Window Width Values
star297 1:1579bcd31410 110 #define FDSWW_4 0
star297 1:1579bcd31410 111 #define FDSWW_8 1
star297 1:1579bcd31410 112 #define FDSWW_16 2
star297 1:1579bcd31410 113 #define FDSWW_32 3
star297 1:1579bcd31410 114 #define FDSWW_64 4
star297 1:1579bcd31410 115 #define FDSWW_128 5
star297 1:1579bcd31410 116 #define FDSWW_256 6
star297 1:1579bcd31410 117 #define FDSWW_512 7
star297 1:1579bcd31410 118
star297 1:1579bcd31410 119 /*
star297 1:1579bcd31410 120 Mask Bit definitions used f
star297 1:1579bcd31410 121 */
star297 1:1579bcd31410 122 #define mBIT0 1
star297 1:1579bcd31410 123 #define mBIT1 2
star297 1:1579bcd31410 124 #define mBIT2 4
star297 1:1579bcd31410 125 #define mBIT3 8
star297 1:1579bcd31410 126 #define mBIT4 16
star297 1:1579bcd31410 127 #define mBIT5 32
star297 1:1579bcd31410 128 #define mBIT6 64
star297 1:1579bcd31410 129 #define mBIT7 128
star297 1:1579bcd31410 130 #define mBIT8 256
star297 1:1579bcd31410 131 #define mBIT9 512
star297 1:1579bcd31410 132 #define mBIT10 1024
star297 1:1579bcd31410 133 #define mBIT11 2048
star297 1:1579bcd31410 134 #define mBIT12 4096
star297 1:1579bcd31410 135 #define mBIT13 8192
star297 1:1579bcd31410 136 #define mBIT14 16384
star297 1:1579bcd31410 137 #define mBIT15 32768
star297 1:1579bcd31410 138 #define mBIT16 65536
star297 1:1579bcd31410 139 #define mBIT17 131072
star297 1:1579bcd31410 140 #define mBIT18 262144
star297 1:1579bcd31410 141 #define mBIT19 524288
star297 1:1579bcd31410 142 #define mBIT20 1048576
star297 1:1579bcd31410 143 #define mBIT21 2097152
star297 1:1579bcd31410 144 #define mBIT22 4194304
star297 1:1579bcd31410 145 #define mBIT23 8388608
star297 1:1579bcd31410 146 #define mBIT24 16777216
star297 1:1579bcd31410 147 #define mBIT25 33554432
star297 1:1579bcd31410 148 #define mBIT26 67108864
star297 1:1579bcd31410 149 #define mBIT27 134217728
star297 1:1579bcd31410 150 #define mBIT28 268435456
star297 1:1579bcd31410 151 #define mBIT29 536870912
star297 1:1579bcd31410 152 #define mBIT30 1073741824
star297 1:1579bcd31410 153 #define mBIT31 2147483648
star297 1:1579bcd31410 154
star297 1:1579bcd31410 155 #define mBIT32 1
star297 1:1579bcd31410 156 #define mBIT33 2
star297 1:1579bcd31410 157 #define mBIT34 4
star297 1:1579bcd31410 158 #define mBIT35 8
star297 1:1579bcd31410 159 #define mBIT36 16
star297 1:1579bcd31410 160 #define mBIT37 32
star297 1:1579bcd31410 161 #define mBIT38 64
star297 1:1579bcd31410 162 #define mBIT39 128
star297 1:1579bcd31410 163 #define mBIT40 256
star297 1:1579bcd31410 164 #define mBIT41 512
star297 1:1579bcd31410 165 #define mBIT42 1024
star297 1:1579bcd31410 166 #define mBIT43 2048
star297 1:1579bcd31410 167 #define mBIT44 4096
star297 1:1579bcd31410 168 #define mBIT45 8192
star297 1:1579bcd31410 169 #define mBIT46 16384
star297 1:1579bcd31410 170 #define mBIT47 32768
star297 1:1579bcd31410 171 #define mBIT48 65536
star297 1:1579bcd31410 172 #define mBIT49 131072
star297 1:1579bcd31410 173 #define mBIT50 262144
star297 1:1579bcd31410 174 #define mBIT51 524288
star297 1:1579bcd31410 175 #define mBIT52 1048576
star297 1:1579bcd31410 176 #define mBIT53 2097152
star297 1:1579bcd31410 177 #define mBIT54 4194304
star297 1:1579bcd31410 178 #define mBIT55 8388608
star297 1:1579bcd31410 179 #define mBIT56 16777216
star297 1:1579bcd31410 180 #define mBIT57 33554432
star297 1:1579bcd31410 181 #define mBIT58 67108864
star297 1:1579bcd31410 182 #define mBIT59 134217728
star297 1:1579bcd31410 183 #define mBIT60 268435456
star297 1:1579bcd31410 184 #define mBIT61 536870912
star297 1:1579bcd31410 185 #define mBIT62 1073741824
star297 1:1579bcd31410 186 #define mBIT63 2147483648
star297 1:1579bcd31410 187
star297 1:1579bcd31410 188 #endif /* __LCDConfig_H_ */
star297 1:1579bcd31410 189