The SZ / BSP_DISCO_F746NG_patch_fixed

bugfixes and reduced version for disco board only

Dependents:   Scope DISCO-F746NG_Sinewave DISCO-F746NG_Sweep DISCO-F746NG_Oscilloscope ... more

Fork of BSP_DISCO_F746NG_patch by Nirvana Jay

stm32746g_discovery_sdram.h@7:a4e658110084, 2016-01-31 (annotated)

Committer:
the_sz
Date:
Sun Jan 31 17:45:21 2016 +0000
Revision:
7:a4e658110084
Parent:
0:c9112f0c67e3 
remove debug line

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 0:c9112f0c67e3 1 /**
bcostm 0:c9112f0c67e3 2 ******************************************************************************
bcostm 0:c9112f0c67e3 3 * @file stm32746g_discovery_sdram.h
bcostm 0:c9112f0c67e3 4 * @author MCD Application Team
bcostm 0:c9112f0c67e3 5 * @version V1.0.0
bcostm 0:c9112f0c67e3 6 * @date 25-June-2015
bcostm 0:c9112f0c67e3 7 * @brief This file contains the common defines and functions prototypes for
bcostm 0:c9112f0c67e3 8 * the stm32746g_discovery_sdram.c driver.
bcostm 0:c9112f0c67e3 9 ******************************************************************************
bcostm 0:c9112f0c67e3 10 * @attention
bcostm 0:c9112f0c67e3 11 *
bcostm 0:c9112f0c67e3 12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bcostm 0:c9112f0c67e3 13 *
bcostm 0:c9112f0c67e3 14 * Redistribution and use in source and binary forms, with or without modification,
bcostm 0:c9112f0c67e3 15 * are permitted provided that the following conditions are met:
bcostm 0:c9112f0c67e3 16 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 0:c9112f0c67e3 17 * this list of conditions and the following disclaimer.
bcostm 0:c9112f0c67e3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 0:c9112f0c67e3 19 * this list of conditions and the following disclaimer in the documentation
bcostm 0:c9112f0c67e3 20 * and/or other materials provided with the distribution.
bcostm 0:c9112f0c67e3 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 0:c9112f0c67e3 22 * may be used to endorse or promote products derived from this software
bcostm 0:c9112f0c67e3 23 * without specific prior written permission.
bcostm 0:c9112f0c67e3 24 *
bcostm 0:c9112f0c67e3 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 0:c9112f0c67e3 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 0:c9112f0c67e3 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 0:c9112f0c67e3 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 0:c9112f0c67e3 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 0:c9112f0c67e3 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 0:c9112f0c67e3 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 0:c9112f0c67e3 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 0:c9112f0c67e3 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 0:c9112f0c67e3 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 0:c9112f0c67e3 35 *
bcostm 0:c9112f0c67e3 36 ******************************************************************************
bcostm 0:c9112f0c67e3 37 */
bcostm 0:c9112f0c67e3 38
bcostm 0:c9112f0c67e3 39 /* Define to prevent recursive inclusion -------------------------------------*/
bcostm 0:c9112f0c67e3 40 #ifndef __STM32746G_DISCOVERY_SDRAM_H
bcostm 0:c9112f0c67e3 41 #define __STM32746G_DISCOVERY_SDRAM_H
bcostm 0:c9112f0c67e3 42
bcostm 0:c9112f0c67e3 43 #ifdef __cplusplus
bcostm 0:c9112f0c67e3 44 extern "C" {
bcostm 0:c9112f0c67e3 45 #endif
bcostm 0:c9112f0c67e3 46
bcostm 0:c9112f0c67e3 47 /* Includes ------------------------------------------------------------------*/
bcostm 0:c9112f0c67e3 48 #include "stm32f7xx_hal.h"
bcostm 0:c9112f0c67e3 49
bcostm 0:c9112f0c67e3 50 /** @addtogroup BSP
bcostm 0:c9112f0c67e3 51 * @{
bcostm 0:c9112f0c67e3 52 */
bcostm 0:c9112f0c67e3 53
bcostm 0:c9112f0c67e3 54 /** @addtogroup STM32746G_DISCOVERY
bcostm 0:c9112f0c67e3 55 * @{
bcostm 0:c9112f0c67e3 56 */
bcostm 0:c9112f0c67e3 57
bcostm 0:c9112f0c67e3 58 /** @addtogroup STM32746G_DISCOVERY_SDRAM
bcostm 0:c9112f0c67e3 59 * @{
bcostm 0:c9112f0c67e3 60 */
bcostm 0:c9112f0c67e3 61
bcostm 0:c9112f0c67e3 62 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types
bcostm 0:c9112f0c67e3 63 * @{
bcostm 0:c9112f0c67e3 64 */
bcostm 0:c9112f0c67e3 65
bcostm 0:c9112f0c67e3 66 /**
bcostm 0:c9112f0c67e3 67 * @brief SDRAM status structure definition
bcostm 0:c9112f0c67e3 68 */
bcostm 0:c9112f0c67e3 69 #define SDRAM_OK ((uint8_t)0x00)
bcostm 0:c9112f0c67e3 70 #define SDRAM_ERROR ((uint8_t)0x01)
bcostm 0:c9112f0c67e3 71
bcostm 0:c9112f0c67e3 72 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants
bcostm 0:c9112f0c67e3 73 * @{
bcostm 0:c9112f0c67e3 74 */
bcostm 0:c9112f0c67e3 75 #define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
bcostm 0:c9112f0c67e3 76 #define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
bcostm 0:c9112f0c67e3 77
bcostm 0:c9112f0c67e3 78 /* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
bcostm 0:c9112f0c67e3 79 #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
bcostm 0:c9112f0c67e3 80
bcostm 0:c9112f0c67e3 81 #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
bcostm 0:c9112f0c67e3 82 /* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
bcostm 0:c9112f0c67e3 83
bcostm 0:c9112f0c67e3 84 #define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
bcostm 0:c9112f0c67e3 85
bcostm 0:c9112f0c67e3 86 #define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
bcostm 0:c9112f0c67e3 87
bcostm 0:c9112f0c67e3 88 /* DMA definitions for SDRAM DMA transfer */
bcostm 0:c9112f0c67e3 89 #define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
bcostm 0:c9112f0c67e3 90 #define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
bcostm 0:c9112f0c67e3 91 #define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
bcostm 0:c9112f0c67e3 92 #define SDRAM_DMAx_STREAM DMA2_Stream0
bcostm 0:c9112f0c67e3 93 #define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
bcostm 0:c9112f0c67e3 94 #define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
bcostm 0:c9112f0c67e3 95 /**
bcostm 0:c9112f0c67e3 96 * @}
bcostm 0:c9112f0c67e3 97 */
bcostm 0:c9112f0c67e3 98
bcostm 0:c9112f0c67e3 99 /**
bcostm 0:c9112f0c67e3 100 * @brief FMC SDRAM Mode definition register defines
bcostm 0:c9112f0c67e3 101 */
bcostm 0:c9112f0c67e3 102 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
bcostm 0:c9112f0c67e3 103 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
bcostm 0:c9112f0c67e3 104 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
bcostm 0:c9112f0c67e3 105 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
bcostm 0:c9112f0c67e3 106 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
bcostm 0:c9112f0c67e3 107 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
bcostm 0:c9112f0c67e3 108 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
bcostm 0:c9112f0c67e3 109 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
bcostm 0:c9112f0c67e3 110 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
bcostm 0:c9112f0c67e3 111 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
bcostm 0:c9112f0c67e3 112 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
bcostm 0:c9112f0c67e3 113 /**
bcostm 0:c9112f0c67e3 114 * @}
bcostm 0:c9112f0c67e3 115 */
bcostm 0:c9112f0c67e3 116
bcostm 0:c9112f0c67e3 117 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro
bcostm 0:c9112f0c67e3 118 * @{
bcostm 0:c9112f0c67e3 119 */
bcostm 0:c9112f0c67e3 120 /**
bcostm 0:c9112f0c67e3 121 * @}
bcostm 0:c9112f0c67e3 122 */
bcostm 0:c9112f0c67e3 123
bcostm 0:c9112f0c67e3 124 /** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions
bcostm 0:c9112f0c67e3 125 * @{
bcostm 0:c9112f0c67e3 126 */
bcostm 0:c9112f0c67e3 127 uint8_t BSP_SDRAM_Init(void);
bcostm 0:c9112f0c67e3 128 uint8_t BSP_SDRAM_DeInit(void);
bcostm 0:c9112f0c67e3 129 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
bcostm 0:c9112f0c67e3 130 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
bcostm 0:c9112f0c67e3 131 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
bcostm 0:c9112f0c67e3 132 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
bcostm 0:c9112f0c67e3 133 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
bcostm 0:c9112f0c67e3 134 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
bcostm 0:c9112f0c67e3 135 void BSP_SDRAM_DMA_IRQHandler(void);
bcostm 0:c9112f0c67e3 136
bcostm 0:c9112f0c67e3 137 /* These functions can be modified in case the current settings (e.g. DMA stream)
bcostm 0:c9112f0c67e3 138 need to be changed for specific application needs */
bcostm 0:c9112f0c67e3 139 void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
bcostm 0:c9112f0c67e3 140 void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
bcostm 0:c9112f0c67e3 141
bcostm 0:c9112f0c67e3 142
bcostm 0:c9112f0c67e3 143 /**
bcostm 0:c9112f0c67e3 144 * @}
bcostm 0:c9112f0c67e3 145 */
bcostm 0:c9112f0c67e3 146
bcostm 0:c9112f0c67e3 147 /**
bcostm 0:c9112f0c67e3 148 * @}
bcostm 0:c9112f0c67e3 149 */
bcostm 0:c9112f0c67e3 150
bcostm 0:c9112f0c67e3 151 /**
bcostm 0:c9112f0c67e3 152 * @}
bcostm 0:c9112f0c67e3 153 */
bcostm 0:c9112f0c67e3 154
bcostm 0:c9112f0c67e3 155 /**
bcostm 0:c9112f0c67e3 156 * @}
bcostm 0:c9112f0c67e3 157 */
bcostm 0:c9112f0c67e3 158
bcostm 0:c9112f0c67e3 159 #ifdef __cplusplus
bcostm 0:c9112f0c67e3 160 }
bcostm 0:c9112f0c67e3 161 #endif
bcostm 0:c9112f0c67e3 162
bcostm 0:c9112f0c67e3 163 #endif /* __STM32746G_DISCOVERY_SDRAM_H */
bcostm 0:c9112f0c67e3 164
bcostm 0:c9112f0c67e3 165 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/