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mcp2515_defs.h

00001 /* from Microchip Example */
00002 
00003 #ifndef MCP2515_DEFS_H_
00004 #define MCP2515_DEFS_H_
00005 
00006 /*
00007 mcp2515_defs.h
00008 
00009 This file contains constants that are specific to the MCP2515.
00010 
00011 Version     Date        Description
00012 ----------------------------------------------------------------------
00013 v1.00       2003/12/11  Initial release
00014 Copyright 2003 Kimberly Otten Software Consulting
00015 
00016 Changes M. Thomas:
00017 - rename to mcp2515_defs.h
00018 - added handy definitions from kvaser-sample
00019 - status-bits
00020 
00021 */
00022 
00023 // Begin mt
00024 #define MCP_SIDH        0
00025 #define MCP_SIDL        1
00026 #define MCP_EID8        2
00027 #define MCP_EID0        3
00028 
00029 #define MCP_TXB_EXIDE_M     0x08    /* In TXBnSIDL */
00030 #define MCP_DLC_MASK        0x0F    /* 4 LSBits */
00031 #define MCP_RTR_MASK        0x40    /* (1<<6) Bit 6 */
00032 
00033 #define MCP_RXB_RX_ANY      0x60
00034 #define MCP_RXB_RX_EXT      0x40
00035 #define MCP_RXB_RX_STD      0x20
00036 #define MCP_RXB_RX_STDEXT   0x00
00037 #define MCP_RXB_RX_MASK     0x60
00038 #define MCP_RXB_BUKT_MASK   (1<<2)
00039 
00040 /*
00041 ** Bits in the TXBnCTRL registers.
00042 */
00043 #define MCP_TXB_TXBUFE_M    0x80
00044 #define MCP_TXB_ABTF_M      0x40
00045 #define MCP_TXB_MLOA_M      0x20
00046 #define MCP_TXB_TXERR_M     0x10
00047 #define MCP_TXB_TXREQ_M     0x08
00048 #define MCP_TXB_TXIE_M      0x04
00049 #define MCP_TXB_TXP10_M     0x03
00050 
00051 #define MCP_TXB_RTR_M       0x40    // In TXBnDLC
00052 #define MCP_RXB_IDE_M       0x08    // In RXBnSIDL
00053 #define MCP_RXB_RTR_M       0x40    // In RXBnDLC
00054 
00055 #define MCP_STAT_RXIF_MASK   (0x03)
00056 #define MCP_STAT_RX0IF (1<<0)
00057 #define MCP_STAT_RX1IF (1<<1)
00058 
00059 #define MCP_EFLG_RX1OVR (1<<7)
00060 #define MCP_EFLG_RX0OVR (1<<6)
00061 #define MCP_EFLG_TXBO   (1<<5)
00062 #define MCP_EFLG_TXEP   (1<<4)
00063 #define MCP_EFLG_RXEP   (1<<3)
00064 #define MCP_EFLG_TXWAR  (1<<2)
00065 #define MCP_EFLG_RXWAR  (1<<1)
00066 #define MCP_EFLG_EWARN  (1<<0)
00067 #define MCP_EFLG_ERRORMASK  (0xF8) /* 5 MS-Bits */
00068 
00069 // End mt
00070 
00071 
00072 // Define MCP2515 register addresses
00073 
00074 #define MCP_RXF0SIDH    0x00
00075 #define MCP_RXF0SIDL    0x01
00076 #define MCP_RXF0EID8    0x02
00077 #define MCP_RXF0EID0    0x03
00078 #define MCP_RXF1SIDH    0x04
00079 #define MCP_RXF1SIDL    0x05
00080 #define MCP_RXF1EID8    0x06
00081 #define MCP_RXF1EID0    0x07
00082 #define MCP_RXF2SIDH    0x08
00083 #define MCP_RXF2SIDL    0x09
00084 #define MCP_RXF2EID8    0x0A
00085 #define MCP_RXF2EID0    0x0B
00086 #define MCP_CANSTAT     0x0E
00087 #define MCP_CANCTRL     0x0F
00088 #define MCP_RXF3SIDH    0x10
00089 #define MCP_RXF3SIDL    0x11
00090 #define MCP_RXF3EID8    0x12
00091 #define MCP_RXF3EID0    0x13
00092 #define MCP_RXF4SIDH    0x14
00093 #define MCP_RXF4SIDL    0x15
00094 #define MCP_RXF4EID8    0x16
00095 #define MCP_RXF4EID0    0x17
00096 #define MCP_RXF5SIDH    0x18
00097 #define MCP_RXF5SIDL    0x19
00098 #define MCP_RXF5EID8    0x1A
00099 #define MCP_RXF5EID0    0x1B
00100 #define MCP_TEC         0x1C
00101 #define MCP_REC         0x1D
00102 #define MCP_RXM0SIDH    0x20
00103 #define MCP_RXM0SIDL    0x21
00104 #define MCP_RXM0EID8    0x22
00105 #define MCP_RXM0EID0    0x23
00106 #define MCP_RXM1SIDH    0x24
00107 #define MCP_RXM1SIDL    0x25
00108 #define MCP_RXM1EID8    0x26
00109 #define MCP_RXM1EID0    0x27
00110 #define MCP_CNF3        0x28
00111 #define MCP_CNF2        0x29
00112 #define MCP_CNF1        0x2A
00113 #define MCP_CANINTE     0x2B
00114 #define MCP_CANINTF     0x2C
00115 #define MCP_EFLG        0x2D
00116 #define MCP_TXB0CTRL    0x30
00117 #define MCP_TXB1CTRL    0x40
00118 #define MCP_TXB2CTRL    0x50
00119 #define MCP_RXB0CTRL    0x60
00120 #define MCP_RXB0SIDH    0x61
00121 #define MCP_RXB1CTRL    0x70
00122 #define MCP_RXB1SIDH    0x71
00123 
00124 
00125 #define MCP_TX_INT      0x1C        // Enable all transmit interrupts
00126 #define MCP_TX01_INT    0x0C        // Enable TXB0 and TXB1 interrupts
00127 #define MCP_RX_INT      0x03        // Enable receive interrupts
00128 #define MCP_NO_INT      0x00        // Disable all interrupts
00129 
00130 #define MCP_TX01_MASK   0x14
00131 #define MCP_TX_MASK     0x54
00132 
00133 // Define SPI Instruction Set
00134 
00135 #define MCP_WRITE       0x02
00136 
00137 #define MCP_READ        0x03
00138 
00139 #define MCP_BITMOD      0x05
00140 
00141 #define MCP_LOAD_TX0    0x40
00142 #define MCP_LOAD_TX1    0x42
00143 #define MCP_LOAD_TX2    0x44
00144 
00145 #define MCP_RTS_TX0     0x81
00146 #define MCP_RTS_TX1     0x82
00147 #define MCP_RTS_TX2     0x84
00148 #define MCP_RTS_ALL     0x87
00149 
00150 #define MCP_READ_RX0    0x90
00151 #define MCP_READ_RX1    0x94
00152 
00153 #define MCP_READ_STATUS 0xA0
00154 
00155 #define MCP_RX_STATUS   0xB0
00156 
00157 #define MCP_RESET       0xC0
00158 
00159 
00160 // CANCTRL Register Values
00161 
00162 #define MODE_NORMAL     0x00
00163 #define MODE_SLEEP      0x20
00164 #define MODE_LOOPBACK   0x40
00165 #define MODE_LISTENONLY 0x60
00166 #define MODE_CONFIG     0x80
00167 #define MODE_POWERUP    0xE0
00168 #define MODE_MASK       0xE0
00169 #define ABORT_TX        0x10
00170 #define MODE_ONESHOT    0x08
00171 #define CLKOUT_ENABLE   0x04
00172 #define CLKOUT_DISABLE  0x00
00173 #define CLKOUT_PS1      0x00
00174 #define CLKOUT_PS2      0x01
00175 #define CLKOUT_PS4      0x02
00176 #define CLKOUT_PS8      0x03
00177 
00178 
00179 // CNF1 Register Values
00180 
00181 #define SJW1            0x00
00182 #define SJW2            0x40
00183 #define SJW3            0x80
00184 #define SJW4            0xC0
00185 
00186 
00187 // CNF2 Register Values
00188 
00189 #define BTLMODE         0x80
00190 #define SAMPLE_1X       0x00
00191 #define SAMPLE_3X       0x40
00192 
00193 
00194 // CNF3 Register Values
00195 
00196 #define SOF_ENABLE      0x80
00197 #define SOF_DISABLE     0x00
00198 #define WAKFIL_ENABLE   0x40
00199 #define WAKFIL_DISABLE  0x00
00200 
00201 
00202 // CANINTF Register Bits
00203 
00204 #define MCP_RX0IF       0x01
00205 #define MCP_RX1IF       0x02
00206 #define MCP_TX0IF       0x04
00207 #define MCP_TX1IF       0x08
00208 #define MCP_TX2IF       0x10
00209 #define MCP_ERRIF       0x20
00210 #define MCP_WAKIF       0x40
00211 #define MCP_MERRF       0x80
00212 
00213 
00214 
00215 #endif