Jason Engelman
Dependents: Kamal_CAN ReadFromSerial446 USNA-UMBC-KF-02_v3-noise USNA-UMBC-KF-01
mcp2515_defs.h@0:d8f50b1e384f, 2010-01-30 (annotated)
- Committer:
- tecnosys
- Date:
- Sat Jan 30 08:46:04 2010 +0000
- Revision:
- 0:d8f50b1e384f
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| tecnosys | 0:d8f50b1e384f | 1 | /* from Microchip Example */ |
| tecnosys | 0:d8f50b1e384f | 2 | |
| tecnosys | 0:d8f50b1e384f | 3 | #ifndef MCP2515_DEFS_H_ |
| tecnosys | 0:d8f50b1e384f | 4 | #define MCP2515_DEFS_H_ |
| tecnosys | 0:d8f50b1e384f | 5 | |
| tecnosys | 0:d8f50b1e384f | 6 | /* |
| tecnosys | 0:d8f50b1e384f | 7 | mcp2515_defs.h |
| tecnosys | 0:d8f50b1e384f | 8 | |
| tecnosys | 0:d8f50b1e384f | 9 | This file contains constants that are specific to the MCP2515. |
| tecnosys | 0:d8f50b1e384f | 10 | |
| tecnosys | 0:d8f50b1e384f | 11 | Version Date Description |
| tecnosys | 0:d8f50b1e384f | 12 | ---------------------------------------------------------------------- |
| tecnosys | 0:d8f50b1e384f | 13 | v1.00 2003/12/11 Initial release |
| tecnosys | 0:d8f50b1e384f | 14 | Copyright 2003 Kimberly Otten Software Consulting |
| tecnosys | 0:d8f50b1e384f | 15 | |
| tecnosys | 0:d8f50b1e384f | 16 | Changes M. Thomas: |
| tecnosys | 0:d8f50b1e384f | 17 | - rename to mcp2515_defs.h |
| tecnosys | 0:d8f50b1e384f | 18 | - added handy definitions from kvaser-sample |
| tecnosys | 0:d8f50b1e384f | 19 | - status-bits |
| tecnosys | 0:d8f50b1e384f | 20 | |
| tecnosys | 0:d8f50b1e384f | 21 | */ |
| tecnosys | 0:d8f50b1e384f | 22 | |
| tecnosys | 0:d8f50b1e384f | 23 | // Begin mt |
| tecnosys | 0:d8f50b1e384f | 24 | #define MCP_SIDH 0 |
| tecnosys | 0:d8f50b1e384f | 25 | #define MCP_SIDL 1 |
| tecnosys | 0:d8f50b1e384f | 26 | #define MCP_EID8 2 |
| tecnosys | 0:d8f50b1e384f | 27 | #define MCP_EID0 3 |
| tecnosys | 0:d8f50b1e384f | 28 | |
| tecnosys | 0:d8f50b1e384f | 29 | #define MCP_TXB_EXIDE_M 0x08 /* In TXBnSIDL */ |
| tecnosys | 0:d8f50b1e384f | 30 | #define MCP_DLC_MASK 0x0F /* 4 LSBits */ |
| tecnosys | 0:d8f50b1e384f | 31 | #define MCP_RTR_MASK 0x40 /* (1<<6) Bit 6 */ |
| tecnosys | 0:d8f50b1e384f | 32 | |
| tecnosys | 0:d8f50b1e384f | 33 | #define MCP_RXB_RX_ANY 0x60 |
| tecnosys | 0:d8f50b1e384f | 34 | #define MCP_RXB_RX_EXT 0x40 |
| tecnosys | 0:d8f50b1e384f | 35 | #define MCP_RXB_RX_STD 0x20 |
| tecnosys | 0:d8f50b1e384f | 36 | #define MCP_RXB_RX_STDEXT 0x00 |
| tecnosys | 0:d8f50b1e384f | 37 | #define MCP_RXB_RX_MASK 0x60 |
| tecnosys | 0:d8f50b1e384f | 38 | #define MCP_RXB_BUKT_MASK (1<<2) |
| tecnosys | 0:d8f50b1e384f | 39 | |
| tecnosys | 0:d8f50b1e384f | 40 | /* |
| tecnosys | 0:d8f50b1e384f | 41 | ** Bits in the TXBnCTRL registers. |
| tecnosys | 0:d8f50b1e384f | 42 | */ |
| tecnosys | 0:d8f50b1e384f | 43 | #define MCP_TXB_TXBUFE_M 0x80 |
| tecnosys | 0:d8f50b1e384f | 44 | #define MCP_TXB_ABTF_M 0x40 |
| tecnosys | 0:d8f50b1e384f | 45 | #define MCP_TXB_MLOA_M 0x20 |
| tecnosys | 0:d8f50b1e384f | 46 | #define MCP_TXB_TXERR_M 0x10 |
| tecnosys | 0:d8f50b1e384f | 47 | #define MCP_TXB_TXREQ_M 0x08 |
| tecnosys | 0:d8f50b1e384f | 48 | #define MCP_TXB_TXIE_M 0x04 |
| tecnosys | 0:d8f50b1e384f | 49 | #define MCP_TXB_TXP10_M 0x03 |
| tecnosys | 0:d8f50b1e384f | 50 | |
| tecnosys | 0:d8f50b1e384f | 51 | #define MCP_TXB_RTR_M 0x40 // In TXBnDLC |
| tecnosys | 0:d8f50b1e384f | 52 | #define MCP_RXB_IDE_M 0x08 // In RXBnSIDL |
| tecnosys | 0:d8f50b1e384f | 53 | #define MCP_RXB_RTR_M 0x40 // In RXBnDLC |
| tecnosys | 0:d8f50b1e384f | 54 | |
| tecnosys | 0:d8f50b1e384f | 55 | #define MCP_STAT_RXIF_MASK (0x03) |
| tecnosys | 0:d8f50b1e384f | 56 | #define MCP_STAT_RX0IF (1<<0) |
| tecnosys | 0:d8f50b1e384f | 57 | #define MCP_STAT_RX1IF (1<<1) |
| tecnosys | 0:d8f50b1e384f | 58 | |
| tecnosys | 0:d8f50b1e384f | 59 | #define MCP_EFLG_RX1OVR (1<<7) |
| tecnosys | 0:d8f50b1e384f | 60 | #define MCP_EFLG_RX0OVR (1<<6) |
| tecnosys | 0:d8f50b1e384f | 61 | #define MCP_EFLG_TXBO (1<<5) |
| tecnosys | 0:d8f50b1e384f | 62 | #define MCP_EFLG_TXEP (1<<4) |
| tecnosys | 0:d8f50b1e384f | 63 | #define MCP_EFLG_RXEP (1<<3) |
| tecnosys | 0:d8f50b1e384f | 64 | #define MCP_EFLG_TXWAR (1<<2) |
| tecnosys | 0:d8f50b1e384f | 65 | #define MCP_EFLG_RXWAR (1<<1) |
| tecnosys | 0:d8f50b1e384f | 66 | #define MCP_EFLG_EWARN (1<<0) |
| tecnosys | 0:d8f50b1e384f | 67 | #define MCP_EFLG_ERRORMASK (0xF8) /* 5 MS-Bits */ |
| tecnosys | 0:d8f50b1e384f | 68 | |
| tecnosys | 0:d8f50b1e384f | 69 | // End mt |
| tecnosys | 0:d8f50b1e384f | 70 | |
| tecnosys | 0:d8f50b1e384f | 71 | |
| tecnosys | 0:d8f50b1e384f | 72 | // Define MCP2515 register addresses |
| tecnosys | 0:d8f50b1e384f | 73 | |
| tecnosys | 0:d8f50b1e384f | 74 | #define MCP_RXF0SIDH 0x00 |
| tecnosys | 0:d8f50b1e384f | 75 | #define MCP_RXF0SIDL 0x01 |
| tecnosys | 0:d8f50b1e384f | 76 | #define MCP_RXF0EID8 0x02 |
| tecnosys | 0:d8f50b1e384f | 77 | #define MCP_RXF0EID0 0x03 |
| tecnosys | 0:d8f50b1e384f | 78 | #define MCP_RXF1SIDH 0x04 |
| tecnosys | 0:d8f50b1e384f | 79 | #define MCP_RXF1SIDL 0x05 |
| tecnosys | 0:d8f50b1e384f | 80 | #define MCP_RXF1EID8 0x06 |
| tecnosys | 0:d8f50b1e384f | 81 | #define MCP_RXF1EID0 0x07 |
| tecnosys | 0:d8f50b1e384f | 82 | #define MCP_RXF2SIDH 0x08 |
| tecnosys | 0:d8f50b1e384f | 83 | #define MCP_RXF2SIDL 0x09 |
| tecnosys | 0:d8f50b1e384f | 84 | #define MCP_RXF2EID8 0x0A |
| tecnosys | 0:d8f50b1e384f | 85 | #define MCP_RXF2EID0 0x0B |
| tecnosys | 0:d8f50b1e384f | 86 | #define MCP_CANSTAT 0x0E |
| tecnosys | 0:d8f50b1e384f | 87 | #define MCP_CANCTRL 0x0F |
| tecnosys | 0:d8f50b1e384f | 88 | #define MCP_RXF3SIDH 0x10 |
| tecnosys | 0:d8f50b1e384f | 89 | #define MCP_RXF3SIDL 0x11 |
| tecnosys | 0:d8f50b1e384f | 90 | #define MCP_RXF3EID8 0x12 |
| tecnosys | 0:d8f50b1e384f | 91 | #define MCP_RXF3EID0 0x13 |
| tecnosys | 0:d8f50b1e384f | 92 | #define MCP_RXF4SIDH 0x14 |
| tecnosys | 0:d8f50b1e384f | 93 | #define MCP_RXF4SIDL 0x15 |
| tecnosys | 0:d8f50b1e384f | 94 | #define MCP_RXF4EID8 0x16 |
| tecnosys | 0:d8f50b1e384f | 95 | #define MCP_RXF4EID0 0x17 |
| tecnosys | 0:d8f50b1e384f | 96 | #define MCP_RXF5SIDH 0x18 |
| tecnosys | 0:d8f50b1e384f | 97 | #define MCP_RXF5SIDL 0x19 |
| tecnosys | 0:d8f50b1e384f | 98 | #define MCP_RXF5EID8 0x1A |
| tecnosys | 0:d8f50b1e384f | 99 | #define MCP_RXF5EID0 0x1B |
| tecnosys | 0:d8f50b1e384f | 100 | #define MCP_TEC 0x1C |
| tecnosys | 0:d8f50b1e384f | 101 | #define MCP_REC 0x1D |
| tecnosys | 0:d8f50b1e384f | 102 | #define MCP_RXM0SIDH 0x20 |
| tecnosys | 0:d8f50b1e384f | 103 | #define MCP_RXM0SIDL 0x21 |
| tecnosys | 0:d8f50b1e384f | 104 | #define MCP_RXM0EID8 0x22 |
| tecnosys | 0:d8f50b1e384f | 105 | #define MCP_RXM0EID0 0x23 |
| tecnosys | 0:d8f50b1e384f | 106 | #define MCP_RXM1SIDH 0x24 |
| tecnosys | 0:d8f50b1e384f | 107 | #define MCP_RXM1SIDL 0x25 |
| tecnosys | 0:d8f50b1e384f | 108 | #define MCP_RXM1EID8 0x26 |
| tecnosys | 0:d8f50b1e384f | 109 | #define MCP_RXM1EID0 0x27 |
| tecnosys | 0:d8f50b1e384f | 110 | #define MCP_CNF3 0x28 |
| tecnosys | 0:d8f50b1e384f | 111 | #define MCP_CNF2 0x29 |
| tecnosys | 0:d8f50b1e384f | 112 | #define MCP_CNF1 0x2A |
| tecnosys | 0:d8f50b1e384f | 113 | #define MCP_CANINTE 0x2B |
| tecnosys | 0:d8f50b1e384f | 114 | #define MCP_CANINTF 0x2C |
| tecnosys | 0:d8f50b1e384f | 115 | #define MCP_EFLG 0x2D |
| tecnosys | 0:d8f50b1e384f | 116 | #define MCP_TXB0CTRL 0x30 |
| tecnosys | 0:d8f50b1e384f | 117 | #define MCP_TXB1CTRL 0x40 |
| tecnosys | 0:d8f50b1e384f | 118 | #define MCP_TXB2CTRL 0x50 |
| tecnosys | 0:d8f50b1e384f | 119 | #define MCP_RXB0CTRL 0x60 |
| tecnosys | 0:d8f50b1e384f | 120 | #define MCP_RXB0SIDH 0x61 |
| tecnosys | 0:d8f50b1e384f | 121 | #define MCP_RXB1CTRL 0x70 |
| tecnosys | 0:d8f50b1e384f | 122 | #define MCP_RXB1SIDH 0x71 |
| tecnosys | 0:d8f50b1e384f | 123 | |
| tecnosys | 0:d8f50b1e384f | 124 | |
| tecnosys | 0:d8f50b1e384f | 125 | #define MCP_TX_INT 0x1C // Enable all transmit interrupts |
| tecnosys | 0:d8f50b1e384f | 126 | #define MCP_TX01_INT 0x0C // Enable TXB0 and TXB1 interrupts |
| tecnosys | 0:d8f50b1e384f | 127 | #define MCP_RX_INT 0x03 // Enable receive interrupts |
| tecnosys | 0:d8f50b1e384f | 128 | #define MCP_NO_INT 0x00 // Disable all interrupts |
| tecnosys | 0:d8f50b1e384f | 129 | |
| tecnosys | 0:d8f50b1e384f | 130 | #define MCP_TX01_MASK 0x14 |
| tecnosys | 0:d8f50b1e384f | 131 | #define MCP_TX_MASK 0x54 |
| tecnosys | 0:d8f50b1e384f | 132 | |
| tecnosys | 0:d8f50b1e384f | 133 | // Define SPI Instruction Set |
| tecnosys | 0:d8f50b1e384f | 134 | |
| tecnosys | 0:d8f50b1e384f | 135 | #define MCP_WRITE 0x02 |
| tecnosys | 0:d8f50b1e384f | 136 | |
| tecnosys | 0:d8f50b1e384f | 137 | #define MCP_READ 0x03 |
| tecnosys | 0:d8f50b1e384f | 138 | |
| tecnosys | 0:d8f50b1e384f | 139 | #define MCP_BITMOD 0x05 |
| tecnosys | 0:d8f50b1e384f | 140 | |
| tecnosys | 0:d8f50b1e384f | 141 | #define MCP_LOAD_TX0 0x40 |
| tecnosys | 0:d8f50b1e384f | 142 | #define MCP_LOAD_TX1 0x42 |
| tecnosys | 0:d8f50b1e384f | 143 | #define MCP_LOAD_TX2 0x44 |
| tecnosys | 0:d8f50b1e384f | 144 | |
| tecnosys | 0:d8f50b1e384f | 145 | #define MCP_RTS_TX0 0x81 |
| tecnosys | 0:d8f50b1e384f | 146 | #define MCP_RTS_TX1 0x82 |
| tecnosys | 0:d8f50b1e384f | 147 | #define MCP_RTS_TX2 0x84 |
| tecnosys | 0:d8f50b1e384f | 148 | #define MCP_RTS_ALL 0x87 |
| tecnosys | 0:d8f50b1e384f | 149 | |
| tecnosys | 0:d8f50b1e384f | 150 | #define MCP_READ_RX0 0x90 |
| tecnosys | 0:d8f50b1e384f | 151 | #define MCP_READ_RX1 0x94 |
| tecnosys | 0:d8f50b1e384f | 152 | |
| tecnosys | 0:d8f50b1e384f | 153 | #define MCP_READ_STATUS 0xA0 |
| tecnosys | 0:d8f50b1e384f | 154 | |
| tecnosys | 0:d8f50b1e384f | 155 | #define MCP_RX_STATUS 0xB0 |
| tecnosys | 0:d8f50b1e384f | 156 | |
| tecnosys | 0:d8f50b1e384f | 157 | #define MCP_RESET 0xC0 |
| tecnosys | 0:d8f50b1e384f | 158 | |
| tecnosys | 0:d8f50b1e384f | 159 | |
| tecnosys | 0:d8f50b1e384f | 160 | // CANCTRL Register Values |
| tecnosys | 0:d8f50b1e384f | 161 | |
| tecnosys | 0:d8f50b1e384f | 162 | #define MODE_NORMAL 0x00 |
| tecnosys | 0:d8f50b1e384f | 163 | #define MODE_SLEEP 0x20 |
| tecnosys | 0:d8f50b1e384f | 164 | #define MODE_LOOPBACK 0x40 |
| tecnosys | 0:d8f50b1e384f | 165 | #define MODE_LISTENONLY 0x60 |
| tecnosys | 0:d8f50b1e384f | 166 | #define MODE_CONFIG 0x80 |
| tecnosys | 0:d8f50b1e384f | 167 | #define MODE_POWERUP 0xE0 |
| tecnosys | 0:d8f50b1e384f | 168 | #define MODE_MASK 0xE0 |
| tecnosys | 0:d8f50b1e384f | 169 | #define ABORT_TX 0x10 |
| tecnosys | 0:d8f50b1e384f | 170 | #define MODE_ONESHOT 0x08 |
| tecnosys | 0:d8f50b1e384f | 171 | #define CLKOUT_ENABLE 0x04 |
| tecnosys | 0:d8f50b1e384f | 172 | #define CLKOUT_DISABLE 0x00 |
| tecnosys | 0:d8f50b1e384f | 173 | #define CLKOUT_PS1 0x00 |
| tecnosys | 0:d8f50b1e384f | 174 | #define CLKOUT_PS2 0x01 |
| tecnosys | 0:d8f50b1e384f | 175 | #define CLKOUT_PS4 0x02 |
| tecnosys | 0:d8f50b1e384f | 176 | #define CLKOUT_PS8 0x03 |
| tecnosys | 0:d8f50b1e384f | 177 | |
| tecnosys | 0:d8f50b1e384f | 178 | |
| tecnosys | 0:d8f50b1e384f | 179 | // CNF1 Register Values |
| tecnosys | 0:d8f50b1e384f | 180 | |
| tecnosys | 0:d8f50b1e384f | 181 | #define SJW1 0x00 |
| tecnosys | 0:d8f50b1e384f | 182 | #define SJW2 0x40 |
| tecnosys | 0:d8f50b1e384f | 183 | #define SJW3 0x80 |
| tecnosys | 0:d8f50b1e384f | 184 | #define SJW4 0xC0 |
| tecnosys | 0:d8f50b1e384f | 185 | |
| tecnosys | 0:d8f50b1e384f | 186 | |
| tecnosys | 0:d8f50b1e384f | 187 | // CNF2 Register Values |
| tecnosys | 0:d8f50b1e384f | 188 | |
| tecnosys | 0:d8f50b1e384f | 189 | #define BTLMODE 0x80 |
| tecnosys | 0:d8f50b1e384f | 190 | #define SAMPLE_1X 0x00 |
| tecnosys | 0:d8f50b1e384f | 191 | #define SAMPLE_3X 0x40 |
| tecnosys | 0:d8f50b1e384f | 192 | |
| tecnosys | 0:d8f50b1e384f | 193 | |
| tecnosys | 0:d8f50b1e384f | 194 | // CNF3 Register Values |
| tecnosys | 0:d8f50b1e384f | 195 | |
| tecnosys | 0:d8f50b1e384f | 196 | #define SOF_ENABLE 0x80 |
| tecnosys | 0:d8f50b1e384f | 197 | #define SOF_DISABLE 0x00 |
| tecnosys | 0:d8f50b1e384f | 198 | #define WAKFIL_ENABLE 0x40 |
| tecnosys | 0:d8f50b1e384f | 199 | #define WAKFIL_DISABLE 0x00 |
| tecnosys | 0:d8f50b1e384f | 200 | |
| tecnosys | 0:d8f50b1e384f | 201 | |
| tecnosys | 0:d8f50b1e384f | 202 | // CANINTF Register Bits |
| tecnosys | 0:d8f50b1e384f | 203 | |
| tecnosys | 0:d8f50b1e384f | 204 | #define MCP_RX0IF 0x01 |
| tecnosys | 0:d8f50b1e384f | 205 | #define MCP_RX1IF 0x02 |
| tecnosys | 0:d8f50b1e384f | 206 | #define MCP_TX0IF 0x04 |
| tecnosys | 0:d8f50b1e384f | 207 | #define MCP_TX1IF 0x08 |
| tecnosys | 0:d8f50b1e384f | 208 | #define MCP_TX2IF 0x10 |
| tecnosys | 0:d8f50b1e384f | 209 | #define MCP_ERRIF 0x20 |
| tecnosys | 0:d8f50b1e384f | 210 | #define MCP_WAKIF 0x40 |
| tecnosys | 0:d8f50b1e384f | 211 | #define MCP_MERRF 0x80 |
| tecnosys | 0:d8f50b1e384f | 212 | |
| tecnosys | 0:d8f50b1e384f | 213 | |
| tecnosys | 0:d8f50b1e384f | 214 | |
| tecnosys | 0:d8f50b1e384f | 215 | #endif |