Jason Engelman
Port of Keils USBCDC example, compiles ok. Gets stuck at init
usbreg.h@0:0b777ff85deb, 2010-07-05 (annotated)
- Committer:
- tecnosys
- Date:
- Mon Jul 05 10:16:57 2010 +0000
- Revision:
- 0:0b777ff85deb
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| tecnosys | 0:0b777ff85deb | 1 | /*---------------------------------------------------------------------------- |
| tecnosys | 0:0b777ff85deb | 2 | * U S B - K e r n e l |
| tecnosys | 0:0b777ff85deb | 3 | *---------------------------------------------------------------------------- |
| tecnosys | 0:0b777ff85deb | 4 | * Name: usbreg.h |
| tecnosys | 0:0b777ff85deb | 5 | * Purpose: USB Hardware Layer Definitions for NXP LPC Family MCUs |
| tecnosys | 0:0b777ff85deb | 6 | * Version: V1.20 |
| tecnosys | 0:0b777ff85deb | 7 | *---------------------------------------------------------------------------- |
| tecnosys | 0:0b777ff85deb | 8 | * This software is supplied "AS IS" without any warranties, express, |
| tecnosys | 0:0b777ff85deb | 9 | * implied or statutory, including but not limited to the implied |
| tecnosys | 0:0b777ff85deb | 10 | * warranties of fitness for purpose, satisfactory quality and |
| tecnosys | 0:0b777ff85deb | 11 | * noninfringement. Keil extends you a royalty-free right to reproduce |
| tecnosys | 0:0b777ff85deb | 12 | * and distribute executable files created using this software for use |
| tecnosys | 0:0b777ff85deb | 13 | * on NXP Semiconductors LPC family microcontroller devices only. Nothing |
| tecnosys | 0:0b777ff85deb | 14 | * else gives you the right to use this software. |
| tecnosys | 0:0b777ff85deb | 15 | * |
| tecnosys | 0:0b777ff85deb | 16 | * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. |
| tecnosys | 0:0b777ff85deb | 17 | *---------------------------------------------------------------------------*/ |
| tecnosys | 0:0b777ff85deb | 18 | |
| tecnosys | 0:0b777ff85deb | 19 | #ifndef __USBREG_H |
| tecnosys | 0:0b777ff85deb | 20 | #define __USBREG_H |
| tecnosys | 0:0b777ff85deb | 21 | |
| tecnosys | 0:0b777ff85deb | 22 | /* Device Interrupt Bit Definitions */ |
| tecnosys | 0:0b777ff85deb | 23 | #define FRAME_INT 0x00000001 |
| tecnosys | 0:0b777ff85deb | 24 | #define EP_FAST_INT 0x00000002 |
| tecnosys | 0:0b777ff85deb | 25 | #define EP_SLOW_INT 0x00000004 |
| tecnosys | 0:0b777ff85deb | 26 | #define DEV_STAT_INT 0x00000008 |
| tecnosys | 0:0b777ff85deb | 27 | #define CCEMTY_INT 0x00000010 |
| tecnosys | 0:0b777ff85deb | 28 | #define CDFULL_INT 0x00000020 |
| tecnosys | 0:0b777ff85deb | 29 | #define RxENDPKT_INT 0x00000040 |
| tecnosys | 0:0b777ff85deb | 30 | #define TxENDPKT_INT 0x00000080 |
| tecnosys | 0:0b777ff85deb | 31 | #define EP_RLZED_INT 0x00000100 |
| tecnosys | 0:0b777ff85deb | 32 | #define ERR_INT 0x00000200 |
| tecnosys | 0:0b777ff85deb | 33 | |
| tecnosys | 0:0b777ff85deb | 34 | /* Rx & Tx Packet Length Definitions */ |
| tecnosys | 0:0b777ff85deb | 35 | #define PKT_LNGTH_MASK 0x000003FF |
| tecnosys | 0:0b777ff85deb | 36 | #define PKT_DV 0x00000400 |
| tecnosys | 0:0b777ff85deb | 37 | #define PKT_RDY 0x00000800 |
| tecnosys | 0:0b777ff85deb | 38 | |
| tecnosys | 0:0b777ff85deb | 39 | /* USB Control Definitions */ |
| tecnosys | 0:0b777ff85deb | 40 | #define CTRL_RD_EN 0x00000001 |
| tecnosys | 0:0b777ff85deb | 41 | #define CTRL_WR_EN 0x00000002 |
| tecnosys | 0:0b777ff85deb | 42 | |
| tecnosys | 0:0b777ff85deb | 43 | /* Command Codes */ |
| tecnosys | 0:0b777ff85deb | 44 | #define CMD_SET_ADDR 0x00D00500 |
| tecnosys | 0:0b777ff85deb | 45 | #define CMD_CFG_DEV 0x00D80500 |
| tecnosys | 0:0b777ff85deb | 46 | #define CMD_SET_MODE 0x00F30500 |
| tecnosys | 0:0b777ff85deb | 47 | #define CMD_RD_FRAME 0x00F50500 |
| tecnosys | 0:0b777ff85deb | 48 | #define DAT_RD_FRAME 0x00F50200 |
| tecnosys | 0:0b777ff85deb | 49 | #define CMD_RD_TEST 0x00FD0500 |
| tecnosys | 0:0b777ff85deb | 50 | #define DAT_RD_TEST 0x00FD0200 |
| tecnosys | 0:0b777ff85deb | 51 | #define CMD_SET_DEV_STAT 0x00FE0500 |
| tecnosys | 0:0b777ff85deb | 52 | #define CMD_GET_DEV_STAT 0x00FE0500 |
| tecnosys | 0:0b777ff85deb | 53 | #define DAT_GET_DEV_STAT 0x00FE0200 |
| tecnosys | 0:0b777ff85deb | 54 | #define CMD_GET_ERR_CODE 0x00FF0500 |
| tecnosys | 0:0b777ff85deb | 55 | #define DAT_GET_ERR_CODE 0x00FF0200 |
| tecnosys | 0:0b777ff85deb | 56 | #define CMD_RD_ERR_STAT 0x00FB0500 |
| tecnosys | 0:0b777ff85deb | 57 | #define DAT_RD_ERR_STAT 0x00FB0200 |
| tecnosys | 0:0b777ff85deb | 58 | #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) |
| tecnosys | 0:0b777ff85deb | 59 | #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) |
| tecnosys | 0:0b777ff85deb | 60 | #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) |
| tecnosys | 0:0b777ff85deb | 61 | #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) |
| tecnosys | 0:0b777ff85deb | 62 | #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) |
| tecnosys | 0:0b777ff85deb | 63 | #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) |
| tecnosys | 0:0b777ff85deb | 64 | #define CMD_CLR_BUF 0x00F20500 |
| tecnosys | 0:0b777ff85deb | 65 | #define DAT_CLR_BUF 0x00F20200 |
| tecnosys | 0:0b777ff85deb | 66 | #define CMD_VALID_BUF 0x00FA0500 |
| tecnosys | 0:0b777ff85deb | 67 | |
| tecnosys | 0:0b777ff85deb | 68 | /* Device Address Register Definitions */ |
| tecnosys | 0:0b777ff85deb | 69 | #define DEV_ADDR_MASK 0x7F |
| tecnosys | 0:0b777ff85deb | 70 | #define DEV_EN 0x80 |
| tecnosys | 0:0b777ff85deb | 71 | |
| tecnosys | 0:0b777ff85deb | 72 | /* Device Configure Register Definitions */ |
| tecnosys | 0:0b777ff85deb | 73 | #define CONF_DVICE 0x01 |
| tecnosys | 0:0b777ff85deb | 74 | |
| tecnosys | 0:0b777ff85deb | 75 | /* Device Mode Register Definitions */ |
| tecnosys | 0:0b777ff85deb | 76 | #define AP_CLK 0x01 |
| tecnosys | 0:0b777ff85deb | 77 | #define INAK_CI 0x02 |
| tecnosys | 0:0b777ff85deb | 78 | #define INAK_CO 0x04 |
| tecnosys | 0:0b777ff85deb | 79 | #define INAK_II 0x08 |
| tecnosys | 0:0b777ff85deb | 80 | #define INAK_IO 0x10 |
| tecnosys | 0:0b777ff85deb | 81 | #define INAK_BI 0x20 |
| tecnosys | 0:0b777ff85deb | 82 | #define INAK_BO 0x40 |
| tecnosys | 0:0b777ff85deb | 83 | |
| tecnosys | 0:0b777ff85deb | 84 | /* Device Status Register Definitions */ |
| tecnosys | 0:0b777ff85deb | 85 | #define DEV_CON 0x01 |
| tecnosys | 0:0b777ff85deb | 86 | #define DEV_CON_CH 0x02 |
| tecnosys | 0:0b777ff85deb | 87 | #define DEV_SUS 0x04 |
| tecnosys | 0:0b777ff85deb | 88 | #define DEV_SUS_CH 0x08 |
| tecnosys | 0:0b777ff85deb | 89 | #define DEV_RST 0x10 |
| tecnosys | 0:0b777ff85deb | 90 | |
| tecnosys | 0:0b777ff85deb | 91 | /* Error Code Register Definitions */ |
| tecnosys | 0:0b777ff85deb | 92 | #define ERR_EC_MASK 0x0F |
| tecnosys | 0:0b777ff85deb | 93 | #define ERR_EA 0x10 |
| tecnosys | 0:0b777ff85deb | 94 | |
| tecnosys | 0:0b777ff85deb | 95 | /* Error Status Register Definitions */ |
| tecnosys | 0:0b777ff85deb | 96 | #define ERR_PID 0x01 |
| tecnosys | 0:0b777ff85deb | 97 | #define ERR_UEPKT 0x02 |
| tecnosys | 0:0b777ff85deb | 98 | #define ERR_DCRC 0x04 |
| tecnosys | 0:0b777ff85deb | 99 | #define ERR_TIMOUT 0x08 |
| tecnosys | 0:0b777ff85deb | 100 | #define ERR_EOP 0x10 |
| tecnosys | 0:0b777ff85deb | 101 | #define ERR_B_OVRN 0x20 |
| tecnosys | 0:0b777ff85deb | 102 | #define ERR_BTSTF 0x40 |
| tecnosys | 0:0b777ff85deb | 103 | #define ERR_TGL 0x80 |
| tecnosys | 0:0b777ff85deb | 104 | |
| tecnosys | 0:0b777ff85deb | 105 | /* Endpoint Select Register Definitions */ |
| tecnosys | 0:0b777ff85deb | 106 | #define EP_SEL_F 0x01 |
| tecnosys | 0:0b777ff85deb | 107 | #define EP_SEL_ST 0x02 |
| tecnosys | 0:0b777ff85deb | 108 | #define EP_SEL_STP 0x04 |
| tecnosys | 0:0b777ff85deb | 109 | #define EP_SEL_PO 0x08 |
| tecnosys | 0:0b777ff85deb | 110 | #define EP_SEL_EPN 0x10 |
| tecnosys | 0:0b777ff85deb | 111 | #define EP_SEL_B_1_FULL 0x20 |
| tecnosys | 0:0b777ff85deb | 112 | #define EP_SEL_B_2_FULL 0x40 |
| tecnosys | 0:0b777ff85deb | 113 | |
| tecnosys | 0:0b777ff85deb | 114 | /* Endpoint Status Register Definitions */ |
| tecnosys | 0:0b777ff85deb | 115 | #define EP_STAT_ST 0x01 |
| tecnosys | 0:0b777ff85deb | 116 | #define EP_STAT_DA 0x20 |
| tecnosys | 0:0b777ff85deb | 117 | #define EP_STAT_RF_MO 0x40 |
| tecnosys | 0:0b777ff85deb | 118 | #define EP_STAT_CND_ST 0x80 |
| tecnosys | 0:0b777ff85deb | 119 | |
| tecnosys | 0:0b777ff85deb | 120 | /* Clear Buffer Register Definitions */ |
| tecnosys | 0:0b777ff85deb | 121 | #define CLR_BUF_PO 0x01 |
| tecnosys | 0:0b777ff85deb | 122 | |
| tecnosys | 0:0b777ff85deb | 123 | |
| tecnosys | 0:0b777ff85deb | 124 | /* DMA Interrupt Bit Definitions */ |
| tecnosys | 0:0b777ff85deb | 125 | #define EOT_INT 0x01 |
| tecnosys | 0:0b777ff85deb | 126 | #define NDD_REQ_INT 0x02 |
| tecnosys | 0:0b777ff85deb | 127 | #define SYS_ERR_INT 0x04 |
| tecnosys | 0:0b777ff85deb | 128 | |
| tecnosys | 0:0b777ff85deb | 129 | |
| tecnosys | 0:0b777ff85deb | 130 | #endif /* __USBREG_H */ |