Library for NXP's MMA8653

Committer:
takuhachisu
Date:
Fri Aug 31 08:21:23 2018 +0000
Revision:
1:e8b14e0a4584
Parent:
0:c101a5ec5ef2
Library for NXP's MMA8653;

Who changed what in which revision?

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takuhachisu 0:c101a5ec5ef2 1 #ifndef MMA8652_H
takuhachisu 0:c101a5ec5ef2 2 #define MMA8652_H
takuhachisu 0:c101a5ec5ef2 3
takuhachisu 0:c101a5ec5ef2 4 #include "mbed.h"
takuhachisu 0:c101a5ec5ef2 5
takuhachisu 0:c101a5ec5ef2 6
takuhachisu 0:c101a5ec5ef2 7 // MMA8653 Slave Address
takuhachisu 0:c101a5ec5ef2 8 #define SLAVE_ADDR_7_BIT 0x1D
takuhachisu 0:c101a5ec5ef2 9
takuhachisu 0:c101a5ec5ef2 10 #define UINT14_MAX 16383
takuhachisu 0:c101a5ec5ef2 11
takuhachisu 0:c101a5ec5ef2 12 // MMA8653 internal register addresses
takuhachisu 0:c101a5ec5ef2 13 #define STATUS 0x00
takuhachisu 0:c101a5ec5ef2 14 #define OUT_X_MSB 0x01
takuhachisu 0:c101a5ec5ef2 15 #define OUT_X_LSB 0x02
takuhachisu 0:c101a5ec5ef2 16 #define OUT_Y_MSB 0x03
takuhachisu 0:c101a5ec5ef2 17 #define OUT_Y_LSB 0x04
takuhachisu 0:c101a5ec5ef2 18 #define OUT_Z_MSB 0x05
takuhachisu 0:c101a5ec5ef2 19 #define OUT_Z_LSB 0x06
takuhachisu 0:c101a5ec5ef2 20 #define SYSMOD 0x0B
takuhachisu 0:c101a5ec5ef2 21 #define INT_SOURCE 0x0C
takuhachisu 0:c101a5ec5ef2 22 #define WHO_AM_I 0x0D
takuhachisu 0:c101a5ec5ef2 23 #define XYZ_DATA_CFG 0x0E
takuhachisu 0:c101a5ec5ef2 24 #define PL_STATUS 0x10
takuhachisu 0:c101a5ec5ef2 25 #define PL_CFG 0x11
takuhachisu 0:c101a5ec5ef2 26 #define PL_COUNT 0x12
takuhachisu 0:c101a5ec5ef2 27 #define PL_BF_ZCOMP 0x13
takuhachisu 0:c101a5ec5ef2 28 #define PL_THS_REG 0x14
takuhachisu 0:c101a5ec5ef2 29 #define FF_MT_CFG 0x15
takuhachisu 0:c101a5ec5ef2 30 #define FF_MT_SRC 0x16
takuhachisu 0:c101a5ec5ef2 31 #define FF_MT_THS 0x17
takuhachisu 0:c101a5ec5ef2 32 #define FF_MT_COUNT 0x18
takuhachisu 0:c101a5ec5ef2 33 #define ASLP_COUNT 0x29
takuhachisu 0:c101a5ec5ef2 34 #define CTRL_REG1 0x2A
takuhachisu 0:c101a5ec5ef2 35 #define CTRL_REG2 0x2B
takuhachisu 0:c101a5ec5ef2 36 #define CTRL_REG3 0x2C
takuhachisu 0:c101a5ec5ef2 37 #define CTRL_REG4 0x2D
takuhachisu 0:c101a5ec5ef2 38 #define CTRL_REG5 0x2E
takuhachisu 0:c101a5ec5ef2 39 #define OFF_X 0x2F
takuhachisu 0:c101a5ec5ef2 40 #define OFF_Y 0x30
takuhachisu 0:c101a5ec5ef2 41 #define OFF_Z 0x31
takuhachisu 0:c101a5ec5ef2 42
takuhachisu 0:c101a5ec5ef2 43 #define MMA8652_STATUS 0x00
takuhachisu 0:c101a5ec5ef2 44 #define MMA8652_OUT_X_MSB 0x01
takuhachisu 0:c101a5ec5ef2 45 #define MMA8652_WHOAMI 0x0D
takuhachisu 0:c101a5ec5ef2 46 #define MMA8652_XYZ_DATA_CFG 0x0E
takuhachisu 0:c101a5ec5ef2 47 #define MMA8652_CTRL_REG1 0x2A
takuhachisu 0:c101a5ec5ef2 48 #define MMA8652_WHOAMI_VAL 0x4A
takuhachisu 0:c101a5ec5ef2 49
takuhachisu 0:c101a5ec5ef2 50 /** Library for the NXP MMA8653
takuhachisu 0:c101a5ec5ef2 51 *
takuhachisu 0:c101a5ec5ef2 52 */
takuhachisu 0:c101a5ec5ef2 53 class MMA8653
takuhachisu 0:c101a5ec5ef2 54 {
takuhachisu 0:c101a5ec5ef2 55 public:
takuhachisu 0:c101a5ec5ef2 56 // Output buffer data format using full scale in register 0x0E[1-0]
takuhachisu 0:c101a5ec5ef2 57 enum FS {
takuhachisu 0:c101a5ec5ef2 58 PM2G = 0,
takuhachisu 0:c101a5ec5ef2 59 PM4G,
takuhachisu 0:c101a5ec5ef2 60 PM8G
takuhachisu 0:c101a5ec5ef2 61 };
takuhachisu 1:e8b14e0a4584 62
takuhachisu 1:e8b14e0a4584 63 // Data rate selection in register 0x02A[5-3]
takuhachisu 1:e8b14e0a4584 64 enum DR {
takuhachisu 1:e8b14e0a4584 65 DR800HZ = 0,
takuhachisu 1:e8b14e0a4584 66 DR400HZ,
takuhachisu 1:e8b14e0a4584 67 DR200HZ,
takuhachisu 1:e8b14e0a4584 68 DR100HZ,
takuhachisu 1:e8b14e0a4584 69 DR50HZ,
takuhachisu 1:e8b14e0a4584 70 DR12_5HZ,
takuhachisu 1:e8b14e0a4584 71 DR6_25HZ,
takuhachisu 1:e8b14e0a4584 72 DR1_56HZ
takuhachisu 1:e8b14e0a4584 73 };
takuhachisu 1:e8b14e0a4584 74
takuhachisu 0:c101a5ec5ef2 75 // Fast-read mode in register 0x02A[1]
takuhachisu 0:c101a5ec5ef2 76 enum F_READ {
takuhachisu 0:c101a5ec5ef2 77 Normal = 0,
takuhachisu 0:c101a5ec5ef2 78 FastRead
takuhachisu 0:c101a5ec5ef2 79 };
takuhachisu 1:e8b14e0a4584 80
takuhachisu 0:c101a5ec5ef2 81 /**
takuhachisu 0:c101a5ec5ef2 82 * Create a MMA8653 object
takuhachisu 0:c101a5ec5ef2 83 *
takuhachisu 0:c101a5ec5ef2 84 * @param &i2c pointer of I2C object
takuhachisu 0:c101a5ec5ef2 85 * @param dr dynamic range setting
takuhachisu 0:c101a5ec5ef2 86 * @param fr fast read setting
takuhachisu 0:c101a5ec5ef2 87 */
takuhachisu 1:e8b14e0a4584 88 MMA8653(I2C &i2c, FS fs = PM2G, DR dr= DR800HZ, F_READ fr = Normal);
takuhachisu 1:e8b14e0a4584 89
takuhachisu 0:c101a5ec5ef2 90 /**
takuhachisu 0:c101a5ec5ef2 91 * Read 3-axis acceleration in floating point values (unit: G)
takuhachisu 0:c101a5ec5ef2 92 *
takuhachisu 0:c101a5ec5ef2 93 * @param *val array where acceleration data will be stored
takuhachisu 0:c101a5ec5ef2 94 */
takuhachisu 0:c101a5ec5ef2 95 void ReadXYZ(float *val);
takuhachisu 0:c101a5ec5ef2 96
takuhachisu 0:c101a5ec5ef2 97 /**
takuhachisu 0:c101a5ec5ef2 98 * Read 3-axis acceleration in signed 16-bit values (fast read should be off)
takuhachisu 0:c101a5ec5ef2 99 *
takuhachisu 0:c101a5ec5ef2 100 * @param *val array where acceleration data will be stored
takuhachisu 0:c101a5ec5ef2 101 */
takuhachisu 0:c101a5ec5ef2 102 void ReadXYZ_s16(short *val);
takuhachisu 1:e8b14e0a4584 103
takuhachisu 0:c101a5ec5ef2 104 /**
takuhachisu 0:c101a5ec5ef2 105 * Read 3-axis acceleration in signed 8-bit values (fast read should be on)
takuhachisu 0:c101a5ec5ef2 106 *
takuhachisu 0:c101a5ec5ef2 107 * @param *val array where acceleration data will be stored
takuhachisu 0:c101a5ec5ef2 108 */
takuhachisu 0:c101a5ec5ef2 109 void ReadXYZ_s8(signed char *val);
takuhachisu 0:c101a5ec5ef2 110
takuhachisu 0:c101a5ec5ef2 111 private:
takuhachisu 0:c101a5ec5ef2 112 void byteWrite(char reg, char *val, int len);
takuhachisu 0:c101a5ec5ef2 113 void byteRead(char reg, char *val, int len);
takuhachisu 0:c101a5ec5ef2 114 FS dynamicRange;
takuhachisu 0:c101a5ec5ef2 115 bool fastReadFlag;
takuhachisu 0:c101a5ec5ef2 116 I2C *_i2c;
takuhachisu 0:c101a5ec5ef2 117 };
takuhachisu 0:c101a5ec5ef2 118
takuhachisu 0:c101a5ec5ef2 119 #endif