ov7670sreg.h

00001 #define REG_GAIN        0x00    /* Gain lower 8 bits (rest in vref) */
00002 #define REG_BLUE        0x01    /* blue gain */
00003 #define REG_RED         0x02    /* red gain */
00004 #define REG_VREF        0x03    /* Pieces of GAIN, VSTART, VSTOP */
00005 #define REG_COM1        0x04    /* Control 1 */
00006 #define COM1_CCIR656    0x40    /* CCIR656 enable */
00007 #define REG_BAVE        0x05    /* U/B Average level */
00008 #define REG_GbAVE       0x06    /* Y/Gb Average level */
00009 #define REG_AECHH       0x07    /* AEC MS 5 bits */
00010 #define REG_RAVE        0x08    /* V/R Average level */
00011 #define REG_COM2        0x09    /* Control 2 */
00012 #define COM2_SSLEEP     0x10    /* Soft sleep mode */
00013 #define REG_PID         0x0a    /* Product ID MSB */
00014 #define REG_VER         0x0b    /* Product ID LSB */
00015 #define REG_COM3        0x0c    /* Control 3 */
00016 #define COM3_SWAP       0x40    /* Byte swap */
00017 #define COM3_SCALEEN    0x08    /* Enable scaling */
00018 #define COM3_DCWEN      0x04    /* Enable downsamp/crop/window */
00019 #define REG_COM4        0x0d    /* Control 4 */
00020 #define REG_COM5        0x0e    /* All "reserved" */
00021 #define REG_COM6        0x0f    /* Control 6 */
00022 #define REG_AECH        0x10    /* More bits of AEC value */
00023 #define REG_CLKRC       0x11    /* Clocl control */
00024 #define CLK_EXT         0x40    /* Use external clock directly */
00025 #define CLK_SCALE       0x3f    /* Mask for internal clock scale */
00026 #define REG_COM7        0x12    /* Control 7 */
00027 #define COM7_RESET      0x80    /* Register reset */
00028 #define COM7_FMT_MASK   0x38
00029 #define COM7_FMT_VGA    0x00
00030 #define COM7_FMT_CIF    0x20    /* CIF format */
00031 #define COM7_FMT_QVGA   0x10    /* QVGA format */
00032 #define COM7_FMT_QCIF   0x08    /* QCIF format */
00033 #define COM7_RGB        0x04    /* bits 0 and 2 - RGB format */
00034 #define COM7_YUV        0x00    /* YUV */
00035 #define COM7_BAYER      0x01    /* Bayer format */
00036 #define COM7_PBAYER     0x05    /* "Processed bayer" */
00037 #define REG_COM8        0x13    /* Control 8 */
00038 #define COM8_FASTAEC    0x80    /* Enable fast AGC/AEC */
00039 #define COM8_AECSTEP    0x40    /* Unlimited AEC step size */
00040 #define COM8_BFILT      0x20    /* Band filter enable */
00041 #define COM8_AGC        0x04    /* Auto gain enable */
00042 #define COM8_AWB        0x02    /* White balance enable */
00043 #define COM8_AEC        0x01    /* Auto exposure enable */
00044 #define REG_COM9        0x14    /* Control 9  - gain ceiling */
00045 #define REG_COM10       0x15    /* Control 10 */
00046 #define COM10_HSYNC     0x40    /* HSYNC instead of HREF */
00047 #define COM10_PCLK_HB   0x20    /* Suppress PCLK on horiz blank */
00048 #define COM10_HREF_REV  0x08    /* Reverse HREF */
00049 #define COM10_VS_LEAD   0x04    /* VSYNC on clock leading edge */
00050 #define COM10_VS_NEG    0x02    /* VSYNC negative */
00051 #define COM10_HS_NEG    0x01    /* HSYNC negative */
00052 #define REG_HSTART      0x17    /* Horiz start high bits */
00053 #define REG_HSTOP       0x18    /* Horiz stop high bits */
00054 #define REG_VSTART      0x19    /* Vert start high bits */
00055 #define REG_VSTOP       0x1a    /* Vert stop high bits */
00056 #define REG_PSHFT       0x1b    /* Pixel delay after HREF */
00057 #define REG_MIDH        0x1c    /* Manuf. ID high */
00058 #define REG_MIDL        0x1d    /* Manuf. ID low */
00059 #define REG_MVFP        0x1e    /* Mirror / vflip */
00060 #define MVFP_MIRROR     0x20    /* Mirror image */
00061 #define MVFP_FLIP       0x10    /* Vertical flip */
00062 #define REG_AEW         0x24    /* AGC upper limit */
00063 #define REG_AEB         0x25    /* AGC lower limit */
00064 #define REG_VPT         0x26    /* AGC/AEC fast mode op region */
00065 #define REG_HSYST       0x30    /* HSYNC rising edge delay */
00066 #define REG_HSYEN       0x31    /* HSYNC falling edge delay */
00067 #define REG_HREF        0x32    /* HREF pieces */
00068 #define REG_TSLB        0x3a    /* lots of stuff */
00069 #define TSLB_YLAST      0x04    /* UYVY or VYUY - see com13 */
00070 #define REG_COM11       0x3b    /* Control 11 */
00071 #define COM11_NIGHT     0x80    /* NIght mode enable */
00072 #define COM11_NMFR      0x60    /* Two bit NM frame rate */
00073 #define COM11_HZAUTO    0x10    /* Auto detect 50/60 Hz */
00074 #define COM11_50HZ      0x08    /* Manual 50Hz select */
00075 #define COM11_EXP       0x02
00076 #define REG_COM12       0x3c    /* Control 12 */
00077 #define COM12_HREF      0x80    /* HREF always */
00078 #define REG_COM13       0x3d    /* Control 13 */
00079 #define COM13_GAMMA     0x80    /* Gamma enable */
00080 #define COM13_UVSAT     0x40    /* UV saturation auto adjustment */
00081 #define COM13_UVSWAP    0x01    /* V before U - w/TSLB */
00082 #define REG_COM14       0x3e    /* Control 14 */
00083 #define COM14_DCWEN     0x10    /* DCW/PCLK-scale enable */
00084 #define REG_EDGE        0x3f    /* Edge enhancement factor */
00085 #define REG_COM15       0x40    /* Control 15 */
00086 #define COM15_R10F0     0x00    /* Data range 10 to F0 */
00087 #define COM15_R01FE     0x80    /*            01 to FE */
00088 #define COM15_R00FF     0xc0    /*            00 to FF */
00089 #define COM15_RGB565    0x10    /* RGB565 output */
00090 #define COM15_RGB555    0x30    /* RGB555 output */
00091 #define REG_COM16       0x41    /* Control 16 */
00092 #define COM16_AWBGAIN   0x08    /* AWB gain enable */
00093 #define REG_COM17       0x42    /* Control 17 */
00094 #define COM17_AECWIN    0xc0    /* AEC window - must match COM4 */
00095 #define COM17_CBAR      0x08    /* DSP Color bar */
00096 
00097 #define REG_BRIGHT      0x55    /* Brightness */
00098 #define REG_REG76       0x76    /* OV's name */
00099 #define R76_BLKPCOR     0x80    /* Black pixel correction enable */
00100 #define R76_WHTPCOR     0x40    /* White pixel correction enable */
00101 #define REG_RGB444      0x8c    /* RGB 444 control */
00102 #define R444_ENABLE     0x02    /* Turn on RGB444, overrides 5x5 */
00103 #define R444_RGBX       0x01    /* Empty nibble at end */
00104 #define REG_HAECC1      0x9f    /* Hist AEC/AGC control 1 */
00105 #define REG_HAECC2      0xa0    /* Hist AEC/AGC control 2 */
00106 #define REG_BD50MAX     0xa5    /* 50hz banding step limit */
00107 #define REG_HAECC3      0xa6    /* Hist AEC/AGC control 3 */
00108 #define REG_HAECC4      0xa7    /* Hist AEC/AGC control 4 */
00109 #define REG_HAECC5      0xa8    /* Hist AEC/AGC control 5 */
00110 #define REG_HAECC6      0xa9    /* Hist AEC/AGC control 6 */
00111 #define REG_HAECC7      0xaa    /* Hist AEC/AGC control 7 */
00112 #define REG_BD60MAX     0xab    /* 60hz banding step limit */
00113 
00114 #define MTX1            0x4f    /* Matrix Coefficient 1 */
00115 #define MTX2            0x50    /* Matrix Coefficient 2 */
00116 #define MTX3            0x51    /* Matrix Coefficient 3 */
00117 #define MTX4            0x52    /* Matrix Coefficient 4 */
00118 #define MTX5            0x53    /* Matrix Coefficient 5 */
00119 #define MTX6            0x54    /* Matrix Coefficient 6 */
00120 #define REG_CONTRAS     0x56    /* Contrast control */
00121 #define MTXS            0x58    /* Matrix Coefficient Sign */
00122 #define AWBC7           0x59    /* AWB Control 7 */
00123 #define AWBC8           0x5a    /* AWB Control 8 */
00124 #define AWBC9           0x5b    /* AWB Control 9 */
00125 #define AWBC10          0x5c    /* AWB Control 10 */
00126 #define AWBC11          0x5d    /* AWB Control 11 */
00127 #define AWBC12          0x5e    /* AWB Control 12 */
00128 #define REG_GFIX        0x69    /* Fix gain control */
00129 #define GGAIN           0x6a    /* G Channel AWB Gain */
00130 #define DBLV            0x6b    
00131 #define AWBCTR3         0x6c    /* AWB Control 3 */
00132 #define AWBCTR2         0x6d    /* AWB Control 2 */
00133 #define AWBCTR1         0x6e    /* AWB Control 1 */
00134 #define AWBCTR0         0x6f    /* AWB Control 0 */