steven niu / mDMA Featured

mDMA implements DMA APIs for mbed. It is inspired by modDMA and simpleDMA. Compared with other mbed DMA implementations, mDMA has new features like 1) support LLI 2) support more than 4KB data transfer 3) support vectorized transfer. 4) support burst transfer. 5) Improved memory-memory transfer. It could beat memcpy 6) The library implementation fit the code structure of mbed sdk. Currently only support LPC1768 but could be extended to other platforms.

Dependents:   test_mDMA

dma_api.h@1:9421d79fb372, 2015-03-09 (annotated)

Committer:
steniu01
Date:
Mon Mar 09 21:47:24 2015 +0000
Revision:
1:9421d79fb372
Parent:
0:8e50c5fd42f6 
improved the coding style

Who changed what in which revision?

UserRevisionLine numberNew contents of line
steniu01 0:8e50c5fd42f6 1 #ifndef MBED_DMA_API_H
steniu01 0:8e50c5fd42f6 2 #define MBED_DMA_API_H
steniu01 0:8e50c5fd42f6 3
steniu01 0:8e50c5fd42f6 4
steniu01 0:8e50c5fd42f6 5
steniu01 0:8e50c5fd42f6 6 #include "device.h"
steniu01 0:8e50c5fd42f6 7 #include "platform.h"
steniu01 0:8e50c5fd42f6 8 #include <stdbool.h>
steniu01 0:8e50c5fd42f6 9
steniu01 0:8e50c5fd42f6 10
steniu01 0:8e50c5fd42f6 11
steniu01 0:8e50c5fd42f6 12 #ifdef __cplusplus
steniu01 0:8e50c5fd42f6 13 extern "C" {
steniu01 0:8e50c5fd42f6 14 #endif
steniu01 0:8e50c5fd42f6 15
steniu01 0:8e50c5fd42f6 16 //Declare number of DMA channels available. Defined in the dma_api.c
steniu01 0:8e50c5fd42f6 17 extern int _channel_num ;
steniu01 0:8e50c5fd42f6 18
steniu01 0:8e50c5fd42f6 19
steniu01 0:8e50c5fd42f6 20 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
steniu01 0:8e50c5fd42f6 21
steniu01 0:8e50c5fd42f6 22
steniu01 0:8e50c5fd42f6 23 //DMA transfer type
steniu01 0:8e50c5fd42f6 24 typedef enum {
steniu01 0:8e50c5fd42f6 25 M2M = 0x00,
steniu01 0:8e50c5fd42f6 26 M2P = 0x01,
steniu01 0:8e50c5fd42f6 27 P2M = 0x02,
steniu01 0:8e50c5fd42f6 28 P2P = 0x03
steniu01 0:8e50c5fd42f6 29 } TransferType;
steniu01 0:8e50c5fd42f6 30
steniu01 0:8e50c5fd42f6 31
steniu01 0:8e50c5fd42f6 32
steniu01 0:8e50c5fd42f6 33 // DMA Trigger type.
steniu01 0:8e50c5fd42f6 34 // To be done: trigger type should be able to caculated automatically according to source/destination address
steniu01 0:8e50c5fd42f6 35 typedef enum {
steniu01 0:8e50c5fd42f6 36 ALWAYS ,
steniu01 0:8e50c5fd42f6 37 _SSP0_TX,
steniu01 0:8e50c5fd42f6 38 _SSP0_RX,
steniu01 0:8e50c5fd42f6 39 _SSP1_TX,
steniu01 0:8e50c5fd42f6 40 _SSP1_RX,
steniu01 0:8e50c5fd42f6 41 _ADC,
steniu01 0:8e50c5fd42f6 42 _I2S0,
steniu01 0:8e50c5fd42f6 43 _I2S1,
steniu01 0:8e50c5fd42f6 44 _DAC,
steniu01 0:8e50c5fd42f6 45 _UART0_TX,
steniu01 0:8e50c5fd42f6 46 _UART0_RX,
steniu01 0:8e50c5fd42f6 47 _UART1_TX,
steniu01 0:8e50c5fd42f6 48 _UART1_RX,
steniu01 0:8e50c5fd42f6 49 _UART2_TX,
steniu01 0:8e50c5fd42f6 50 _UART2_RX,
steniu01 0:8e50c5fd42f6 51 _UART3_TX,
steniu01 0:8e50c5fd42f6 52 _UART3_RX,
steniu01 0:8e50c5fd42f6 53 _MATCH0_0,
steniu01 0:8e50c5fd42f6 54 _MATCH0_1,
steniu01 0:8e50c5fd42f6 55 _MATCH1_0,
steniu01 0:8e50c5fd42f6 56 _MATCH1_1,
steniu01 0:8e50c5fd42f6 57 _MATCH2_0,
steniu01 0:8e50c5fd42f6 58 _MATCH2_1,
steniu01 0:8e50c5fd42f6 59 _MATCH3_0,
steniu01 0:8e50c5fd42f6 60 _MATCH3_1
steniu01 0:8e50c5fd42f6 61 } TriggerType;
steniu01 0:8e50c5fd42f6 62
steniu01 0:8e50c5fd42f6 63 //define DMA interrupt type: ERR, generated when err happens; FINISH, generated when transfer finish
steniu01 0:8e50c5fd42f6 64 typedef enum {ERR, FINISH} DMA_IT;
steniu01 0:8e50c5fd42f6 65
steniu01 0:8e50c5fd42f6 66 // declear DMA IRQ. The real IRQ number will be defined in per platform file dma_api.c
steniu01 0:8e50c5fd42f6 67 extern IRQn_Type _DMA_IRQ;
steniu01 0:8e50c5fd42f6 68
steniu01 0:8e50c5fd42f6 69
steniu01 0:8e50c5fd42f6 70 // Forward declaration
steniu01 0:8e50c5fd42f6 71 // DMA Init structures definition. It is used to describe DMA configurable features.
steniu01 0:8e50c5fd42f6 72
steniu01 0:8e50c5fd42f6 73 typedef struct DMA_InitTypeDef DMA_InitTypeDef;
steniu01 0:8e50c5fd42f6 74
steniu01 0:8e50c5fd42f6 75 typedef struct LLI
steniu01 0:8e50c5fd42f6 76 {
steniu01 0:8e50c5fd42f6 77 uint32_t LLI_src;
steniu01 0:8e50c5fd42f6 78 uint32_t LLI_dst;
steniu01 0:8e50c5fd42f6 79 uint32_t LLI_next;
steniu01 0:8e50c5fd42f6 80 uint32_t LLI_control; // Only care about transfer size, as other charactors will be same as initial transfer
steniu01 0:8e50c5fd42f6 81 }LLI;
steniu01 0:8e50c5fd42f6 82
steniu01 0:8e50c5fd42f6 83 void DMA_destination(DMA_InitTypeDef* DMA_InitStruct, const uint32_t dst, unsigned int width, bool inc);
steniu01 0:8e50c5fd42f6 84 void DMA_source(DMA_InitTypeDef* DMA_InitStruct, const uint32_t src, unsigned int width, bool inc);
steniu01 0:8e50c5fd42f6 85 void DMA_trigger_source(DMA_InitTypeDef* DMA_InitStruct, TriggerType trig);
steniu01 0:8e50c5fd42f6 86 void DMA_trigger_destination(DMA_InitTypeDef* DMA_InitStruct, TriggerType trig);
steniu01 0:8e50c5fd42f6 87
steniu01 0:8e50c5fd42f6 88 /**
steniu01 0:8e50c5fd42f6 89 * @brief Initializes the DMAy Channelx according to the specified parameters
steniu01 0:8e50c5fd42f6 90 * in the DMA_InitStruct.
steniu01 0:8e50c5fd42f6 91 * @param channel. The chosen channel number.
steniu01 0:8e50c5fd42f6 92 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
steniu01 0:8e50c5fd42f6 93 * the configuration information for the specified DMA Channel.
steniu01 0:8e50c5fd42f6 94 * @retval None
steniu01 0:8e50c5fd42f6 95 */
steniu01 0:8e50c5fd42f6 96 void DMA_init(int channel, DMA_InitTypeDef* DMA_InitStruct);
steniu01 0:8e50c5fd42f6 97
steniu01 0:8e50c5fd42f6 98 void DMA_start(int channel, DMA_InitTypeDef* DMA_InitStruct, unsigned int lengh);
steniu01 0:8e50c5fd42f6 99 //void DMA_next(DMA_InitTypeDef* DMA_InitStruct, LLI* list);
steniu01 0:8e50c5fd42f6 100 void DMA_next(DMA_InitTypeDef* DMA_InitStruct, const uint32_t src, const uint32_t dst, uint32_t size); // The input size has to smaller than 4096bytes.
steniu01 0:8e50c5fd42f6 101 /**
steniu01 0:8e50c5fd42f6 102 * @brief Check whether channel is active or not
steniu01 0:8e50c5fd42f6 103 * @param channel. The channel number.
steniu01 0:8e50c5fd42f6 104 * @retval 0 or 1
steniu01 0:8e50c5fd42f6 105 */
steniu01 0:8e50c5fd42f6 106 bool DMA_channel_active(int channel);
steniu01 0:8e50c5fd42f6 107
steniu01 0:8e50c5fd42f6 108
steniu01 0:8e50c5fd42f6 109
steniu01 0:8e50c5fd42f6 110 /**
steniu01 0:8e50c5fd42f6 111 * @brief Reset the DMA channel to default reset value
steniu01 0:8e50c5fd42f6 112 * @param channel. The chosen channel number
steniu01 0:8e50c5fd42f6 113 * @retval None
steniu01 0:8e50c5fd42f6 114 */
steniu01 0:8e50c5fd42f6 115 void DMA_reset(int channel);
steniu01 0:8e50c5fd42f6 116
steniu01 0:8e50c5fd42f6 117
steniu01 0:8e50c5fd42f6 118 /**
steniu01 0:8e50c5fd42f6 119 * @brief Allocate a struct pointer point to DMA_InitTypeDef type memory space. Fills each DMA_InitStruct member with its default value.
steniu01 0:8e50c5fd42f6 120 * @param None
steniu01 0:8e50c5fd42f6 121 * @retval a pointer point to a DMA_InitTypeDef structure.
steniu01 0:8e50c5fd42f6 122 */
steniu01 0:8e50c5fd42f6 123 DMA_InitTypeDef* DMA_struct_create(void);
steniu01 0:8e50c5fd42f6 124
steniu01 0:8e50c5fd42f6 125
steniu01 0:8e50c5fd42f6 126
steniu01 0:8e50c5fd42f6 127 /**
steniu01 0:8e50c5fd42f6 128 * @brief Delete the memory allocated for the DMA_InitTypeDef structure
steniu01 0:8e50c5fd42f6 129 * @param A pointer point to a DMA_InitTypeDef structure
steniu01 0:8e50c5fd42f6 130 * @retval None
steniu01 0:8e50c5fd42f6 131 */
steniu01 0:8e50c5fd42f6 132 void DMA_struct_delete(DMA_InitTypeDef* ptr);
steniu01 0:8e50c5fd42f6 133
steniu01 0:8e50c5fd42f6 134
steniu01 0:8e50c5fd42f6 135 typedef void (*func_ptr)();
steniu01 0:8e50c5fd42f6 136
steniu01 0:8e50c5fd42f6 137
steniu01 0:8e50c5fd42f6 138
steniu01 0:8e50c5fd42f6 139 void DMA_IRQ_handler(void);
steniu01 0:8e50c5fd42f6 140 void DMA_IRQ_attach(int channel, int status, func_ptr ptr);
steniu01 0:8e50c5fd42f6 141 void DMA_IRQ_detach(int channel);
steniu01 0:8e50c5fd42f6 142
steniu01 0:8e50c5fd42f6 143 #ifdef __cplusplus
steniu01 0:8e50c5fd42f6 144 }
steniu01 0:8e50c5fd42f6 145 #endif
steniu01 0:8e50c5fd42f6 146
steniu01 0:8e50c5fd42f6 147 #endif