steven niu / Mbed 2 deprecated LPC1768_DMA_implementation

first workable version

Dependencies:   LPC1768_DMA mbed

The test have been created to verify m2m and m2p. In the m2m test, it copy data from source address to destination address using dma. In the m2p test, it send the data from memory to UART via dma. The test is to test the HAL level API. Once the user side API created, more test will be added. I currently only test the m2m and m2p case. It is appreciated if anyone want to test other types and peripherals using the API I created.

main.cpp@2:322a046a24ab, 2014-08-21 (annotated)

Committer:
steniu01
Date:
Thu Aug 21 00:06:38 2014 +0000
Revision:
2:322a046a24ab
Parent:
0:da18b3e74c8c 
m

Who changed what in which revision?

UserRevisionLine numberNew contents of line
steniu01 0:da18b3e74c8c 1 #include "mbed.h"
steniu01 0:da18b3e74c8c 2
steniu01 0:da18b3e74c8c 3 #include "LPC1768_dma.h"
steniu01 0:da18b3e74c8c 4
steniu01 0:da18b3e74c8c 5 volatile uint32_t DMATCCount = 0;
steniu01 0:da18b3e74c8c 6 volatile uint32_t DMAErrCount = 0;
steniu01 0:da18b3e74c8c 7
steniu01 0:da18b3e74c8c 8 void DMA_IRQHandler (void);
steniu01 0:da18b3e74c8c 9 uint32_t DMA_Init( uint32_t DMAMode );
steniu01 0:da18b3e74c8c 10
steniu01 0:da18b3e74c8c 11 RawSerial pc (USBTX, USBRX);
steniu01 0:da18b3e74c8c 12
steniu01 2:322a046a24ab 13
steniu01 0:da18b3e74c8c 14 int main(void)
steniu01 0:da18b3e74c8c 15 {
steniu01 0:da18b3e74c8c 16
steniu01 0:da18b3e74c8c 17 /* test the DMA M2M, copy data from src to dest, and then print out the dest mem data */
steniu01 0:da18b3e74c8c 18 printf("start to test DMA M2M test!\r\n");
steniu01 0:da18b3e74c8c 19
steniu01 0:da18b3e74c8c 20 char src[] = "Hello world! \r\n";
steniu01 0:da18b3e74c8c 21 uint8_t size = sizeof (src);
steniu01 0:da18b3e74c8c 22 char *dst = (char *) malloc(size);
steniu01 0:da18b3e74c8c 23 memset (dst, '\0', size);
steniu01 0:da18b3e74c8c 24
steniu01 0:da18b3e74c8c 25 uint32_t DMA_SRC = (uint32_t)src;
steniu01 0:da18b3e74c8c 26 uint32_t DMA_DST = (uint32_t)dst;
steniu01 0:da18b3e74c8c 27
steniu01 0:da18b3e74c8c 28 DMA_InitTypeDef dma_init_struct;
steniu01 0:da18b3e74c8c 29 DMA_StructInit(&dma_init_struct);
steniu01 0:da18b3e74c8c 30
steniu01 0:da18b3e74c8c 31 /* Initialize structure */
steniu01 0:da18b3e74c8c 32 dma_init_struct.DMA_DestAddr = DMA_DST;
steniu01 0:da18b3e74c8c 33 dma_init_struct.DMA_SrcAddr = DMA_SRC;
steniu01 0:da18b3e74c8c 34 dma_init_struct.DMA_TransferSize = size;
steniu01 0:da18b3e74c8c 35 dma_init_struct.DMA_SrcBurst = 0x01; // 1 byte
steniu01 0:da18b3e74c8c 36 dma_init_struct.DMA_DestBurst = 0x01;
steniu01 0:da18b3e74c8c 37 dma_init_struct.DMA_SrcWidth = 0x00; // byte
steniu01 0:da18b3e74c8c 38 dma_init_struct.DMA_DestWidth = 0x00;
steniu01 0:da18b3e74c8c 39 dma_init_struct.DMA_SrcInc = 1;
steniu01 0:da18b3e74c8c 40 dma_init_struct.DMA_DestInc = 1;
steniu01 0:da18b3e74c8c 41 dma_init_struct.DMA_TermInt = 1; // enable count interrupt:w
steniu01 0:da18b3e74c8c 42 dma_init_struct.DMA_TransferType = M2M;
steniu01 0:da18b3e74c8c 43
steniu01 0:da18b3e74c8c 44 LPC_SC->PCONP |= (1 << 29); /* Enable GPDMA clock */
steniu01 0:da18b3e74c8c 45 DMA_init(LPC_GPDMACH0, &dma_init_struct); //initialize the channel
steniu01 0:da18b3e74c8c 46 LPC_GPDMA->DMACConfig = 0x01; // enable DMA and little endian
steniu01 0:da18b3e74c8c 47 while ( (LPC_GPDMA->DMACConfig & 0x01) == 0);
steniu01 0:da18b3e74c8c 48
steniu01 0:da18b3e74c8c 49 // set the IRQ routine
steniu01 0:da18b3e74c8c 50 NVIC_SetVector(DMA_IRQn, (uint32_t)DMA_IRQHandler);
steniu01 0:da18b3e74c8c 51 NVIC_EnableIRQ(DMA_IRQn);
steniu01 0:da18b3e74c8c 52
steniu01 0:da18b3e74c8c 53
steniu01 0:da18b3e74c8c 54 DMA_Cmd(LPC_GPDMACH0, ENABLE); // enable channel
steniu01 0:da18b3e74c8c 55 DMA_ITConfig (LPC_GPDMACH0, DMA_ITC, ENABLE);
steniu01 0:da18b3e74c8c 56
steniu01 0:da18b3e74c8c 57
steniu01 0:da18b3e74c8c 58 printf("src text: %s", src);
steniu01 0:da18b3e74c8c 59
steniu01 0:da18b3e74c8c 60 while (!DMATCCount); /* Wait until DMA is done */
steniu01 0:da18b3e74c8c 61
steniu01 0:da18b3e74c8c 62
steniu01 0:da18b3e74c8c 63 printf("dst text: %s", dst);
steniu01 0:da18b3e74c8c 64
steniu01 0:da18b3e74c8c 65 if (strcmp (src, dst) != 0)
steniu01 0:da18b3e74c8c 66 printf("error! \r\n");
steniu01 0:da18b3e74c8c 67 else
steniu01 0:da18b3e74c8c 68 printf("correct! \r\n");
steniu01 0:da18b3e74c8c 69
steniu01 0:da18b3e74c8c 70
steniu01 0:da18b3e74c8c 71
steniu01 0:da18b3e74c8c 72 /*test m2P, send the memory data to UART;*/
steniu01 0:da18b3e74c8c 73 char src2[] = "Hello world! This message was transmitted via UART DMA from memory \r\n";
steniu01 0:da18b3e74c8c 74 uint8_t size2 = sizeof (src2);
steniu01 0:da18b3e74c8c 75
steniu01 0:da18b3e74c8c 76 uint32_t DMA_SRC2 = (uint32_t)src2;
steniu01 0:da18b3e74c8c 77 pc.printf ("start to test M2P \r\n");
steniu01 0:da18b3e74c8c 78
steniu01 0:da18b3e74c8c 79 /* Initialize structure */
steniu01 0:da18b3e74c8c 80 LPC_UART0->FCR |= 1<<3 ; //enable UART DMA mode
steniu01 0:da18b3e74c8c 81
steniu01 0:da18b3e74c8c 82 dma_init_struct.DMA_DestAddr = (uint32_t) &(LPC_UART0->THR);
steniu01 0:da18b3e74c8c 83 dma_init_struct.DMA_SrcAddr = DMA_SRC2;
steniu01 0:da18b3e74c8c 84 dma_init_struct.DMA_TransferSize = size2;
steniu01 0:da18b3e74c8c 85 dma_init_struct.DMA_SrcBurst = 0x00; // 1 byte
steniu01 0:da18b3e74c8c 86 dma_init_struct.DMA_DestBurst = 0x00;
steniu01 0:da18b3e74c8c 87 dma_init_struct.DMA_SrcWidth = 0x00; // byte
steniu01 0:da18b3e74c8c 88 dma_init_struct.DMA_DestWidth = 0x00;
steniu01 0:da18b3e74c8c 89 dma_init_struct.DMA_SrcInc = 1;
steniu01 0:da18b3e74c8c 90 dma_init_struct.DMA_DestInc = 0;
steniu01 0:da18b3e74c8c 91 dma_init_struct.DMA_TermInt = 1; // enable count interrupt:w
steniu01 0:da18b3e74c8c 92 dma_init_struct.DMA_TransferType = M2P;
steniu01 0:da18b3e74c8c 93 dma_init_struct.DMA_DestPeripheral = 8;
steniu01 0:da18b3e74c8c 94
steniu01 0:da18b3e74c8c 95 LPC_SC->PCONP |= (1 << 29); // Enable GPDMA clock
steniu01 0:da18b3e74c8c 96
steniu01 0:da18b3e74c8c 97 DMA_init(LPC_GPDMACH1, &dma_init_struct); //initialize the channel
steniu01 0:da18b3e74c8c 98 LPC_GPDMA->DMACConfig = 0x01; // enable DMA and little endian; have to initial firstly then enable
steniu01 0:da18b3e74c8c 99 while ( (LPC_GPDMA->DMACConfig & 0x01) == 0);
steniu01 0:da18b3e74c8c 100
steniu01 0:da18b3e74c8c 101
steniu01 0:da18b3e74c8c 102 NVIC_SetVector(DMA_IRQn, (uint32_t)DMA_IRQHandler);
steniu01 0:da18b3e74c8c 103 NVIC_EnableIRQ(DMA_IRQn);
steniu01 0:da18b3e74c8c 104 DMA_Cmd(LPC_GPDMACH1, ENABLE); // enable channel
steniu01 0:da18b3e74c8c 105 DMA_ITConfig (LPC_GPDMACH1, DMA_ITC, ENABLE);
steniu01 0:da18b3e74c8c 106
steniu01 0:da18b3e74c8c 107
steniu01 0:da18b3e74c8c 108 while ( DMA_EnabledChannels() && 2);
steniu01 0:da18b3e74c8c 109
steniu01 0:da18b3e74c8c 110 while (1);
steniu01 0:da18b3e74c8c 111 }
steniu01 0:da18b3e74c8c 112
steniu01 0:da18b3e74c8c 113 void DMA_IRQHandler (void)
steniu01 0:da18b3e74c8c 114 {
steniu01 0:da18b3e74c8c 115 uint32_t regVal;
steniu01 0:da18b3e74c8c 116 DMATCCount++;
steniu01 0:da18b3e74c8c 117 regVal = LPC_GPDMA->DMACIntTCStat;
steniu01 0:da18b3e74c8c 118 if ( regVal )
steniu01 0:da18b3e74c8c 119 {
steniu01 0:da18b3e74c8c 120 DMATCCount++;
steniu01 0:da18b3e74c8c 121 LPC_GPDMA->DMACIntTCClear |= regVal;
steniu01 0:da18b3e74c8c 122 }
steniu01 0:da18b3e74c8c 123 regVal = LPC_GPDMA->DMACIntErrStat;
steniu01 0:da18b3e74c8c 124 if ( regVal )
steniu01 0:da18b3e74c8c 125 {
steniu01 0:da18b3e74c8c 126 DMAErrCount++;
steniu01 0:da18b3e74c8c 127 LPC_GPDMA->DMACIntErrClr |= regVal;
steniu01 0:da18b3e74c8c 128 }
steniu01 0:da18b3e74c8c 129 return;
steniu01 0:da18b3e74c8c 130 }