LPC1768_dma.h

00001 #ifndef LPC1768_DMA_H
00002 #define LPC1768_DMA_H
00003 
00004 #include "mbed.h"
00005 /** 
00006   * @brief  DMA Init structure definition
00007   */
00008 /*DMA channel control register*/
00009 #define DMA_CCxControl_TransferSize_Pos 0
00010 #define DMA_CCxControl_SBSize_Pos 12
00011 #define DMA_CCxControl_DBSize_Pos 15
00012 #define DMA_CCxControl_SWidth_Pos 18
00013 #define DMA_CCxControl_DWidth_Pos 21
00014 #define DMA_CCxControl_SI_Pos 26
00015 #define DMA_CCxControl_DI_Pos 27
00016 #define DMA_CCxControl_I_Pos 31
00017 
00018 /*DMA Channel config register*/
00019 #define DMA_CCxConfig_E_Pos 0
00020 #define DMA_CCxConfig_SrcPeripheral_Pos 1
00021 #define DMA_CCxConfig_DestPeripheral_Pos 6
00022 #define DMA_CCxConfig_TransferType_Pos 11
00023 #define DMA_CCxConfig_IE_Pos 14
00024 #define DMA_CCxConfig_ITC_Pos 15
00025 #define DMA_CCxConfig_L_Pos 16
00026 #define DMA_CCxConfig_A_Pos 17
00027 #define DMA_CCxConfig_H_Pos 18
00028 
00029 /*DMA Interrupt*/
00030 #define DMA_IE                        ((uint32_t)0x00004000)
00031 #define DMA_ITC                       ((uint32_t)0x00008000) 
00032 
00033 typedef enum
00034 {
00035     M2M = 0x00,
00036     M2P = 0x01,
00037     P2M = 0x02,
00038     P2P = 0x03
00039 } TransferType;
00040 
00041 
00042 typedef struct
00043 {
00044     uint32_t DestAddr;
00045     uint32_t SrcAddr;
00046     uint32_t next;
00047     uint32_t control;
00048 } DMA_LLI;
00049 
00050 typedef struct
00051 {
00052     uint32_t DMA_DestAddr; /*!< Specifies the destination base address for DMAy Channelx. */
00053     uint32_t DMA_SrcAddr;     /*!< Specifies the source base address for DMAy Channelx. */
00054 //    DMA_LLI LLI; /UNDO *!< Specifies the next linked item   */
00055     uint32_t DMA_TransferSize;/*!< Specifies the source  transfer size    */
00056     uint32_t DMA_SrcBurst; /*!< Specifies the source  burst size    */
00057     uint32_t DMA_DestBurst; /*!< Specifies the destination burst size   */
00058     uint32_t DMA_SrcWidth; /*!< Specifies the source transfer width   */
00059     uint32_t DMA_DestWidth; /*!< Specifies the destination transfer width   */
00060     uint32_t DMA_SrcInc;  /*!< Specifies whether the source is incremented or not */
00061     uint32_t DMA_DestInc; /*!< Specifies whether the destination is incremented or not */
00062     uint32_t DMA_TermInt; /*!< Specifies whether the terminal count interrupt enabled or not */
00063     
00064     /*!< Specifies the features set by channel config register */
00065     uint32_t  DMA_SrcPeripheral;
00066     uint32_t  DMA_DestPeripheral;
00067     TransferType  DMA_TransferType;       
00068 } DMA_InitTypeDef;
00069 
00070 
00071 
00072 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
00073 typedef enum {COUNTER, ERR} DMA_IT;
00074 
00075 
00076 void DMA_init(LPC_GPDMACH_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
00077 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
00078 void DMA_Cmd(LPC_GPDMACH_TypeDef*  DMAy_Channelx, FunctionalState NewState);
00079 void DMA_ITConfig (LPC_GPDMACH_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
00080 void DMA_ClearITPendingBit(LPC_GPDMACH_TypeDef* DMAy_Channelx, uint32_t DMA_IT);
00081 uint32_t DMA_EnabledChannels(void);
00082 bool DMA_ChannelActive (LPC_GPDMACH_TypeDef* DMAy_Channelx);
00083 
00084 #endif