LPC1768_dma.cpp

00001 #include "LPC1768_dma.h"
00002 /**
00003   * @brief  Initializes the DMAy Channelx according to the specified parameters 
00004   *         in the DMA_InitStruct.
00005   * @param  x can be 1 to 7 for DMA1 to select the DMA Channel.
00006   * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
00007   *         the configuration information for the specified DMA Channel.
00008   * @retval None
00009   */
00010 void DMA_init(LPC_GPDMACH_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
00011 {
00012     uint32_t tmpreg = 0;
00013 
00014     
00015   /* clear the pending interrupts on the channel to be used by writing to the DMACIntTCClear and DMACIntErrClear register. */  
00016     if (DMAy_Channelx == LPC_GPDMACH0){
00017       /* Reset interrupt pending bits for DMA1 Channel1 */
00018         LPC_GPDMA->DMACIntTCClear = 1<<0;
00019         LPC_GPDMA->DMACIntErrClr = 1<<0;
00020     }
00021     else if (DMAy_Channelx == LPC_GPDMACH1){
00022      /* Reset interrupt pending bits for DMA1 Channel2 */
00023         LPC_GPDMA->DMACIntTCClear = 1<<1;
00024         LPC_GPDMA->DMACIntErrClr = 1<<1;
00025     }
00026     else if (DMAy_Channelx == LPC_GPDMACH2){
00027     /* Reset interrupt pending bits for DMA1 Channel3 */
00028         LPC_GPDMA->DMACIntTCClear = 1<<2;
00029         LPC_GPDMA->DMACIntErrClr = 1<<2;
00030     }
00031     else if (DMAy_Channelx == LPC_GPDMACH3){
00032     /* Reset interrupt pending bits for DMA1 Channel3 */
00033         LPC_GPDMA->DMACIntTCClear = 1<<3;
00034         LPC_GPDMA->DMACIntErrClr = 1<<3;
00035     }
00036     else if (DMAy_Channelx == LPC_GPDMACH4){
00037     /* Reset interrupt pending bits for DMA1 Channel4 */
00038         LPC_GPDMA->DMACIntTCClear = 1<<4;
00039         LPC_GPDMA->DMACIntErrClr = 1<<4;
00040     }
00041     else if (DMAy_Channelx == LPC_GPDMACH5){
00042     /* Reset interrupt pending bits for DMA1 Channel5 */
00043         LPC_GPDMA->DMACIntTCClear = 1<<5;
00044         LPC_GPDMA->DMACIntErrClr = 1<<5;
00045     }
00046     else if (DMAy_Channelx == LPC_GPDMACH6){
00047     /* Reset interrupt pending bits for DMA1 Channel6 */
00048         LPC_GPDMA->DMACIntTCClear = 1<<6;
00049         LPC_GPDMA->DMACIntErrClr = 1<<6;
00050     }
00051     else if (DMAy_Channelx == LPC_GPDMACH7) {
00052       /* Reset interrupt pending bits for DMA1 Channel7 */
00053         LPC_GPDMA->DMACIntTCClear = 1<<7;
00054         LPC_GPDMA->DMACIntErrClr = 1<<7;
00055     }
00056     
00057     
00058     
00059    // tmpreg = DMAy_Channelx->DMACControl;
00060     //tmpreg &= CControl_CLEAR_MASK; //undo
00061     
00062     DMAy_Channelx->DMACCSrcAddr = DMA_InitStruct->DMA_SrcAddr;
00063     DMAy_Channelx->DMACCDestAddr = DMA_InitStruct->DMA_DestAddr;
00064     //DMAy_Channelx->DMACCLLI = DMA_InitStruct->LLI->next; //undo
00065     DMAy_Channelx->DMACCControl |= (DMA_InitStruct->DMA_TransferSize<<DMA_CCxControl_TransferSize_Pos) |
00066                                   (DMA_InitStruct->DMA_SrcBurst<<DMA_CCxControl_SBSize_Pos)  |
00067                                   (DMA_InitStruct->DMA_DestBurst<<DMA_CCxControl_DBSize_Pos) |
00068                                   (DMA_InitStruct->DMA_SrcWidth<<DMA_CCxControl_SWidth_Pos)  |
00069                                   (DMA_InitStruct->DMA_DestWidth<<DMA_CCxControl_DWidth_Pos) |
00070                                   (DMA_InitStruct->DMA_SrcInc<<DMA_CCxControl_SI_Pos)    |
00071                                   (DMA_InitStruct->DMA_DestInc<<DMA_CCxControl_DI_Pos)   |
00072                                   (DMA_InitStruct->DMA_TermInt<<DMA_CCxControl_I_Pos ); 
00073     
00074     DMAy_Channelx->DMACCConfig |= (DMA_InitStruct->DMA_SrcPeripheral<<DMA_CCxConfig_SrcPeripheral_Pos)|
00075                                   (DMA_InitStruct->DMA_DestPeripheral<<DMA_CCxConfig_DestPeripheral_Pos)|
00076                                   (DMA_InitStruct->DMA_TransferType<< DMA_CCxConfig_TransferType_Pos);   
00077     
00078     //DMAy_Channelx->DMACCConfig=;
00079 
00080 }
00081 
00082 /**
00083   * @brief  Fills each DMA_InitStruct member with its default value.
00084   * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
00085   *         be initialized.
00086   * @retval None
00087   */
00088 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
00089 {
00090 /*-------------- Reset DMA init structure parameters values ------------------*/
00091   
00092     DMA_InitStruct->DMA_DestAddr=0; 
00093     DMA_InitStruct->DMA_SrcAddr=0;    
00094     //DMA_InitStruct->LLI;//undo
00095     DMA_InitStruct->DMA_TransferSize=0;
00096     DMA_InitStruct->DMA_SrcBurst=0; 
00097     DMA_InitStruct->DMA_DestBurst=0;
00098     DMA_InitStruct->DMA_SrcWidth=0;
00099     DMA_InitStruct->DMA_DestWidth=0;
00100     DMA_InitStruct->DMA_SrcInc=0; 
00101     DMA_InitStruct->DMA_DestInc=0; 
00102     DMA_InitStruct->DMA_TermInt=0; 
00103     
00104     DMA_InitStruct->DMA_SrcPeripheral=0;
00105     DMA_InitStruct->DMA_DestPeripheral=0;
00106     DMA_InitStruct->DMA_TransferType=M2M;       
00107 }
00108 
00109 
00110 
00111 
00112 /**
00113   * @brief  Enables or disables the specified DMAy Channelx.
00114   * @param  x can be 1 to 7 for DMA1 to select the DMA Channel.  
00115   * @param  NewState: new state of the DMAy Channelx. 
00116   *         This parameter can be: ENABLE or DISABLE.
00117   * @retval None
00118   */
00119 void DMA_Cmd(LPC_GPDMACH_TypeDef*  DMAy_Channelx, FunctionalState NewState)
00120 {
00121     /* Check the parameters */
00122     //assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00123     //assert_param(IS_DMA_CONTROL(cmd));
00124 
00125   if (NewState != DISABLE)
00126   {
00127     /* Enable the selected DMAy Channelx */
00128     DMAy_Channelx->DMACCConfig |= 1ul<<DMA_CCxConfig_E_Pos;
00129   }
00130   else
00131   {
00132     /* Disable the selected DMAy Channelx */
00133     DMAy_Channelx->DMACCConfig &= (uint16_t)(~1ul<<DMA_CCxConfig_E_Pos);
00134   }
00135 }
00136 
00137 
00138 
00139 /* mask and unmask selected Interrupt: err interrupt or counter interrupt*/
00140 void DMA_ITConfig (LPC_GPDMACH_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
00141 {
00142     if (NewState != DISABLE)
00143     {
00144         /*unmask the selected DMA interrupts*/
00145         if(DMA_IT == DMA_ITC )
00146         {
00147             DMAy_Channelx->DMACCConfig |= 1ul <<DMA_CCxConfig_ITC_Pos;
00148             DMAy_Channelx->DMACCControl |= 1ul <<DMA_CCxControl_I_Pos;
00149         } 
00150         else if (DMA_IT == DMA_IE )
00151         {
00152             DMAy_Channelx->DMACCConfig |= 1ul<< DMA_CCxConfig_IE_Pos;
00153         }
00154         
00155     }
00156     else 
00157     {
00158          /*mask the selected DMA interrupts*/
00159           if(DMA_IT == DMA_ITC )
00160         {
00161             DMAy_Channelx->DMACCConfig &= ~(1ul <<DMA_CCxConfig_ITC_Pos);
00162             DMAy_Channelx->DMACCControl &= ~(1ul <<DMA_CCxControl_I_Pos);
00163         } 
00164         else if (DMA_IT == DMA_IE)
00165         {
00166             DMAy_Channelx->DMACCConfig &= ~(1ul <<DMA_CCxConfig_IE_Pos);
00167         }  
00168     }    
00169 }
00170 
00171 void DMA_ClearITPendingBit(LPC_GPDMACH_TypeDef* DMAy_Channelx, uint32_t DMA_IT)
00172 {
00173    
00174   /* clear the pending interrupts on the channel to be used by writing to the DMACIntTCClear and DMACIntErrClear register. */  
00175     if (DMAy_Channelx == LPC_GPDMACH0){
00176       /* Reset interrupt pending bits for DMA1 Channel1 */
00177         LPC_GPDMA->DMACIntTCClear = 1<<0;
00178         LPC_GPDMA->DMACIntErrClr = 1<<0;
00179     }
00180     else if (DMAy_Channelx == LPC_GPDMACH1){
00181      /* Reset interrupt pending bits for DMA1 Channel2 */
00182         LPC_GPDMA->DMACIntTCClear = 1<<1;
00183         LPC_GPDMA->DMACIntErrClr = 1<<1;
00184     }
00185     else if (DMAy_Channelx == LPC_GPDMACH2){
00186     /* Reset interrupt pending bits for DMA1 Channel3 */
00187         LPC_GPDMA->DMACIntTCClear = 1<<2;
00188         LPC_GPDMA->DMACIntErrClr = 1<<2;
00189     }
00190     else if (DMAy_Channelx== LPC_GPDMACH3){
00191     /* Reset interrupt pending bits for DMA1 Channel3 */
00192         LPC_GPDMA->DMACIntTCClear = 1<<3;
00193         LPC_GPDMA->DMACIntErrClr = 1<<3;
00194     }
00195     else if (DMAy_Channelx == LPC_GPDMACH4){
00196     /* Reset interrupt pending bits for DMA1 Channel4 */
00197         LPC_GPDMA->DMACIntTCClear = 1<<4;
00198         LPC_GPDMA->DMACIntErrClr = 1<<4;
00199     }
00200     else if (DMAy_Channelx == LPC_GPDMACH5){
00201     /* Reset interrupt pending bits for DMA1 Channel5 */
00202         LPC_GPDMA->DMACIntTCClear = 1<<5;
00203         LPC_GPDMA->DMACIntErrClr = 1<<5;
00204     }
00205     else if (DMAy_Channelx == LPC_GPDMACH6){
00206     /* Reset interrupt pending bits for DMA1 Channel6 */
00207         LPC_GPDMA->DMACIntTCClear = 1<<6;
00208         LPC_GPDMA->DMACIntErrClr = 1<<6;
00209     }
00210     else if (DMAy_Channelx == LPC_GPDMACH7) {
00211       /* Reset interrupt pending bits for DMA1 Channel7 */
00212         LPC_GPDMA->DMACIntTCClear = 1<<7;
00213         LPC_GPDMA->DMACIntErrClr = 1<<7;
00214     }
00215     
00216 }
00217 
00218 /*check which channels are free*/
00219 uint32_t DMA_EnabledChannels(void){
00220     
00221     return (LPC_GPDMA->DMACEnbldChns & 0xff);
00222     
00223 }
00224 
00225 bool DMA_ChannelActive (LPC_GPDMACH_TypeDef* DMAy_Channelx){
00226     if( DMAy_Channelx->DMACCConfig && 1<<DMA_CCxConfig_A_Pos) 
00227       return 1;
00228     else
00229       return 0;   
00230 }