First release
Dependencies: EthernetInterface HTTPServer TextLCD mbed-rpc mbed-rtos mbed
ov7670reg.h
00001 // This code was written by Mr.Sadaei Osakabe. 00002 // Original code is located at 00003 // https://mbed.org/users/diasea/code/OV7670_with_AL422B_Color_Size_test/ 00004 00005 // size register 00006 #define REG_COM7 0x12 /* Control 7 */ 00007 #define REG_HSTART 0x17 /* Horiz start high bits */ 00008 #define REG_HSTOP 0x18 /* Horiz stop high bits */ 00009 #define REG_HREF 0x32 /* HREF pieces */ 00010 #define REG_VSTART 0x19 /* Vert start high bits */ 00011 #define REG_VSTOP 0x1a /* Vert stop high bits */ 00012 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 00013 #define REG_COM3 0x0c /* Control 3 */ 00014 #define REG_COM14 0x3e /* Control 14 */ 00015 #define REG_SCALING_XSC 0x70 00016 #define REG_SCALING_YSC 0x71 00017 #define REG_SCALING_DCWCTR 0x72 00018 #define REG_SCALING_PCLK_DIV 0x73 00019 #define REG_SCALING_PCLK_DELAY 0xa2 00020 00021 // VGA setting 00022 #define COM7_VGA 0x00 00023 #define HSTART_VGA 0x13 00024 #define HSTOP_VGA 0x01 00025 #define HREF_VGA 0x36 //0xb6 0x36 00026 #define VSTART_VGA 0x02 00027 #define VSTOP_VGA 0x7a 00028 #define VREF_VGA 0x0a 00029 #define COM3_VGA 0x00 00030 #define COM14_VGA 0x00 00031 #define SCALING_XSC_VGA 0x3a 00032 #define SCALING_YSC_VGA 0x35 00033 #define SCALING_DCWCTR_VGA 0x11 00034 #define SCALING_PCLK_DIV_VGA 0xf0 00035 #define SCALING_PCLK_DELAY_VGA 0x02 00036 00037 // QVGA setting 00038 #define COM7_QVGA 0x00 00039 #define HSTART_QVGA 0x16 00040 #define HSTOP_QVGA 0x04 00041 #define HREF_QVGA 0x00 00042 #define VSTART_QVGA 0x02 00043 #define VSTOP_QVGA 0x7a 00044 #define VREF_QVGA 0x0a 00045 #define COM3_QVGA 0x04 00046 #define COM14_QVGA 0x19 00047 #define SCALING_XSC_QVGA 0x3a 00048 #define SCALING_YSC_QVGA 0x35 00049 #define SCALING_DCWCTR_QVGA 0x11 00050 #define SCALING_PCLK_DIV_QVGA 0xf1 00051 #define SCALING_PCLK_DELAY_QVGA 0x02 00052 00053 // QQVGA setting 00054 #define COM7_QQVGA 0x00 00055 #define HSTART_QQVGA 0x16 00056 #define HSTOP_QQVGA 0x04 00057 #define HREF_QQVGA 0xa4 //0x24? 0xa4? 00058 #define VSTART_QQVGA 0x02 00059 #define VSTOP_QQVGA 0x7a 00060 #define VREF_QQVGA 0x0a 00061 #define COM3_QQVGA 0x04 00062 #define COM14_QQVGA 0x1a 00063 #define SCALING_XSC_QQVGA 0x3a 00064 #define SCALING_YSC_QQVGA 0x35 00065 #define SCALING_DCWCTR_QQVGA 0x22 00066 #define SCALING_PCLK_DIV_QQVGA 0xf2 00067 #define SCALING_PCLK_DELAY_QQVGA 0x02 00068 00069 // CIF setting no tested linux src 2.6.29-rc5 ov7670_soc.c 00070 #define COM7_CIF 0x00 00071 #define HSTART_CIF 0x15 00072 #define HSTOP_CIF 0x0b 00073 #define HREF_CIF 0xb6 00074 #define VSTART_CIF 0x03 00075 #define VSTOP_CIF 0x7b 00076 #define VREF_CIF 0x02 00077 #define COM3_CIF 0x08 00078 #define COM14_CIF 0x11 00079 #define SCALING_XSC_CIF 0x3a 00080 #define SCALING_YSC_CIF 0x35 00081 #define SCALING_DCWCTR_CIF 0x11 00082 #define SCALING_PCLK_DIV_CIF 0xf1 00083 #define SCALING_PCLK_DELAY_CIF 0x02 00084 00085 // QCIF setting no tested no tested linux src 2.6.29-rc5 ov7670_soc.c 00086 #define COM7_QCIF 0x00 00087 #define HSTART_QCIF 0x39 00088 #define HSTOP_QCIF 0x03 00089 #define HREF_QCIF 0x80 00090 #define VSTART_QCIF 0x03 00091 #define VSTOP_QCIF 0x7b 00092 #define VREF_QCIF 0x02 00093 #define COM3_QCIF 0x0c 00094 #define COM14_QCIF 0x11 00095 #define SCALING_XSC_QCIF 0x3a 00096 #define SCALING_YSC_QCIF 0x35 00097 #define SCALING_DCWCTR_QCIF 0x11 00098 #define SCALING_PCLK_DIV_QCIF 0xf1 00099 #define SCALING_PCLK_DELAY_QCIF 0x52 00100 00101 // YUV 00102 #define REG_COM13 0x3d /* Control 13 */ 00103 #define REG_TSLB 0x3a /* lots of stuff */ 00104 00105 #define COM7_YUV 0x00 /* YUV */ 00106 #define COM13_UV 0x00 /* U before V - w/TSLB */ 00107 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 00108 #define TSLB_VLAST 0x00 /* YUYV - see com13 */ 00109 #define TSLB_ULAST 0x00 /* YVYU - see com13 */ 00110 #define TSLB_YLAST 0x08 /* UYVY or VYUY - see com13 */ 00111 00112 // RGB 00113 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 00114 00115 // RGB444 00116 #define REG_RGB444 0x8c /* RGB 444 control */ 00117 #define REG_COM15 0x40 /* Control 15 */ 00118 00119 #define RGB444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 00120 #define RGB444_XBGR 0x00 00121 #define RGB444_BGRX 0x01 /* Empty nibble at end */ 00122 #define COM15_RGB444 0x10 /* RGB444 output */ 00123 00124 // RGB555 00125 #define RGB444_DISABLE 0x00 /* Turn off RGB444, overrides 5x5 */ 00126 #define COM15_RGB555 0x30 /* RGB555 output */ 00127 00128 // RGB565 00129 #define COM15_RGB565 0x10 /* RGB565 output */ 00130 00131 // Bayer RGB 00132 #define COM7_BAYER 0x01 /* Bayer format */ 00133 #define COM7_PBAYER 0x05 /* "Processed bayer" */ 00134 00135 00136 // data format 00137 #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 00138 #define COM15_R01FE 0x80 /* 01 to FE */ 00139 #define COM15_R00FF 0xc0 /* 00 to FF */ 00140 00141 // Night mode, flicker, banding / 00142 #define REG_COM11 0x3b /* Control 11 */ 00143 #define COM11_NIGHT 0x80 /* NIght mode enable */ 00144 #define COM11_NIGHT_MIN_RATE_1_1 0x00 /* Normal mode same */ 00145 #define COM11_NIGHT_MIN_RATE_1_2 0x20 /* Normal mode 1/2 */ 00146 #define COM11_NIGHT_MIN_RATE_1_4 0x40 /* Normal mode 1/4 */ 00147 #define COM11_NIGHT_MIN_RATE_1_8 0x60 /* Normal mode 1/5 */ 00148 #define COM11_HZAUTO_ON 0x10 /* Auto detect 50/60 Hz on */ 00149 #define COM11_HZAUTO_OFF 0x00 /* Auto detect 50/60 Hz off */ 00150 #define COM11_60HZ 0x00 /* Manual 60Hz select */ 00151 #define COM11_50HZ 0x08 /* Manual 50Hz select */ 00152 #define COM11_EXP 0x02 00153 00154 #define REG_MTX1 0x4f 00155 #define REG_MTX2 0x50 00156 #define REG_MTX3 0x51 00157 #define REG_MTX4 0x52 00158 #define REG_MTX5 0x53 00159 #define REG_MTX6 0x54 00160 #define REG_BRIGHT 0x55 /* Brightness */ 00161 #define REG_CONTRAS 0x56 /* Contrast control */ 00162 #define REG_CONTRAS_CENTER 0x57 00163 #define REG_MTXS 0x58 00164 #define REG_MANU 0x67 00165 #define REG_MANV 0x68 00166 #define REG_GFIX 0x69 /* Fix gain control */ 00167 #define REG_GGAIN 0x6a 00168 #define REG_DBLV 0x6b 00169 00170 #define REG_COM9 0x14 // Control 9 - gain ceiling 00171 #define COM9_AGC_2X 0x00 00172 #define COM9_AGC_4X 0x10 00173 #define COM9_AGC_8X 0x20 00174 #define COM9_AGC_16X 0x30 00175 #define COM9_AGC_32X 0x40 00176 #define COM9_AGC_64X 0x50 00177 #define COM9_AGC_128X 0x60 00178 #define COM9_AGC_MASK 0x70 00179 #define COM9_FREEZE 0x01 00180 #define COM13_GAMMA 0x80 /* Gamma enable */ 00181 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 00182 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 00183 #define REG_BLUE 0x01 /* blue gain */ 00184 #define REG_RED 0x02 /* red gain */ 00185 #define REG_COM1 0x04 /* Control 1 */ 00186 #define COM1_CCIR656 0x40 /* CCIR656 enable */ 00187 #define REG_BAVE 0x05 /* U/B Average level */ 00188 #define REG_GbAVE 0x06 /* Y/Gb Average level */ 00189 #define REG_AECHH 0x07 /* AEC MS 5 bits */ 00190 #define REG_RAVE 0x08 /* V/R Average level */ 00191 #define REG_COM2 0x09 /* Control 2 */ 00192 #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 00193 #define REG_PID 0x0a /* Product ID MSB */ 00194 #define REG_VER 0x0b /* Product ID LSB */ 00195 #define COM3_SWAP 0x40 /* Byte swap */ 00196 #define COM3_SCALEEN 0x08 /* Enable scaling */ 00197 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 00198 #define REG_COM4 0x0d /* Control 4 */ 00199 #define REG_COM5 0x0e /* All "reserved" */ 00200 #define REG_COM6 0x0f /* Control 6 */ 00201 #define REG_AECH 0x10 /* More bits of AEC value */ 00202 #define REG_CLKRC 0x11 /* Clocl control */ 00203 #define CLK_EXT 0x40 /* Use external clock directly */ 00204 #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 00205 #define COM7_RESET 0x80 /* Register reset */ 00206 #define COM7_FMT_MASK 0x38 00207 #define COM7_FMT_VGA 0x00 00208 #define COM7_FMT_CIF 0x20 /* CIF format */ 00209 #define COM7_FMT_QVGA 0x10 /* QVGA format */ 00210 #define COM7_FMT_QCIF 0x08 /* QCIF format */ 00211 #define REG_COM8 0x13 /* Control 8 */ 00212 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 00213 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 00214 #define COM8_BFILT 0x20 /* Band filter enable */ 00215 #define COM8_AGC 0x04 /* Auto gain enable */ 00216 #define COM8_AWB 0x02 /* White balance enable */ 00217 #define COM8_AEC 0x01 /* Auto exposure enable */ 00218 #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 00219 #define REG_COM10 0x15 /* Control 10 */ 00220 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 00221 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 00222 #define COM10_HREF_REV 0x08 /* Reverse HREF */ 00223 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 00224 #define COM10_VS_NEG 0x02 /* VSYNC negative */ 00225 #define COM10_HS_NEG 0x01 /* HSYNC negative */ 00226 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 00227 #define REG_MIDH 0x1c /* Manuf. ID high */ 00228 #define REG_MIDL 0x1d /* Manuf. ID low */ 00229 #define REG_MVFP 0x1e /* Mirror / vflip */ 00230 #define MVFP_MIRROR 0x20 /* Mirror image */ 00231 #define MVFP_FLIP 0x10 /* Vertical flip */ 00232 #define REG_AEW 0x24 /* AGC upper limit */ 00233 #define REG_AEB 0x25 /* AGC lower limit */ 00234 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 00235 #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 00236 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 00237 #define REG_COM12 0x3c /* Control 12 */ 00238 #define COM12_HREF 0x80 /* HREF always */ 00239 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 00240 #define REG_EDGE 0x3f /* Edge enhancement factor */ 00241 #define REG_COM16 0x41 /* Control 16 */ 00242 #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 00243 #define REG_COM17 0x42 /* Control 17 */ 00244 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 00245 #define COM17_CBAR 0x08 /* DSP Color bar */ 00246 #define REG_CMATRIX_BASE 0x4f 00247 #define CMATRIX_LEN 6 00248 #define REG_REG76 0x76 /* OV's name */ 00249 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 00250 #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 00251 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 00252 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 00253 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 00254 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 00255 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 00256 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 00257 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 00258 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 00259 #define REG_BD60MAX 0xab /* 60hz banding step limit */
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