Sippakorn Saeng-aroon / Mbed 2 deprecated InventorStudio_LCP2

v1.1

Dependencies:   mbed QEI

RF/MFRC522.h@4:4b28e4aa1742, 2019-05-05 (annotated)

Committer:
sippasaeng
Date:
Sun May 05 18:17:07 2019 +0000
Revision:
4:4b28e4aa1742
v1.1 update char-->int type

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sippasaeng 4:4b28e4aa1742 1 /**
sippasaeng 4:4b28e4aa1742 2 * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
sippasaeng 4:4b28e4aa1742 3 * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
sippasaeng 4:4b28e4aa1742 4 * Created by Miguel Balboa (circuitito.com), Jan, 2012.
sippasaeng 4:4b28e4aa1742 5 * Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
sippasaeng 4:4b28e4aa1742 6 * Ported to mbed by Martin Olejar, Dec, 2013
sippasaeng 4:4b28e4aa1742 7 *
sippasaeng 4:4b28e4aa1742 8 * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
sippasaeng 4:4b28e4aa1742 9 * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
sippasaeng 4:4b28e4aa1742 10 *
sippasaeng 4:4b28e4aa1742 11 * There are three hardware components involved:
sippasaeng 4:4b28e4aa1742 12 * 1) The micro controller: An Arduino
sippasaeng 4:4b28e4aa1742 13 * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
sippasaeng 4:4b28e4aa1742 14 * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
sippasaeng 4:4b28e4aa1742 15 *
sippasaeng 4:4b28e4aa1742 16 * The microcontroller and card reader uses SPI for communication.
sippasaeng 4:4b28e4aa1742 17 * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
sippasaeng 4:4b28e4aa1742 18 *
sippasaeng 4:4b28e4aa1742 19 * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
sippasaeng 4:4b28e4aa1742 20 * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
sippasaeng 4:4b28e4aa1742 21 * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
sippasaeng 4:4b28e4aa1742 22 * Details are found in chapter 6, Type A: Initialization and anticollision.
sippasaeng 4:4b28e4aa1742 23 *
sippasaeng 4:4b28e4aa1742 24 * If only the PICC UID is wanted, the above documents has all the needed information.
sippasaeng 4:4b28e4aa1742 25 * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
sippasaeng 4:4b28e4aa1742 26 * The MIFARE Classic chips and protocol is described in the datasheets:
sippasaeng 4:4b28e4aa1742 27 * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
sippasaeng 4:4b28e4aa1742 28 * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
sippasaeng 4:4b28e4aa1742 29 * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
sippasaeng 4:4b28e4aa1742 30 * The MIFARE Ultralight chip and protocol is described in the datasheets:
sippasaeng 4:4b28e4aa1742 31 * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
sippasaeng 4:4b28e4aa1742 32 * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
sippasaeng 4:4b28e4aa1742 33 *
sippasaeng 4:4b28e4aa1742 34 * MIFARE Classic 1K (MF1S503x):
sippasaeng 4:4b28e4aa1742 35 * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
sippasaeng 4:4b28e4aa1742 36 * The blocks are numbered 0-63.
sippasaeng 4:4b28e4aa1742 37 * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
sippasaeng 4:4b28e4aa1742 38 * Bytes 0-5: Key A
sippasaeng 4:4b28e4aa1742 39 * Bytes 6-8: Access Bits
sippasaeng 4:4b28e4aa1742 40 * Bytes 9: User data
sippasaeng 4:4b28e4aa1742 41 * Bytes 10-15: Key B (or user data)
sippasaeng 4:4b28e4aa1742 42 * Block 0 is read only manufacturer data.
sippasaeng 4:4b28e4aa1742 43 * To access a block, an authentication using a key from the block's sector must be performed first.
sippasaeng 4:4b28e4aa1742 44 * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
sippasaeng 4:4b28e4aa1742 45 * All keys are set to FFFFFFFFFFFFh at chip delivery.
sippasaeng 4:4b28e4aa1742 46 * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
sippasaeng 4:4b28e4aa1742 47 * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
sippasaeng 4:4b28e4aa1742 48 * MIFARE Classic 4K (MF1S703x):
sippasaeng 4:4b28e4aa1742 49 * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
sippasaeng 4:4b28e4aa1742 50 * The blocks are numbered 0-255.
sippasaeng 4:4b28e4aa1742 51 * The last block in each sector is the Sector Trailer like above.
sippasaeng 4:4b28e4aa1742 52 * MIFARE Classic Mini (MF1 IC S20):
sippasaeng 4:4b28e4aa1742 53 * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
sippasaeng 4:4b28e4aa1742 54 * The blocks are numbered 0-19.
sippasaeng 4:4b28e4aa1742 55 * The last block in each sector is the Sector Trailer like above.
sippasaeng 4:4b28e4aa1742 56 *
sippasaeng 4:4b28e4aa1742 57 * MIFARE Ultralight (MF0ICU1):
sippasaeng 4:4b28e4aa1742 58 * Has 16 pages of 4 bytes = 64 bytes.
sippasaeng 4:4b28e4aa1742 59 * Pages 0 + 1 is used for the 7-byte UID.
sippasaeng 4:4b28e4aa1742 60 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
sippasaeng 4:4b28e4aa1742 61 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
sippasaeng 4:4b28e4aa1742 62 * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
sippasaeng 4:4b28e4aa1742 63 * MIFARE Ultralight C (MF0ICU2):
sippasaeng 4:4b28e4aa1742 64 * Has 48 pages of 4 bytes = 64 bytes.
sippasaeng 4:4b28e4aa1742 65 * Pages 0 + 1 is used for the 7-byte UID.
sippasaeng 4:4b28e4aa1742 66 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
sippasaeng 4:4b28e4aa1742 67 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
sippasaeng 4:4b28e4aa1742 68 * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
sippasaeng 4:4b28e4aa1742 69 * Page 40 Lock bytes
sippasaeng 4:4b28e4aa1742 70 * Page 41 16 bit one way counter
sippasaeng 4:4b28e4aa1742 71 * Pages 42-43 Authentication configuration
sippasaeng 4:4b28e4aa1742 72 * Pages 44-47 Authentication key
sippasaeng 4:4b28e4aa1742 73 */
sippasaeng 4:4b28e4aa1742 74 #ifndef MFRC522_h
sippasaeng 4:4b28e4aa1742 75 #define MFRC522_h
sippasaeng 4:4b28e4aa1742 76
sippasaeng 4:4b28e4aa1742 77 #include "mbed.h"
sippasaeng 4:4b28e4aa1742 78
sippasaeng 4:4b28e4aa1742 79 /**
sippasaeng 4:4b28e4aa1742 80 * MFRC522 example
sippasaeng 4:4b28e4aa1742 81 *
sippasaeng 4:4b28e4aa1742 82 * @code
sippasaeng 4:4b28e4aa1742 83 * #include "mbed.h"
sippasaeng 4:4b28e4aa1742 84 * #include "MFRC522.h"
sippasaeng 4:4b28e4aa1742 85 *
sippasaeng 4:4b28e4aa1742 86 * //KL25Z Pins for MFRC522 SPI interface
sippasaeng 4:4b28e4aa1742 87 * #define SPI_MOSI PTC6
sippasaeng 4:4b28e4aa1742 88 * #define SPI_MISO PTC7
sippasaeng 4:4b28e4aa1742 89 * #define SPI_SCLK PTC5
sippasaeng 4:4b28e4aa1742 90 * #define SPI_CS PTC4
sippasaeng 4:4b28e4aa1742 91 * // KL25Z Pin for MFRC522 reset
sippasaeng 4:4b28e4aa1742 92 * #define MF_RESET PTC3
sippasaeng 4:4b28e4aa1742 93 * // KL25Z Pins for Debug UART port
sippasaeng 4:4b28e4aa1742 94 * #define UART_RX PTA1
sippasaeng 4:4b28e4aa1742 95 * #define UART_TX PTA2
sippasaeng 4:4b28e4aa1742 96 *
sippasaeng 4:4b28e4aa1742 97 * DigitalOut LedRed (LED_RED);
sippasaeng 4:4b28e4aa1742 98 * DigitalOut LedGreen (LED_GREEN);
sippasaeng 4:4b28e4aa1742 99 *
sippasaeng 4:4b28e4aa1742 100 * Serial DebugUART(UART_TX, UART_RX);
sippasaeng 4:4b28e4aa1742 101 * MFRC522 RfChip (SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS, MF_RESET);
sippasaeng 4:4b28e4aa1742 102 *
sippasaeng 4:4b28e4aa1742 103 * int main(void) {
sippasaeng 4:4b28e4aa1742 104 * // Set debug UART speed
sippasaeng 4:4b28e4aa1742 105 * DebugUART.baud(115200);
sippasaeng 4:4b28e4aa1742 106 *
sippasaeng 4:4b28e4aa1742 107 * // Init. RC522 Chip
sippasaeng 4:4b28e4aa1742 108 * RfChip.PCD_Init();
sippasaeng 4:4b28e4aa1742 109 *
sippasaeng 4:4b28e4aa1742 110 * while (true) {
sippasaeng 4:4b28e4aa1742 111 * LedRed = 1;
sippasaeng 4:4b28e4aa1742 112 * LedGreen = 1;
sippasaeng 4:4b28e4aa1742 113 *
sippasaeng 4:4b28e4aa1742 114 * // Look for new cards
sippasaeng 4:4b28e4aa1742 115 * if ( ! RfChip.PICC_IsNewCardPresent())
sippasaeng 4:4b28e4aa1742 116 * {
sippasaeng 4:4b28e4aa1742 117 * wait_ms(500);
sippasaeng 4:4b28e4aa1742 118 * continue;
sippasaeng 4:4b28e4aa1742 119 * }
sippasaeng 4:4b28e4aa1742 120 *
sippasaeng 4:4b28e4aa1742 121 * LedRed = 0;
sippasaeng 4:4b28e4aa1742 122 *
sippasaeng 4:4b28e4aa1742 123 * // Select one of the cards
sippasaeng 4:4b28e4aa1742 124 * if ( ! RfChip.PICC_ReadCardSerial())
sippasaeng 4:4b28e4aa1742 125 * {
sippasaeng 4:4b28e4aa1742 126 * wait_ms(500);
sippasaeng 4:4b28e4aa1742 127 * continue;
sippasaeng 4:4b28e4aa1742 128 * }
sippasaeng 4:4b28e4aa1742 129 *
sippasaeng 4:4b28e4aa1742 130 * LedRed = 1;
sippasaeng 4:4b28e4aa1742 131 * LedGreen = 0;
sippasaeng 4:4b28e4aa1742 132 *
sippasaeng 4:4b28e4aa1742 133 * // Print Card UID
sippasaeng 4:4b28e4aa1742 134 * printf("Card UID: ");
sippasaeng 4:4b28e4aa1742 135 * for (uint8_t i = 0; i < RfChip.uid.size; i++)
sippasaeng 4:4b28e4aa1742 136 * {
sippasaeng 4:4b28e4aa1742 137 * printf(" %X02", RfChip.uid.uidByte[i]);
sippasaeng 4:4b28e4aa1742 138 * }
sippasaeng 4:4b28e4aa1742 139 * printf("\n\r");
sippasaeng 4:4b28e4aa1742 140 *
sippasaeng 4:4b28e4aa1742 141 * // Print Card type
sippasaeng 4:4b28e4aa1742 142 * uint8_t piccType = RfChip.PICC_GetType(RfChip.uid.sak);
sippasaeng 4:4b28e4aa1742 143 * printf("PICC Type: %s \n\r", RfChip.PICC_GetTypeName(piccType));
sippasaeng 4:4b28e4aa1742 144 * wait_ms(1000);
sippasaeng 4:4b28e4aa1742 145 * }
sippasaeng 4:4b28e4aa1742 146 * }
sippasaeng 4:4b28e4aa1742 147 * @endcode
sippasaeng 4:4b28e4aa1742 148 */
sippasaeng 4:4b28e4aa1742 149
sippasaeng 4:4b28e4aa1742 150 class MFRC522 {
sippasaeng 4:4b28e4aa1742 151 public:
sippasaeng 4:4b28e4aa1742 152
sippasaeng 4:4b28e4aa1742 153 /**
sippasaeng 4:4b28e4aa1742 154 * MFRC522 registers (described in chapter 9 of the datasheet).
sippasaeng 4:4b28e4aa1742 155 * When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
sippasaeng 4:4b28e4aa1742 156 */
sippasaeng 4:4b28e4aa1742 157 enum PCD_Register {
sippasaeng 4:4b28e4aa1742 158 // Page 0: Command and status
sippasaeng 4:4b28e4aa1742 159 // 0x00 // reserved for future use
sippasaeng 4:4b28e4aa1742 160 CommandReg = 0x01 << 1, // starts and stops command execution
sippasaeng 4:4b28e4aa1742 161 ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
sippasaeng 4:4b28e4aa1742 162 DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
sippasaeng 4:4b28e4aa1742 163 ComIrqReg = 0x04 << 1, // interrupt request bits
sippasaeng 4:4b28e4aa1742 164 DivIrqReg = 0x05 << 1, // interrupt request bits
sippasaeng 4:4b28e4aa1742 165 ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
sippasaeng 4:4b28e4aa1742 166 Status1Reg = 0x07 << 1, // communication status bits
sippasaeng 4:4b28e4aa1742 167 Status2Reg = 0x08 << 1, // receiver and transmitter status bits
sippasaeng 4:4b28e4aa1742 168 FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
sippasaeng 4:4b28e4aa1742 169 FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
sippasaeng 4:4b28e4aa1742 170 WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
sippasaeng 4:4b28e4aa1742 171 ControlReg = 0x0C << 1, // miscellaneous control registers
sippasaeng 4:4b28e4aa1742 172 BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
sippasaeng 4:4b28e4aa1742 173 CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
sippasaeng 4:4b28e4aa1742 174 // 0x0F // reserved for future use
sippasaeng 4:4b28e4aa1742 175
sippasaeng 4:4b28e4aa1742 176 // Page 1:Command
sippasaeng 4:4b28e4aa1742 177 // 0x10 // reserved for future use
sippasaeng 4:4b28e4aa1742 178 ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
sippasaeng 4:4b28e4aa1742 179 TxModeReg = 0x12 << 1, // defines transmission data rate and framing
sippasaeng 4:4b28e4aa1742 180 RxModeReg = 0x13 << 1, // defines reception data rate and framing
sippasaeng 4:4b28e4aa1742 181 TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
sippasaeng 4:4b28e4aa1742 182 TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
sippasaeng 4:4b28e4aa1742 183 TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
sippasaeng 4:4b28e4aa1742 184 RxSelReg = 0x17 << 1, // selects internal receiver settings
sippasaeng 4:4b28e4aa1742 185 RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
sippasaeng 4:4b28e4aa1742 186 DemodReg = 0x19 << 1, // defines demodulator settings
sippasaeng 4:4b28e4aa1742 187 // 0x1A // reserved for future use
sippasaeng 4:4b28e4aa1742 188 // 0x1B // reserved for future use
sippasaeng 4:4b28e4aa1742 189 MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
sippasaeng 4:4b28e4aa1742 190 MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
sippasaeng 4:4b28e4aa1742 191 // 0x1E // reserved for future use
sippasaeng 4:4b28e4aa1742 192 SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
sippasaeng 4:4b28e4aa1742 193
sippasaeng 4:4b28e4aa1742 194 // Page 2: Configuration
sippasaeng 4:4b28e4aa1742 195 // 0x20 // reserved for future use
sippasaeng 4:4b28e4aa1742 196 CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
sippasaeng 4:4b28e4aa1742 197 CRCResultRegL = 0x22 << 1,
sippasaeng 4:4b28e4aa1742 198 // 0x23 // reserved for future use
sippasaeng 4:4b28e4aa1742 199 ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
sippasaeng 4:4b28e4aa1742 200 // 0x25 // reserved for future use
sippasaeng 4:4b28e4aa1742 201 RFCfgReg = 0x26 << 1, // configures the receiver gain
sippasaeng 4:4b28e4aa1742 202 GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
sippasaeng 4:4b28e4aa1742 203 CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
sippasaeng 4:4b28e4aa1742 204 ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
sippasaeng 4:4b28e4aa1742 205 TModeReg = 0x2A << 1, // defines settings for the internal timer
sippasaeng 4:4b28e4aa1742 206 TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
sippasaeng 4:4b28e4aa1742 207 TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
sippasaeng 4:4b28e4aa1742 208 TReloadRegL = 0x2D << 1,
sippasaeng 4:4b28e4aa1742 209 TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
sippasaeng 4:4b28e4aa1742 210 TCntValueRegL = 0x2F << 1,
sippasaeng 4:4b28e4aa1742 211
sippasaeng 4:4b28e4aa1742 212 // Page 3:Test Registers
sippasaeng 4:4b28e4aa1742 213 // 0x30 // reserved for future use
sippasaeng 4:4b28e4aa1742 214 TestSel1Reg = 0x31 << 1, // general test signal configuration
sippasaeng 4:4b28e4aa1742 215 TestSel2Reg = 0x32 << 1, // general test signal configuration
sippasaeng 4:4b28e4aa1742 216 TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
sippasaeng 4:4b28e4aa1742 217 TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
sippasaeng 4:4b28e4aa1742 218 TestBusReg = 0x35 << 1, // shows the status of the internal test bus
sippasaeng 4:4b28e4aa1742 219 AutoTestReg = 0x36 << 1, // controls the digital self test
sippasaeng 4:4b28e4aa1742 220 VersionReg = 0x37 << 1, // shows the software version
sippasaeng 4:4b28e4aa1742 221 AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
sippasaeng 4:4b28e4aa1742 222 TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
sippasaeng 4:4b28e4aa1742 223 TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
sippasaeng 4:4b28e4aa1742 224 TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
sippasaeng 4:4b28e4aa1742 225 // 0x3C // reserved for production tests
sippasaeng 4:4b28e4aa1742 226 // 0x3D // reserved for production tests
sippasaeng 4:4b28e4aa1742 227 // 0x3E // reserved for production tests
sippasaeng 4:4b28e4aa1742 228 // 0x3F // reserved for production tests
sippasaeng 4:4b28e4aa1742 229 };
sippasaeng 4:4b28e4aa1742 230
sippasaeng 4:4b28e4aa1742 231 // MFRC522 commands Described in chapter 10 of the datasheet.
sippasaeng 4:4b28e4aa1742 232 enum PCD_Command {
sippasaeng 4:4b28e4aa1742 233 PCD_Idle = 0x00, // no action, cancels current command execution
sippasaeng 4:4b28e4aa1742 234 PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
sippasaeng 4:4b28e4aa1742 235 PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
sippasaeng 4:4b28e4aa1742 236 PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
sippasaeng 4:4b28e4aa1742 237 PCD_Transmit = 0x04, // transmits data from the FIFO buffer
sippasaeng 4:4b28e4aa1742 238 PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
sippasaeng 4:4b28e4aa1742 239 PCD_Receive = 0x08, // activates the receiver circuits
sippasaeng 4:4b28e4aa1742 240 PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
sippasaeng 4:4b28e4aa1742 241 PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
sippasaeng 4:4b28e4aa1742 242 PCD_SoftReset = 0x0F // resets the MFRC522
sippasaeng 4:4b28e4aa1742 243 };
sippasaeng 4:4b28e4aa1742 244
sippasaeng 4:4b28e4aa1742 245 // Commands sent to the PICC.
sippasaeng 4:4b28e4aa1742 246 enum PICC_Command {
sippasaeng 4:4b28e4aa1742 247 // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
sippasaeng 4:4b28e4aa1742 248 PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
sippasaeng 4:4b28e4aa1742 249 PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
sippasaeng 4:4b28e4aa1742 250 PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
sippasaeng 4:4b28e4aa1742 251 PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
sippasaeng 4:4b28e4aa1742 252 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
sippasaeng 4:4b28e4aa1742 253 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
sippasaeng 4:4b28e4aa1742 254 PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
sippasaeng 4:4b28e4aa1742 255
sippasaeng 4:4b28e4aa1742 256 // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
sippasaeng 4:4b28e4aa1742 257 // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
sippasaeng 4:4b28e4aa1742 258 // The read/write commands can also be used for MIFARE Ultralight.
sippasaeng 4:4b28e4aa1742 259 PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
sippasaeng 4:4b28e4aa1742 260 PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
sippasaeng 4:4b28e4aa1742 261 PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
sippasaeng 4:4b28e4aa1742 262 PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
sippasaeng 4:4b28e4aa1742 263 PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
sippasaeng 4:4b28e4aa1742 264 PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
sippasaeng 4:4b28e4aa1742 265 PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
sippasaeng 4:4b28e4aa1742 266 PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
sippasaeng 4:4b28e4aa1742 267
sippasaeng 4:4b28e4aa1742 268 // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
sippasaeng 4:4b28e4aa1742 269 // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
sippasaeng 4:4b28e4aa1742 270 PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
sippasaeng 4:4b28e4aa1742 271 };
sippasaeng 4:4b28e4aa1742 272
sippasaeng 4:4b28e4aa1742 273 // MIFARE constants that does not fit anywhere else
sippasaeng 4:4b28e4aa1742 274 enum MIFARE_Misc {
sippasaeng 4:4b28e4aa1742 275 MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
sippasaeng 4:4b28e4aa1742 276 MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
sippasaeng 4:4b28e4aa1742 277 };
sippasaeng 4:4b28e4aa1742 278
sippasaeng 4:4b28e4aa1742 279 // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
sippasaeng 4:4b28e4aa1742 280 enum PICC_Type {
sippasaeng 4:4b28e4aa1742 281 PICC_TYPE_UNKNOWN = 0,
sippasaeng 4:4b28e4aa1742 282 PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
sippasaeng 4:4b28e4aa1742 283 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
sippasaeng 4:4b28e4aa1742 284 PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
sippasaeng 4:4b28e4aa1742 285 PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
sippasaeng 4:4b28e4aa1742 286 PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
sippasaeng 4:4b28e4aa1742 287 PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
sippasaeng 4:4b28e4aa1742 288 PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
sippasaeng 4:4b28e4aa1742 289 PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
sippasaeng 4:4b28e4aa1742 290 PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
sippasaeng 4:4b28e4aa1742 291 };
sippasaeng 4:4b28e4aa1742 292
sippasaeng 4:4b28e4aa1742 293 // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
sippasaeng 4:4b28e4aa1742 294 enum StatusCode {
sippasaeng 4:4b28e4aa1742 295 STATUS_OK = 1, // Success
sippasaeng 4:4b28e4aa1742 296 STATUS_ERROR = 2, // Error in communication
sippasaeng 4:4b28e4aa1742 297 STATUS_COLLISION = 3, // Collision detected
sippasaeng 4:4b28e4aa1742 298 STATUS_TIMEOUT = 4, // Timeout in communication.
sippasaeng 4:4b28e4aa1742 299 STATUS_NO_ROOM = 5, // A buffer is not big enough.
sippasaeng 4:4b28e4aa1742 300 STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
sippasaeng 4:4b28e4aa1742 301 STATUS_INVALID = 7, // Invalid argument.
sippasaeng 4:4b28e4aa1742 302 STATUS_CRC_WRONG = 8, // The CRC_A does not match
sippasaeng 4:4b28e4aa1742 303 STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
sippasaeng 4:4b28e4aa1742 304 };
sippasaeng 4:4b28e4aa1742 305
sippasaeng 4:4b28e4aa1742 306 // A struct used for passing the UID of a PICC.
sippasaeng 4:4b28e4aa1742 307 typedef struct {
sippasaeng 4:4b28e4aa1742 308 uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
sippasaeng 4:4b28e4aa1742 309 uint8_t uidByte[10];
sippasaeng 4:4b28e4aa1742 310 uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
sippasaeng 4:4b28e4aa1742 311 } Uid;
sippasaeng 4:4b28e4aa1742 312
sippasaeng 4:4b28e4aa1742 313 // A struct used for passing a MIFARE Crypto1 key
sippasaeng 4:4b28e4aa1742 314 typedef struct {
sippasaeng 4:4b28e4aa1742 315 uint8_t keyByte[MF_KEY_SIZE];
sippasaeng 4:4b28e4aa1742 316 } MIFARE_Key;
sippasaeng 4:4b28e4aa1742 317
sippasaeng 4:4b28e4aa1742 318 // Member variables
sippasaeng 4:4b28e4aa1742 319 Uid uid; // Used by PICC_ReadCardSerial().
sippasaeng 4:4b28e4aa1742 320
sippasaeng 4:4b28e4aa1742 321 // Size of the MFRC522 FIFO
sippasaeng 4:4b28e4aa1742 322 static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
sippasaeng 4:4b28e4aa1742 323
sippasaeng 4:4b28e4aa1742 324 /**
sippasaeng 4:4b28e4aa1742 325 * MFRC522 constructor
sippasaeng 4:4b28e4aa1742 326 *
sippasaeng 4:4b28e4aa1742 327 * @param mosi SPI MOSI pin
sippasaeng 4:4b28e4aa1742 328 * @param miso SPI MISO pin
sippasaeng 4:4b28e4aa1742 329 * @param sclk SPI SCLK pin
sippasaeng 4:4b28e4aa1742 330 * @param cs SPI CS pin
sippasaeng 4:4b28e4aa1742 331 * @param reset Reset pin
sippasaeng 4:4b28e4aa1742 332 */
sippasaeng 4:4b28e4aa1742 333 MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
sippasaeng 4:4b28e4aa1742 334
sippasaeng 4:4b28e4aa1742 335 /**
sippasaeng 4:4b28e4aa1742 336 * MFRC522 destructor
sippasaeng 4:4b28e4aa1742 337 */
sippasaeng 4:4b28e4aa1742 338 ~MFRC522();
sippasaeng 4:4b28e4aa1742 339
sippasaeng 4:4b28e4aa1742 340
sippasaeng 4:4b28e4aa1742 341 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 342 //! @name Functions for manipulating the MFRC522
sippasaeng 4:4b28e4aa1742 343 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 344 //@{
sippasaeng 4:4b28e4aa1742 345
sippasaeng 4:4b28e4aa1742 346 /**
sippasaeng 4:4b28e4aa1742 347 * Initializes the MFRC522 chip.
sippasaeng 4:4b28e4aa1742 348 */
sippasaeng 4:4b28e4aa1742 349 void PCD_Init (void);
sippasaeng 4:4b28e4aa1742 350
sippasaeng 4:4b28e4aa1742 351 /**
sippasaeng 4:4b28e4aa1742 352 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
sippasaeng 4:4b28e4aa1742 353 */
sippasaeng 4:4b28e4aa1742 354 void PCD_Reset (void);
sippasaeng 4:4b28e4aa1742 355
sippasaeng 4:4b28e4aa1742 356 /**
sippasaeng 4:4b28e4aa1742 357 * Turns the antenna on by enabling pins TX1 and TX2.
sippasaeng 4:4b28e4aa1742 358 * After a reset these pins disabled.
sippasaeng 4:4b28e4aa1742 359 */
sippasaeng 4:4b28e4aa1742 360 void PCD_AntennaOn (void);
sippasaeng 4:4b28e4aa1742 361
sippasaeng 4:4b28e4aa1742 362 /**
sippasaeng 4:4b28e4aa1742 363 * Writes a byte to the specified register in the MFRC522 chip.
sippasaeng 4:4b28e4aa1742 364 * The interface is described in the datasheet section 8.1.2.
sippasaeng 4:4b28e4aa1742 365 *
sippasaeng 4:4b28e4aa1742 366 * @param reg The register to write to. One of the PCD_Register enums.
sippasaeng 4:4b28e4aa1742 367 * @param value The value to write.
sippasaeng 4:4b28e4aa1742 368 */
sippasaeng 4:4b28e4aa1742 369 void PCD_WriteRegister (uint8_t reg, uint8_t value);
sippasaeng 4:4b28e4aa1742 370
sippasaeng 4:4b28e4aa1742 371 /**
sippasaeng 4:4b28e4aa1742 372 * Writes a number of bytes to the specified register in the MFRC522 chip.
sippasaeng 4:4b28e4aa1742 373 * The interface is described in the datasheet section 8.1.2.
sippasaeng 4:4b28e4aa1742 374 *
sippasaeng 4:4b28e4aa1742 375 * @param reg The register to write to. One of the PCD_Register enums.
sippasaeng 4:4b28e4aa1742 376 * @param count The number of bytes to write to the register
sippasaeng 4:4b28e4aa1742 377 * @param values The values to write. Byte array.
sippasaeng 4:4b28e4aa1742 378 */
sippasaeng 4:4b28e4aa1742 379 void PCD_WriteRegister (uint8_t reg, uint8_t count, uint8_t *values);
sippasaeng 4:4b28e4aa1742 380
sippasaeng 4:4b28e4aa1742 381 /**
sippasaeng 4:4b28e4aa1742 382 * Reads a byte from the specified register in the MFRC522 chip.
sippasaeng 4:4b28e4aa1742 383 * The interface is described in the datasheet section 8.1.2.
sippasaeng 4:4b28e4aa1742 384 *
sippasaeng 4:4b28e4aa1742 385 * @param reg The register to read from. One of the PCD_Register enums.
sippasaeng 4:4b28e4aa1742 386 * @returns Register value
sippasaeng 4:4b28e4aa1742 387 */
sippasaeng 4:4b28e4aa1742 388 uint8_t PCD_ReadRegister (uint8_t reg);
sippasaeng 4:4b28e4aa1742 389
sippasaeng 4:4b28e4aa1742 390 /**
sippasaeng 4:4b28e4aa1742 391 * Reads a number of bytes from the specified register in the MFRC522 chip.
sippasaeng 4:4b28e4aa1742 392 * The interface is described in the datasheet section 8.1.2.
sippasaeng 4:4b28e4aa1742 393 *
sippasaeng 4:4b28e4aa1742 394 * @param reg The register to read from. One of the PCD_Register enums.
sippasaeng 4:4b28e4aa1742 395 * @param count The number of bytes to read.
sippasaeng 4:4b28e4aa1742 396 * @param values Byte array to store the values in.
sippasaeng 4:4b28e4aa1742 397 * @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
sippasaeng 4:4b28e4aa1742 398 */
sippasaeng 4:4b28e4aa1742 399 void PCD_ReadRegister (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
sippasaeng 4:4b28e4aa1742 400
sippasaeng 4:4b28e4aa1742 401 /**
sippasaeng 4:4b28e4aa1742 402 * Sets the bits given in mask in register reg.
sippasaeng 4:4b28e4aa1742 403 *
sippasaeng 4:4b28e4aa1742 404 * @param reg The register to update. One of the PCD_Register enums.
sippasaeng 4:4b28e4aa1742 405 * @param mask The bits to set.
sippasaeng 4:4b28e4aa1742 406 */
sippasaeng 4:4b28e4aa1742 407 void PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
sippasaeng 4:4b28e4aa1742 408
sippasaeng 4:4b28e4aa1742 409 /**
sippasaeng 4:4b28e4aa1742 410 * Clears the bits given in mask from register reg.
sippasaeng 4:4b28e4aa1742 411 *
sippasaeng 4:4b28e4aa1742 412 * @param reg The register to update. One of the PCD_Register enums.
sippasaeng 4:4b28e4aa1742 413 * @param mask The bits to clear.
sippasaeng 4:4b28e4aa1742 414 */
sippasaeng 4:4b28e4aa1742 415 void PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
sippasaeng 4:4b28e4aa1742 416
sippasaeng 4:4b28e4aa1742 417 /**
sippasaeng 4:4b28e4aa1742 418 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
sippasaeng 4:4b28e4aa1742 419 *
sippasaeng 4:4b28e4aa1742 420 * @param data Pointer to the data to transfer to the FIFO for CRC calculation.
sippasaeng 4:4b28e4aa1742 421 * @param length The number of bytes to transfer.
sippasaeng 4:4b28e4aa1742 422 * @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
sippasaeng 4:4b28e4aa1742 423 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 424 */
sippasaeng 4:4b28e4aa1742 425 uint8_t PCD_CalculateCRC (uint8_t *data, uint8_t length, uint8_t *result);
sippasaeng 4:4b28e4aa1742 426
sippasaeng 4:4b28e4aa1742 427 /**
sippasaeng 4:4b28e4aa1742 428 * Executes the Transceive command.
sippasaeng 4:4b28e4aa1742 429 * CRC validation can only be done if backData and backLen are specified.
sippasaeng 4:4b28e4aa1742 430 *
sippasaeng 4:4b28e4aa1742 431 * @param sendData Pointer to the data to transfer to the FIFO.
sippasaeng 4:4b28e4aa1742 432 * @param sendLen Number of bytes to transfer to the FIFO.
sippasaeng 4:4b28e4aa1742 433 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
sippasaeng 4:4b28e4aa1742 434 * @param backLen Max number of bytes to write to *backData. Out: The number of bytes returned.
sippasaeng 4:4b28e4aa1742 435 * @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
sippasaeng 4:4b28e4aa1742 436 * @param rxAlign Defines the bit position in backData[0] for the first bit received. Default 0.
sippasaeng 4:4b28e4aa1742 437 * @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
sippasaeng 4:4b28e4aa1742 438 *
sippasaeng 4:4b28e4aa1742 439 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 440 */
sippasaeng 4:4b28e4aa1742 441 uint8_t PCD_TransceiveData (uint8_t *sendData,
sippasaeng 4:4b28e4aa1742 442 uint8_t sendLen,
sippasaeng 4:4b28e4aa1742 443 uint8_t *backData,
sippasaeng 4:4b28e4aa1742 444 uint8_t *backLen,
sippasaeng 4:4b28e4aa1742 445 uint8_t *validBits = NULL,
sippasaeng 4:4b28e4aa1742 446 uint8_t rxAlign = 0,
sippasaeng 4:4b28e4aa1742 447 bool checkCRC = false);
sippasaeng 4:4b28e4aa1742 448
sippasaeng 4:4b28e4aa1742 449
sippasaeng 4:4b28e4aa1742 450 /**
sippasaeng 4:4b28e4aa1742 451 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
sippasaeng 4:4b28e4aa1742 452 * CRC validation can only be done if backData and backLen are specified.
sippasaeng 4:4b28e4aa1742 453 *
sippasaeng 4:4b28e4aa1742 454 * @param command The command to execute. One of the PCD_Command enums.
sippasaeng 4:4b28e4aa1742 455 * @param waitIRq The bits in the ComIrqReg register that signals successful completion of the command.
sippasaeng 4:4b28e4aa1742 456 * @param sendData Pointer to the data to transfer to the FIFO.
sippasaeng 4:4b28e4aa1742 457 * @param sendLen Number of bytes to transfer to the FIFO.
sippasaeng 4:4b28e4aa1742 458 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
sippasaeng 4:4b28e4aa1742 459 * @param backLen In: Max number of bytes to write to *backData. Out: The number of bytes returned.
sippasaeng 4:4b28e4aa1742 460 * @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
sippasaeng 4:4b28e4aa1742 461 * @param rxAlign In: Defines the bit position in backData[0] for the first bit received. Default 0.
sippasaeng 4:4b28e4aa1742 462 * @param checkCRC In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
sippasaeng 4:4b28e4aa1742 463 *
sippasaeng 4:4b28e4aa1742 464 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 465 */
sippasaeng 4:4b28e4aa1742 466 uint8_t PCD_CommunicateWithPICC(uint8_t command,
sippasaeng 4:4b28e4aa1742 467 uint8_t waitIRq,
sippasaeng 4:4b28e4aa1742 468 uint8_t *sendData,
sippasaeng 4:4b28e4aa1742 469 uint8_t sendLen,
sippasaeng 4:4b28e4aa1742 470 uint8_t *backData = NULL,
sippasaeng 4:4b28e4aa1742 471 uint8_t *backLen = NULL,
sippasaeng 4:4b28e4aa1742 472 uint8_t *validBits = NULL,
sippasaeng 4:4b28e4aa1742 473 uint8_t rxAlign = 0,
sippasaeng 4:4b28e4aa1742 474 bool checkCRC = false);
sippasaeng 4:4b28e4aa1742 475
sippasaeng 4:4b28e4aa1742 476 /**
sippasaeng 4:4b28e4aa1742 477 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
sippasaeng 4:4b28e4aa1742 478 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
sippasaeng 4:4b28e4aa1742 479 *
sippasaeng 4:4b28e4aa1742 480 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
sippasaeng 4:4b28e4aa1742 481 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
sippasaeng 4:4b28e4aa1742 482 *
sippasaeng 4:4b28e4aa1742 483 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 484 */
sippasaeng 4:4b28e4aa1742 485 uint8_t PICC_RequestA (uint8_t *bufferATQA, uint8_t *bufferSize);
sippasaeng 4:4b28e4aa1742 486
sippasaeng 4:4b28e4aa1742 487 /**
sippasaeng 4:4b28e4aa1742 488 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
sippasaeng 4:4b28e4aa1742 489 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
sippasaeng 4:4b28e4aa1742 490 *
sippasaeng 4:4b28e4aa1742 491 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
sippasaeng 4:4b28e4aa1742 492 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
sippasaeng 4:4b28e4aa1742 493 *
sippasaeng 4:4b28e4aa1742 494 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 495 */
sippasaeng 4:4b28e4aa1742 496 uint8_t PICC_WakeupA (uint8_t *bufferATQA, uint8_t *bufferSize);
sippasaeng 4:4b28e4aa1742 497
sippasaeng 4:4b28e4aa1742 498 /**
sippasaeng 4:4b28e4aa1742 499 * Transmits REQA or WUPA commands.
sippasaeng 4:4b28e4aa1742 500 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
sippasaeng 4:4b28e4aa1742 501 *
sippasaeng 4:4b28e4aa1742 502 * @param command The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
sippasaeng 4:4b28e4aa1742 503 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
sippasaeng 4:4b28e4aa1742 504 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
sippasaeng 4:4b28e4aa1742 505 *
sippasaeng 4:4b28e4aa1742 506 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 507 */
sippasaeng 4:4b28e4aa1742 508 uint8_t PICC_REQA_or_WUPA (uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
sippasaeng 4:4b28e4aa1742 509
sippasaeng 4:4b28e4aa1742 510 /**
sippasaeng 4:4b28e4aa1742 511 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
sippasaeng 4:4b28e4aa1742 512 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
sippasaeng 4:4b28e4aa1742 513 * On success:
sippasaeng 4:4b28e4aa1742 514 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
sippasaeng 4:4b28e4aa1742 515 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
sippasaeng 4:4b28e4aa1742 516 *
sippasaeng 4:4b28e4aa1742 517 * A PICC UID consists of 4, 7 or 10 bytes.
sippasaeng 4:4b28e4aa1742 518 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
sippasaeng 4:4b28e4aa1742 519 *
sippasaeng 4:4b28e4aa1742 520 * UID size Number of UID bytes Cascade levels Example of PICC
sippasaeng 4:4b28e4aa1742 521 * ======== =================== ============== ===============
sippasaeng 4:4b28e4aa1742 522 * single 4 1 MIFARE Classic
sippasaeng 4:4b28e4aa1742 523 * double 7 2 MIFARE Ultralight
sippasaeng 4:4b28e4aa1742 524 * triple 10 3 Not currently in use?
sippasaeng 4:4b28e4aa1742 525 *
sippasaeng 4:4b28e4aa1742 526 *
sippasaeng 4:4b28e4aa1742 527 * @param uid Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
sippasaeng 4:4b28e4aa1742 528 * @param validBits The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
sippasaeng 4:4b28e4aa1742 529 *
sippasaeng 4:4b28e4aa1742 530 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 531 */
sippasaeng 4:4b28e4aa1742 532 uint8_t PICC_Select (Uid *uid, uint8_t validBits = 0);
sippasaeng 4:4b28e4aa1742 533
sippasaeng 4:4b28e4aa1742 534 /**
sippasaeng 4:4b28e4aa1742 535 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
sippasaeng 4:4b28e4aa1742 536 *
sippasaeng 4:4b28e4aa1742 537 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 538 */
sippasaeng 4:4b28e4aa1742 539 uint8_t PICC_HaltA (void);
sippasaeng 4:4b28e4aa1742 540
sippasaeng 4:4b28e4aa1742 541 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 542 //@}
sippasaeng 4:4b28e4aa1742 543
sippasaeng 4:4b28e4aa1742 544
sippasaeng 4:4b28e4aa1742 545 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 546 //! @name Functions for communicating with MIFARE PICCs
sippasaeng 4:4b28e4aa1742 547 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 548 //@{
sippasaeng 4:4b28e4aa1742 549
sippasaeng 4:4b28e4aa1742 550 /**
sippasaeng 4:4b28e4aa1742 551 * Executes the MFRC522 MFAuthent command.
sippasaeng 4:4b28e4aa1742 552 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
sippasaeng 4:4b28e4aa1742 553 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
sippasaeng 4:4b28e4aa1742 554 * For use with MIFARE Classic PICCs.
sippasaeng 4:4b28e4aa1742 555 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
sippasaeng 4:4b28e4aa1742 556 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
sippasaeng 4:4b28e4aa1742 557 *
sippasaeng 4:4b28e4aa1742 558 * All keys are set to FFFFFFFFFFFFh at chip delivery.
sippasaeng 4:4b28e4aa1742 559 *
sippasaeng 4:4b28e4aa1742 560 * @param command PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
sippasaeng 4:4b28e4aa1742 561 * @param blockAddr The block number. See numbering in the comments in the .h file.
sippasaeng 4:4b28e4aa1742 562 * @param key Pointer to the Crypteo1 key to use (6 bytes)
sippasaeng 4:4b28e4aa1742 563 * @param uid Pointer to Uid struct. The first 4 bytes of the UID is used.
sippasaeng 4:4b28e4aa1742 564 *
sippasaeng 4:4b28e4aa1742 565 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
sippasaeng 4:4b28e4aa1742 566 */
sippasaeng 4:4b28e4aa1742 567 uint8_t PCD_Authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
sippasaeng 4:4b28e4aa1742 568
sippasaeng 4:4b28e4aa1742 569 /**
sippasaeng 4:4b28e4aa1742 570 * Used to exit the PCD from its authenticated state.
sippasaeng 4:4b28e4aa1742 571 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
sippasaeng 4:4b28e4aa1742 572 */
sippasaeng 4:4b28e4aa1742 573 void PCD_StopCrypto1 (void);
sippasaeng 4:4b28e4aa1742 574
sippasaeng 4:4b28e4aa1742 575 /**
sippasaeng 4:4b28e4aa1742 576 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
sippasaeng 4:4b28e4aa1742 577 *
sippasaeng 4:4b28e4aa1742 578 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
sippasaeng 4:4b28e4aa1742 579 *
sippasaeng 4:4b28e4aa1742 580 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
sippasaeng 4:4b28e4aa1742 581 * The MF0ICU1 returns a NAK for higher addresses.
sippasaeng 4:4b28e4aa1742 582 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
sippasaeng 4:4b28e4aa1742 583 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
sippasaeng 4:4b28e4aa1742 584 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
sippasaeng 4:4b28e4aa1742 585 *
sippasaeng 4:4b28e4aa1742 586 * The buffer must be at least 18 bytes because a CRC_A is also returned.
sippasaeng 4:4b28e4aa1742 587 * Checks the CRC_A before returning STATUS_OK.
sippasaeng 4:4b28e4aa1742 588 *
sippasaeng 4:4b28e4aa1742 589 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
sippasaeng 4:4b28e4aa1742 590 * @param buffer The buffer to store the data in
sippasaeng 4:4b28e4aa1742 591 * @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
sippasaeng 4:4b28e4aa1742 592 *
sippasaeng 4:4b28e4aa1742 593 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 594 */
sippasaeng 4:4b28e4aa1742 595 uint8_t MIFARE_Read (uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
sippasaeng 4:4b28e4aa1742 596
sippasaeng 4:4b28e4aa1742 597 /**
sippasaeng 4:4b28e4aa1742 598 * Writes 16 bytes to the active PICC.
sippasaeng 4:4b28e4aa1742 599 *
sippasaeng 4:4b28e4aa1742 600 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
sippasaeng 4:4b28e4aa1742 601 *
sippasaeng 4:4b28e4aa1742 602 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
sippasaeng 4:4b28e4aa1742 603 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
sippasaeng 4:4b28e4aa1742 604 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
sippasaeng 4:4b28e4aa1742 605 *
sippasaeng 4:4b28e4aa1742 606 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
sippasaeng 4:4b28e4aa1742 607 * @param buffer The 16 bytes to write to the PICC
sippasaeng 4:4b28e4aa1742 608 * @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
sippasaeng 4:4b28e4aa1742 609 *
sippasaeng 4:4b28e4aa1742 610 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 611 */
sippasaeng 4:4b28e4aa1742 612 uint8_t MIFARE_Write (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
sippasaeng 4:4b28e4aa1742 613
sippasaeng 4:4b28e4aa1742 614 /**
sippasaeng 4:4b28e4aa1742 615 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
sippasaeng 4:4b28e4aa1742 616 *
sippasaeng 4:4b28e4aa1742 617 * @param page The page (2-15) to write to.
sippasaeng 4:4b28e4aa1742 618 * @param buffer The 4 bytes to write to the PICC
sippasaeng 4:4b28e4aa1742 619 * @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
sippasaeng 4:4b28e4aa1742 620 *
sippasaeng 4:4b28e4aa1742 621 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 622 */
sippasaeng 4:4b28e4aa1742 623 uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
sippasaeng 4:4b28e4aa1742 624
sippasaeng 4:4b28e4aa1742 625 /**
sippasaeng 4:4b28e4aa1742 626 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
sippasaeng 4:4b28e4aa1742 627 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
sippasaeng 4:4b28e4aa1742 628 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
sippasaeng 4:4b28e4aa1742 629 * Use MIFARE_Transfer() to store the result in a block.
sippasaeng 4:4b28e4aa1742 630 *
sippasaeng 4:4b28e4aa1742 631 * @param blockAddr The block (0-0xff) number.
sippasaeng 4:4b28e4aa1742 632 * @param delta This number is subtracted from the value of block blockAddr.
sippasaeng 4:4b28e4aa1742 633 *
sippasaeng 4:4b28e4aa1742 634 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 635 */
sippasaeng 4:4b28e4aa1742 636 uint8_t MIFARE_Decrement (uint8_t blockAddr, uint32_t delta);
sippasaeng 4:4b28e4aa1742 637
sippasaeng 4:4b28e4aa1742 638 /**
sippasaeng 4:4b28e4aa1742 639 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
sippasaeng 4:4b28e4aa1742 640 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
sippasaeng 4:4b28e4aa1742 641 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
sippasaeng 4:4b28e4aa1742 642 * Use MIFARE_Transfer() to store the result in a block.
sippasaeng 4:4b28e4aa1742 643 *
sippasaeng 4:4b28e4aa1742 644 * @param blockAddr The block (0-0xff) number.
sippasaeng 4:4b28e4aa1742 645 * @param delta This number is added to the value of block blockAddr.
sippasaeng 4:4b28e4aa1742 646 *
sippasaeng 4:4b28e4aa1742 647 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 648 */
sippasaeng 4:4b28e4aa1742 649 uint8_t MIFARE_Increment (uint8_t blockAddr, uint32_t delta);
sippasaeng 4:4b28e4aa1742 650
sippasaeng 4:4b28e4aa1742 651 /**
sippasaeng 4:4b28e4aa1742 652 * MIFARE Restore copies the value of the addressed block into a volatile memory.
sippasaeng 4:4b28e4aa1742 653 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
sippasaeng 4:4b28e4aa1742 654 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
sippasaeng 4:4b28e4aa1742 655 * Use MIFARE_Transfer() to store the result in a block.
sippasaeng 4:4b28e4aa1742 656 *
sippasaeng 4:4b28e4aa1742 657 * @param blockAddr The block (0-0xff) number.
sippasaeng 4:4b28e4aa1742 658 *
sippasaeng 4:4b28e4aa1742 659 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 660 */
sippasaeng 4:4b28e4aa1742 661 uint8_t MIFARE_Restore (uint8_t blockAddr);
sippasaeng 4:4b28e4aa1742 662
sippasaeng 4:4b28e4aa1742 663 /**
sippasaeng 4:4b28e4aa1742 664 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
sippasaeng 4:4b28e4aa1742 665 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
sippasaeng 4:4b28e4aa1742 666 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
sippasaeng 4:4b28e4aa1742 667 *
sippasaeng 4:4b28e4aa1742 668 * @param blockAddr The block (0-0xff) number.
sippasaeng 4:4b28e4aa1742 669 *
sippasaeng 4:4b28e4aa1742 670 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 671 */
sippasaeng 4:4b28e4aa1742 672 uint8_t MIFARE_Transfer (uint8_t blockAddr);
sippasaeng 4:4b28e4aa1742 673
sippasaeng 4:4b28e4aa1742 674 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 675 //@}
sippasaeng 4:4b28e4aa1742 676
sippasaeng 4:4b28e4aa1742 677
sippasaeng 4:4b28e4aa1742 678 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 679 //! @name Support functions
sippasaeng 4:4b28e4aa1742 680 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 681 //@{
sippasaeng 4:4b28e4aa1742 682
sippasaeng 4:4b28e4aa1742 683 /**
sippasaeng 4:4b28e4aa1742 684 * Wrapper for MIFARE protocol communication.
sippasaeng 4:4b28e4aa1742 685 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
sippasaeng 4:4b28e4aa1742 686 *
sippasaeng 4:4b28e4aa1742 687 * @param sendData Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
sippasaeng 4:4b28e4aa1742 688 * @param sendLen Number of bytes in sendData.
sippasaeng 4:4b28e4aa1742 689 * @param acceptTimeout True => A timeout is also success
sippasaeng 4:4b28e4aa1742 690 *
sippasaeng 4:4b28e4aa1742 691 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 692 */
sippasaeng 4:4b28e4aa1742 693 uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
sippasaeng 4:4b28e4aa1742 694
sippasaeng 4:4b28e4aa1742 695 /**
sippasaeng 4:4b28e4aa1742 696 * Translates the SAK (Select Acknowledge) to a PICC type.
sippasaeng 4:4b28e4aa1742 697 *
sippasaeng 4:4b28e4aa1742 698 * @param sak The SAK byte returned from PICC_Select().
sippasaeng 4:4b28e4aa1742 699 *
sippasaeng 4:4b28e4aa1742 700 * @return PICC_Type
sippasaeng 4:4b28e4aa1742 701 */
sippasaeng 4:4b28e4aa1742 702 uint8_t PICC_GetType (uint8_t sak);
sippasaeng 4:4b28e4aa1742 703
sippasaeng 4:4b28e4aa1742 704 /**
sippasaeng 4:4b28e4aa1742 705 * Returns a string pointer to the PICC type name.
sippasaeng 4:4b28e4aa1742 706 *
sippasaeng 4:4b28e4aa1742 707 * @param type One of the PICC_Type enums.
sippasaeng 4:4b28e4aa1742 708 *
sippasaeng 4:4b28e4aa1742 709 * @return A string pointer to the PICC type name.
sippasaeng 4:4b28e4aa1742 710 */
sippasaeng 4:4b28e4aa1742 711 char* PICC_GetTypeName (uint8_t type);
sippasaeng 4:4b28e4aa1742 712
sippasaeng 4:4b28e4aa1742 713 /**
sippasaeng 4:4b28e4aa1742 714 * Returns a string pointer to a status code name.
sippasaeng 4:4b28e4aa1742 715 *
sippasaeng 4:4b28e4aa1742 716 * @param code One of the StatusCode enums.
sippasaeng 4:4b28e4aa1742 717 *
sippasaeng 4:4b28e4aa1742 718 * @return A string pointer to a status code name.
sippasaeng 4:4b28e4aa1742 719 */
sippasaeng 4:4b28e4aa1742 720 char* GetStatusCodeName (uint8_t code);
sippasaeng 4:4b28e4aa1742 721
sippasaeng 4:4b28e4aa1742 722 /**
sippasaeng 4:4b28e4aa1742 723 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
sippasaeng 4:4b28e4aa1742 724 *
sippasaeng 4:4b28e4aa1742 725 * @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
sippasaeng 4:4b28e4aa1742 726 * @param g0 Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
sippasaeng 4:4b28e4aa1742 727 * @param g1 Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
sippasaeng 4:4b28e4aa1742 728 * @param g2 Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
sippasaeng 4:4b28e4aa1742 729 * @param g3 Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
sippasaeng 4:4b28e4aa1742 730 */
sippasaeng 4:4b28e4aa1742 731 void MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
sippasaeng 4:4b28e4aa1742 732 uint8_t g0,
sippasaeng 4:4b28e4aa1742 733 uint8_t g1,
sippasaeng 4:4b28e4aa1742 734 uint8_t g2,
sippasaeng 4:4b28e4aa1742 735 uint8_t g3);
sippasaeng 4:4b28e4aa1742 736
sippasaeng 4:4b28e4aa1742 737 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 738 //@}
sippasaeng 4:4b28e4aa1742 739
sippasaeng 4:4b28e4aa1742 740
sippasaeng 4:4b28e4aa1742 741 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 742 //! @name Convenience functions - does not add extra functionality
sippasaeng 4:4b28e4aa1742 743 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 744 //@{
sippasaeng 4:4b28e4aa1742 745
sippasaeng 4:4b28e4aa1742 746 /**
sippasaeng 4:4b28e4aa1742 747 * Returns true if a PICC responds to PICC_CMD_REQA.
sippasaeng 4:4b28e4aa1742 748 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
sippasaeng 4:4b28e4aa1742 749 *
sippasaeng 4:4b28e4aa1742 750 * @return bool
sippasaeng 4:4b28e4aa1742 751 */
sippasaeng 4:4b28e4aa1742 752 bool PICC_IsNewCardPresent(void);
sippasaeng 4:4b28e4aa1742 753
sippasaeng 4:4b28e4aa1742 754 /**
sippasaeng 4:4b28e4aa1742 755 * Simple wrapper around PICC_Select.
sippasaeng 4:4b28e4aa1742 756 * Returns true if a UID could be read.
sippasaeng 4:4b28e4aa1742 757 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
sippasaeng 4:4b28e4aa1742 758 * The read UID is available in the class variable uid.
sippasaeng 4:4b28e4aa1742 759 *
sippasaeng 4:4b28e4aa1742 760 * @return bool
sippasaeng 4:4b28e4aa1742 761 */
sippasaeng 4:4b28e4aa1742 762 bool PICC_ReadCardSerial (void);
sippasaeng 4:4b28e4aa1742 763
sippasaeng 4:4b28e4aa1742 764 // ************************************************************************************
sippasaeng 4:4b28e4aa1742 765 //@}
sippasaeng 4:4b28e4aa1742 766
sippasaeng 4:4b28e4aa1742 767
sippasaeng 4:4b28e4aa1742 768 private:
sippasaeng 4:4b28e4aa1742 769 SPI m_SPI;
sippasaeng 4:4b28e4aa1742 770 DigitalOut m_CS;
sippasaeng 4:4b28e4aa1742 771 DigitalOut m_RESET;
sippasaeng 4:4b28e4aa1742 772
sippasaeng 4:4b28e4aa1742 773 /**
sippasaeng 4:4b28e4aa1742 774 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
sippasaeng 4:4b28e4aa1742 775 *
sippasaeng 4:4b28e4aa1742 776 * @param command The command to use
sippasaeng 4:4b28e4aa1742 777 * @param blockAddr The block (0-0xff) number.
sippasaeng 4:4b28e4aa1742 778 * @param data The data to transfer in step 2
sippasaeng 4:4b28e4aa1742 779 *
sippasaeng 4:4b28e4aa1742 780 * @return STATUS_OK on success, STATUS_??? otherwise.
sippasaeng 4:4b28e4aa1742 781 */
sippasaeng 4:4b28e4aa1742 782 uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
sippasaeng 4:4b28e4aa1742 783 };
sippasaeng 4:4b28e4aa1742 784
sippasaeng 4:4b28e4aa1742 785 #endif