umb_adau1361a.cpp

00001 #include "umb_adau1361a.h"
00002 
00003 namespace shimabara
00004 {
00005 
00006      
00007         // 48kHz PLL setting for 12MHz input
00008             // Denominator : 0x7D = 125
00009             // Nunerator : 0x0c = 12
00010             // Fractional PLL, *4 multiplying
00011             // PLL Enable : Freq is 12Mhz * ( 4 + 12/125 ) = 49.125Mhz (1024 core clock)
00012     static const char init_pll_48[] = {0x40, 0x02, 0x00, 0x7D, 0x00, 0x0C, 0x21, 0x01};     
00013             // R17: Converter 0, SRC = 1 * core clock
00014     static const char init_src_48[] = {0x40, 0x17, 0x00};      
00015 
00016         // 96kHz PLL setting for 12MHz input
00017 #define init_pll_96 init_pll_48
00018             // R17: Converter 0, SRC = 1 * core clock
00019     static const char init_src_96[] = {0x40, 0x17, 0x06};      
00020 
00021 
00022         // 32kHz PLL setting for 12MHz input
00023 #define init_pll_32 init_pll_48
00024             // R17: Converter 0, SRC = 1 * core clock
00025     static const char init_src_32[] = {0x40, 0x17, 0x05};      
00026 
00027 
00028         // 44.1kHz PLL setting for 12MHz input
00029             // Denominator : 0x271 = 625
00030             // Nunerator : 0x1dd = 447
00031             // Fractional PLL, *3 multiplying
00032             // PLL Enable : Freq is 12Mhz * ( 3 + 477/625 ) = 45.1584Mhz (1024 core clock)
00033     static const char init_pll_441[] = {0x40, 0x02, 0x02, 0x71, 0x01, 0xDD, 0x19, 0x01};     
00034             // R17: Converter 0, SRC = 1 * core clock
00035 #define init_src_441 init_src_48
00036 
00037         // Set UMB_ADAU1361A. No mono output, No cross channel Mix, No analog path through.
00038     static const char config_UMB_ADAU1361A[][3] =
00039     {
00040             // Configuration for UMB-ADAU1361-A http://dsps.shop-pro.jp/?pid=82798273
00041         {0x40, 0x0a, 0x0B},     // R4: Rec Mixer Left 0,  Mixer enable, LINNG 0dB
00042         {0x40, 0x0c, 0x0B},     // R6: Rec Mixer Right 0, Mixer enable, RINNG 0dB
00043         {0x40, 0x15, 0x01},     // R15:Serial Port control, Set code as Master mode I2S.
00044         {0x40, 0x19, 0x63},     // R19:ADC Control. Enable ADC, Both Cannel ADC on, HPF on
00045         {0x40, 0x29, 0x03},     // R35:Left Right Play back enable. Play back power Management
00046         {0x40, 0x2a, 0x03},     // R36:DAC Control 0. Enable DAC. Both channels on.
00047         {0x40, 0x1c, 0x21},     // R22:MIXER 3, Left DAC Mixer (set L DAC to L Mixer )
00048         {0x40, 0x1e, 0x41},     // R24:MIXER 4, Right DAC Mixer (set R DAC to R Mixer )
00049         {0x40, 0x20, 0x03},     // R26:MIXER 5, Left out mixer. L out MIX5G3 and enable
00050         {0x40, 0x21, 0x09},     // R27:MIXER 6, Right out mixer. R out MIX6G4 and enable.
00051     };
00052 
00053         // Clear PLL regsiter and then, set up PLL registers for given Fs.
00054     void UMB_ADAU1361A::configure_pll(void)
00055     {
00056                     // set Fs ( xternal clock in is 12MHz )
00057         switch  ( fs )  // fs is member variable. 
00058         {
00059         case Fs_96:
00060             send_command( init_pll_96, sizeof(init_pll_96) );
00061             wait_pll_lock();
00062             send_command( init_src_96, sizeof(init_src_96) );
00063             break;
00064         case Fs_441:
00065             send_command( init_pll_441, sizeof(init_pll_441) );
00066             wait_pll_lock();
00067             send_command( init_src_441, sizeof(init_src_441) );
00068             break;
00069         case Fs_32:
00070             send_command( init_pll_32, sizeof(init_pll_32) );
00071             wait_pll_lock();
00072             send_command( init_src_32, sizeof(init_src_32) );
00073             break;
00074         case Fs_48:
00075         default: 
00076             send_command( init_pll_48, sizeof(init_pll_48) );
00077             wait_pll_lock();
00078             send_command( init_src_48, sizeof(init_src_48) );
00079             break;
00080         }
00081 
00082     }
00083 
00084     void UMB_ADAU1361A::configure_board(void)
00085     {
00086         send_command_table( config_UMB_ADAU1361A, sizeof(config_UMB_ADAU1361A)/3 );
00087     }
00088 
00089 }
00090