Shivanand Gowda / S70FL01GS

Serial Peripheral Interface (SPI) Serial Single IO NOR Flash Memory Interfacing 1Gb

Dependents:   SPI_FLASH_MEM_1Gb

Fork of S25FL256S by Shivanand Gowda

S25FL256S.h@4:8c463abb67d5, 2018-05-19 (annotated)

Committer:
shivanandgowdakr
Date:
Sat May 19 09:56:14 2018 +0000
Revision:
4:8c463abb67d5
Child:
5:c2707c92ecb5
S25FL256S  Interface with Nucleo and Tested on 19/05/2018

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shivanandgowdakr 4:8c463abb67d5 1 // S25FL256S.h
shivanandgowdakr 4:8c463abb67d5 2
shivanandgowdakr 4:8c463abb67d5 3 #ifndef S25FL256S_H
shivanandgowdakr 4:8c463abb67d5 4 #define S25FL256S_H
shivanandgowdakr 4:8c463abb67d5 5
shivanandgowdakr 4:8c463abb67d5 6 #include "mbed.h"
shivanandgowdakr 4:8c463abb67d5 7 #include <string>
shivanandgowdakr 4:8c463abb67d5 8
shivanandgowdakr 4:8c463abb67d5 9 #define SPI_FREQ 5000000 //Change SPI Frequency Here
shivanandgowdakr 4:8c463abb67d5 10 #define SPI_MODE 0 // SPI Mode can be 0 or 3 . see data sheet
shivanandgowdakr 4:8c463abb67d5 11 #define SPI_NBIT 8 // Number of bits 8.
shivanandgowdakr 4:8c463abb67d5 12
shivanandgowdakr 4:8c463abb67d5 13
shivanandgowdakr 4:8c463abb67d5 14
shivanandgowdakr 4:8c463abb67d5 15 #define DUMMY_ADDR 0x00
shivanandgowdakr 4:8c463abb67d5 16 #define WAIT_TIME 1
shivanandgowdakr 4:8c463abb67d5 17
shivanandgowdakr 4:8c463abb67d5 18 #define ADDR_BMASK3 0xff000000
shivanandgowdakr 4:8c463abb67d5 19 #define ADDR_BMASK2 0x00ff0000
shivanandgowdakr 4:8c463abb67d5 20 #define ADDR_BMASK1 0x0000ff00
shivanandgowdakr 4:8c463abb67d5 21 #define ADDR_BMASK0 0x000000ff
shivanandgowdakr 4:8c463abb67d5 22
shivanandgowdakr 4:8c463abb67d5 23 #define ADDR_BSHIFT3 24
shivanandgowdakr 4:8c463abb67d5 24 #define ADDR_BSHIFT2 16
shivanandgowdakr 4:8c463abb67d5 25 #define ADDR_BSHIFT1 8
shivanandgowdakr 4:8c463abb67d5 26 #define ADDR_BSHIFT0 0
shivanandgowdakr 4:8c463abb67d5 27
shivanandgowdakr 4:8c463abb67d5 28 #define RDSR1 0x05 // 6th bit P_ERR Program Error-->1, NO error 0
shivanandgowdakr 4:8c463abb67d5 29 //5th bit E_ERR Program Error-->1, No ERROR 0
shivanandgowdakr 4:8c463abb67d5 30 //0th WIP --> 1 indicates Busy Writing, 0--> Free, Done
shivanandgowdakr 4:8c463abb67d5 31 // read Bits 6,5,0
shivanandgowdakr 4:8c463abb67d5 32 #define READ_ID 0x90 // Read Electronic Manufacturer Signature
shivanandgowdakr 4:8c463abb67d5 33 #define RDID 0x9F //Read ID (JEDEC Manufacturer ID and JEDEC CFI)
shivanandgowdakr 4:8c463abb67d5 34 #define RES 0xAB // Read Electronic Signature
shivanandgowdakr 4:8c463abb67d5 35
shivanandgowdakr 4:8c463abb67d5 36 //4 Byte Address4PP 12h)
shivanandgowdakr 4:8c463abb67d5 37
shivanandgowdakr 4:8c463abb67d5 38 #define FOUR_FAST_READ 0x0C //Read Fast (4-byte Address) 0C
shivanandgowdakr 4:8c463abb67d5 39 #define FOUR_READ 0x13 //Read (4-byte Address)
shivanandgowdakr 4:8c463abb67d5 40 #define FOUR_DOR 0x3C //Read Dual Out (FOUR_-byte Address) 3C
shivanandgowdakr 4:8c463abb67d5 41 #define FOUR_QOR 0x6C //Read Quad Out (FOUR_-byte Address)
shivanandgowdakr 4:8c463abb67d5 42 #define FOUR_DIOR 0xBC // Dual I/O Read (FOUR_-byte Address) BC
shivanandgowdakr 4:8c463abb67d5 43 #define FOUR_QIOR 0xEC //FOUR_QIOR Quad I/O Read (FOUR_-byte Address) EC
shivanandgowdakr 4:8c463abb67d5 44 #define FOUR_DDRFR 0x0E //Read DDR Fast (FOUR_-byte Address)
shivanandgowdakr 4:8c463abb67d5 45 #define FOUR_DDRDIOR 0xBE // DDR Dual I/O Read (FOUR_-byte Address) BE
shivanandgowdakr 4:8c463abb67d5 46 #define FOUR_DDRQIOR 0xEE
shivanandgowdakr 4:8c463abb67d5 47 #define FOUR_PP 0x12 // FOUR_PP Page Program (FOUR_-byte Address) 12
shivanandgowdakr 4:8c463abb67d5 48 #define FOUR_QPP 0x34 //Quad Page Program (FOUR_-byte Address)
shivanandgowdakr 4:8c463abb67d5 49 #define FOUR_P4E 0x21 // Parameter 4-kB Erase (4-byte Address) 21
shivanandgowdakr 4:8c463abb67d5 50 #define FOUR_SE 0xDC // Erase 64/256 kB (4-byte Address) DC
shivanandgowdakr 4:8c463abb67d5 51
shivanandgowdakr 4:8c463abb67d5 52 //3 Byte Address
shivanandgowdakr 4:8c463abb67d5 53
shivanandgowdakr 4:8c463abb67d5 54 #define READ 0x03 //READ Read (3-byte Address) 03
shivanandgowdakr 4:8c463abb67d5 55 #define FAST_READ 0x0B //FAST_READ Read Fast (3-byte Address) 0B
shivanandgowdakr 4:8c463abb67d5 56 #define DOR 0x3B //DOR Read Dual Out (3-byte Address) 3B
shivanandgowdakr 4:8c463abb67d5 57 #define Q0R 0x6B //QOR Read Quad Out (3-byte Address) 6B
shivanandgowdakr 4:8c463abb67d5 58 #define DIOR 0xBB //DIOR Dual I/O Read (3-byte Address) BB
shivanandgowdakr 4:8c463abb67d5 59 #define QIOR 0xEB //QIOR Quad I/O Read (3-byte Address) EB
shivanandgowdakr 4:8c463abb67d5 60 #define DDRFR 0x0D //DDRFR Read DDR Fast (3-byte Address) 0D
shivanandgowdakr 4:8c463abb67d5 61 #define DDRDIOR 0xBD //DDRDIOR DDR Dual I/O Read (3-byte Address) BD
shivanandgowdakr 4:8c463abb67d5 62 #define DDRQIOR 0xED //DDRQIOR DDR Quad I/O Read (3-byte Address) ED
shivanandgowdakr 4:8c463abb67d5 63 #define PP 0x02 //PP Page Program (3-byte Address) 02
shivanandgowdakr 4:8c463abb67d5 64 #define Qpp 0x32 //QPP Quad Page Program (3-byte Address) 32
shivanandgowdakr 4:8c463abb67d5 65 #define P4E 0x20 //P4E Parameter 4-kB Erase (3-byte Address) 20
shivanandgowdakr 4:8c463abb67d5 66 #define SE 0xD8 //SE Erase 64 / 256 kB (3-byte Address) D8
shivanandgowdakr 4:8c463abb67d5 67 #define BE 0x60 // Erase Entire Chip.
shivanandgowdakr 4:8c463abb67d5 68
shivanandgowdakr 4:8c463abb67d5 69 #define RDSR1 0x05 //RDSR1 Read Status Register-1 05
shivanandgowdakr 4:8c463abb67d5 70 #define RDSR2 0x07 //RDSR2 Read Status Register-2 07
shivanandgowdakr 4:8c463abb67d5 71 #define RDCR 0x35 //RDCR Read Configuration Register-1 35
shivanandgowdakr 4:8c463abb67d5 72 #define WRR 0x01 //Write Register (Status-1, Configuration-1)
shivanandgowdakr 4:8c463abb67d5 73 #define WRDI 0x04 //Write Disable 04
shivanandgowdakr 4:8c463abb67d5 74 #define WREN 0x06 //WREN Write Enable 06
shivanandgowdakr 4:8c463abb67d5 75 #define CLSR 0x30 //CLSR Clear Status Register-1 - Erase/Prog. Fail Reset 30
shivanandgowdakr 4:8c463abb67d5 76 #define ECCRD 0x18 //ECCRD ECC Read (4-byte address) 18
shivanandgowdakr 4:8c463abb67d5 77 #define ABRD 0x14 //ABRD AutoBoot Register Read 14
shivanandgowdakr 4:8c463abb67d5 78 #define ABWR 0x15 //AutoBoot Register Write 15
shivanandgowdakr 4:8c463abb67d5 79 #define BRRD 0x16 //Bank Register Read 16
shivanandgowdakr 4:8c463abb67d5 80 #define BRWR 0x17 //Bank Register Write 17
shivanandgowdakr 4:8c463abb67d5 81 #define BRAC 0xB9 //BRAC Bank Register Access (Legacy Command formerly used for Deep Power Down) B9
shivanandgowdakr 4:8c463abb67d5 82 #define DLPRD 0x41 //DLPRD Data Learning Pattern Read 41
shivanandgowdakr 4:8c463abb67d5 83 #define PNVDLR 0x43 //PNVDLR Program NV Data Learning Register 43
shivanandgowdakr 4:8c463abb67d5 84 #define WVDLR 0x4A //Write Volatile Data Learning Register 4A
shivanandgowdakr 4:8c463abb67d5 85 #define PGSP 0x85 //Program Suspend 85
shivanandgowdakr 4:8c463abb67d5 86 #define PGRS 0x8A //Program Resume 8A
shivanandgowdakr 4:8c463abb67d5 87 #define ERSP 0x75 //Erase Suspend 75
shivanandgowdakr 4:8c463abb67d5 88 #define ERRS 0x7A //Erase Resume 7A
shivanandgowdakr 4:8c463abb67d5 89 #define OTPP 0x42 //OTP Program 42
shivanandgowdakr 4:8c463abb67d5 90 #define OTPR 0x4B //OTP Read 4B
shivanandgowdakr 4:8c463abb67d5 91
shivanandgowdakr 4:8c463abb67d5 92 //Advanced Sector Protection
shivanandgowdakr 4:8c463abb67d5 93
shivanandgowdakr 4:8c463abb67d5 94 #define DYBRD 0xE0 //DYB Read E0 133
shivanandgowdakr 4:8c463abb67d5 95 #define DYBWR 0xE1 //DYB Write E1 133
shivanandgowdakr 4:8c463abb67d5 96 #define PPBRD 0xE2 //PPB Read E2 133
shivanandgowdakr 4:8c463abb67d5 97 #define PPBP 0xE3 //PPB Program E3 133
shivanandgowdakr 4:8c463abb67d5 98 #define PPBE 0xE4 //PPB Erase E4 133
shivanandgowdakr 4:8c463abb67d5 99 #define ASPRD 0x2B //ASP Read 2B 133
shivanandgowdakr 4:8c463abb67d5 100 #define ASPP 0x2F //ASP Program 2F 133
shivanandgowdakr 4:8c463abb67d5 101 #define PLBRD 0xA7 //PPB Lock Bit Read A7 133
shivanandgowdakr 4:8c463abb67d5 102 #define PLBWR 0xA6 //PPB Lock Bit Write A6 133
shivanandgowdakr 4:8c463abb67d5 103 #define PASSRD 0xE7 //Password Read E7 133
shivanandgowdakr 4:8c463abb67d5 104 #define PASSP 0xE8 //Password Program E8 133
shivanandgowdakr 4:8c463abb67d5 105 #define PASSU 0xE9 //Password Unlock E9 133
shivanandgowdakr 4:8c463abb67d5 106 #define DUMMY 0x00 // Dummy write to read
shivanandgowdakr 4:8c463abb67d5 107 //Reset
shivanandgowdakr 4:8c463abb67d5 108
shivanandgowdakr 4:8c463abb67d5 109 #define RESET 0xF0 //Software Reset F0 133
shivanandgowdakr 4:8c463abb67d5 110 #define MBR 0xFF //Mode Bit Reset FF 133
shivanandgowdakr 4:8c463abb67d5 111 #define DUMMYBYTE 0x00 //Dummy byte for Read Operation
shivanandgowdakr 4:8c463abb67d5 112
shivanandgowdakr 4:8c463abb67d5 113 class S25FL256S: public SPI {
shivanandgowdakr 4:8c463abb67d5 114 public:
shivanandgowdakr 4:8c463abb67d5 115 S25FL256S(PinName mosi, PinName miso, PinName sclk, PinName cs);
shivanandgowdakr 4:8c463abb67d5 116
shivanandgowdakr 4:8c463abb67d5 117 int readByte(int addr); // takes a 32-bit (4 bytes) address and returns the data (1 byte) at that location
shivanandgowdakr 4:8c463abb67d5 118 void readStream(int addr, char* buf, int count); // takes a 32-bit address, reads count bytes, and stores results in buf
shivanandgowdakr 4:8c463abb67d5 119
shivanandgowdakr 4:8c463abb67d5 120 void writeByte(int addr, int data); // takes a 32-bit (4 bytes) address and a byte of data to write at that location
shivanandgowdakr 4:8c463abb67d5 121 void writeStream(int addr, char* buf, int count); // write count bytes of data from buf to memory, starting at addr
shivanandgowdakr 4:8c463abb67d5 122 void writeString(int add, string str);
shivanandgowdakr 4:8c463abb67d5 123 void sectorErase(int addr);
shivanandgowdakr 4:8c463abb67d5 124 void chipErase(); //erase all data on chip
shivanandgowdakr 4:8c463abb67d5 125 uint8_t readRegister();
shivanandgowdakr 4:8c463abb67d5 126 uint8_t checkIfBusy(); // Check if IC is bury writing or erasing
shivanandgowdakr 4:8c463abb67d5 127 void writeRegister(uint8_t regValue); //Write status register or configuration register
shivanandgowdakr 4:8c463abb67d5 128 void reset(void); // Reset Chip
shivanandgowdakr 4:8c463abb67d5 129 void clearRegister(); // Clear Status Register
shivanandgowdakr 4:8c463abb67d5 130 void Read_Identification(uint8_t *buf);
shivanandgowdakr 4:8c463abb67d5 131 long raedLong(int address); // Read long int number
shivanandgowdakr 4:8c463abb67d5 132 void writeLong(int addr, long value); // Write Long Integer Number
shivanandgowdakr 4:8c463abb67d5 133 private:
shivanandgowdakr 4:8c463abb67d5 134 void writeEnable(); // write enable
shivanandgowdakr 4:8c463abb67d5 135 void writeDisable(); // write disable
shivanandgowdakr 4:8c463abb67d5 136 void chipEnable(); // chip enable
shivanandgowdakr 4:8c463abb67d5 137 void chipDisable();
shivanandgowdakr 4:8c463abb67d5 138 // chip disable
shivanandgowdakr 4:8c463abb67d5 139
shivanandgowdakr 4:8c463abb67d5 140 // SPI _spi;
shivanandgowdakr 4:8c463abb67d5 141 DigitalOut _cs;
shivanandgowdakr 4:8c463abb67d5 142 };
shivanandgowdakr 4:8c463abb67d5 143
shivanandgowdakr 4:8c463abb67d5 144 #endif