Beacon tx main incomplete
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tx.cpp
00001 #include "tx.h" 00002 00003 SPI spi(D11, D12, D13); // mosi, miso, sclk 00004 DigitalOut cs(D10); //slave select or chip select 00005 00006 void FCTN_BEA_TX_MAIN() 00007 { 00008 BEA_TX_MAIN_STATUS = 1; 00009 if(BEA_FEN){ 00010 if(BEA_TX_EN){ 00011 if(BEA_TX_STANDBY){ 00012 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_STANDBY); 00013 BEA_TX_MAIN_STATUS = 0; 00014 break; 00015 } 00016 else{ 00017 if(check_POWER_LEVEL()){ //Power level is measured using SoC(State of Charge) 00018 SHORT_BEA_TX(); 00019 if(Check_ACK_RECEIVED()){ 00020 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_SB_SI_SUCCESS); 00021 BEA_TX_MAIN_STATUS = 0; 00022 break; 00023 } 00024 else{ 00025 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_FAILURE); 00026 BEA_TX_MAIN_STATUS = 0; 00027 break; 00028 } 00029 } 00030 else{ 00031 INC_BEA_LOW_POWER_COUNTER(); 00032 if(LOW_POWER_COUNTER=3){ 00033 SHORT_BEA_TX(); 00034 if(Check_ACK_RECEIVED()){ 00035 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_SB_LI_SUCCESS); 00036 BEA_TX_MAIN_STATUS = 0; 00037 break; 00038 } 00039 else{ 00040 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_FAILURE); 00041 BEA_TX_MAIN_STATUS = 0; 00042 break; 00043 } 00044 } 00045 else{ 00046 BEA_TX_MAIN_STATUS = 0; 00047 break; 00048 } 00049 } 00050 } 00051 } 00052 else { 00053 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_DISABLED); 00054 BEA_TX_MAIN_STATUS = 0; 00055 break; 00056 } 00057 } 00058 else { 00059 Set_BEA_TX_MAIN_STATE_STATUS(BEA_RF_SILENCE); 00060 BEA_TX_MAIN_STATUS = 0; 00061 break; 00062 } 00063 00064 } 00065 00066 void Set_BEA_TX_MAIN_STATE_STATUS(uint8_t STATUS){ 00067 BEA_TX_MAIN_STATE_STATUS = STATUS; 00068 } 00069 check_POWER_LEVEL(){ 00070 00071 } 00072 void SHORT_BEA_TX() 00073 { 00074 /* 00075 init(); 00076 //init complete 00077 pc.printf("init complete.....press t to send\n"); 00078 while(pc.getc()=='t') 00079 { */ 00080 //button.rise(&interrupt_func); //interrupt enabled ( rising edge of pin 9) 00081 wait(0.02); // pl. update this value or even avoid it!!! 00082 int i=0; 00083 //extract values from short_beacon[] 00084 uint8_t byte_counter = 0; 00085 struct Short_beacon{ 00086 uint8_t Voltage[1]; 00087 uint8_t AngularSpeed[2]; 00088 uint8_t SubsystemStatus[1]; 00089 uint8_t Temp[3]; 00090 uint8_t ErrorFlag[1]; 00091 }Shortbeacon = { {0x88}, {0x99, 0xAA} , {0xAA},{0xAA,0xDD,0xEE}, {0x00} }; 00092 00093 //filling hk data 00094 //uint8_t short_beacon[] = { 0xAB, 0x8A, 0xE2, 0xBB, 0xB8, 0xA2, 0x8E,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]}; 00095 uint8_t short_beacon[] = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]}; 00096 //mask 00097 /*uint8_t data[] = "Hello World!"; 00098 pc.printf("%d %d %d %d %d %d %d %d %d %d %d %d",data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7],data[8],data[9],data[10],data[11],data[12]);*/ 00099 00100 //setModeIdle(); 00101 writereg(RF22_REG_07_OPERATING_MODE1,0x01); //ready mode 00102 clearTxBuf(); 00103 //writing data first time 00104 cs = 0; 00105 spi.write(0xFF); 00106 for(i=7; i>0;i--) 00107 { 00108 pc.printf("i=%d \n",i); 00109 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) 00110 { 00111 i--; 00112 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) 00113 { 00114 spi.write(0x00); 00115 //pc.printf("0x00\n"); 00116 } 00117 else 00118 { 00119 spi.write(0x0F); 00120 //pc.printf("0x0F\n"); 00121 } 00122 } 00123 else 00124 { 00125 i--; 00126 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) 00127 { 00128 spi.write(0xF0); 00129 //pc.printf("0xF0\n"); 00130 } 00131 else 00132 { 00133 spi.write(0xFF); 00134 //pc.printf("0xFF\n"); 00135 } 00136 } 00137 } 00138 cs = 1; 00139 byte_counter++; 00140 //Check for fifoThresh 00141 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20) pc.printf("fifothresh1?\n"); 00142 00143 //Set to Tx mode 00144 writereg(RF22_REG_07_OPERATING_MODE1,0x09); 00145 00146 while(byte_counter!=15){ 00147 pc.printf("%d\n",byte_counter); 00148 cs = 0; 00149 spi.write(0xFF); 00150 for(i=7; i>0;i--) 00151 { 00152 pc.printf("i=%d \n",i); 00153 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) 00154 { 00155 i--; 00156 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) 00157 { 00158 spi.write(0x00); 00159 //pc.printf("0x00\n"); 00160 } 00161 else 00162 { 00163 spi.write(0x0F); 00164 //pc.printf("0x0F\n"); 00165 } 00166 } 00167 else 00168 { 00169 i--; 00170 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) 00171 { 00172 spi.write(0xF0); 00173 //pc.printf("0xF0\n"); 00174 } 00175 else 00176 { 00177 spi.write(0xFF); 00178 //pc.printf("0xFF\n"); 00179 } 00180 } 00181 } 00182 cs = 1; 00183 byte_counter++; 00184 wait(0.01); 00185 //Check for fifoThresh 00186 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20) pc.printf("fifothresh2?\n"); 00187 } 00188 //rf22.waitPacketSent(); 00189 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) != 0x04)pc.printf(" chck pkt sent!\n"); 00190 pc.printf(" packet sent "); 00191 } 00192 } 00193 void writereg(uint8_t reg,uint8_t val) 00194 { 00195 cs = 0;__disable_irq();spi.write(reg | 0x80);spi.write(val);__enable_irq();cs = 1; 00196 } 00197 uint8_t readreg(uint8_t reg) 00198 { 00199 int val;cs = 0;__disable_irq();spi.write(reg & ~0x80);val = spi.write(0);__enable_irq();cs = 1;return val; 00200 } 00201 void clearTxBuf() 00202 { 00203 writereg(RF22_REG_08_OPERATING_MODE2,0x01); 00204 writereg(RF22_REG_08_OPERATING_MODE2,0x00); 00205 } 00206 void clearRxBuf() 00207 { 00208 writereg(RF22_REG_08_OPERATING_MODE2,0x02); 00209 writereg(RF22_REG_08_OPERATING_MODE2,0x00); 00210 } 00211 int setFrequency(float centre,float afcPullInRange) 00212 { 00213 //freq setting begins 00214 uint8_t fbsel = 0x40; 00215 uint8_t afclimiter; 00216 if (centre >= 480.0) { 00217 centre /= 2; 00218 fbsel |= 0x20; 00219 afclimiter = afcPullInRange * 1000000.0 / 1250.0; 00220 } else { 00221 if (afcPullInRange < 0.0 || afcPullInRange > 0.159375) 00222 return false; 00223 afclimiter = afcPullInRange * 1000000.0 / 625.0; 00224 } 00225 centre /= 10.0; 00226 float integerPart = floor(centre); 00227 float fractionalPart = centre - integerPart; 00228 00229 uint8_t fb = (uint8_t)integerPart - 24; // Range 0 to 23 00230 fbsel |= fb; 00231 uint16_t fc = fractionalPart * 64000; 00232 writereg(RF22_REG_73_FREQUENCY_OFFSET1, 0); // REVISIT 00233 writereg(RF22_REG_74_FREQUENCY_OFFSET2, 0); 00234 writereg(RF22_REG_75_FREQUENCY_BAND_SELECT, fbsel); 00235 writereg(RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1, fc >> 8); 00236 writereg(RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0, fc & 0xff); 00237 writereg(RF22_REG_2A_AFC_LIMITER, afclimiter); 00238 return 0; 00239 } 00240 00241 void Init_BEACON_HW() 00242 { 00243 cs=1; // chip must be deselected 00244 wait(1); //change the time later 00245 spi.format(8,0); 00246 spi.frequency(10000000); //10MHz SCLK 00247 if (readreg(RF22_REG_00_DEVICE_TYPE) == 0x08) pc.printf("spi connection valid\n"); 00248 else pc.printf("error in spi connection\n"); 00249 //reset() 00250 writereg(RF22_REG_07_OPERATING_MODE1,0x80); //sw_reset 00251 wait(1); //takes time to reset 00252 00253 clearTxBuf(); 00254 clearRxBuf(); 00255 //txfifoalmostempty 00256 writereg(RF22_REG_7D_TX_FIFO_CONTROL2,10); 00257 //rxfifoalmostfull 00258 writereg(RF22_REG_7E_RX_FIFO_CONTROL,20); 00259 //Packet-engine registers 00260 writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x8E); //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM 00261 //&0x77 = diasable packet rx-tx handling 00262 writereg(RF22_REG_32_HEADER_CONTROL1,0x88); //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3 00263 writereg(RF22_REG_33_HEADER_CONTROL2,0x42); //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2 00264 writereg(RF22_REG_34_PREAMBLE_LENGTH,8); //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8; 00265 writereg(RF22_REG_36_SYNC_WORD3,0x2D); //syncword3=2D 00266 writereg(RF22_REG_37_SYNC_WORD2,0xD4); //syncword2=D4 00267 writereg(RF22_REG_3F_CHECK_HEADER3,0); //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS 00268 writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab); //header_to 00269 writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc); //header_from 00270 writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd); //header_ids 00271 writereg(RF22_REG_3D_TRANSMIT_HEADER0,0xde); //header_flags 00272 writereg(RF22_REG_3F_CHECK_HEADER3,0xab); 00273 writereg(RF22_REG_40_CHECK_HEADER2,0xbc); 00274 writereg(RF22_REG_41_CHECK_HEADER1,0xcd); 00275 writereg(RF22_REG_42_CHECK_HEADER0,0xde); 00276 00277 //RSSI threshold for clear channel indicator 00278 writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5); //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm 00279 00280 writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state ?? 00281 writereg(RF22_REG_0C_GPIO_CONFIGURATION1,0x12); // RX state ?? 00282 00283 //interrupts 00284 // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR); 00285 // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL); 00286 00287 setFrequency(435.0, 0.05); 00288 00289 //return !(statusRead() & RF22_FREQERR); 00290 if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00) 00291 pc.printf("frequency not set properly\n"); 00292 //frequency set 00293 00294 //setModemConfig(FSK_Rb2_4Fd36); FSK_Rb2_4Fd36, ///< FSK, No Manchester, Rb = 2.4kbs, Fd = 36kHz 00295 //setmodemregisters 00296 //0x1b, 0x03, 0x41, 0x60, 0x27, 0x52, 0x00, 0x07, 0x40, 0x0a, 0x1e, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x22, 0x3a = FSK_RB2_4FD36 00297 //0xc8, 0x03, 0x39, 0x20, 0x68, 0xdc, 0x00, 0x6b, 0x2a, 0x08, 0x2a, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x21, 0x08 = OOK,2.4, 335 00298 writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0xdf); 00299 writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03); 00300 writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x39); 00301 writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0x20); 00302 writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x68); //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk 00303 writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0xdc); 00304 writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00); 00305 writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x6B); 00306 writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2C); 00307 writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x11); //not required for fsk (OOK counter value) 00308 writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x2A); //?? 00309 writereg(RF22_REG_58,0x80); 00310 writereg(RF22_REG_69_AGC_OVERRIDE1,0x60); 00311 writereg(RF22_REG_6E_TX_DATA_RATE1,0x09); 00312 writereg(RF22_REG_6F_TX_DATA_RATE0,0xd5); 00313 writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c); 00314 writereg(RF22_REG_71_MODULATION_CONTROL2,0x21);//ook = 0x21 //fsk = 0x22 00315 writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x50); 00316 //set tx power 00317 writereg(RF22_REG_6D_TX_POWER,0x07); //20dbm 00318 writereg(RF22_REG_3E_PACKET_LENGTH,TX_DATA); //packet length 00319 } 00320 00321 Check_ACK_RECEIVED(){ 00322 00323 } 00324 void INC_BEA_LOW_POWER_COUNTER(){ 00325 LOW_POWER_COUNTER++; 00326 }
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