pradeep shekhar
/
FCTN_BEA_TX_MAIN
Beacon tx main incomplete
tx.cpp
- Committer:
- shekhar
- Date:
- 2014-12-27
- Revision:
- 0:deb91804edc5
File content as of revision 0:deb91804edc5:
#include "tx.h" SPI spi(D11, D12, D13); // mosi, miso, sclk DigitalOut cs(D10); //slave select or chip select void FCTN_BEA_TX_MAIN() { BEA_TX_MAIN_STATUS = 1; if(BEA_FEN){ if(BEA_TX_EN){ if(BEA_TX_STANDBY){ Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_STANDBY); BEA_TX_MAIN_STATUS = 0; break; } else{ if(check_POWER_LEVEL()){ //Power level is measured using SoC(State of Charge) SHORT_BEA_TX(); if(Check_ACK_RECEIVED()){ Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_SB_SI_SUCCESS); BEA_TX_MAIN_STATUS = 0; break; } else{ Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_FAILURE); BEA_TX_MAIN_STATUS = 0; break; } } else{ INC_BEA_LOW_POWER_COUNTER(); if(LOW_POWER_COUNTER=3){ SHORT_BEA_TX(); if(Check_ACK_RECEIVED()){ Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_SB_LI_SUCCESS); BEA_TX_MAIN_STATUS = 0; break; } else{ Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_FAILURE); BEA_TX_MAIN_STATUS = 0; break; } } else{ BEA_TX_MAIN_STATUS = 0; break; } } } } else { Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_DISABLED); BEA_TX_MAIN_STATUS = 0; break; } } else { Set_BEA_TX_MAIN_STATE_STATUS(BEA_RF_SILENCE); BEA_TX_MAIN_STATUS = 0; break; } } void Set_BEA_TX_MAIN_STATE_STATUS(uint8_t STATUS){ BEA_TX_MAIN_STATE_STATUS = STATUS; } check_POWER_LEVEL(){ } void SHORT_BEA_TX() { /* init(); //init complete pc.printf("init complete.....press t to send\n"); while(pc.getc()=='t') { */ //button.rise(&interrupt_func); //interrupt enabled ( rising edge of pin 9) wait(0.02); // pl. update this value or even avoid it!!! int i=0; //extract values from short_beacon[] uint8_t byte_counter = 0; struct Short_beacon{ uint8_t Voltage[1]; uint8_t AngularSpeed[2]; uint8_t SubsystemStatus[1]; uint8_t Temp[3]; uint8_t ErrorFlag[1]; }Shortbeacon = { {0x88}, {0x99, 0xAA} , {0xAA},{0xAA,0xDD,0xEE}, {0x00} }; //filling hk data //uint8_t short_beacon[] = { 0xAB, 0x8A, 0xE2, 0xBB, 0xB8, 0xA2, 0x8E,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]}; uint8_t short_beacon[] = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]}; //mask /*uint8_t data[] = "Hello World!"; pc.printf("%d %d %d %d %d %d %d %d %d %d %d %d",data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7],data[8],data[9],data[10],data[11],data[12]);*/ //setModeIdle(); writereg(RF22_REG_07_OPERATING_MODE1,0x01); //ready mode clearTxBuf(); //writing data first time cs = 0; spi.write(0xFF); for(i=7; i>0;i--) { pc.printf("i=%d \n",i); if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) { i--; if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) { spi.write(0x00); //pc.printf("0x00\n"); } else { spi.write(0x0F); //pc.printf("0x0F\n"); } } else { i--; if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) { spi.write(0xF0); //pc.printf("0xF0\n"); } else { spi.write(0xFF); //pc.printf("0xFF\n"); } } } cs = 1; byte_counter++; //Check for fifoThresh while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20) pc.printf("fifothresh1?\n"); //Set to Tx mode writereg(RF22_REG_07_OPERATING_MODE1,0x09); while(byte_counter!=15){ pc.printf("%d\n",byte_counter); cs = 0; spi.write(0xFF); for(i=7; i>0;i--) { pc.printf("i=%d \n",i); if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) { i--; if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) { spi.write(0x00); //pc.printf("0x00\n"); } else { spi.write(0x0F); //pc.printf("0x0F\n"); } } else { i--; if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i)) { spi.write(0xF0); //pc.printf("0xF0\n"); } else { spi.write(0xFF); //pc.printf("0xFF\n"); } } } cs = 1; byte_counter++; wait(0.01); //Check for fifoThresh while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20) pc.printf("fifothresh2?\n"); } //rf22.waitPacketSent(); while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) != 0x04)pc.printf(" chck pkt sent!\n"); pc.printf(" packet sent "); } } void writereg(uint8_t reg,uint8_t val) { cs = 0;__disable_irq();spi.write(reg | 0x80);spi.write(val);__enable_irq();cs = 1; } uint8_t readreg(uint8_t reg) { int val;cs = 0;__disable_irq();spi.write(reg & ~0x80);val = spi.write(0);__enable_irq();cs = 1;return val; } void clearTxBuf() { writereg(RF22_REG_08_OPERATING_MODE2,0x01); writereg(RF22_REG_08_OPERATING_MODE2,0x00); } void clearRxBuf() { writereg(RF22_REG_08_OPERATING_MODE2,0x02); writereg(RF22_REG_08_OPERATING_MODE2,0x00); } int setFrequency(float centre,float afcPullInRange) { //freq setting begins uint8_t fbsel = 0x40; uint8_t afclimiter; if (centre >= 480.0) { centre /= 2; fbsel |= 0x20; afclimiter = afcPullInRange * 1000000.0 / 1250.0; } else { if (afcPullInRange < 0.0 || afcPullInRange > 0.159375) return false; afclimiter = afcPullInRange * 1000000.0 / 625.0; } centre /= 10.0; float integerPart = floor(centre); float fractionalPart = centre - integerPart; uint8_t fb = (uint8_t)integerPart - 24; // Range 0 to 23 fbsel |= fb; uint16_t fc = fractionalPart * 64000; writereg(RF22_REG_73_FREQUENCY_OFFSET1, 0); // REVISIT writereg(RF22_REG_74_FREQUENCY_OFFSET2, 0); writereg(RF22_REG_75_FREQUENCY_BAND_SELECT, fbsel); writereg(RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1, fc >> 8); writereg(RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0, fc & 0xff); writereg(RF22_REG_2A_AFC_LIMITER, afclimiter); return 0; } void Init_BEACON_HW() { cs=1; // chip must be deselected wait(1); //change the time later spi.format(8,0); spi.frequency(10000000); //10MHz SCLK if (readreg(RF22_REG_00_DEVICE_TYPE) == 0x08) pc.printf("spi connection valid\n"); else pc.printf("error in spi connection\n"); //reset() writereg(RF22_REG_07_OPERATING_MODE1,0x80); //sw_reset wait(1); //takes time to reset clearTxBuf(); clearRxBuf(); //txfifoalmostempty writereg(RF22_REG_7D_TX_FIFO_CONTROL2,10); //rxfifoalmostfull writereg(RF22_REG_7E_RX_FIFO_CONTROL,20); //Packet-engine registers writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x8E); //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM //&0x77 = diasable packet rx-tx handling writereg(RF22_REG_32_HEADER_CONTROL1,0x88); //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3 writereg(RF22_REG_33_HEADER_CONTROL2,0x42); //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2 writereg(RF22_REG_34_PREAMBLE_LENGTH,8); //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8; writereg(RF22_REG_36_SYNC_WORD3,0x2D); //syncword3=2D writereg(RF22_REG_37_SYNC_WORD2,0xD4); //syncword2=D4 writereg(RF22_REG_3F_CHECK_HEADER3,0); //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab); //header_to writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc); //header_from writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd); //header_ids writereg(RF22_REG_3D_TRANSMIT_HEADER0,0xde); //header_flags writereg(RF22_REG_3F_CHECK_HEADER3,0xab); writereg(RF22_REG_40_CHECK_HEADER2,0xbc); writereg(RF22_REG_41_CHECK_HEADER1,0xcd); writereg(RF22_REG_42_CHECK_HEADER0,0xde); //RSSI threshold for clear channel indicator writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5); //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state ?? writereg(RF22_REG_0C_GPIO_CONFIGURATION1,0x12); // RX state ?? //interrupts // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR); // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL); setFrequency(435.0, 0.05); //return !(statusRead() & RF22_FREQERR); if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00) pc.printf("frequency not set properly\n"); //frequency set //setModemConfig(FSK_Rb2_4Fd36); FSK_Rb2_4Fd36, ///< FSK, No Manchester, Rb = 2.4kbs, Fd = 36kHz //setmodemregisters //0x1b, 0x03, 0x41, 0x60, 0x27, 0x52, 0x00, 0x07, 0x40, 0x0a, 0x1e, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x22, 0x3a = FSK_RB2_4FD36 //0xc8, 0x03, 0x39, 0x20, 0x68, 0xdc, 0x00, 0x6b, 0x2a, 0x08, 0x2a, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x21, 0x08 = OOK,2.4, 335 writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0xdf); writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03); writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x39); writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0x20); writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x68); //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0xdc); writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00); writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x6B); writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2C); writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x11); //not required for fsk (OOK counter value) writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x2A); //?? writereg(RF22_REG_58,0x80); writereg(RF22_REG_69_AGC_OVERRIDE1,0x60); writereg(RF22_REG_6E_TX_DATA_RATE1,0x09); writereg(RF22_REG_6F_TX_DATA_RATE0,0xd5); writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c); writereg(RF22_REG_71_MODULATION_CONTROL2,0x21);//ook = 0x21 //fsk = 0x22 writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x50); //set tx power writereg(RF22_REG_6D_TX_POWER,0x07); //20dbm writereg(RF22_REG_3E_PACKET_LENGTH,TX_DATA); //packet length } Check_ACK_RECEIVED(){ } void INC_BEA_LOW_POWER_COUNTER(){ LOW_POWER_COUNTER++; }