pradeep shekhar / Mbed 2 deprecated FCTN_BEA_TX_MAIN

Beacon tx main incomplete

Dependencies:   mbed

tx.cpp@0:deb91804edc5, 2014-12-27 (annotated)

Committer:
shekhar
Date:
Sat Dec 27 10:56:14 2014 +0000
Revision:
0:deb91804edc5
Beacon tx main incomplete;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shekhar 0:deb91804edc5 1 #include "tx.h"
shekhar 0:deb91804edc5 2
shekhar 0:deb91804edc5 3 SPI spi(D11, D12, D13); // mosi, miso, sclk
shekhar 0:deb91804edc5 4 DigitalOut cs(D10); //slave select or chip select
shekhar 0:deb91804edc5 5
shekhar 0:deb91804edc5 6 void FCTN_BEA_TX_MAIN()
shekhar 0:deb91804edc5 7 {
shekhar 0:deb91804edc5 8 BEA_TX_MAIN_STATUS = 1;
shekhar 0:deb91804edc5 9 if(BEA_FEN){
shekhar 0:deb91804edc5 10 if(BEA_TX_EN){
shekhar 0:deb91804edc5 11 if(BEA_TX_STANDBY){
shekhar 0:deb91804edc5 12 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_STANDBY);
shekhar 0:deb91804edc5 13 BEA_TX_MAIN_STATUS = 0;
shekhar 0:deb91804edc5 14 break;
shekhar 0:deb91804edc5 15 }
shekhar 0:deb91804edc5 16 else{
shekhar 0:deb91804edc5 17 if(check_POWER_LEVEL()){ //Power level is measured using SoC(State of Charge)
shekhar 0:deb91804edc5 18 SHORT_BEA_TX();
shekhar 0:deb91804edc5 19 if(Check_ACK_RECEIVED()){
shekhar 0:deb91804edc5 20 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_SB_SI_SUCCESS);
shekhar 0:deb91804edc5 21 BEA_TX_MAIN_STATUS = 0;
shekhar 0:deb91804edc5 22 break;
shekhar 0:deb91804edc5 23 }
shekhar 0:deb91804edc5 24 else{
shekhar 0:deb91804edc5 25 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_FAILURE);
shekhar 0:deb91804edc5 26 BEA_TX_MAIN_STATUS = 0;
shekhar 0:deb91804edc5 27 break;
shekhar 0:deb91804edc5 28 }
shekhar 0:deb91804edc5 29 }
shekhar 0:deb91804edc5 30 else{
shekhar 0:deb91804edc5 31 INC_BEA_LOW_POWER_COUNTER();
shekhar 0:deb91804edc5 32 if(LOW_POWER_COUNTER=3){
shekhar 0:deb91804edc5 33 SHORT_BEA_TX();
shekhar 0:deb91804edc5 34 if(Check_ACK_RECEIVED()){
shekhar 0:deb91804edc5 35 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_SB_LI_SUCCESS);
shekhar 0:deb91804edc5 36 BEA_TX_MAIN_STATUS = 0;
shekhar 0:deb91804edc5 37 break;
shekhar 0:deb91804edc5 38 }
shekhar 0:deb91804edc5 39 else{
shekhar 0:deb91804edc5 40 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_FAILURE);
shekhar 0:deb91804edc5 41 BEA_TX_MAIN_STATUS = 0;
shekhar 0:deb91804edc5 42 break;
shekhar 0:deb91804edc5 43 }
shekhar 0:deb91804edc5 44 }
shekhar 0:deb91804edc5 45 else{
shekhar 0:deb91804edc5 46 BEA_TX_MAIN_STATUS = 0;
shekhar 0:deb91804edc5 47 break;
shekhar 0:deb91804edc5 48 }
shekhar 0:deb91804edc5 49 }
shekhar 0:deb91804edc5 50 }
shekhar 0:deb91804edc5 51 }
shekhar 0:deb91804edc5 52 else {
shekhar 0:deb91804edc5 53 Set_BEA_TX_MAIN_STATE_STATUS(BEA_TX_DISABLED);
shekhar 0:deb91804edc5 54 BEA_TX_MAIN_STATUS = 0;
shekhar 0:deb91804edc5 55 break;
shekhar 0:deb91804edc5 56 }
shekhar 0:deb91804edc5 57 }
shekhar 0:deb91804edc5 58 else {
shekhar 0:deb91804edc5 59 Set_BEA_TX_MAIN_STATE_STATUS(BEA_RF_SILENCE);
shekhar 0:deb91804edc5 60 BEA_TX_MAIN_STATUS = 0;
shekhar 0:deb91804edc5 61 break;
shekhar 0:deb91804edc5 62 }
shekhar 0:deb91804edc5 63
shekhar 0:deb91804edc5 64 }
shekhar 0:deb91804edc5 65
shekhar 0:deb91804edc5 66 void Set_BEA_TX_MAIN_STATE_STATUS(uint8_t STATUS){
shekhar 0:deb91804edc5 67 BEA_TX_MAIN_STATE_STATUS = STATUS;
shekhar 0:deb91804edc5 68 }
shekhar 0:deb91804edc5 69 check_POWER_LEVEL(){
shekhar 0:deb91804edc5 70
shekhar 0:deb91804edc5 71 }
shekhar 0:deb91804edc5 72 void SHORT_BEA_TX()
shekhar 0:deb91804edc5 73 {
shekhar 0:deb91804edc5 74 /*
shekhar 0:deb91804edc5 75 init();
shekhar 0:deb91804edc5 76 //init complete
shekhar 0:deb91804edc5 77 pc.printf("init complete.....press t to send\n");
shekhar 0:deb91804edc5 78 while(pc.getc()=='t')
shekhar 0:deb91804edc5 79 { */
shekhar 0:deb91804edc5 80 //button.rise(&interrupt_func); //interrupt enabled ( rising edge of pin 9)
shekhar 0:deb91804edc5 81 wait(0.02); // pl. update this value or even avoid it!!!
shekhar 0:deb91804edc5 82 int i=0;
shekhar 0:deb91804edc5 83 //extract values from short_beacon[]
shekhar 0:deb91804edc5 84 uint8_t byte_counter = 0;
shekhar 0:deb91804edc5 85 struct Short_beacon{
shekhar 0:deb91804edc5 86 uint8_t Voltage[1];
shekhar 0:deb91804edc5 87 uint8_t AngularSpeed[2];
shekhar 0:deb91804edc5 88 uint8_t SubsystemStatus[1];
shekhar 0:deb91804edc5 89 uint8_t Temp[3];
shekhar 0:deb91804edc5 90 uint8_t ErrorFlag[1];
shekhar 0:deb91804edc5 91 }Shortbeacon = { {0x88}, {0x99, 0xAA} , {0xAA},{0xAA,0xDD,0xEE}, {0x00} };
shekhar 0:deb91804edc5 92
shekhar 0:deb91804edc5 93 //filling hk data
shekhar 0:deb91804edc5 94 //uint8_t short_beacon[] = { 0xAB, 0x8A, 0xE2, 0xBB, 0xB8, 0xA2, 0x8E,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]};
shekhar 0:deb91804edc5 95 uint8_t short_beacon[] = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]};
shekhar 0:deb91804edc5 96 //mask
shekhar 0:deb91804edc5 97 /*uint8_t data[] = "Hello World!";
shekhar 0:deb91804edc5 98 pc.printf("%d %d %d %d %d %d %d %d %d %d %d %d",data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7],data[8],data[9],data[10],data[11],data[12]);*/
shekhar 0:deb91804edc5 99
shekhar 0:deb91804edc5 100 //setModeIdle();
shekhar 0:deb91804edc5 101 writereg(RF22_REG_07_OPERATING_MODE1,0x01); //ready mode
shekhar 0:deb91804edc5 102 clearTxBuf();
shekhar 0:deb91804edc5 103 //writing data first time
shekhar 0:deb91804edc5 104 cs = 0;
shekhar 0:deb91804edc5 105 spi.write(0xFF);
shekhar 0:deb91804edc5 106 for(i=7; i>0;i--)
shekhar 0:deb91804edc5 107 {
shekhar 0:deb91804edc5 108 pc.printf("i=%d \n",i);
shekhar 0:deb91804edc5 109 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i))
shekhar 0:deb91804edc5 110 {
shekhar 0:deb91804edc5 111 i--;
shekhar 0:deb91804edc5 112 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i))
shekhar 0:deb91804edc5 113 {
shekhar 0:deb91804edc5 114 spi.write(0x00);
shekhar 0:deb91804edc5 115 //pc.printf("0x00\n");
shekhar 0:deb91804edc5 116 }
shekhar 0:deb91804edc5 117 else
shekhar 0:deb91804edc5 118 {
shekhar 0:deb91804edc5 119 spi.write(0x0F);
shekhar 0:deb91804edc5 120 //pc.printf("0x0F\n");
shekhar 0:deb91804edc5 121 }
shekhar 0:deb91804edc5 122 }
shekhar 0:deb91804edc5 123 else
shekhar 0:deb91804edc5 124 {
shekhar 0:deb91804edc5 125 i--;
shekhar 0:deb91804edc5 126 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i))
shekhar 0:deb91804edc5 127 {
shekhar 0:deb91804edc5 128 spi.write(0xF0);
shekhar 0:deb91804edc5 129 //pc.printf("0xF0\n");
shekhar 0:deb91804edc5 130 }
shekhar 0:deb91804edc5 131 else
shekhar 0:deb91804edc5 132 {
shekhar 0:deb91804edc5 133 spi.write(0xFF);
shekhar 0:deb91804edc5 134 //pc.printf("0xFF\n");
shekhar 0:deb91804edc5 135 }
shekhar 0:deb91804edc5 136 }
shekhar 0:deb91804edc5 137 }
shekhar 0:deb91804edc5 138 cs = 1;
shekhar 0:deb91804edc5 139 byte_counter++;
shekhar 0:deb91804edc5 140 //Check for fifoThresh
shekhar 0:deb91804edc5 141 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20) pc.printf("fifothresh1?\n");
shekhar 0:deb91804edc5 142
shekhar 0:deb91804edc5 143 //Set to Tx mode
shekhar 0:deb91804edc5 144 writereg(RF22_REG_07_OPERATING_MODE1,0x09);
shekhar 0:deb91804edc5 145
shekhar 0:deb91804edc5 146 while(byte_counter!=15){
shekhar 0:deb91804edc5 147 pc.printf("%d\n",byte_counter);
shekhar 0:deb91804edc5 148 cs = 0;
shekhar 0:deb91804edc5 149 spi.write(0xFF);
shekhar 0:deb91804edc5 150 for(i=7; i>0;i--)
shekhar 0:deb91804edc5 151 {
shekhar 0:deb91804edc5 152 pc.printf("i=%d \n",i);
shekhar 0:deb91804edc5 153 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i))
shekhar 0:deb91804edc5 154 {
shekhar 0:deb91804edc5 155 i--;
shekhar 0:deb91804edc5 156 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i))
shekhar 0:deb91804edc5 157 {
shekhar 0:deb91804edc5 158 spi.write(0x00);
shekhar 0:deb91804edc5 159 //pc.printf("0x00\n");
shekhar 0:deb91804edc5 160 }
shekhar 0:deb91804edc5 161 else
shekhar 0:deb91804edc5 162 {
shekhar 0:deb91804edc5 163 spi.write(0x0F);
shekhar 0:deb91804edc5 164 //pc.printf("0x0F\n");
shekhar 0:deb91804edc5 165 }
shekhar 0:deb91804edc5 166 }
shekhar 0:deb91804edc5 167 else
shekhar 0:deb91804edc5 168 {
shekhar 0:deb91804edc5 169 i--;
shekhar 0:deb91804edc5 170 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!= pow(2.0,i))
shekhar 0:deb91804edc5 171 {
shekhar 0:deb91804edc5 172 spi.write(0xF0);
shekhar 0:deb91804edc5 173 //pc.printf("0xF0\n");
shekhar 0:deb91804edc5 174 }
shekhar 0:deb91804edc5 175 else
shekhar 0:deb91804edc5 176 {
shekhar 0:deb91804edc5 177 spi.write(0xFF);
shekhar 0:deb91804edc5 178 //pc.printf("0xFF\n");
shekhar 0:deb91804edc5 179 }
shekhar 0:deb91804edc5 180 }
shekhar 0:deb91804edc5 181 }
shekhar 0:deb91804edc5 182 cs = 1;
shekhar 0:deb91804edc5 183 byte_counter++;
shekhar 0:deb91804edc5 184 wait(0.01);
shekhar 0:deb91804edc5 185 //Check for fifoThresh
shekhar 0:deb91804edc5 186 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20) pc.printf("fifothresh2?\n");
shekhar 0:deb91804edc5 187 }
shekhar 0:deb91804edc5 188 //rf22.waitPacketSent();
shekhar 0:deb91804edc5 189 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) != 0x04)pc.printf(" chck pkt sent!\n");
shekhar 0:deb91804edc5 190 pc.printf(" packet sent ");
shekhar 0:deb91804edc5 191 }
shekhar 0:deb91804edc5 192 }
shekhar 0:deb91804edc5 193 void writereg(uint8_t reg,uint8_t val)
shekhar 0:deb91804edc5 194 {
shekhar 0:deb91804edc5 195 cs = 0;__disable_irq();spi.write(reg | 0x80);spi.write(val);__enable_irq();cs = 1;
shekhar 0:deb91804edc5 196 }
shekhar 0:deb91804edc5 197 uint8_t readreg(uint8_t reg)
shekhar 0:deb91804edc5 198 {
shekhar 0:deb91804edc5 199 int val;cs = 0;__disable_irq();spi.write(reg & ~0x80);val = spi.write(0);__enable_irq();cs = 1;return val;
shekhar 0:deb91804edc5 200 }
shekhar 0:deb91804edc5 201 void clearTxBuf()
shekhar 0:deb91804edc5 202 {
shekhar 0:deb91804edc5 203 writereg(RF22_REG_08_OPERATING_MODE2,0x01);
shekhar 0:deb91804edc5 204 writereg(RF22_REG_08_OPERATING_MODE2,0x00);
shekhar 0:deb91804edc5 205 }
shekhar 0:deb91804edc5 206 void clearRxBuf()
shekhar 0:deb91804edc5 207 {
shekhar 0:deb91804edc5 208 writereg(RF22_REG_08_OPERATING_MODE2,0x02);
shekhar 0:deb91804edc5 209 writereg(RF22_REG_08_OPERATING_MODE2,0x00);
shekhar 0:deb91804edc5 210 }
shekhar 0:deb91804edc5 211 int setFrequency(float centre,float afcPullInRange)
shekhar 0:deb91804edc5 212 {
shekhar 0:deb91804edc5 213 //freq setting begins
shekhar 0:deb91804edc5 214 uint8_t fbsel = 0x40;
shekhar 0:deb91804edc5 215 uint8_t afclimiter;
shekhar 0:deb91804edc5 216 if (centre >= 480.0) {
shekhar 0:deb91804edc5 217 centre /= 2;
shekhar 0:deb91804edc5 218 fbsel |= 0x20;
shekhar 0:deb91804edc5 219 afclimiter = afcPullInRange * 1000000.0 / 1250.0;
shekhar 0:deb91804edc5 220 } else {
shekhar 0:deb91804edc5 221 if (afcPullInRange < 0.0 || afcPullInRange > 0.159375)
shekhar 0:deb91804edc5 222 return false;
shekhar 0:deb91804edc5 223 afclimiter = afcPullInRange * 1000000.0 / 625.0;
shekhar 0:deb91804edc5 224 }
shekhar 0:deb91804edc5 225 centre /= 10.0;
shekhar 0:deb91804edc5 226 float integerPart = floor(centre);
shekhar 0:deb91804edc5 227 float fractionalPart = centre - integerPart;
shekhar 0:deb91804edc5 228
shekhar 0:deb91804edc5 229 uint8_t fb = (uint8_t)integerPart - 24; // Range 0 to 23
shekhar 0:deb91804edc5 230 fbsel |= fb;
shekhar 0:deb91804edc5 231 uint16_t fc = fractionalPart * 64000;
shekhar 0:deb91804edc5 232 writereg(RF22_REG_73_FREQUENCY_OFFSET1, 0); // REVISIT
shekhar 0:deb91804edc5 233 writereg(RF22_REG_74_FREQUENCY_OFFSET2, 0);
shekhar 0:deb91804edc5 234 writereg(RF22_REG_75_FREQUENCY_BAND_SELECT, fbsel);
shekhar 0:deb91804edc5 235 writereg(RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1, fc >> 8);
shekhar 0:deb91804edc5 236 writereg(RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0, fc & 0xff);
shekhar 0:deb91804edc5 237 writereg(RF22_REG_2A_AFC_LIMITER, afclimiter);
shekhar 0:deb91804edc5 238 return 0;
shekhar 0:deb91804edc5 239 }
shekhar 0:deb91804edc5 240
shekhar 0:deb91804edc5 241 void Init_BEACON_HW()
shekhar 0:deb91804edc5 242 {
shekhar 0:deb91804edc5 243 cs=1; // chip must be deselected
shekhar 0:deb91804edc5 244 wait(1); //change the time later
shekhar 0:deb91804edc5 245 spi.format(8,0);
shekhar 0:deb91804edc5 246 spi.frequency(10000000); //10MHz SCLK
shekhar 0:deb91804edc5 247 if (readreg(RF22_REG_00_DEVICE_TYPE) == 0x08) pc.printf("spi connection valid\n");
shekhar 0:deb91804edc5 248 else pc.printf("error in spi connection\n");
shekhar 0:deb91804edc5 249 //reset()
shekhar 0:deb91804edc5 250 writereg(RF22_REG_07_OPERATING_MODE1,0x80); //sw_reset
shekhar 0:deb91804edc5 251 wait(1); //takes time to reset
shekhar 0:deb91804edc5 252
shekhar 0:deb91804edc5 253 clearTxBuf();
shekhar 0:deb91804edc5 254 clearRxBuf();
shekhar 0:deb91804edc5 255 //txfifoalmostempty
shekhar 0:deb91804edc5 256 writereg(RF22_REG_7D_TX_FIFO_CONTROL2,10);
shekhar 0:deb91804edc5 257 //rxfifoalmostfull
shekhar 0:deb91804edc5 258 writereg(RF22_REG_7E_RX_FIFO_CONTROL,20);
shekhar 0:deb91804edc5 259 //Packet-engine registers
shekhar 0:deb91804edc5 260 writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x8E); //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM
shekhar 0:deb91804edc5 261 //&0x77 = diasable packet rx-tx handling
shekhar 0:deb91804edc5 262 writereg(RF22_REG_32_HEADER_CONTROL1,0x88); //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3
shekhar 0:deb91804edc5 263 writereg(RF22_REG_33_HEADER_CONTROL2,0x42); //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2
shekhar 0:deb91804edc5 264 writereg(RF22_REG_34_PREAMBLE_LENGTH,8); //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8;
shekhar 0:deb91804edc5 265 writereg(RF22_REG_36_SYNC_WORD3,0x2D); //syncword3=2D
shekhar 0:deb91804edc5 266 writereg(RF22_REG_37_SYNC_WORD2,0xD4); //syncword2=D4
shekhar 0:deb91804edc5 267 writereg(RF22_REG_3F_CHECK_HEADER3,0); //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS
shekhar 0:deb91804edc5 268 writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab); //header_to
shekhar 0:deb91804edc5 269 writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc); //header_from
shekhar 0:deb91804edc5 270 writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd); //header_ids
shekhar 0:deb91804edc5 271 writereg(RF22_REG_3D_TRANSMIT_HEADER0,0xde); //header_flags
shekhar 0:deb91804edc5 272 writereg(RF22_REG_3F_CHECK_HEADER3,0xab);
shekhar 0:deb91804edc5 273 writereg(RF22_REG_40_CHECK_HEADER2,0xbc);
shekhar 0:deb91804edc5 274 writereg(RF22_REG_41_CHECK_HEADER1,0xcd);
shekhar 0:deb91804edc5 275 writereg(RF22_REG_42_CHECK_HEADER0,0xde);
shekhar 0:deb91804edc5 276
shekhar 0:deb91804edc5 277 //RSSI threshold for clear channel indicator
shekhar 0:deb91804edc5 278 writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5); //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm
shekhar 0:deb91804edc5 279
shekhar 0:deb91804edc5 280 writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state ??
shekhar 0:deb91804edc5 281 writereg(RF22_REG_0C_GPIO_CONFIGURATION1,0x12); // RX state ??
shekhar 0:deb91804edc5 282
shekhar 0:deb91804edc5 283 //interrupts
shekhar 0:deb91804edc5 284 // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR);
shekhar 0:deb91804edc5 285 // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL);
shekhar 0:deb91804edc5 286
shekhar 0:deb91804edc5 287 setFrequency(435.0, 0.05);
shekhar 0:deb91804edc5 288
shekhar 0:deb91804edc5 289 //return !(statusRead() & RF22_FREQERR);
shekhar 0:deb91804edc5 290 if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00)
shekhar 0:deb91804edc5 291 pc.printf("frequency not set properly\n");
shekhar 0:deb91804edc5 292 //frequency set
shekhar 0:deb91804edc5 293
shekhar 0:deb91804edc5 294 //setModemConfig(FSK_Rb2_4Fd36); FSK_Rb2_4Fd36, ///< FSK, No Manchester, Rb = 2.4kbs, Fd = 36kHz
shekhar 0:deb91804edc5 295 //setmodemregisters
shekhar 0:deb91804edc5 296 //0x1b, 0x03, 0x41, 0x60, 0x27, 0x52, 0x00, 0x07, 0x40, 0x0a, 0x1e, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x22, 0x3a = FSK_RB2_4FD36
shekhar 0:deb91804edc5 297 //0xc8, 0x03, 0x39, 0x20, 0x68, 0xdc, 0x00, 0x6b, 0x2a, 0x08, 0x2a, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x21, 0x08 = OOK,2.4, 335
shekhar 0:deb91804edc5 298 writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0xdf);
shekhar 0:deb91804edc5 299 writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03);
shekhar 0:deb91804edc5 300 writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x39);
shekhar 0:deb91804edc5 301 writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0x20);
shekhar 0:deb91804edc5 302 writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x68); //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk
shekhar 0:deb91804edc5 303 writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0xdc);
shekhar 0:deb91804edc5 304 writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00);
shekhar 0:deb91804edc5 305 writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x6B);
shekhar 0:deb91804edc5 306 writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2C);
shekhar 0:deb91804edc5 307 writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x11); //not required for fsk (OOK counter value)
shekhar 0:deb91804edc5 308 writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x2A); //??
shekhar 0:deb91804edc5 309 writereg(RF22_REG_58,0x80);
shekhar 0:deb91804edc5 310 writereg(RF22_REG_69_AGC_OVERRIDE1,0x60);
shekhar 0:deb91804edc5 311 writereg(RF22_REG_6E_TX_DATA_RATE1,0x09);
shekhar 0:deb91804edc5 312 writereg(RF22_REG_6F_TX_DATA_RATE0,0xd5);
shekhar 0:deb91804edc5 313 writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c);
shekhar 0:deb91804edc5 314 writereg(RF22_REG_71_MODULATION_CONTROL2,0x21);//ook = 0x21 //fsk = 0x22
shekhar 0:deb91804edc5 315 writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x50);
shekhar 0:deb91804edc5 316 //set tx power
shekhar 0:deb91804edc5 317 writereg(RF22_REG_6D_TX_POWER,0x07); //20dbm
shekhar 0:deb91804edc5 318 writereg(RF22_REG_3E_PACKET_LENGTH,TX_DATA); //packet length
shekhar 0:deb91804edc5 319 }
shekhar 0:deb91804edc5 320
shekhar 0:deb91804edc5 321 Check_ACK_RECEIVED(){
shekhar 0:deb91804edc5 322
shekhar 0:deb91804edc5 323 }
shekhar 0:deb91804edc5 324 void INC_BEA_LOW_POWER_COUNTER(){
shekhar 0:deb91804edc5 325 LOW_POWER_COUNTER++;
shekhar 0:deb91804edc5 326 }