Diff: main.cpp

Revision:

1:91c435a6966b

Parent:

0:15b2487c185c

Child:

2:298924eb2b41

--- a/main.cpp	Sat Aug 15 11:47:12 2015 +0000
+++ b/main.cpp	Sat Aug 15 13:00:15 2015 +0000
@@ -67,12 +67,25 @@
     //Packet-engine registers
     writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x8E);    //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM
     //&0x77 = diasable packet rx-tx handling
-    writereg(RF22_REG_32_HEADER_CONTROL1,0x88);    //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3
+    //how does it works?? what values to be used
+    
+    
+    writereg(RF22_REG_32_HEADER_CONTROL1,0x88);    //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3  //not reqiured for tx
     writereg(RF22_REG_33_HEADER_CONTROL2,0x42);    //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2
+    //why 0x42
     writereg(RF22_REG_34_PREAMBLE_LENGTH,8);       //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8;
+    //why is preamble used??
+    
     writereg(RF22_REG_36_SYNC_WORD3,0x2D);    //syncword3=2D
+    //why??
+    
     writereg(RF22_REG_37_SYNC_WORD2,0xD4);    //syncword2=D4
+    //why??
+    
     writereg(RF22_REG_3F_CHECK_HEADER3,0);    //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS
+    
+    
+    //why all these headers
     writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab);    //header_to
     writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc);    //header_from 
     writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd);    //header_ids
@@ -82,7 +95,7 @@
     writereg(RF22_REG_41_CHECK_HEADER1,0xcd);   
     writereg(RF22_REG_42_CHECK_HEADER0,0xde);
     
-    //RSSI threshold for clear channel indicator
+    //RSSI threshold for clear channel indicator //rx
     writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5);         //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm
     
     writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state                        ??
@@ -92,7 +105,7 @@
     // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR);
     // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL);
     
-    setFrequency(435.0, 0.05);
+    setFrequency(435.0, 0.05);//check
     
     //return !(statusRead() & RF22_FREQERR);
     if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00)
@@ -116,15 +129,26 @@
     writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x2A);         //??
     writereg(RF22_REG_58,0x80);
     writereg(RF22_REG_69_AGC_OVERRIDE1,0x60);
+    
+    //check...
     writereg(RF22_REG_6E_TX_DATA_RATE1,0x09);//TX at 0.123kbps=:6E=0x01; 6F=0x02 
     writereg(RF22_REG_6F_TX_DATA_RATE0,0xd5);//TX at 1.2kbps: 6E=0x09; 6F=0xd5
+    
+    
     writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c);
     writereg(RF22_REG_71_MODULATION_CONTROL2,0x21);//ook = 0x21 //fsk = 0x22
+    
     writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x50);
+    //required for OOK???
+    
     //set tx power
     writereg(RF22_REG_6D_TX_POWER,0x06);    //20dbm
+    //why 0x06?? 0x07 is for max
+    
     //writereg(RF22_REG_6D_TX_POWER,0x00);    //-1dbm
-    writereg(RF22_REG_3E_PACKET_LENGTH,TX_DATA); //packet length     
+    writereg(RF22_REG_3E_PACKET_LENGTH,TX_DATA); //packet length
+    //packet length not required
+         
 }
 int main()
 {