shao ziyang / mbed-dev

mbed library sources. Supersedes mbed-src. Add PORTG support for STM32L476JG (SensorTile kit)

Dependents:   SensorTileTest

Fork of mbed-dev by mbed official

targets/TARGET_Freescale/TARGET_K20XX/spi_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include <math.h>
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 22 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 23 #include "clk_freqs.h"
<> 144:ef7eb2e8f9f7 24 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
<> 144:ef7eb2e8f9f7 27 // determine the SPI to use
<> 144:ef7eb2e8f9f7 28 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 29 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 30 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 31 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 32 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 144:ef7eb2e8f9f7 33 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
<> 144:ef7eb2e8f9f7 36 MBED_ASSERT((int)obj->spi != NC);
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK;
<> 144:ef7eb2e8f9f7 39 SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK);
<> 144:ef7eb2e8f9f7 42 //obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK;
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 // not halt in the debug mode
<> 144:ef7eb2e8f9f7 45 obj->spi->SR |= SPI_SR_EOQF_MASK;
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 // pin out the spi pins
<> 144:ef7eb2e8f9f7 48 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 49 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 50 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 51 if (ssel != NC) {
<> 144:ef7eb2e8f9f7 52 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 53 }
<> 144:ef7eb2e8f9f7 54 }
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 void spi_free(spi_t *obj) {
<> 144:ef7eb2e8f9f7 57 // [TODO]
<> 144:ef7eb2e8f9f7 58 }
<> 144:ef7eb2e8f9f7 59 void spi_format(spi_t *obj, int bits, int mode, int slave) {
<> 144:ef7eb2e8f9f7 60 MBED_ASSERT((bits > 4) || (bits < 16));
<> 144:ef7eb2e8f9f7 61 MBED_ASSERT((mode >= 0) && (mode <= 3));
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 uint8_t polarity = (mode & 0x2) ? 1 : 0;
<> 144:ef7eb2e8f9f7 64 uint8_t phase = (mode & 0x1) ? 1 : 0;
<> 144:ef7eb2e8f9f7 65 uint8_t old_polarity = (obj->spi->CTAR[0] & SPI_CTAR_CPOL_MASK) != 0;
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 // set master/slave
<> 144:ef7eb2e8f9f7 68 if (slave) {
<> 144:ef7eb2e8f9f7 69 obj->spi->MCR &= ~SPI_MCR_MSTR_MASK;
<> 144:ef7eb2e8f9f7 70 } else {
<> 144:ef7eb2e8f9f7 71 obj->spi->MCR |= (1UL << SPI_MCR_MSTR_SHIFT);
<> 144:ef7eb2e8f9f7 72 }
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 // CTAR0 is used
<> 144:ef7eb2e8f9f7 75 obj->spi->CTAR[0] &= ~(SPI_CTAR_CPHA_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_FMSZ_MASK);
<> 144:ef7eb2e8f9f7 76 obj->spi->CTAR[0] |= (polarity << SPI_CTAR_CPOL_SHIFT) | (phase << SPI_CTAR_CPHA_SHIFT) | ((bits - 1) << SPI_CTAR_FMSZ_SHIFT);
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 //If clk idle state was changed, start a dummy transmission
<> 144:ef7eb2e8f9f7 79 //This is a 'feature' in DSPI: https://community.freescale.com/thread/105526
<> 144:ef7eb2e8f9f7 80 if ((old_polarity != polarity) && (slave == 0)) {
<> 144:ef7eb2e8f9f7 81 //Start transfer (CS should be high, so shouldn't matter)
<> 144:ef7eb2e8f9f7 82 spi_master_write(obj, 0xFFFF);
<> 144:ef7eb2e8f9f7 83 }
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 static const uint8_t baudrate_prescaler[] = {2,3,5,7};
<> 144:ef7eb2e8f9f7 87 static const uint16_t baudrate_scaler[] = {2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768};
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 void spi_frequency(spi_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 90 uint32_t f_error = 0;
<> 144:ef7eb2e8f9f7 91 uint32_t p_error = 0xffffffff;
<> 144:ef7eb2e8f9f7 92 uint32_t ref = 0;
<> 144:ef7eb2e8f9f7 93 uint32_t br = 0;
<> 144:ef7eb2e8f9f7 94 uint32_t ref_spr = 0;
<> 144:ef7eb2e8f9f7 95 uint32_t ref_prescaler = 0;
<> 144:ef7eb2e8f9f7 96 uint32_t ref_dr = 0;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 // bus clk
<> 144:ef7eb2e8f9f7 99 uint32_t PCLK = bus_frequency();
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 for (uint32_t i = 0; i < 4; i++) {
<> 144:ef7eb2e8f9f7 102 for (br = 0; br <= 15; br++) {
<> 144:ef7eb2e8f9f7 103 for (uint32_t dr = 0; dr < 2; dr++) {
<> 144:ef7eb2e8f9f7 104 ref = (PCLK * (1U + dr) / baudrate_prescaler[i]) / baudrate_scaler[br];
<> 144:ef7eb2e8f9f7 105 if (ref > (uint32_t)hz)
<> 144:ef7eb2e8f9f7 106 continue;
<> 144:ef7eb2e8f9f7 107 f_error = hz - ref;
<> 144:ef7eb2e8f9f7 108 if (f_error < p_error) {
<> 144:ef7eb2e8f9f7 109 ref_spr = br;
<> 144:ef7eb2e8f9f7 110 ref_prescaler = i;
<> 144:ef7eb2e8f9f7 111 ref_dr = dr;
<> 144:ef7eb2e8f9f7 112 p_error = f_error;
<> 144:ef7eb2e8f9f7 113 }
<> 144:ef7eb2e8f9f7 114 }
<> 144:ef7eb2e8f9f7 115 }
<> 144:ef7eb2e8f9f7 116 }
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 // set PBR and BR
<> 144:ef7eb2e8f9f7 119 obj->spi->CTAR[0] &= ~(SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK | SPI_CTAR_DBR_MASK);
<> 144:ef7eb2e8f9f7 120 obj->spi->CTAR[0] |= (ref_prescaler << SPI_CTAR_PBR_SHIFT) | (ref_spr << SPI_CTAR_BR_SHIFT) | (ref_dr << SPI_CTAR_DBR_SHIFT);
<> 144:ef7eb2e8f9f7 121 }
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 static inline int spi_writeable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 124 return (obj->spi->SR & SPI_SR_TFFF_MASK) ? 1 : 0;
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 static inline int spi_readable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 128 return (obj->spi->SR & SPI_SR_RFDF_MASK) ? 1 : 0;
<> 144:ef7eb2e8f9f7 129 }
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 int spi_master_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 132 //clear RX buffer flag
<> 144:ef7eb2e8f9f7 133 obj->spi->SR |= SPI_SR_RFDF_MASK;
<> 144:ef7eb2e8f9f7 134 // wait tx buffer empty
<> 144:ef7eb2e8f9f7 135 while(!spi_writeable(obj));
<> 144:ef7eb2e8f9f7 136 obj->spi->PUSHR = SPI_PUSHR_TXDATA(value & 0xffff) /*| SPI_PUSHR_EOQ_MASK*/;
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 // wait rx buffer full
<> 144:ef7eb2e8f9f7 139 while (!spi_readable(obj));
<> 144:ef7eb2e8f9f7 140 return obj->spi->POPR;
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 int spi_slave_receive(spi_t *obj) {
<> 144:ef7eb2e8f9f7 144 return spi_readable(obj);
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 int spi_slave_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 148 obj->spi->SR |= SPI_SR_RFDF_MASK;
<> 144:ef7eb2e8f9f7 149 return obj->spi->POPR;
<> 144:ef7eb2e8f9f7 150 }
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 void spi_slave_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 153 while (!spi_writeable(obj));
<> 144:ef7eb2e8f9f7 154 }