shao ziyang / mbed-dev

mbed library sources. Supersedes mbed-src. Add PORTG support for STM32L476JG (SensorTile kit)

Dependents:   SensorTileTest

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC2460/spi_api.c@154:1375a99fb16d, 2017-01-02 (annotated)

Committer:
shaoziyang
Date:
Mon Jan 02 15:52:04 2017 +0000
Revision:
154:1375a99fb16d
Parent:
149:156823d33999 
Mbed for ST SensorTile kit, fixed GPIOG bug, add PORTG support.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include <math.h>
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 20 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 21 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 22 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 static const PinMap PinMap_SPI_SCLK[] = {
<> 144:ef7eb2e8f9f7 25 {P0_7 , SPI_1, 2},
<> 144:ef7eb2e8f9f7 26 {P0_15, SPI_0, 2},
<> 144:ef7eb2e8f9f7 27 {P1_20, SPI_0, 3},
<> 144:ef7eb2e8f9f7 28 {P1_31, SPI_1, 2},
<> 144:ef7eb2e8f9f7 29 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 30 };
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 static const PinMap PinMap_SPI_MOSI[] = {
<> 144:ef7eb2e8f9f7 33 {P0_9 , SPI_1, 2},
<> 144:ef7eb2e8f9f7 34 {P0_13, SPI_1, 2},
<> 144:ef7eb2e8f9f7 35 {P0_18, SPI_0, 2},
<> 144:ef7eb2e8f9f7 36 {P1_24, SPI_0, 3},
<> 144:ef7eb2e8f9f7 37 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 38 };
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 static const PinMap PinMap_SPI_MISO[] = {
<> 144:ef7eb2e8f9f7 41 {P0_8 , SPI_1, 2},
<> 144:ef7eb2e8f9f7 42 {P0_12, SPI_1, 2},
<> 144:ef7eb2e8f9f7 43 {P0_17, SPI_0, 2},
<> 144:ef7eb2e8f9f7 44 {P1_23, SPI_0, 3},
<> 144:ef7eb2e8f9f7 45 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 46 };
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 static const PinMap PinMap_SPI_SSEL[] = {
<> 144:ef7eb2e8f9f7 49 {P0_6 , SPI_1, 2},
<> 144:ef7eb2e8f9f7 50 {P0_14, SPI_1, 3},
<> 144:ef7eb2e8f9f7 51 {P0_16, SPI_0, 2},
<> 144:ef7eb2e8f9f7 52 {P1_21, SPI_0, 3},
<> 144:ef7eb2e8f9f7 53 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 54 };
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 static inline int ssp_disable(spi_t *obj);
<> 144:ef7eb2e8f9f7 57 static inline int ssp_enable(spi_t *obj);
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
<> 144:ef7eb2e8f9f7 60 // determine the SPI to use
<> 144:ef7eb2e8f9f7 61 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 62 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 63 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 64 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 65 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 144:ef7eb2e8f9f7 66 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 144:ef7eb2e8f9f7 67 obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
<> 144:ef7eb2e8f9f7 68 MBED_ASSERT((int)obj->spi != NC);
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 // enable power and clocking
<> 144:ef7eb2e8f9f7 71 switch ((int)obj->spi) {
<> 144:ef7eb2e8f9f7 72 case SPI_0: LPC_SC->PCONP |= 1 << PCSSP0; break;
<> 144:ef7eb2e8f9f7 73 case SPI_1: LPC_SC->PCONP |= 1 << PCSSP1; break;
<> 144:ef7eb2e8f9f7 74 }
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 // set default format and frequency
<> 144:ef7eb2e8f9f7 77 if (ssel == NC) {
<> 144:ef7eb2e8f9f7 78 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
<> 144:ef7eb2e8f9f7 79 } else {
<> 144:ef7eb2e8f9f7 80 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82 spi_frequency(obj, 1000000);
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 // enable the ssp channel
<> 144:ef7eb2e8f9f7 85 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 // pin out the spi pins
<> 144:ef7eb2e8f9f7 88 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 89 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 90 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 91 if (ssel != NC) {
<> 144:ef7eb2e8f9f7 92 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94 }
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 void spi_free(spi_t *obj) {}
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 void spi_format(spi_t *obj, int bits, int mode, int slave) {
<> 144:ef7eb2e8f9f7 99 MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
<> 144:ef7eb2e8f9f7 100 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 int polarity = (mode & 0x2) ? 1 : 0;
<> 144:ef7eb2e8f9f7 103 int phase = (mode & 0x1) ? 1 : 0;
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 // set it up
<> 144:ef7eb2e8f9f7 106 int DSS = bits - 1; // DSS (data select size)
<> 144:ef7eb2e8f9f7 107 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
<> 144:ef7eb2e8f9f7 108 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 int FRF = 0; // FRF (frame format) = SPI
<> 144:ef7eb2e8f9f7 111 uint32_t tmp = obj->spi->CR0;
<> 144:ef7eb2e8f9f7 112 tmp &= ~(0xFFFF);
<> 144:ef7eb2e8f9f7 113 tmp |= DSS << 0
<> 144:ef7eb2e8f9f7 114 | FRF << 4
<> 144:ef7eb2e8f9f7 115 | SPO << 6
<> 144:ef7eb2e8f9f7 116 | SPH << 7;
<> 144:ef7eb2e8f9f7 117 obj->spi->CR0 = tmp;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 tmp = obj->spi->CR1;
<> 144:ef7eb2e8f9f7 120 tmp &= ~(0xD);
<> 144:ef7eb2e8f9f7 121 tmp |= 0 << 0 // LBM - loop back mode - off
<> 144:ef7eb2e8f9f7 122 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
<> 144:ef7eb2e8f9f7 123 | 0 << 3; // SOD - slave output disable - na
<> 144:ef7eb2e8f9f7 124 obj->spi->CR1 = tmp;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 127 }
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 void spi_frequency(spi_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 130 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 // setup the spi clock diveder to /1
<> 144:ef7eb2e8f9f7 133 switch ((int)obj->spi) {
<> 144:ef7eb2e8f9f7 134 case SPI_0:
<> 144:ef7eb2e8f9f7 135 LPC_SC->PCLKSEL1 &= ~(3 << 10);
<> 144:ef7eb2e8f9f7 136 LPC_SC->PCLKSEL1 |= (1 << 10);
<> 144:ef7eb2e8f9f7 137 break;
<> 144:ef7eb2e8f9f7 138 case SPI_1:
<> 144:ef7eb2e8f9f7 139 LPC_SC->PCLKSEL0 &= ~(3 << 20);
<> 144:ef7eb2e8f9f7 140 LPC_SC->PCLKSEL0 |= (1 << 20);
<> 144:ef7eb2e8f9f7 141 break;
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 uint32_t PCLK = SystemCoreClock;
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 int prescaler;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
<> 144:ef7eb2e8f9f7 149 int prescale_hz = PCLK / prescaler;
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 // calculate the divider
<> 144:ef7eb2e8f9f7 152 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 // check we can support the divider
<> 144:ef7eb2e8f9f7 155 if (divider < 256) {
<> 144:ef7eb2e8f9f7 156 // prescaler
<> 144:ef7eb2e8f9f7 157 obj->spi->CPSR = prescaler;
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 // divider
<> 144:ef7eb2e8f9f7 160 obj->spi->CR0 &= ~(0xFFFF << 8);
<> 144:ef7eb2e8f9f7 161 obj->spi->CR0 |= (divider - 1) << 8;
<> 144:ef7eb2e8f9f7 162 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 163 return;
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166 error("Couldn't setup requested SPI frequency");
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 static inline int ssp_disable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 170 return obj->spi->CR1 &= ~(1 << 1);
<> 144:ef7eb2e8f9f7 171 }
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 static inline int ssp_enable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 174 return obj->spi->CR1 |= (1 << 1);
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 static inline int ssp_readable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 178 return obj->spi->SR & (1 << 2);
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 static inline int ssp_writeable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 182 return obj->spi->SR & (1 << 1);
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 static inline void ssp_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 186 while (!ssp_writeable(obj));
<> 144:ef7eb2e8f9f7 187 obj->spi->DR = value;
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 static inline int ssp_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 191 while (!ssp_readable(obj));
<> 144:ef7eb2e8f9f7 192 return obj->spi->DR;
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 static inline int ssp_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 196 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 int spi_master_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 200 ssp_write(obj, value);
<> 144:ef7eb2e8f9f7 201 return ssp_read(obj);
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 int spi_slave_receive(spi_t *obj) {
<> 144:ef7eb2e8f9f7 205 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 int spi_slave_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 209 return obj->spi->DR;
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 void spi_slave_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 213 while (ssp_writeable(obj) == 0) ;
<> 144:ef7eb2e8f9f7 214 obj->spi->DR = value;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 int spi_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 218 return ssp_busy(obj);
<> 144:ef7eb2e8f9f7 219 }