Sergey Solodunov
my fork of nrf51-sdk
Fork of
nrf51-sdk
by 
Nordic Semiconductor
Diff: source/nordic_sdk/components/device/nrf51.h
- Revision:
- 27:0fe148f1bca3
- Parent:
- 24:2aea0c1c57ee
- Child:
- 28:041dac1366b2
diff -r 74a59a70d9c3 -r 0fe148f1bca3 source/nordic_sdk/components/device/nrf51.h
--- a/source/nordic_sdk/components/device/nrf51.h Thu Apr 07 17:37:50 2016 +0100
+++ b/source/nordic_sdk/components/device/nrf51.h Thu Apr 07 17:37:52 2016 +0100
@@ -28,8 +28,8 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- */
-
+ */
+
#ifndef NRF51_H
#define NRF51_H
@@ -271,6 +271,27 @@
/* ================================================================================ */
+/* ================ PU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Patch unit. (PU)
+ */
+
+typedef struct { /*!< PU Structure */
+ __I uint32_t RESERVED0[448];
+ __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
+ __I uint32_t RESERVED1[24];
+ __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
+ __I uint32_t RESERVED2[24];
+ __IO uint32_t PATCHEN; /*!< Patch enable register. */
+ __IO uint32_t PATCHENSET; /*!< Patch enable register. */
+ __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
+} NRF_PU_Type;
+
+
+/* ================================================================================ */
/* ================ AMLI ================ */
/* ================================================================================ */
@@ -323,11 +344,11 @@
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
__I uint32_t RESERVED4[61];
__I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
- __I uint32_t RESERVED5;
+ __I uint32_t CD; /*!< Carrier detect. */
__I uint32_t RXMATCH; /*!< Received address. */
__I uint32_t RXCRC; /*!< Received CRC. */
__I uint32_t DAI; /*!< Device address match index. */
- __I uint32_t RESERVED6[60];
+ __I uint32_t RESERVED5[60];
__IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
__IO uint32_t FREQUENCY; /*!< Frequency. */
__IO uint32_t TXPOWER; /*!< Output power. */
@@ -346,22 +367,22 @@
__IO uint32_t TEST; /*!< Test features enable register. */
__IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
__I uint32_t RSSISAMPLE; /*!< RSSI sample. */
- __I uint32_t RESERVED7;
+ __I uint32_t RESERVED6;
__I uint32_t STATE; /*!< Current radio state. */
__IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
- __I uint32_t RESERVED8[2];
+ __I uint32_t RESERVED7[2];
__IO uint32_t BCC; /*!< Bit counter compare. */
- __I uint32_t RESERVED9[39];
+ __I uint32_t RESERVED8[39];
__IO uint32_t DAB[8]; /*!< Device address base segment. */
__IO uint32_t DAP[8]; /*!< Device address prefix. */
__IO uint32_t DACNF; /*!< Device address match configuration. */
- __I uint32_t RESERVED10[56];
+ __I uint32_t RESERVED9[56];
__IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
__IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
__IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
__IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
__IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
- __I uint32_t RESERVED11[561];
+ __I uint32_t RESERVED10[561];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_RADIO_Type;
@@ -392,16 +413,14 @@
__IO uint32_t EVENTS_ERROR; /*!< Error detected. */
__I uint32_t RESERVED4[7];
__IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
- __I uint32_t RESERVED5[46];
- __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
- __I uint32_t RESERVED6[64];
+ __I uint32_t RESERVED5[111];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED7[93];
+ __I uint32_t RESERVED6[93];
__IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
- __I uint32_t RESERVED8[31];
+ __I uint32_t RESERVED7[31];
__IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
- __I uint32_t RESERVED9;
+ __I uint32_t RESERVED8;
__IO uint32_t PSELRTS; /*!< Pin select for RTS. */
__IO uint32_t PSELTXD; /*!< Pin select for TXD. */
__IO uint32_t PSELCTS; /*!< Pin select for CTS. */
@@ -410,11 +429,11 @@
Once read the character is consumed. If read when no character
available, the UART will stop working. */
__O uint32_t TXD; /*!< TXD register. */
- __I uint32_t RESERVED10;
+ __I uint32_t RESERVED9;
__IO uint32_t BAUDRATE; /*!< UART Baudrate. */
- __I uint32_t RESERVED11[17];
+ __I uint32_t RESERVED10[17];
__IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
- __I uint32_t RESERVED12[675];
+ __I uint32_t RESERVED11[675];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_UART_Type;
@@ -577,28 +596,32 @@
__IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
__I uint32_t RESERVED3[2];
__IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
- __I uint32_t RESERVED4[3];
+ __I uint32_t RESERVED4;
+ __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
+ __I uint32_t RESERVED5;
__IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
- __I uint32_t RESERVED5[10];
+ __I uint32_t RESERVED6[10];
__IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
- __I uint32_t RESERVED6[109];
+ __I uint32_t RESERVED7[44];
+ __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
+ __I uint32_t RESERVED8[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED7[125];
+ __I uint32_t RESERVED9[125];
__IO uint32_t ENABLE; /*!< Enable SPIM. */
- __I uint32_t RESERVED8;
+ __I uint32_t RESERVED10;
SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
- __I uint32_t RESERVED9[4];
+ __I uint32_t RESERVED11[4];
__IO uint32_t FREQUENCY; /*!< SPI frequency. */
- __I uint32_t RESERVED10[3];
+ __I uint32_t RESERVED12[3];
SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
- __I uint32_t RESERVED11;
+ __I uint32_t RESERVED13;
SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
- __I uint32_t RESERVED12;
+ __I uint32_t RESERVED14;
__IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED13[26];
+ __I uint32_t RESERVED15[26];
__IO uint32_t ORC; /*!< Over-read character. */
- __I uint32_t RESERVED14[654];
+ __I uint32_t RESERVED16[654];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_SPIM_Type;
@@ -1177,6 +1200,7 @@
#define NRF_POWER_BASE 0x40000000UL
#define NRF_CLOCK_BASE 0x40000000UL
#define NRF_MPU_BASE 0x40000000UL
+#define NRF_PU_BASE 0x40000000UL
#define NRF_AMLI_BASE 0x40000000UL
#define NRF_RADIO_BASE 0x40001000UL
#define NRF_UART0_BASE 0x40002000UL
@@ -1216,6 +1240,7 @@
#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
+#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)