Sergey Solodunov / nrf51-sdk

my fork of nrf51-sdk

Dependents:   nRF51822

Fork of nrf51-sdk by Nordic Semiconductor

source/nordic_sdk/components/device/nrf51.h@32:6335323e4327, 2016-04-07 (annotated)

Committer:
vcoubard
Date:
Thu Apr 07 17:38:06 2016 +0100
Revision:
32:6335323e4327
Parent:
31:c05fa48ed560 
Synchronized with git rev 8a57aa2d

Author: Liyou Zhou

Change README to point to sdk v10

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vcoubard 29:286940b7ee5a 1 /*
vcoubard 29:286940b7ee5a 2 * Copyright (c) Nordic Semiconductor ASA
vcoubard 29:286940b7ee5a 3 * All rights reserved.
vcoubard 29:286940b7ee5a 4 *
vcoubard 29:286940b7ee5a 5 * Redistribution and use in source and binary forms, with or without modification,
vcoubard 29:286940b7ee5a 6 * are permitted provided that the following conditions are met:
vcoubard 29:286940b7ee5a 7 *
vcoubard 29:286940b7ee5a 8 * 1. Redistributions of source code must retain the above copyright notice, this
vcoubard 29:286940b7ee5a 9 * list of conditions and the following disclaimer.
vcoubard 29:286940b7ee5a 10 *
vcoubard 29:286940b7ee5a 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
vcoubard 29:286940b7ee5a 12 * list of conditions and the following disclaimer in the documentation and/or
vcoubard 29:286940b7ee5a 13 * other materials provided with the distribution.
vcoubard 29:286940b7ee5a 14 *
vcoubard 29:286940b7ee5a 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
vcoubard 29:286940b7ee5a 16 * contributors to this software may be used to endorse or promote products
vcoubard 29:286940b7ee5a 17 * derived from this software without specific prior written permission.
vcoubard 29:286940b7ee5a 18 *
vcoubard 29:286940b7ee5a 19 *
vcoubard 29:286940b7ee5a 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vcoubard 29:286940b7ee5a 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vcoubard 29:286940b7ee5a 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vcoubard 29:286940b7ee5a 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vcoubard 29:286940b7ee5a 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vcoubard 29:286940b7ee5a 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vcoubard 29:286940b7ee5a 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vcoubard 29:286940b7ee5a 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vcoubard 29:286940b7ee5a 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vcoubard 29:286940b7ee5a 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vcoubard 29:286940b7ee5a 30 *
vcoubard 29:286940b7ee5a 31 */
vcoubard 29:286940b7ee5a 32
vcoubard 1:ebc0e0ef0a11 33 #ifndef NRF51_H
vcoubard 1:ebc0e0ef0a11 34 #define NRF51_H
vcoubard 1:ebc0e0ef0a11 35
vcoubard 1:ebc0e0ef0a11 36 #ifdef __cplusplus
vcoubard 1:ebc0e0ef0a11 37 extern "C" {
vcoubard 1:ebc0e0ef0a11 38 #endif
vcoubard 1:ebc0e0ef0a11 39
vcoubard 1:ebc0e0ef0a11 40
vcoubard 1:ebc0e0ef0a11 41 /* ------------------------- Interrupt Number Definition ------------------------ */
vcoubard 1:ebc0e0ef0a11 42
vcoubard 1:ebc0e0ef0a11 43 typedef enum {
vcoubard 1:ebc0e0ef0a11 44 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
vcoubard 1:ebc0e0ef0a11 45 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
vcoubard 1:ebc0e0ef0a11 46 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
vcoubard 1:ebc0e0ef0a11 47 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
vcoubard 1:ebc0e0ef0a11 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
vcoubard 1:ebc0e0ef0a11 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
vcoubard 1:ebc0e0ef0a11 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
vcoubard 1:ebc0e0ef0a11 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
vcoubard 1:ebc0e0ef0a11 52 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
vcoubard 1:ebc0e0ef0a11 53 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
vcoubard 1:ebc0e0ef0a11 54 RADIO_IRQn = 1, /*!< 1 RADIO */
vcoubard 1:ebc0e0ef0a11 55 UART0_IRQn = 2, /*!< 2 UART0 */
vcoubard 1:ebc0e0ef0a11 56 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
vcoubard 1:ebc0e0ef0a11 57 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
vcoubard 1:ebc0e0ef0a11 58 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
vcoubard 1:ebc0e0ef0a11 59 ADC_IRQn = 7, /*!< 7 ADC */
vcoubard 1:ebc0e0ef0a11 60 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
vcoubard 1:ebc0e0ef0a11 61 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
vcoubard 1:ebc0e0ef0a11 62 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
vcoubard 1:ebc0e0ef0a11 63 RTC0_IRQn = 11, /*!< 11 RTC0 */
vcoubard 1:ebc0e0ef0a11 64 TEMP_IRQn = 12, /*!< 12 TEMP */
vcoubard 1:ebc0e0ef0a11 65 RNG_IRQn = 13, /*!< 13 RNG */
vcoubard 1:ebc0e0ef0a11 66 ECB_IRQn = 14, /*!< 14 ECB */
vcoubard 1:ebc0e0ef0a11 67 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
vcoubard 1:ebc0e0ef0a11 68 WDT_IRQn = 16, /*!< 16 WDT */
vcoubard 1:ebc0e0ef0a11 69 RTC1_IRQn = 17, /*!< 17 RTC1 */
vcoubard 1:ebc0e0ef0a11 70 QDEC_IRQn = 18, /*!< 18 QDEC */
vcoubard 1:ebc0e0ef0a11 71 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
vcoubard 1:ebc0e0ef0a11 72 SWI0_IRQn = 20, /*!< 20 SWI0 */
vcoubard 1:ebc0e0ef0a11 73 SWI1_IRQn = 21, /*!< 21 SWI1 */
vcoubard 1:ebc0e0ef0a11 74 SWI2_IRQn = 22, /*!< 22 SWI2 */
vcoubard 1:ebc0e0ef0a11 75 SWI3_IRQn = 23, /*!< 23 SWI3 */
vcoubard 1:ebc0e0ef0a11 76 SWI4_IRQn = 24, /*!< 24 SWI4 */
vcoubard 1:ebc0e0ef0a11 77 SWI5_IRQn = 25 /*!< 25 SWI5 */
vcoubard 1:ebc0e0ef0a11 78 } IRQn_Type;
vcoubard 1:ebc0e0ef0a11 79
vcoubard 1:ebc0e0ef0a11 80
vcoubard 1:ebc0e0ef0a11 81 /** @addtogroup Configuration_of_CMSIS
vcoubard 1:ebc0e0ef0a11 82 * @{
vcoubard 1:ebc0e0ef0a11 83 */
vcoubard 1:ebc0e0ef0a11 84
vcoubard 1:ebc0e0ef0a11 85
vcoubard 1:ebc0e0ef0a11 86 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 87 /* ================ Processor and Core Peripheral Section ================ */
vcoubard 1:ebc0e0ef0a11 88 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 89
vcoubard 1:ebc0e0ef0a11 90 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
vcoubard 1:ebc0e0ef0a11 91 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
vcoubard 1:ebc0e0ef0a11 92 #define __MPU_PRESENT 0 /*!< MPU present or not */
vcoubard 1:ebc0e0ef0a11 93 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
vcoubard 1:ebc0e0ef0a11 94 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
vcoubard 1:ebc0e0ef0a11 95 /** @} */ /* End of group Configuration_of_CMSIS */
vcoubard 1:ebc0e0ef0a11 96
vcoubard 1:ebc0e0ef0a11 97 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
vcoubard 1:ebc0e0ef0a11 98 #include "system_nrf51.h" /*!< nrf51 System */
vcoubard 1:ebc0e0ef0a11 99
vcoubard 1:ebc0e0ef0a11 100
vcoubard 1:ebc0e0ef0a11 101 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 102 /* ================ Device Specific Peripheral Section ================ */
vcoubard 1:ebc0e0ef0a11 103 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 104
vcoubard 1:ebc0e0ef0a11 105
vcoubard 1:ebc0e0ef0a11 106 /** @addtogroup Device_Peripheral_Registers
vcoubard 1:ebc0e0ef0a11 107 * @{
vcoubard 1:ebc0e0ef0a11 108 */
vcoubard 1:ebc0e0ef0a11 109
vcoubard 1:ebc0e0ef0a11 110
vcoubard 1:ebc0e0ef0a11 111 /* ------------------- Start of section using anonymous unions ------------------ */
vcoubard 1:ebc0e0ef0a11 112 #if defined(__CC_ARM)
vcoubard 1:ebc0e0ef0a11 113 #pragma push
vcoubard 1:ebc0e0ef0a11 114 #pragma anon_unions
vcoubard 1:ebc0e0ef0a11 115 #elif defined(__ICCARM__)
vcoubard 1:ebc0e0ef0a11 116 #pragma language=extended
vcoubard 1:ebc0e0ef0a11 117 #elif defined(__GNUC__)
vcoubard 1:ebc0e0ef0a11 118 /* anonymous unions are enabled by default */
vcoubard 1:ebc0e0ef0a11 119 #elif defined(__TMS470__)
vcoubard 1:ebc0e0ef0a11 120 /* anonymous unions are enabled by default */
vcoubard 1:ebc0e0ef0a11 121 #elif defined(__TASKING__)
vcoubard 1:ebc0e0ef0a11 122 #pragma warning 586
vcoubard 1:ebc0e0ef0a11 123 #else
vcoubard 1:ebc0e0ef0a11 124 #warning Not supported compiler type
vcoubard 1:ebc0e0ef0a11 125 #endif
vcoubard 1:ebc0e0ef0a11 126
vcoubard 1:ebc0e0ef0a11 127
vcoubard 1:ebc0e0ef0a11 128 typedef struct {
vcoubard 1:ebc0e0ef0a11 129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
vcoubard 1:ebc0e0ef0a11 130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
vcoubard 1:ebc0e0ef0a11 131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
vcoubard 1:ebc0e0ef0a11 132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
vcoubard 1:ebc0e0ef0a11 133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
vcoubard 1:ebc0e0ef0a11 134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
vcoubard 1:ebc0e0ef0a11 135 } AMLI_RAMPRI_Type;
vcoubard 1:ebc0e0ef0a11 136
vcoubard 1:ebc0e0ef0a11 137 typedef struct {
vcoubard 1:ebc0e0ef0a11 138 __IO uint32_t SCK; /*!< Pin select for SCK. */
vcoubard 1:ebc0e0ef0a11 139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
vcoubard 1:ebc0e0ef0a11 140 __IO uint32_t MISO; /*!< Pin select for MISO. */
vcoubard 1:ebc0e0ef0a11 141 } SPIM_PSEL_Type;
vcoubard 1:ebc0e0ef0a11 142
vcoubard 1:ebc0e0ef0a11 143 typedef struct {
vcoubard 1:ebc0e0ef0a11 144 __IO uint32_t PTR; /*!< Data pointer. */
vcoubard 1:ebc0e0ef0a11 145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
vcoubard 1:ebc0e0ef0a11 146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
vcoubard 1:ebc0e0ef0a11 147 } SPIM_RXD_Type;
vcoubard 1:ebc0e0ef0a11 148
vcoubard 1:ebc0e0ef0a11 149 typedef struct {
vcoubard 1:ebc0e0ef0a11 150 __IO uint32_t PTR; /*!< Data pointer. */
vcoubard 1:ebc0e0ef0a11 151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
vcoubard 1:ebc0e0ef0a11 152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
vcoubard 1:ebc0e0ef0a11 153 } SPIM_TXD_Type;
vcoubard 1:ebc0e0ef0a11 154
vcoubard 1:ebc0e0ef0a11 155 typedef struct {
vcoubard 1:ebc0e0ef0a11 156 __O uint32_t EN; /*!< Enable channel group. */
vcoubard 1:ebc0e0ef0a11 157 __O uint32_t DIS; /*!< Disable channel group. */
vcoubard 1:ebc0e0ef0a11 158 } PPI_TASKS_CHG_Type;
vcoubard 1:ebc0e0ef0a11 159
vcoubard 1:ebc0e0ef0a11 160 typedef struct {
vcoubard 1:ebc0e0ef0a11 161 __IO uint32_t EEP; /*!< Channel event end-point. */
vcoubard 1:ebc0e0ef0a11 162 __IO uint32_t TEP; /*!< Channel task end-point. */
vcoubard 1:ebc0e0ef0a11 163 } PPI_CH_Type;
vcoubard 1:ebc0e0ef0a11 164
vcoubard 1:ebc0e0ef0a11 165
vcoubard 1:ebc0e0ef0a11 166 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 167 /* ================ POWER ================ */
vcoubard 1:ebc0e0ef0a11 168 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 169
vcoubard 1:ebc0e0ef0a11 170
vcoubard 1:ebc0e0ef0a11 171 /**
vcoubard 1:ebc0e0ef0a11 172 * @brief Power Control. (POWER)
vcoubard 1:ebc0e0ef0a11 173 */
vcoubard 1:ebc0e0ef0a11 174
vcoubard 1:ebc0e0ef0a11 175 typedef struct { /*!< POWER Structure */
vcoubard 1:ebc0e0ef0a11 176 __I uint32_t RESERVED0[30];
vcoubard 1:ebc0e0ef0a11 177 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
vcoubard 1:ebc0e0ef0a11 178 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
vcoubard 1:ebc0e0ef0a11 179 __I uint32_t RESERVED1[34];
vcoubard 1:ebc0e0ef0a11 180 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
vcoubard 1:ebc0e0ef0a11 181 __I uint32_t RESERVED2[126];
vcoubard 1:ebc0e0ef0a11 182 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 183 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 184 __I uint32_t RESERVED3[61];
vcoubard 1:ebc0e0ef0a11 185 __IO uint32_t RESETREAS; /*!< Reset reason. */
vcoubard 1:ebc0e0ef0a11 186 __I uint32_t RESERVED4[9];
vcoubard 1:ebc0e0ef0a11 187 __I uint32_t RAMSTATUS; /*!< Ram status register. */
vcoubard 1:ebc0e0ef0a11 188 __I uint32_t RESERVED5[53];
vcoubard 1:ebc0e0ef0a11 189 __O uint32_t SYSTEMOFF; /*!< System off register. */
vcoubard 1:ebc0e0ef0a11 190 __I uint32_t RESERVED6[3];
vcoubard 1:ebc0e0ef0a11 191 __IO uint32_t POFCON; /*!< Power failure configuration. */
vcoubard 1:ebc0e0ef0a11 192 __I uint32_t RESERVED7[2];
vcoubard 1:ebc0e0ef0a11 193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
vcoubard 1:ebc0e0ef0a11 194 register. */
vcoubard 1:ebc0e0ef0a11 195 __I uint32_t RESERVED8;
vcoubard 1:ebc0e0ef0a11 196 __IO uint32_t RAMON; /*!< Ram on/off. */
vcoubard 1:ebc0e0ef0a11 197 __I uint32_t RESERVED9[7];
vcoubard 1:ebc0e0ef0a11 198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
vcoubard 1:ebc0e0ef0a11 199 is a retained register. */
vcoubard 1:ebc0e0ef0a11 200 __I uint32_t RESERVED10[3];
vcoubard 1:ebc0e0ef0a11 201 __IO uint32_t RAMONB; /*!< Ram on/off. */
vcoubard 1:ebc0e0ef0a11 202 __I uint32_t RESERVED11[8];
vcoubard 1:ebc0e0ef0a11 203 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
vcoubard 1:ebc0e0ef0a11 204 __I uint32_t RESERVED12[291];
vcoubard 1:ebc0e0ef0a11 205 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
vcoubard 1:ebc0e0ef0a11 206 } NRF_POWER_Type;
vcoubard 1:ebc0e0ef0a11 207
vcoubard 1:ebc0e0ef0a11 208
vcoubard 1:ebc0e0ef0a11 209 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 210 /* ================ CLOCK ================ */
vcoubard 1:ebc0e0ef0a11 211 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 212
vcoubard 1:ebc0e0ef0a11 213
vcoubard 1:ebc0e0ef0a11 214 /**
vcoubard 1:ebc0e0ef0a11 215 * @brief Clock control. (CLOCK)
vcoubard 1:ebc0e0ef0a11 216 */
vcoubard 1:ebc0e0ef0a11 217
vcoubard 1:ebc0e0ef0a11 218 typedef struct { /*!< CLOCK Structure */
vcoubard 1:ebc0e0ef0a11 219 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
vcoubard 1:ebc0e0ef0a11 220 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
vcoubard 1:ebc0e0ef0a11 221 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
vcoubard 1:ebc0e0ef0a11 222 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
vcoubard 1:ebc0e0ef0a11 223 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
vcoubard 1:ebc0e0ef0a11 224 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
vcoubard 1:ebc0e0ef0a11 225 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
vcoubard 1:ebc0e0ef0a11 226 __I uint32_t RESERVED0[57];
vcoubard 1:ebc0e0ef0a11 227 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
vcoubard 1:ebc0e0ef0a11 228 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
vcoubard 1:ebc0e0ef0a11 229 __I uint32_t RESERVED1;
vcoubard 1:ebc0e0ef0a11 230 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
vcoubard 1:ebc0e0ef0a11 231 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
vcoubard 1:ebc0e0ef0a11 232 __I uint32_t RESERVED2[124];
vcoubard 1:ebc0e0ef0a11 233 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 234 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 235 __I uint32_t RESERVED3[63];
vcoubard 1:ebc0e0ef0a11 236 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
vcoubard 1:ebc0e0ef0a11 237 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
vcoubard 1:ebc0e0ef0a11 238 __I uint32_t RESERVED4;
vcoubard 1:ebc0e0ef0a11 239 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
vcoubard 1:ebc0e0ef0a11 240 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
vcoubard 1:ebc0e0ef0a11 241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
vcoubard 1:ebc0e0ef0a11 242 triggered. */
vcoubard 1:ebc0e0ef0a11 243 __I uint32_t RESERVED5[62];
vcoubard 1:ebc0e0ef0a11 244 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
vcoubard 1:ebc0e0ef0a11 245 __I uint32_t RESERVED6[7];
vcoubard 1:ebc0e0ef0a11 246 __IO uint32_t CTIV; /*!< Calibration timer interval. */
vcoubard 1:ebc0e0ef0a11 247 __I uint32_t RESERVED7[5];
vcoubard 1:ebc0e0ef0a11 248 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
vcoubard 1:ebc0e0ef0a11 249 } NRF_CLOCK_Type;
vcoubard 1:ebc0e0ef0a11 250
vcoubard 1:ebc0e0ef0a11 251
vcoubard 1:ebc0e0ef0a11 252 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 253 /* ================ MPU ================ */
vcoubard 1:ebc0e0ef0a11 254 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 255
vcoubard 1:ebc0e0ef0a11 256
vcoubard 1:ebc0e0ef0a11 257 /**
vcoubard 1:ebc0e0ef0a11 258 * @brief Memory Protection Unit. (MPU)
vcoubard 1:ebc0e0ef0a11 259 */
vcoubard 1:ebc0e0ef0a11 260
vcoubard 1:ebc0e0ef0a11 261 typedef struct { /*!< MPU Structure */
vcoubard 1:ebc0e0ef0a11 262 __I uint32_t RESERVED0[330];
vcoubard 1:ebc0e0ef0a11 263 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
vcoubard 1:ebc0e0ef0a11 264 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
vcoubard 1:ebc0e0ef0a11 265 __I uint32_t RESERVED1[52];
vcoubard 1:ebc0e0ef0a11 266 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
vcoubard 1:ebc0e0ef0a11 267 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
vcoubard 1:ebc0e0ef0a11 268 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
vcoubard 1:ebc0e0ef0a11 269 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
vcoubard 1:ebc0e0ef0a11 270 } NRF_MPU_Type;
vcoubard 1:ebc0e0ef0a11 271
vcoubard 1:ebc0e0ef0a11 272
vcoubard 1:ebc0e0ef0a11 273 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 274 /* ================ AMLI ================ */
vcoubard 1:ebc0e0ef0a11 275 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 276
vcoubard 1:ebc0e0ef0a11 277
vcoubard 1:ebc0e0ef0a11 278 /**
vcoubard 1:ebc0e0ef0a11 279 * @brief AHB Multi-Layer Interface. (AMLI)
vcoubard 1:ebc0e0ef0a11 280 */
vcoubard 1:ebc0e0ef0a11 281
vcoubard 1:ebc0e0ef0a11 282 typedef struct { /*!< AMLI Structure */
vcoubard 1:ebc0e0ef0a11 283 __I uint32_t RESERVED0[896];
vcoubard 1:ebc0e0ef0a11 284 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
vcoubard 1:ebc0e0ef0a11 285 } NRF_AMLI_Type;
vcoubard 1:ebc0e0ef0a11 286
vcoubard 1:ebc0e0ef0a11 287
vcoubard 1:ebc0e0ef0a11 288 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 289 /* ================ RADIO ================ */
vcoubard 1:ebc0e0ef0a11 290 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 291
vcoubard 1:ebc0e0ef0a11 292
vcoubard 1:ebc0e0ef0a11 293 /**
vcoubard 1:ebc0e0ef0a11 294 * @brief The radio. (RADIO)
vcoubard 1:ebc0e0ef0a11 295 */
vcoubard 1:ebc0e0ef0a11 296
vcoubard 1:ebc0e0ef0a11 297 typedef struct { /*!< RADIO Structure */
vcoubard 1:ebc0e0ef0a11 298 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
vcoubard 1:ebc0e0ef0a11 299 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
vcoubard 1:ebc0e0ef0a11 300 __O uint32_t TASKS_START; /*!< Start radio. */
vcoubard 1:ebc0e0ef0a11 301 __O uint32_t TASKS_STOP; /*!< Stop radio. */
vcoubard 1:ebc0e0ef0a11 302 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
vcoubard 1:ebc0e0ef0a11 303 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
vcoubard 1:ebc0e0ef0a11 304 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
vcoubard 1:ebc0e0ef0a11 305 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
vcoubard 1:ebc0e0ef0a11 306 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
vcoubard 1:ebc0e0ef0a11 307 __I uint32_t RESERVED0[55];
vcoubard 1:ebc0e0ef0a11 308 __IO uint32_t EVENTS_READY; /*!< Ready event. */
vcoubard 1:ebc0e0ef0a11 309 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
vcoubard 1:ebc0e0ef0a11 310 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
vcoubard 1:ebc0e0ef0a11 311 __IO uint32_t EVENTS_END; /*!< End event. */
vcoubard 1:ebc0e0ef0a11 312 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
vcoubard 1:ebc0e0ef0a11 313 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
vcoubard 1:ebc0e0ef0a11 314 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
vcoubard 1:ebc0e0ef0a11 315 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
vcoubard 1:ebc0e0ef0a11 316 sample is ready for readout at the RSSISAMPLE register. */
vcoubard 1:ebc0e0ef0a11 317 __I uint32_t RESERVED1[2];
vcoubard 1:ebc0e0ef0a11 318 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
vcoubard 1:ebc0e0ef0a11 319 __I uint32_t RESERVED2[53];
vcoubard 1:ebc0e0ef0a11 320 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
vcoubard 1:ebc0e0ef0a11 321 __I uint32_t RESERVED3[64];
vcoubard 1:ebc0e0ef0a11 322 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 323 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 324 __I uint32_t RESERVED4[61];
vcoubard 1:ebc0e0ef0a11 325 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
vcoubard 28:041dac1366b2 326 __I uint32_t RESERVED5;
vcoubard 1:ebc0e0ef0a11 327 __I uint32_t RXMATCH; /*!< Received address. */
vcoubard 1:ebc0e0ef0a11 328 __I uint32_t RXCRC; /*!< Received CRC. */
vcoubard 1:ebc0e0ef0a11 329 __I uint32_t DAI; /*!< Device address match index. */
vcoubard 28:041dac1366b2 330 __I uint32_t RESERVED6[60];
vcoubard 1:ebc0e0ef0a11 331 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
vcoubard 1:ebc0e0ef0a11 332 __IO uint32_t FREQUENCY; /*!< Frequency. */
vcoubard 1:ebc0e0ef0a11 333 __IO uint32_t TXPOWER; /*!< Output power. */
vcoubard 1:ebc0e0ef0a11 334 __IO uint32_t MODE; /*!< Data rate and modulation. */
vcoubard 1:ebc0e0ef0a11 335 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
vcoubard 1:ebc0e0ef0a11 336 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
vcoubard 1:ebc0e0ef0a11 337 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
vcoubard 1:ebc0e0ef0a11 338 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
vcoubard 1:ebc0e0ef0a11 339 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
vcoubard 1:ebc0e0ef0a11 340 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
vcoubard 1:ebc0e0ef0a11 341 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
vcoubard 1:ebc0e0ef0a11 342 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
vcoubard 1:ebc0e0ef0a11 343 __IO uint32_t CRCCNF; /*!< CRC configuration. */
vcoubard 1:ebc0e0ef0a11 344 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
vcoubard 1:ebc0e0ef0a11 345 __IO uint32_t CRCINIT; /*!< CRC initial value. */
vcoubard 1:ebc0e0ef0a11 346 __IO uint32_t TEST; /*!< Test features enable register. */
vcoubard 1:ebc0e0ef0a11 347 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
vcoubard 1:ebc0e0ef0a11 348 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
vcoubard 28:041dac1366b2 349 __I uint32_t RESERVED7;
vcoubard 1:ebc0e0ef0a11 350 __I uint32_t STATE; /*!< Current radio state. */
vcoubard 1:ebc0e0ef0a11 351 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
vcoubard 28:041dac1366b2 352 __I uint32_t RESERVED8[2];
vcoubard 1:ebc0e0ef0a11 353 __IO uint32_t BCC; /*!< Bit counter compare. */
vcoubard 28:041dac1366b2 354 __I uint32_t RESERVED9[39];
vcoubard 1:ebc0e0ef0a11 355 __IO uint32_t DAB[8]; /*!< Device address base segment. */
vcoubard 1:ebc0e0ef0a11 356 __IO uint32_t DAP[8]; /*!< Device address prefix. */
vcoubard 1:ebc0e0ef0a11 357 __IO uint32_t DACNF; /*!< Device address match configuration. */
vcoubard 28:041dac1366b2 358 __I uint32_t RESERVED10[56];
vcoubard 1:ebc0e0ef0a11 359 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
vcoubard 1:ebc0e0ef0a11 360 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
vcoubard 1:ebc0e0ef0a11 361 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
vcoubard 1:ebc0e0ef0a11 362 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
vcoubard 1:ebc0e0ef0a11 363 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
vcoubard 28:041dac1366b2 364 __I uint32_t RESERVED11[561];
vcoubard 1:ebc0e0ef0a11 365 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 366 } NRF_RADIO_Type;
vcoubard 1:ebc0e0ef0a11 367
vcoubard 1:ebc0e0ef0a11 368
vcoubard 1:ebc0e0ef0a11 369 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 370 /* ================ UART ================ */
vcoubard 1:ebc0e0ef0a11 371 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 372
vcoubard 1:ebc0e0ef0a11 373
vcoubard 1:ebc0e0ef0a11 374 /**
vcoubard 1:ebc0e0ef0a11 375 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
vcoubard 1:ebc0e0ef0a11 376 */
vcoubard 1:ebc0e0ef0a11 377
vcoubard 1:ebc0e0ef0a11 378 typedef struct { /*!< UART Structure */
vcoubard 1:ebc0e0ef0a11 379 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
vcoubard 1:ebc0e0ef0a11 380 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
vcoubard 1:ebc0e0ef0a11 381 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
vcoubard 1:ebc0e0ef0a11 382 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
vcoubard 1:ebc0e0ef0a11 383 __I uint32_t RESERVED0[3];
vcoubard 1:ebc0e0ef0a11 384 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
vcoubard 1:ebc0e0ef0a11 385 __I uint32_t RESERVED1[56];
vcoubard 1:ebc0e0ef0a11 386 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
vcoubard 1:ebc0e0ef0a11 387 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
vcoubard 1:ebc0e0ef0a11 388 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
vcoubard 1:ebc0e0ef0a11 389 __I uint32_t RESERVED2[4];
vcoubard 1:ebc0e0ef0a11 390 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
vcoubard 1:ebc0e0ef0a11 391 __I uint32_t RESERVED3;
vcoubard 1:ebc0e0ef0a11 392 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
vcoubard 1:ebc0e0ef0a11 393 __I uint32_t RESERVED4[7];
vcoubard 1:ebc0e0ef0a11 394 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
vcoubard 28:041dac1366b2 395 __I uint32_t RESERVED5[46];
vcoubard 28:041dac1366b2 396 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
vcoubard 28:041dac1366b2 397 __I uint32_t RESERVED6[64];
vcoubard 1:ebc0e0ef0a11 398 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 399 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 28:041dac1366b2 400 __I uint32_t RESERVED7[93];
vcoubard 1:ebc0e0ef0a11 401 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
vcoubard 28:041dac1366b2 402 __I uint32_t RESERVED8[31];
vcoubard 1:ebc0e0ef0a11 403 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
vcoubard 28:041dac1366b2 404 __I uint32_t RESERVED9;
vcoubard 1:ebc0e0ef0a11 405 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
vcoubard 1:ebc0e0ef0a11 406 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
vcoubard 1:ebc0e0ef0a11 407 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
vcoubard 1:ebc0e0ef0a11 408 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
vcoubard 1:ebc0e0ef0a11 409 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
vcoubard 1:ebc0e0ef0a11 410 Once read the character is consumed. If read when no character
vcoubard 1:ebc0e0ef0a11 411 available, the UART will stop working. */
vcoubard 1:ebc0e0ef0a11 412 __O uint32_t TXD; /*!< TXD register. */
vcoubard 28:041dac1366b2 413 __I uint32_t RESERVED10;
vcoubard 1:ebc0e0ef0a11 414 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
vcoubard 28:041dac1366b2 415 __I uint32_t RESERVED11[17];
vcoubard 1:ebc0e0ef0a11 416 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
vcoubard 28:041dac1366b2 417 __I uint32_t RESERVED12[675];
vcoubard 1:ebc0e0ef0a11 418 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 419 } NRF_UART_Type;
vcoubard 1:ebc0e0ef0a11 420
vcoubard 1:ebc0e0ef0a11 421
vcoubard 1:ebc0e0ef0a11 422 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 423 /* ================ SPI ================ */
vcoubard 1:ebc0e0ef0a11 424 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 425
vcoubard 1:ebc0e0ef0a11 426
vcoubard 1:ebc0e0ef0a11 427 /**
vcoubard 1:ebc0e0ef0a11 428 * @brief SPI master 0. (SPI)
vcoubard 1:ebc0e0ef0a11 429 */
vcoubard 1:ebc0e0ef0a11 430
vcoubard 1:ebc0e0ef0a11 431 typedef struct { /*!< SPI Structure */
vcoubard 1:ebc0e0ef0a11 432 __I uint32_t RESERVED0[66];
vcoubard 1:ebc0e0ef0a11 433 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
vcoubard 1:ebc0e0ef0a11 434 __I uint32_t RESERVED1[126];
vcoubard 1:ebc0e0ef0a11 435 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 436 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 437 __I uint32_t RESERVED2[125];
vcoubard 1:ebc0e0ef0a11 438 __IO uint32_t ENABLE; /*!< Enable SPI. */
vcoubard 1:ebc0e0ef0a11 439 __I uint32_t RESERVED3;
vcoubard 1:ebc0e0ef0a11 440 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
vcoubard 1:ebc0e0ef0a11 441 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
vcoubard 1:ebc0e0ef0a11 442 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
vcoubard 1:ebc0e0ef0a11 443 __I uint32_t RESERVED4;
vcoubard 1:ebc0e0ef0a11 444 __I uint32_t RXD; /*!< RX data. */
vcoubard 1:ebc0e0ef0a11 445 __IO uint32_t TXD; /*!< TX data. */
vcoubard 1:ebc0e0ef0a11 446 __I uint32_t RESERVED5;
vcoubard 1:ebc0e0ef0a11 447 __IO uint32_t FREQUENCY; /*!< SPI frequency */
vcoubard 1:ebc0e0ef0a11 448 __I uint32_t RESERVED6[11];
vcoubard 1:ebc0e0ef0a11 449 __IO uint32_t CONFIG; /*!< Configuration register. */
vcoubard 1:ebc0e0ef0a11 450 __I uint32_t RESERVED7[681];
vcoubard 1:ebc0e0ef0a11 451 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 452 } NRF_SPI_Type;
vcoubard 1:ebc0e0ef0a11 453
vcoubard 1:ebc0e0ef0a11 454
vcoubard 1:ebc0e0ef0a11 455 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 456 /* ================ TWI ================ */
vcoubard 1:ebc0e0ef0a11 457 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 458
vcoubard 1:ebc0e0ef0a11 459
vcoubard 1:ebc0e0ef0a11 460 /**
vcoubard 1:ebc0e0ef0a11 461 * @brief Two-wire interface master 0. (TWI)
vcoubard 1:ebc0e0ef0a11 462 */
vcoubard 1:ebc0e0ef0a11 463
vcoubard 1:ebc0e0ef0a11 464 typedef struct { /*!< TWI Structure */
vcoubard 1:ebc0e0ef0a11 465 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
vcoubard 1:ebc0e0ef0a11 466 __I uint32_t RESERVED0;
vcoubard 1:ebc0e0ef0a11 467 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
vcoubard 1:ebc0e0ef0a11 468 __I uint32_t RESERVED1[2];
vcoubard 1:ebc0e0ef0a11 469 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
vcoubard 1:ebc0e0ef0a11 470 __I uint32_t RESERVED2;
vcoubard 1:ebc0e0ef0a11 471 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
vcoubard 1:ebc0e0ef0a11 472 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
vcoubard 1:ebc0e0ef0a11 473 __I uint32_t RESERVED3[56];
vcoubard 1:ebc0e0ef0a11 474 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
vcoubard 1:ebc0e0ef0a11 475 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
vcoubard 1:ebc0e0ef0a11 476 __I uint32_t RESERVED4[4];
vcoubard 1:ebc0e0ef0a11 477 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
vcoubard 1:ebc0e0ef0a11 478 __I uint32_t RESERVED5;
vcoubard 1:ebc0e0ef0a11 479 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
vcoubard 1:ebc0e0ef0a11 480 __I uint32_t RESERVED6[4];
vcoubard 1:ebc0e0ef0a11 481 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
vcoubard 1:ebc0e0ef0a11 482 __I uint32_t RESERVED7[3];
vcoubard 1:ebc0e0ef0a11 483 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
vcoubard 1:ebc0e0ef0a11 484 __I uint32_t RESERVED8[45];
vcoubard 1:ebc0e0ef0a11 485 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
vcoubard 1:ebc0e0ef0a11 486 __I uint32_t RESERVED9[64];
vcoubard 1:ebc0e0ef0a11 487 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 488 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 489 __I uint32_t RESERVED10[110];
vcoubard 1:ebc0e0ef0a11 490 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
vcoubard 1:ebc0e0ef0a11 491 __I uint32_t RESERVED11[14];
vcoubard 1:ebc0e0ef0a11 492 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
vcoubard 1:ebc0e0ef0a11 493 __I uint32_t RESERVED12;
vcoubard 1:ebc0e0ef0a11 494 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
vcoubard 1:ebc0e0ef0a11 495 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
vcoubard 1:ebc0e0ef0a11 496 __I uint32_t RESERVED13[2];
vcoubard 1:ebc0e0ef0a11 497 __I uint32_t RXD; /*!< RX data register. */
vcoubard 1:ebc0e0ef0a11 498 __IO uint32_t TXD; /*!< TX data register. */
vcoubard 1:ebc0e0ef0a11 499 __I uint32_t RESERVED14;
vcoubard 1:ebc0e0ef0a11 500 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
vcoubard 1:ebc0e0ef0a11 501 __I uint32_t RESERVED15[24];
vcoubard 1:ebc0e0ef0a11 502 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
vcoubard 1:ebc0e0ef0a11 503 __I uint32_t RESERVED16[668];
vcoubard 1:ebc0e0ef0a11 504 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 505 } NRF_TWI_Type;
vcoubard 1:ebc0e0ef0a11 506
vcoubard 1:ebc0e0ef0a11 507
vcoubard 1:ebc0e0ef0a11 508 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 509 /* ================ SPIS ================ */
vcoubard 1:ebc0e0ef0a11 510 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 511
vcoubard 1:ebc0e0ef0a11 512
vcoubard 1:ebc0e0ef0a11 513 /**
vcoubard 1:ebc0e0ef0a11 514 * @brief SPI slave 1. (SPIS)
vcoubard 1:ebc0e0ef0a11 515 */
vcoubard 1:ebc0e0ef0a11 516
vcoubard 1:ebc0e0ef0a11 517 typedef struct { /*!< SPIS Structure */
vcoubard 1:ebc0e0ef0a11 518 __I uint32_t RESERVED0[9];
vcoubard 1:ebc0e0ef0a11 519 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
vcoubard 1:ebc0e0ef0a11 520 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
vcoubard 1:ebc0e0ef0a11 521 __I uint32_t RESERVED1[54];
vcoubard 1:ebc0e0ef0a11 522 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
vcoubard 32:6335323e4327 523 __I uint32_t RESERVED2[2];
vcoubard 32:6335323e4327 524 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
vcoubard 32:6335323e4327 525 __I uint32_t RESERVED3[5];
vcoubard 1:ebc0e0ef0a11 526 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
vcoubard 32:6335323e4327 527 __I uint32_t RESERVED4[53];
vcoubard 1:ebc0e0ef0a11 528 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
vcoubard 32:6335323e4327 529 __I uint32_t RESERVED5[64];
vcoubard 1:ebc0e0ef0a11 530 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 531 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 32:6335323e4327 532 __I uint32_t RESERVED6[61];
vcoubard 1:ebc0e0ef0a11 533 __I uint32_t SEMSTAT; /*!< Semaphore status. */
vcoubard 32:6335323e4327 534 __I uint32_t RESERVED7[15];
vcoubard 1:ebc0e0ef0a11 535 __IO uint32_t STATUS; /*!< Status from last transaction. */
vcoubard 32:6335323e4327 536 __I uint32_t RESERVED8[47];
vcoubard 1:ebc0e0ef0a11 537 __IO uint32_t ENABLE; /*!< Enable SPIS. */
vcoubard 32:6335323e4327 538 __I uint32_t RESERVED9;
vcoubard 1:ebc0e0ef0a11 539 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
vcoubard 1:ebc0e0ef0a11 540 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
vcoubard 1:ebc0e0ef0a11 541 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
vcoubard 1:ebc0e0ef0a11 542 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
vcoubard 32:6335323e4327 543 __I uint32_t RESERVED10[7];
vcoubard 1:ebc0e0ef0a11 544 __IO uint32_t RXDPTR; /*!< RX data pointer. */
vcoubard 1:ebc0e0ef0a11 545 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
vcoubard 1:ebc0e0ef0a11 546 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
vcoubard 32:6335323e4327 547 __I uint32_t RESERVED11;
vcoubard 1:ebc0e0ef0a11 548 __IO uint32_t TXDPTR; /*!< TX data pointer. */
vcoubard 1:ebc0e0ef0a11 549 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
vcoubard 1:ebc0e0ef0a11 550 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
vcoubard 32:6335323e4327 551 __I uint32_t RESERVED12;
vcoubard 1:ebc0e0ef0a11 552 __IO uint32_t CONFIG; /*!< Configuration register. */
vcoubard 32:6335323e4327 553 __I uint32_t RESERVED13;
vcoubard 1:ebc0e0ef0a11 554 __IO uint32_t DEF; /*!< Default character. */
vcoubard 32:6335323e4327 555 __I uint32_t RESERVED14[24];
vcoubard 1:ebc0e0ef0a11 556 __IO uint32_t ORC; /*!< Over-read character. */
vcoubard 32:6335323e4327 557 __I uint32_t RESERVED15[654];
vcoubard 1:ebc0e0ef0a11 558 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 559 } NRF_SPIS_Type;
vcoubard 1:ebc0e0ef0a11 560
vcoubard 1:ebc0e0ef0a11 561
vcoubard 1:ebc0e0ef0a11 562 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 563 /* ================ SPIM ================ */
vcoubard 1:ebc0e0ef0a11 564 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 565
vcoubard 1:ebc0e0ef0a11 566
vcoubard 1:ebc0e0ef0a11 567 /**
vcoubard 1:ebc0e0ef0a11 568 * @brief SPI master with easyDMA 1. (SPIM)
vcoubard 1:ebc0e0ef0a11 569 */
vcoubard 1:ebc0e0ef0a11 570
vcoubard 1:ebc0e0ef0a11 571 typedef struct { /*!< SPIM Structure */
vcoubard 1:ebc0e0ef0a11 572 __I uint32_t RESERVED0[4];
vcoubard 1:ebc0e0ef0a11 573 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
vcoubard 1:ebc0e0ef0a11 574 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
vcoubard 1:ebc0e0ef0a11 575 __I uint32_t RESERVED1;
vcoubard 1:ebc0e0ef0a11 576 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
vcoubard 1:ebc0e0ef0a11 577 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
vcoubard 1:ebc0e0ef0a11 578 __I uint32_t RESERVED2[56];
vcoubard 1:ebc0e0ef0a11 579 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
vcoubard 1:ebc0e0ef0a11 580 __I uint32_t RESERVED3[2];
vcoubard 1:ebc0e0ef0a11 581 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
vcoubard 28:041dac1366b2 582 __I uint32_t RESERVED4[3];
vcoubard 1:ebc0e0ef0a11 583 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
vcoubard 28:041dac1366b2 584 __I uint32_t RESERVED5[10];
vcoubard 1:ebc0e0ef0a11 585 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
vcoubard 28:041dac1366b2 586 __I uint32_t RESERVED6[109];
vcoubard 1:ebc0e0ef0a11 587 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 588 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 28:041dac1366b2 589 __I uint32_t RESERVED7[125];
vcoubard 1:ebc0e0ef0a11 590 __IO uint32_t ENABLE; /*!< Enable SPIM. */
vcoubard 28:041dac1366b2 591 __I uint32_t RESERVED8;
vcoubard 1:ebc0e0ef0a11 592 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
vcoubard 28:041dac1366b2 593 __I uint32_t RESERVED9[4];
vcoubard 1:ebc0e0ef0a11 594 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
vcoubard 28:041dac1366b2 595 __I uint32_t RESERVED10[3];
vcoubard 1:ebc0e0ef0a11 596 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
vcoubard 28:041dac1366b2 597 __I uint32_t RESERVED11;
vcoubard 1:ebc0e0ef0a11 598 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
vcoubard 28:041dac1366b2 599 __I uint32_t RESERVED12;
vcoubard 1:ebc0e0ef0a11 600 __IO uint32_t CONFIG; /*!< Configuration register. */
vcoubard 28:041dac1366b2 601 __I uint32_t RESERVED13[26];
vcoubard 1:ebc0e0ef0a11 602 __IO uint32_t ORC; /*!< Over-read character. */
vcoubard 28:041dac1366b2 603 __I uint32_t RESERVED14[654];
vcoubard 1:ebc0e0ef0a11 604 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 605 } NRF_SPIM_Type;
vcoubard 1:ebc0e0ef0a11 606
vcoubard 1:ebc0e0ef0a11 607
vcoubard 1:ebc0e0ef0a11 608 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 609 /* ================ GPIOTE ================ */
vcoubard 1:ebc0e0ef0a11 610 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 611
vcoubard 1:ebc0e0ef0a11 612
vcoubard 1:ebc0e0ef0a11 613 /**
vcoubard 1:ebc0e0ef0a11 614 * @brief GPIO tasks and events. (GPIOTE)
vcoubard 1:ebc0e0ef0a11 615 */
vcoubard 1:ebc0e0ef0a11 616
vcoubard 1:ebc0e0ef0a11 617 typedef struct { /*!< GPIOTE Structure */
vcoubard 1:ebc0e0ef0a11 618 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
vcoubard 1:ebc0e0ef0a11 619 __I uint32_t RESERVED0[60];
vcoubard 1:ebc0e0ef0a11 620 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
vcoubard 1:ebc0e0ef0a11 621 __I uint32_t RESERVED1[27];
vcoubard 1:ebc0e0ef0a11 622 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
vcoubard 1:ebc0e0ef0a11 623 __I uint32_t RESERVED2[97];
vcoubard 1:ebc0e0ef0a11 624 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 625 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 626 __I uint32_t RESERVED3[129];
vcoubard 1:ebc0e0ef0a11 627 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
vcoubard 1:ebc0e0ef0a11 628 __I uint32_t RESERVED4[695];
vcoubard 1:ebc0e0ef0a11 629 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 630 } NRF_GPIOTE_Type;
vcoubard 1:ebc0e0ef0a11 631
vcoubard 1:ebc0e0ef0a11 632
vcoubard 1:ebc0e0ef0a11 633 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 634 /* ================ ADC ================ */
vcoubard 1:ebc0e0ef0a11 635 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 636
vcoubard 1:ebc0e0ef0a11 637
vcoubard 1:ebc0e0ef0a11 638 /**
vcoubard 1:ebc0e0ef0a11 639 * @brief Analog to digital converter. (ADC)
vcoubard 1:ebc0e0ef0a11 640 */
vcoubard 1:ebc0e0ef0a11 641
vcoubard 1:ebc0e0ef0a11 642 typedef struct { /*!< ADC Structure */
vcoubard 1:ebc0e0ef0a11 643 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
vcoubard 1:ebc0e0ef0a11 644 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
vcoubard 1:ebc0e0ef0a11 645 __I uint32_t RESERVED0[62];
vcoubard 1:ebc0e0ef0a11 646 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
vcoubard 1:ebc0e0ef0a11 647 __I uint32_t RESERVED1[128];
vcoubard 1:ebc0e0ef0a11 648 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 649 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 650 __I uint32_t RESERVED2[61];
vcoubard 1:ebc0e0ef0a11 651 __I uint32_t BUSY; /*!< ADC busy register. */
vcoubard 1:ebc0e0ef0a11 652 __I uint32_t RESERVED3[63];
vcoubard 1:ebc0e0ef0a11 653 __IO uint32_t ENABLE; /*!< ADC enable. */
vcoubard 1:ebc0e0ef0a11 654 __IO uint32_t CONFIG; /*!< ADC configuration register. */
vcoubard 1:ebc0e0ef0a11 655 __I uint32_t RESULT; /*!< Result of ADC conversion. */
vcoubard 1:ebc0e0ef0a11 656 __I uint32_t RESERVED4[700];
vcoubard 1:ebc0e0ef0a11 657 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 658 } NRF_ADC_Type;
vcoubard 1:ebc0e0ef0a11 659
vcoubard 1:ebc0e0ef0a11 660
vcoubard 1:ebc0e0ef0a11 661 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 662 /* ================ TIMER ================ */
vcoubard 1:ebc0e0ef0a11 663 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 664
vcoubard 1:ebc0e0ef0a11 665
vcoubard 1:ebc0e0ef0a11 666 /**
vcoubard 1:ebc0e0ef0a11 667 * @brief Timer 0. (TIMER)
vcoubard 1:ebc0e0ef0a11 668 */
vcoubard 1:ebc0e0ef0a11 669
vcoubard 1:ebc0e0ef0a11 670 typedef struct { /*!< TIMER Structure */
vcoubard 1:ebc0e0ef0a11 671 __O uint32_t TASKS_START; /*!< Start Timer. */
vcoubard 1:ebc0e0ef0a11 672 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
vcoubard 1:ebc0e0ef0a11 673 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
vcoubard 1:ebc0e0ef0a11 674 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
vcoubard 1:ebc0e0ef0a11 675 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
vcoubard 1:ebc0e0ef0a11 676 __I uint32_t RESERVED0[11];
vcoubard 1:ebc0e0ef0a11 677 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
vcoubard 1:ebc0e0ef0a11 678 __I uint32_t RESERVED1[60];
vcoubard 1:ebc0e0ef0a11 679 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
vcoubard 1:ebc0e0ef0a11 680 __I uint32_t RESERVED2[44];
vcoubard 1:ebc0e0ef0a11 681 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
vcoubard 1:ebc0e0ef0a11 682 __I uint32_t RESERVED3[64];
vcoubard 1:ebc0e0ef0a11 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 685 __I uint32_t RESERVED4[126];
vcoubard 1:ebc0e0ef0a11 686 __IO uint32_t MODE; /*!< Timer Mode selection. */
vcoubard 1:ebc0e0ef0a11 687 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
vcoubard 1:ebc0e0ef0a11 688 __I uint32_t RESERVED5;
vcoubard 1:ebc0e0ef0a11 689 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
vcoubard 1:ebc0e0ef0a11 690 clock frequency is divided by 2^SCALE. */
vcoubard 1:ebc0e0ef0a11 691 __I uint32_t RESERVED6[11];
vcoubard 1:ebc0e0ef0a11 692 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
vcoubard 1:ebc0e0ef0a11 693 __I uint32_t RESERVED7[683];
vcoubard 1:ebc0e0ef0a11 694 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 695 } NRF_TIMER_Type;
vcoubard 1:ebc0e0ef0a11 696
vcoubard 1:ebc0e0ef0a11 697
vcoubard 1:ebc0e0ef0a11 698 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 699 /* ================ RTC ================ */
vcoubard 1:ebc0e0ef0a11 700 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 701
vcoubard 1:ebc0e0ef0a11 702
vcoubard 1:ebc0e0ef0a11 703 /**
vcoubard 1:ebc0e0ef0a11 704 * @brief Real time counter 0. (RTC)
vcoubard 1:ebc0e0ef0a11 705 */
vcoubard 1:ebc0e0ef0a11 706
vcoubard 1:ebc0e0ef0a11 707 typedef struct { /*!< RTC Structure */
vcoubard 1:ebc0e0ef0a11 708 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
vcoubard 1:ebc0e0ef0a11 709 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
vcoubard 1:ebc0e0ef0a11 710 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
vcoubard 1:ebc0e0ef0a11 711 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
vcoubard 1:ebc0e0ef0a11 712 __I uint32_t RESERVED0[60];
vcoubard 1:ebc0e0ef0a11 713 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
vcoubard 1:ebc0e0ef0a11 714 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
vcoubard 1:ebc0e0ef0a11 715 __I uint32_t RESERVED1[14];
vcoubard 1:ebc0e0ef0a11 716 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
vcoubard 1:ebc0e0ef0a11 717 __I uint32_t RESERVED2[109];
vcoubard 1:ebc0e0ef0a11 718 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 719 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 720 __I uint32_t RESERVED3[13];
vcoubard 1:ebc0e0ef0a11 721 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
vcoubard 1:ebc0e0ef0a11 722 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
vcoubard 1:ebc0e0ef0a11 723 the value of EVTEN. */
vcoubard 1:ebc0e0ef0a11 724 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
vcoubard 1:ebc0e0ef0a11 725 gives the value of EVTEN. */
vcoubard 1:ebc0e0ef0a11 726 __I uint32_t RESERVED4[110];
vcoubard 1:ebc0e0ef0a11 727 __I uint32_t COUNTER; /*!< Current COUNTER value. */
vcoubard 1:ebc0e0ef0a11 728 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
vcoubard 1:ebc0e0ef0a11 729 Must be written when RTC is STOPed. */
vcoubard 1:ebc0e0ef0a11 730 __I uint32_t RESERVED5[13];
vcoubard 1:ebc0e0ef0a11 731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
vcoubard 1:ebc0e0ef0a11 732 __I uint32_t RESERVED6[683];
vcoubard 1:ebc0e0ef0a11 733 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 734 } NRF_RTC_Type;
vcoubard 1:ebc0e0ef0a11 735
vcoubard 1:ebc0e0ef0a11 736
vcoubard 1:ebc0e0ef0a11 737 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 738 /* ================ TEMP ================ */
vcoubard 1:ebc0e0ef0a11 739 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 740
vcoubard 1:ebc0e0ef0a11 741
vcoubard 1:ebc0e0ef0a11 742 /**
vcoubard 1:ebc0e0ef0a11 743 * @brief Temperature Sensor. (TEMP)
vcoubard 1:ebc0e0ef0a11 744 */
vcoubard 1:ebc0e0ef0a11 745
vcoubard 1:ebc0e0ef0a11 746 typedef struct { /*!< TEMP Structure */
vcoubard 1:ebc0e0ef0a11 747 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
vcoubard 1:ebc0e0ef0a11 748 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
vcoubard 1:ebc0e0ef0a11 749 __I uint32_t RESERVED0[62];
vcoubard 1:ebc0e0ef0a11 750 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
vcoubard 1:ebc0e0ef0a11 751 __I uint32_t RESERVED1[128];
vcoubard 1:ebc0e0ef0a11 752 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 753 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 754 __I uint32_t RESERVED2[127];
vcoubard 1:ebc0e0ef0a11 755 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
vcoubard 1:ebc0e0ef0a11 756 __I uint32_t RESERVED3[700];
vcoubard 1:ebc0e0ef0a11 757 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 758 } NRF_TEMP_Type;
vcoubard 1:ebc0e0ef0a11 759
vcoubard 1:ebc0e0ef0a11 760
vcoubard 1:ebc0e0ef0a11 761 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 762 /* ================ RNG ================ */
vcoubard 1:ebc0e0ef0a11 763 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 764
vcoubard 1:ebc0e0ef0a11 765
vcoubard 1:ebc0e0ef0a11 766 /**
vcoubard 1:ebc0e0ef0a11 767 * @brief Random Number Generator. (RNG)
vcoubard 1:ebc0e0ef0a11 768 */
vcoubard 1:ebc0e0ef0a11 769
vcoubard 1:ebc0e0ef0a11 770 typedef struct { /*!< RNG Structure */
vcoubard 1:ebc0e0ef0a11 771 __O uint32_t TASKS_START; /*!< Start the random number generator. */
vcoubard 1:ebc0e0ef0a11 772 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
vcoubard 1:ebc0e0ef0a11 773 __I uint32_t RESERVED0[62];
vcoubard 1:ebc0e0ef0a11 774 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
vcoubard 1:ebc0e0ef0a11 775 __I uint32_t RESERVED1[63];
vcoubard 1:ebc0e0ef0a11 776 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
vcoubard 1:ebc0e0ef0a11 777 __I uint32_t RESERVED2[64];
vcoubard 1:ebc0e0ef0a11 778 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
vcoubard 1:ebc0e0ef0a11 779 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
vcoubard 1:ebc0e0ef0a11 780 __I uint32_t RESERVED3[126];
vcoubard 1:ebc0e0ef0a11 781 __IO uint32_t CONFIG; /*!< Configuration register. */
vcoubard 1:ebc0e0ef0a11 782 __I uint32_t VALUE; /*!< RNG random number. */
vcoubard 1:ebc0e0ef0a11 783 __I uint32_t RESERVED4[700];
vcoubard 1:ebc0e0ef0a11 784 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 785 } NRF_RNG_Type;
vcoubard 1:ebc0e0ef0a11 786
vcoubard 1:ebc0e0ef0a11 787
vcoubard 1:ebc0e0ef0a11 788 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 789 /* ================ ECB ================ */
vcoubard 1:ebc0e0ef0a11 790 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 791
vcoubard 1:ebc0e0ef0a11 792
vcoubard 1:ebc0e0ef0a11 793 /**
vcoubard 1:ebc0e0ef0a11 794 * @brief AES ECB Mode Encryption. (ECB)
vcoubard 1:ebc0e0ef0a11 795 */
vcoubard 1:ebc0e0ef0a11 796
vcoubard 1:ebc0e0ef0a11 797 typedef struct { /*!< ECB Structure */
vcoubard 1:ebc0e0ef0a11 798 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
vcoubard 1:ebc0e0ef0a11 799 will not initiate a new encryption and the ERRORECB event will
vcoubard 1:ebc0e0ef0a11 800 be triggered. */
vcoubard 1:ebc0e0ef0a11 801 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
vcoubard 1:ebc0e0ef0a11 802 this will will trigger the ERRORECB event. */
vcoubard 1:ebc0e0ef0a11 803 __I uint32_t RESERVED0[62];
vcoubard 1:ebc0e0ef0a11 804 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
vcoubard 1:ebc0e0ef0a11 805 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
vcoubard 1:ebc0e0ef0a11 806 error. */
vcoubard 1:ebc0e0ef0a11 807 __I uint32_t RESERVED1[127];
vcoubard 1:ebc0e0ef0a11 808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 810 __I uint32_t RESERVED2[126];
vcoubard 1:ebc0e0ef0a11 811 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
vcoubard 1:ebc0e0ef0a11 812 __I uint32_t RESERVED3[701];
vcoubard 1:ebc0e0ef0a11 813 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 814 } NRF_ECB_Type;
vcoubard 1:ebc0e0ef0a11 815
vcoubard 1:ebc0e0ef0a11 816
vcoubard 1:ebc0e0ef0a11 817 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 818 /* ================ AAR ================ */
vcoubard 1:ebc0e0ef0a11 819 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 820
vcoubard 1:ebc0e0ef0a11 821
vcoubard 1:ebc0e0ef0a11 822 /**
vcoubard 1:ebc0e0ef0a11 823 * @brief Accelerated Address Resolver. (AAR)
vcoubard 1:ebc0e0ef0a11 824 */
vcoubard 1:ebc0e0ef0a11 825
vcoubard 1:ebc0e0ef0a11 826 typedef struct { /*!< AAR Structure */
vcoubard 1:ebc0e0ef0a11 827 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
vcoubard 1:ebc0e0ef0a11 828 data structure. */
vcoubard 1:ebc0e0ef0a11 829 __I uint32_t RESERVED0;
vcoubard 1:ebc0e0ef0a11 830 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
vcoubard 1:ebc0e0ef0a11 831 __I uint32_t RESERVED1[61];
vcoubard 1:ebc0e0ef0a11 832 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
vcoubard 1:ebc0e0ef0a11 833 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
vcoubard 1:ebc0e0ef0a11 834 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
vcoubard 1:ebc0e0ef0a11 835 __I uint32_t RESERVED2[126];
vcoubard 1:ebc0e0ef0a11 836 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 837 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 838 __I uint32_t RESERVED3[61];
vcoubard 1:ebc0e0ef0a11 839 __I uint32_t STATUS; /*!< Resolution status. */
vcoubard 1:ebc0e0ef0a11 840 __I uint32_t RESERVED4[63];
vcoubard 1:ebc0e0ef0a11 841 __IO uint32_t ENABLE; /*!< Enable AAR. */
vcoubard 1:ebc0e0ef0a11 842 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
vcoubard 1:ebc0e0ef0a11 843 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
vcoubard 1:ebc0e0ef0a11 844 __I uint32_t RESERVED5;
vcoubard 1:ebc0e0ef0a11 845 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
vcoubard 1:ebc0e0ef0a11 846 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
vcoubard 1:ebc0e0ef0a11 847 during resolution. A minimum of 3 bytes must be reserved. */
vcoubard 1:ebc0e0ef0a11 848 __I uint32_t RESERVED6[697];
vcoubard 1:ebc0e0ef0a11 849 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 850 } NRF_AAR_Type;
vcoubard 1:ebc0e0ef0a11 851
vcoubard 1:ebc0e0ef0a11 852
vcoubard 1:ebc0e0ef0a11 853 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 854 /* ================ CCM ================ */
vcoubard 1:ebc0e0ef0a11 855 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 856
vcoubard 1:ebc0e0ef0a11 857
vcoubard 1:ebc0e0ef0a11 858 /**
vcoubard 1:ebc0e0ef0a11 859 * @brief AES CCM Mode Encryption. (CCM)
vcoubard 1:ebc0e0ef0a11 860 */
vcoubard 1:ebc0e0ef0a11 861
vcoubard 1:ebc0e0ef0a11 862 typedef struct { /*!< CCM Structure */
vcoubard 1:ebc0e0ef0a11 863 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
vcoubard 1:ebc0e0ef0a11 864 itself when completed. */
vcoubard 1:ebc0e0ef0a11 865 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
vcoubard 1:ebc0e0ef0a11 866 completed. */
vcoubard 1:ebc0e0ef0a11 867 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
vcoubard 1:ebc0e0ef0a11 868 __I uint32_t RESERVED0[61];
vcoubard 1:ebc0e0ef0a11 869 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
vcoubard 1:ebc0e0ef0a11 870 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
vcoubard 1:ebc0e0ef0a11 871 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
vcoubard 1:ebc0e0ef0a11 872 __I uint32_t RESERVED1[61];
vcoubard 1:ebc0e0ef0a11 873 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
vcoubard 1:ebc0e0ef0a11 874 __I uint32_t RESERVED2[64];
vcoubard 1:ebc0e0ef0a11 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 877 __I uint32_t RESERVED3[61];
vcoubard 1:ebc0e0ef0a11 878 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
vcoubard 1:ebc0e0ef0a11 879 __I uint32_t RESERVED4[63];
vcoubard 1:ebc0e0ef0a11 880 __IO uint32_t ENABLE; /*!< CCM enable. */
vcoubard 1:ebc0e0ef0a11 881 __IO uint32_t MODE; /*!< Operation mode. */
vcoubard 1:ebc0e0ef0a11 882 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
vcoubard 1:ebc0e0ef0a11 883 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
vcoubard 1:ebc0e0ef0a11 884 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
vcoubard 1:ebc0e0ef0a11 885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
vcoubard 1:ebc0e0ef0a11 886 during resolution. A minimum of 43 bytes must be reserved. */
vcoubard 1:ebc0e0ef0a11 887 __I uint32_t RESERVED5[697];
vcoubard 1:ebc0e0ef0a11 888 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 889 } NRF_CCM_Type;
vcoubard 1:ebc0e0ef0a11 890
vcoubard 1:ebc0e0ef0a11 891
vcoubard 1:ebc0e0ef0a11 892 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 893 /* ================ WDT ================ */
vcoubard 1:ebc0e0ef0a11 894 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 895
vcoubard 1:ebc0e0ef0a11 896
vcoubard 1:ebc0e0ef0a11 897 /**
vcoubard 1:ebc0e0ef0a11 898 * @brief Watchdog Timer. (WDT)
vcoubard 1:ebc0e0ef0a11 899 */
vcoubard 1:ebc0e0ef0a11 900
vcoubard 1:ebc0e0ef0a11 901 typedef struct { /*!< WDT Structure */
vcoubard 1:ebc0e0ef0a11 902 __O uint32_t TASKS_START; /*!< Start the watchdog. */
vcoubard 1:ebc0e0ef0a11 903 __I uint32_t RESERVED0[63];
vcoubard 1:ebc0e0ef0a11 904 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
vcoubard 1:ebc0e0ef0a11 905 __I uint32_t RESERVED1[128];
vcoubard 1:ebc0e0ef0a11 906 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 907 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 908 __I uint32_t RESERVED2[61];
vcoubard 1:ebc0e0ef0a11 909 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
vcoubard 1:ebc0e0ef0a11 910 __I uint32_t REQSTATUS; /*!< Request status. */
vcoubard 1:ebc0e0ef0a11 911 __I uint32_t RESERVED3[63];
vcoubard 1:ebc0e0ef0a11 912 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
vcoubard 1:ebc0e0ef0a11 913 __IO uint32_t RREN; /*!< Reload request enable. */
vcoubard 1:ebc0e0ef0a11 914 __IO uint32_t CONFIG; /*!< Configuration register. */
vcoubard 1:ebc0e0ef0a11 915 __I uint32_t RESERVED4[60];
vcoubard 1:ebc0e0ef0a11 916 __O uint32_t RR[8]; /*!< Reload requests registers. */
vcoubard 1:ebc0e0ef0a11 917 __I uint32_t RESERVED5[631];
vcoubard 1:ebc0e0ef0a11 918 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 919 } NRF_WDT_Type;
vcoubard 1:ebc0e0ef0a11 920
vcoubard 1:ebc0e0ef0a11 921
vcoubard 1:ebc0e0ef0a11 922 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 923 /* ================ QDEC ================ */
vcoubard 1:ebc0e0ef0a11 924 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 925
vcoubard 1:ebc0e0ef0a11 926
vcoubard 1:ebc0e0ef0a11 927 /**
vcoubard 1:ebc0e0ef0a11 928 * @brief Rotary decoder. (QDEC)
vcoubard 1:ebc0e0ef0a11 929 */
vcoubard 1:ebc0e0ef0a11 930
vcoubard 1:ebc0e0ef0a11 931 typedef struct { /*!< QDEC Structure */
vcoubard 1:ebc0e0ef0a11 932 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
vcoubard 1:ebc0e0ef0a11 933 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
vcoubard 1:ebc0e0ef0a11 934 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
vcoubard 1:ebc0e0ef0a11 935 and clears the ACC registers. */
vcoubard 1:ebc0e0ef0a11 936 __I uint32_t RESERVED0[61];
vcoubard 1:ebc0e0ef0a11 937 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
vcoubard 1:ebc0e0ef0a11 938 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
vcoubard 1:ebc0e0ef0a11 939 ACC register different than zero. */
vcoubard 1:ebc0e0ef0a11 940 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
vcoubard 1:ebc0e0ef0a11 941 __I uint32_t RESERVED1[61];
vcoubard 1:ebc0e0ef0a11 942 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
vcoubard 1:ebc0e0ef0a11 943 __I uint32_t RESERVED2[64];
vcoubard 1:ebc0e0ef0a11 944 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 945 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 946 __I uint32_t RESERVED3[125];
vcoubard 1:ebc0e0ef0a11 947 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
vcoubard 1:ebc0e0ef0a11 948 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
vcoubard 1:ebc0e0ef0a11 949 __IO uint32_t SAMPLEPER; /*!< Sample period. */
vcoubard 1:ebc0e0ef0a11 950 __I int32_t SAMPLE; /*!< Motion sample value. */
vcoubard 1:ebc0e0ef0a11 951 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
vcoubard 1:ebc0e0ef0a11 952 __I int32_t ACC; /*!< Accumulated valid transitions register. */
vcoubard 1:ebc0e0ef0a11 953 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
vcoubard 1:ebc0e0ef0a11 954 task. */
vcoubard 1:ebc0e0ef0a11 955 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
vcoubard 1:ebc0e0ef0a11 956 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
vcoubard 1:ebc0e0ef0a11 957 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
vcoubard 1:ebc0e0ef0a11 958 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
vcoubard 1:ebc0e0ef0a11 959 __I uint32_t RESERVED4[5];
vcoubard 1:ebc0e0ef0a11 960 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
vcoubard 1:ebc0e0ef0a11 961 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
vcoubard 1:ebc0e0ef0a11 962 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
vcoubard 1:ebc0e0ef0a11 963 task. */
vcoubard 1:ebc0e0ef0a11 964 __I uint32_t RESERVED5[684];
vcoubard 1:ebc0e0ef0a11 965 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 966 } NRF_QDEC_Type;
vcoubard 1:ebc0e0ef0a11 967
vcoubard 1:ebc0e0ef0a11 968
vcoubard 1:ebc0e0ef0a11 969 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 970 /* ================ LPCOMP ================ */
vcoubard 1:ebc0e0ef0a11 971 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 972
vcoubard 1:ebc0e0ef0a11 973
vcoubard 1:ebc0e0ef0a11 974 /**
vcoubard 1:ebc0e0ef0a11 975 * @brief Low power comparator. (LPCOMP)
vcoubard 1:ebc0e0ef0a11 976 */
vcoubard 1:ebc0e0ef0a11 977
vcoubard 1:ebc0e0ef0a11 978 typedef struct { /*!< LPCOMP Structure */
vcoubard 1:ebc0e0ef0a11 979 __O uint32_t TASKS_START; /*!< Start the comparator. */
vcoubard 1:ebc0e0ef0a11 980 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
vcoubard 1:ebc0e0ef0a11 981 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
vcoubard 1:ebc0e0ef0a11 982 __I uint32_t RESERVED0[61];
vcoubard 1:ebc0e0ef0a11 983 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
vcoubard 1:ebc0e0ef0a11 984 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
vcoubard 1:ebc0e0ef0a11 985 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
vcoubard 1:ebc0e0ef0a11 986 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
vcoubard 1:ebc0e0ef0a11 987 __I uint32_t RESERVED1[60];
vcoubard 1:ebc0e0ef0a11 988 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
vcoubard 1:ebc0e0ef0a11 989 __I uint32_t RESERVED2[64];
vcoubard 1:ebc0e0ef0a11 990 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
vcoubard 1:ebc0e0ef0a11 991 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
vcoubard 1:ebc0e0ef0a11 992 __I uint32_t RESERVED3[61];
vcoubard 1:ebc0e0ef0a11 993 __I uint32_t RESULT; /*!< Result of last compare. */
vcoubard 1:ebc0e0ef0a11 994 __I uint32_t RESERVED4[63];
vcoubard 1:ebc0e0ef0a11 995 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
vcoubard 1:ebc0e0ef0a11 996 __IO uint32_t PSEL; /*!< Input pin select. */
vcoubard 1:ebc0e0ef0a11 997 __IO uint32_t REFSEL; /*!< Reference select. */
vcoubard 1:ebc0e0ef0a11 998 __IO uint32_t EXTREFSEL; /*!< External reference select. */
vcoubard 1:ebc0e0ef0a11 999 __I uint32_t RESERVED5[4];
vcoubard 1:ebc0e0ef0a11 1000 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
vcoubard 1:ebc0e0ef0a11 1001 __I uint32_t RESERVED6[694];
vcoubard 1:ebc0e0ef0a11 1002 __IO uint32_t POWER; /*!< Peripheral power control. */
vcoubard 1:ebc0e0ef0a11 1003 } NRF_LPCOMP_Type;
vcoubard 1:ebc0e0ef0a11 1004
vcoubard 1:ebc0e0ef0a11 1005
vcoubard 1:ebc0e0ef0a11 1006 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1007 /* ================ SWI ================ */
vcoubard 1:ebc0e0ef0a11 1008 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1009
vcoubard 1:ebc0e0ef0a11 1010
vcoubard 1:ebc0e0ef0a11 1011 /**
vcoubard 1:ebc0e0ef0a11 1012 * @brief SW Interrupts. (SWI)
vcoubard 1:ebc0e0ef0a11 1013 */
vcoubard 1:ebc0e0ef0a11 1014
vcoubard 1:ebc0e0ef0a11 1015 typedef struct { /*!< SWI Structure */
vcoubard 1:ebc0e0ef0a11 1016 __I uint32_t UNUSED; /*!< Unused. */
vcoubard 1:ebc0e0ef0a11 1017 } NRF_SWI_Type;
vcoubard 1:ebc0e0ef0a11 1018
vcoubard 1:ebc0e0ef0a11 1019
vcoubard 1:ebc0e0ef0a11 1020 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1021 /* ================ NVMC ================ */
vcoubard 1:ebc0e0ef0a11 1022 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1023
vcoubard 1:ebc0e0ef0a11 1024
vcoubard 1:ebc0e0ef0a11 1025 /**
vcoubard 1:ebc0e0ef0a11 1026 * @brief Non Volatile Memory Controller. (NVMC)
vcoubard 1:ebc0e0ef0a11 1027 */
vcoubard 1:ebc0e0ef0a11 1028
vcoubard 1:ebc0e0ef0a11 1029 typedef struct { /*!< NVMC Structure */
vcoubard 1:ebc0e0ef0a11 1030 __I uint32_t RESERVED0[256];
vcoubard 1:ebc0e0ef0a11 1031 __I uint32_t READY; /*!< Ready flag. */
vcoubard 1:ebc0e0ef0a11 1032 __I uint32_t RESERVED1[64];
vcoubard 1:ebc0e0ef0a11 1033 __IO uint32_t CONFIG; /*!< Configuration register. */
vcoubard 1:ebc0e0ef0a11 1034
vcoubard 1:ebc0e0ef0a11 1035 union {
vcoubard 1:ebc0e0ef0a11 1036 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
vcoubard 1:ebc0e0ef0a11 1037 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
vcoubard 1:ebc0e0ef0a11 1038 };
vcoubard 1:ebc0e0ef0a11 1039 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
vcoubard 1:ebc0e0ef0a11 1040 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
vcoubard 1:ebc0e0ef0a11 1041 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
vcoubard 1:ebc0e0ef0a11 1042 } NRF_NVMC_Type;
vcoubard 1:ebc0e0ef0a11 1043
vcoubard 1:ebc0e0ef0a11 1044
vcoubard 1:ebc0e0ef0a11 1045 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1046 /* ================ PPI ================ */
vcoubard 1:ebc0e0ef0a11 1047 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1048
vcoubard 1:ebc0e0ef0a11 1049
vcoubard 1:ebc0e0ef0a11 1050 /**
vcoubard 1:ebc0e0ef0a11 1051 * @brief PPI controller. (PPI)
vcoubard 1:ebc0e0ef0a11 1052 */
vcoubard 1:ebc0e0ef0a11 1053
vcoubard 1:ebc0e0ef0a11 1054 typedef struct { /*!< PPI Structure */
vcoubard 1:ebc0e0ef0a11 1055 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
vcoubard 1:ebc0e0ef0a11 1056 __I uint32_t RESERVED0[312];
vcoubard 1:ebc0e0ef0a11 1057 __IO uint32_t CHEN; /*!< Channel enable. */
vcoubard 1:ebc0e0ef0a11 1058 __IO uint32_t CHENSET; /*!< Channel enable set. */
vcoubard 1:ebc0e0ef0a11 1059 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
vcoubard 1:ebc0e0ef0a11 1060 __I uint32_t RESERVED1;
vcoubard 1:ebc0e0ef0a11 1061 PPI_CH_Type CH[16]; /*!< PPI Channel. */
vcoubard 1:ebc0e0ef0a11 1062 __I uint32_t RESERVED2[156];
vcoubard 1:ebc0e0ef0a11 1063 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
vcoubard 1:ebc0e0ef0a11 1064 } NRF_PPI_Type;
vcoubard 1:ebc0e0ef0a11 1065
vcoubard 1:ebc0e0ef0a11 1066
vcoubard 1:ebc0e0ef0a11 1067 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1068 /* ================ FICR ================ */
vcoubard 1:ebc0e0ef0a11 1069 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1070
vcoubard 1:ebc0e0ef0a11 1071
vcoubard 1:ebc0e0ef0a11 1072 /**
vcoubard 1:ebc0e0ef0a11 1073 * @brief Factory Information Configuration. (FICR)
vcoubard 1:ebc0e0ef0a11 1074 */
vcoubard 1:ebc0e0ef0a11 1075
vcoubard 1:ebc0e0ef0a11 1076 typedef struct { /*!< FICR Structure */
vcoubard 1:ebc0e0ef0a11 1077 __I uint32_t RESERVED0[4];
vcoubard 1:ebc0e0ef0a11 1078 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
vcoubard 1:ebc0e0ef0a11 1079 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
vcoubard 1:ebc0e0ef0a11 1080 __I uint32_t RESERVED1[4];
vcoubard 1:ebc0e0ef0a11 1081 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
vcoubard 1:ebc0e0ef0a11 1082 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
vcoubard 1:ebc0e0ef0a11 1083 __I uint32_t RESERVED2;
vcoubard 1:ebc0e0ef0a11 1084 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
vcoubard 1:ebc0e0ef0a11 1085
vcoubard 1:ebc0e0ef0a11 1086 union {
vcoubard 1:ebc0e0ef0a11 1087 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
vcoubard 1:ebc0e0ef0a11 1088 kept for backward compatinility purposes. Use SIZERAMBLOCKS
vcoubard 1:ebc0e0ef0a11 1089 instead. */
vcoubard 1:ebc0e0ef0a11 1090 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
vcoubard 1:ebc0e0ef0a11 1091 };
vcoubard 1:ebc0e0ef0a11 1092 __I uint32_t RESERVED3[5];
vcoubard 1:ebc0e0ef0a11 1093 __I uint32_t CONFIGID; /*!< Configuration identifier. */
vcoubard 1:ebc0e0ef0a11 1094 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
vcoubard 1:ebc0e0ef0a11 1095 __I uint32_t RESERVED4[6];
vcoubard 1:ebc0e0ef0a11 1096 __I uint32_t ER[4]; /*!< Encryption root. */
vcoubard 1:ebc0e0ef0a11 1097 __I uint32_t IR[4]; /*!< Identity root. */
vcoubard 1:ebc0e0ef0a11 1098 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
vcoubard 1:ebc0e0ef0a11 1099 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
vcoubard 1:ebc0e0ef0a11 1100 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
vcoubard 1:ebc0e0ef0a11 1101 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
vcoubard 1:ebc0e0ef0a11 1102 mode. */
vcoubard 1:ebc0e0ef0a11 1103 __I uint32_t RESERVED5[10];
vcoubard 1:ebc0e0ef0a11 1104 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
vcoubard 1:ebc0e0ef0a11 1105 mode. */
vcoubard 1:ebc0e0ef0a11 1106 } NRF_FICR_Type;
vcoubard 1:ebc0e0ef0a11 1107
vcoubard 1:ebc0e0ef0a11 1108
vcoubard 1:ebc0e0ef0a11 1109 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1110 /* ================ UICR ================ */
vcoubard 1:ebc0e0ef0a11 1111 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1112
vcoubard 1:ebc0e0ef0a11 1113
vcoubard 1:ebc0e0ef0a11 1114 /**
vcoubard 1:ebc0e0ef0a11 1115 * @brief User Information Configuration. (UICR)
vcoubard 1:ebc0e0ef0a11 1116 */
vcoubard 1:ebc0e0ef0a11 1117
vcoubard 1:ebc0e0ef0a11 1118 typedef struct { /*!< UICR Structure */
vcoubard 1:ebc0e0ef0a11 1119 __IO uint32_t CLENR0; /*!< Length of code region 0. */
vcoubard 1:ebc0e0ef0a11 1120 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
vcoubard 1:ebc0e0ef0a11 1121 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
vcoubard 1:ebc0e0ef0a11 1122 __I uint32_t RESERVED0;
vcoubard 1:ebc0e0ef0a11 1123 __I uint32_t FWID; /*!< Firmware ID. */
vcoubard 1:ebc0e0ef0a11 1124
vcoubard 1:ebc0e0ef0a11 1125 union {
vcoubard 1:ebc0e0ef0a11 1126 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
vcoubard 1:ebc0e0ef0a11 1127 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
vcoubard 1:ebc0e0ef0a11 1128 };
vcoubard 1:ebc0e0ef0a11 1129 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
vcoubard 1:ebc0e0ef0a11 1130 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
vcoubard 1:ebc0e0ef0a11 1131 } NRF_UICR_Type;
vcoubard 1:ebc0e0ef0a11 1132
vcoubard 1:ebc0e0ef0a11 1133
vcoubard 1:ebc0e0ef0a11 1134 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1135 /* ================ GPIO ================ */
vcoubard 1:ebc0e0ef0a11 1136 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1137
vcoubard 1:ebc0e0ef0a11 1138
vcoubard 1:ebc0e0ef0a11 1139 /**
vcoubard 1:ebc0e0ef0a11 1140 * @brief General purpose input and output. (GPIO)
vcoubard 1:ebc0e0ef0a11 1141 */
vcoubard 1:ebc0e0ef0a11 1142
vcoubard 1:ebc0e0ef0a11 1143 typedef struct { /*!< GPIO Structure */
vcoubard 1:ebc0e0ef0a11 1144 __I uint32_t RESERVED0[321];
vcoubard 1:ebc0e0ef0a11 1145 __IO uint32_t OUT; /*!< Write GPIO port. */
vcoubard 1:ebc0e0ef0a11 1146 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
vcoubard 1:ebc0e0ef0a11 1147 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
vcoubard 1:ebc0e0ef0a11 1148 __I uint32_t IN; /*!< Read GPIO port. */
vcoubard 1:ebc0e0ef0a11 1149 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
vcoubard 1:ebc0e0ef0a11 1150 __IO uint32_t DIRSET; /*!< DIR set register. */
vcoubard 1:ebc0e0ef0a11 1151 __IO uint32_t DIRCLR; /*!< DIR clear register. */
vcoubard 1:ebc0e0ef0a11 1152 __I uint32_t RESERVED1[120];
vcoubard 1:ebc0e0ef0a11 1153 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
vcoubard 1:ebc0e0ef0a11 1154 } NRF_GPIO_Type;
vcoubard 1:ebc0e0ef0a11 1155
vcoubard 1:ebc0e0ef0a11 1156
vcoubard 1:ebc0e0ef0a11 1157 /* -------------------- End of section using anonymous unions ------------------- */
vcoubard 1:ebc0e0ef0a11 1158 #if defined(__CC_ARM)
vcoubard 1:ebc0e0ef0a11 1159 #pragma pop
vcoubard 1:ebc0e0ef0a11 1160 #elif defined(__ICCARM__)
vcoubard 1:ebc0e0ef0a11 1161 /* leave anonymous unions enabled */
vcoubard 1:ebc0e0ef0a11 1162 #elif defined(__GNUC__)
vcoubard 1:ebc0e0ef0a11 1163 /* anonymous unions are enabled by default */
vcoubard 1:ebc0e0ef0a11 1164 #elif defined(__TMS470__)
vcoubard 1:ebc0e0ef0a11 1165 /* anonymous unions are enabled by default */
vcoubard 1:ebc0e0ef0a11 1166 #elif defined(__TASKING__)
vcoubard 1:ebc0e0ef0a11 1167 #pragma warning restore
vcoubard 1:ebc0e0ef0a11 1168 #else
vcoubard 1:ebc0e0ef0a11 1169 #warning Not supported compiler type
vcoubard 1:ebc0e0ef0a11 1170 #endif
vcoubard 1:ebc0e0ef0a11 1171
vcoubard 1:ebc0e0ef0a11 1172
vcoubard 1:ebc0e0ef0a11 1173
vcoubard 1:ebc0e0ef0a11 1174
vcoubard 1:ebc0e0ef0a11 1175 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1176 /* ================ Peripheral memory map ================ */
vcoubard 1:ebc0e0ef0a11 1177 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1178
vcoubard 1:ebc0e0ef0a11 1179 #define NRF_POWER_BASE 0x40000000UL
vcoubard 1:ebc0e0ef0a11 1180 #define NRF_CLOCK_BASE 0x40000000UL
vcoubard 1:ebc0e0ef0a11 1181 #define NRF_MPU_BASE 0x40000000UL
vcoubard 1:ebc0e0ef0a11 1182 #define NRF_AMLI_BASE 0x40000000UL
vcoubard 1:ebc0e0ef0a11 1183 #define NRF_RADIO_BASE 0x40001000UL
vcoubard 1:ebc0e0ef0a11 1184 #define NRF_UART0_BASE 0x40002000UL
vcoubard 1:ebc0e0ef0a11 1185 #define NRF_SPI0_BASE 0x40003000UL
vcoubard 1:ebc0e0ef0a11 1186 #define NRF_TWI0_BASE 0x40003000UL
vcoubard 1:ebc0e0ef0a11 1187 #define NRF_SPI1_BASE 0x40004000UL
vcoubard 1:ebc0e0ef0a11 1188 #define NRF_TWI1_BASE 0x40004000UL
vcoubard 1:ebc0e0ef0a11 1189 #define NRF_SPIS1_BASE 0x40004000UL
vcoubard 1:ebc0e0ef0a11 1190 #define NRF_SPIM1_BASE 0x40004000UL
vcoubard 1:ebc0e0ef0a11 1191 #define NRF_GPIOTE_BASE 0x40006000UL
vcoubard 1:ebc0e0ef0a11 1192 #define NRF_ADC_BASE 0x40007000UL
vcoubard 1:ebc0e0ef0a11 1193 #define NRF_TIMER0_BASE 0x40008000UL
vcoubard 1:ebc0e0ef0a11 1194 #define NRF_TIMER1_BASE 0x40009000UL
vcoubard 1:ebc0e0ef0a11 1195 #define NRF_TIMER2_BASE 0x4000A000UL
vcoubard 1:ebc0e0ef0a11 1196 #define NRF_RTC0_BASE 0x4000B000UL
vcoubard 1:ebc0e0ef0a11 1197 #define NRF_TEMP_BASE 0x4000C000UL
vcoubard 1:ebc0e0ef0a11 1198 #define NRF_RNG_BASE 0x4000D000UL
vcoubard 1:ebc0e0ef0a11 1199 #define NRF_ECB_BASE 0x4000E000UL
vcoubard 1:ebc0e0ef0a11 1200 #define NRF_AAR_BASE 0x4000F000UL
vcoubard 1:ebc0e0ef0a11 1201 #define NRF_CCM_BASE 0x4000F000UL
vcoubard 1:ebc0e0ef0a11 1202 #define NRF_WDT_BASE 0x40010000UL
vcoubard 1:ebc0e0ef0a11 1203 #define NRF_RTC1_BASE 0x40011000UL
vcoubard 1:ebc0e0ef0a11 1204 #define NRF_QDEC_BASE 0x40012000UL
vcoubard 1:ebc0e0ef0a11 1205 #define NRF_LPCOMP_BASE 0x40013000UL
vcoubard 1:ebc0e0ef0a11 1206 #define NRF_SWI_BASE 0x40014000UL
vcoubard 1:ebc0e0ef0a11 1207 #define NRF_NVMC_BASE 0x4001E000UL
vcoubard 1:ebc0e0ef0a11 1208 #define NRF_PPI_BASE 0x4001F000UL
vcoubard 1:ebc0e0ef0a11 1209 #define NRF_FICR_BASE 0x10000000UL
vcoubard 1:ebc0e0ef0a11 1210 #define NRF_UICR_BASE 0x10001000UL
vcoubard 1:ebc0e0ef0a11 1211 #define NRF_GPIO_BASE 0x50000000UL
vcoubard 1:ebc0e0ef0a11 1212
vcoubard 1:ebc0e0ef0a11 1213
vcoubard 1:ebc0e0ef0a11 1214 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1215 /* ================ Peripheral declaration ================ */
vcoubard 1:ebc0e0ef0a11 1216 /* ================================================================================ */
vcoubard 1:ebc0e0ef0a11 1217
vcoubard 1:ebc0e0ef0a11 1218 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
vcoubard 1:ebc0e0ef0a11 1219 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
vcoubard 1:ebc0e0ef0a11 1220 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
vcoubard 1:ebc0e0ef0a11 1221 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
vcoubard 1:ebc0e0ef0a11 1222 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
vcoubard 1:ebc0e0ef0a11 1223 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
vcoubard 1:ebc0e0ef0a11 1224 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
vcoubard 1:ebc0e0ef0a11 1225 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
vcoubard 1:ebc0e0ef0a11 1226 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
vcoubard 1:ebc0e0ef0a11 1227 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
vcoubard 1:ebc0e0ef0a11 1228 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
vcoubard 1:ebc0e0ef0a11 1229 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
vcoubard 1:ebc0e0ef0a11 1230 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
vcoubard 1:ebc0e0ef0a11 1231 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
vcoubard 1:ebc0e0ef0a11 1232 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
vcoubard 1:ebc0e0ef0a11 1233 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
vcoubard 1:ebc0e0ef0a11 1234 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
vcoubard 1:ebc0e0ef0a11 1235 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
vcoubard 1:ebc0e0ef0a11 1236 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
vcoubard 1:ebc0e0ef0a11 1237 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
vcoubard 1:ebc0e0ef0a11 1238 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
vcoubard 1:ebc0e0ef0a11 1239 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
vcoubard 1:ebc0e0ef0a11 1240 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
vcoubard 1:ebc0e0ef0a11 1241 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
vcoubard 1:ebc0e0ef0a11 1242 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
vcoubard 1:ebc0e0ef0a11 1243 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
vcoubard 1:ebc0e0ef0a11 1244 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
vcoubard 1:ebc0e0ef0a11 1245 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
vcoubard 1:ebc0e0ef0a11 1246 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
vcoubard 1:ebc0e0ef0a11 1247 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
vcoubard 1:ebc0e0ef0a11 1248 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
vcoubard 1:ebc0e0ef0a11 1249 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
vcoubard 1:ebc0e0ef0a11 1250 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
vcoubard 1:ebc0e0ef0a11 1251
vcoubard 1:ebc0e0ef0a11 1252
vcoubard 1:ebc0e0ef0a11 1253 /** @} */ /* End of group Device_Peripheral_Registers */
vcoubard 1:ebc0e0ef0a11 1254 /** @} */ /* End of group nrf51 */
vcoubard 1:ebc0e0ef0a11 1255 /** @} */ /* End of group Nordic Semiconductor */
vcoubard 1:ebc0e0ef0a11 1256
vcoubard 1:ebc0e0ef0a11 1257 #ifdef __cplusplus
vcoubard 1:ebc0e0ef0a11 1258 }
vcoubard 1:ebc0e0ef0a11 1259 #endif
vcoubard 1:ebc0e0ef0a11 1260
vcoubard 1:ebc0e0ef0a11 1261
vcoubard 1:ebc0e0ef0a11 1262 #endif /* nrf51_H */
vcoubard 1:ebc0e0ef0a11 1263