nrf51-sdk - my fork of nrf51-sdk

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my fork of nrf51-sdk

Fork of nrf51-sdk by Nordic Semiconductor

source/nordic_sdk/components/device/nrf51.h@29:286940b7ee5a, 2016-04-07 (annotated)

Committer:: vcoubard
Date:: Thu Apr 07 17:38:01 2016 +0100
Revision:: 29:286940b7ee5a
Parent:: 28:041dac1366b2
Child:: 30:7193e01c2913

Synchronized with git rev 22c7454f

Author: Liyou Zhou

Add copyright license headers.

Who changed what in which revision?

User	Revision	Line number	New contents of line
vcoubard	29:286940b7ee5a	1	/*
vcoubard	29:286940b7ee5a	2	* Copyright (c) Nordic Semiconductor ASA
vcoubard	29:286940b7ee5a	3	* All rights reserved.
vcoubard	29:286940b7ee5a	4	*
vcoubard	29:286940b7ee5a	5	* Redistribution and use in source and binary forms, with or without modification,
vcoubard	29:286940b7ee5a	6	* are permitted provided that the following conditions are met:
vcoubard	29:286940b7ee5a	7	*
vcoubard	29:286940b7ee5a	8	* 1. Redistributions of source code must retain the above copyright notice, this
vcoubard	29:286940b7ee5a	9	* list of conditions and the following disclaimer.
vcoubard	29:286940b7ee5a	10	*
vcoubard	29:286940b7ee5a	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
vcoubard	29:286940b7ee5a	12	* list of conditions and the following disclaimer in the documentation and/or
vcoubard	29:286940b7ee5a	13	* other materials provided with the distribution.
vcoubard	29:286940b7ee5a	14	*
vcoubard	29:286940b7ee5a	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
vcoubard	29:286940b7ee5a	16	* contributors to this software may be used to endorse or promote products
vcoubard	29:286940b7ee5a	17	* derived from this software without specific prior written permission.
vcoubard	29:286940b7ee5a	18	*
vcoubard	29:286940b7ee5a	19	*
vcoubard	29:286940b7ee5a	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vcoubard	29:286940b7ee5a	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vcoubard	29:286940b7ee5a	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vcoubard	29:286940b7ee5a	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vcoubard	29:286940b7ee5a	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vcoubard	29:286940b7ee5a	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vcoubard	29:286940b7ee5a	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vcoubard	29:286940b7ee5a	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vcoubard	29:286940b7ee5a	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vcoubard	29:286940b7ee5a	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vcoubard	29:286940b7ee5a	30	*
vcoubard	29:286940b7ee5a	31	*/
vcoubard	29:286940b7ee5a	32
vcoubard	28:041dac1366b2	33
vcoubard	28:041dac1366b2	34	/**************************************************************************************************//
vcoubard	28:041dac1366b2	35	* @file nrf51.h
vcoubard	28:041dac1366b2	36	*
vcoubard	28:041dac1366b2	37	* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
vcoubard	28:041dac1366b2	38	* nrf51 from Nordic Semiconductor.
vcoubard	28:041dac1366b2	39	*
vcoubard	28:041dac1366b2	40	* @version V522
vcoubard	28:041dac1366b2	41	* @date 20. October 2015
vcoubard	28:041dac1366b2	42	*
vcoubard	28:041dac1366b2	43	* @note Generated with SVDConv V2.81d
vcoubard	28:041dac1366b2	44	* from CMSIS SVD File 'nrf51.svd' Version 522,
vcoubard	28:041dac1366b2	45	*
vcoubard	28:041dac1366b2	46	* @par Copyright (c) 2013, Nordic Semiconductor ASA
vcoubard	28:041dac1366b2	47	* All rights reserved.
vcoubard	28:041dac1366b2	48	*
vcoubard	28:041dac1366b2	49	* Redistribution and use in source and binary forms, with or without
vcoubard	28:041dac1366b2	50	* modification, are permitted provided that the following conditions are met:
vcoubard	28:041dac1366b2	51	*
vcoubard	28:041dac1366b2	52	* * Redistributions of source code must retain the above copyright notice, this
vcoubard	28:041dac1366b2	53	* list of conditions and the following disclaimer.
vcoubard	28:041dac1366b2	54	*
vcoubard	28:041dac1366b2	55	* * Redistributions in binary form must reproduce the above copyright notice,
vcoubard	28:041dac1366b2	56	* this list of conditions and the following disclaimer in the documentation
vcoubard	28:041dac1366b2	57	* and/or other materials provided with the distribution.
vcoubard	28:041dac1366b2	58	*
vcoubard	28:041dac1366b2	59	* * Neither the name of Nordic Semiconductor ASA nor the names of its
vcoubard	28:041dac1366b2	60	* contributors may be used to endorse or promote products derived from
vcoubard	28:041dac1366b2	61	* this software without specific prior written permission.
vcoubard	28:041dac1366b2	62	*
vcoubard	28:041dac1366b2	63	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vcoubard	28:041dac1366b2	64	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vcoubard	28:041dac1366b2	65	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vcoubard	28:041dac1366b2	66	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vcoubard	28:041dac1366b2	67	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vcoubard	28:041dac1366b2	68	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vcoubard	28:041dac1366b2	69	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vcoubard	28:041dac1366b2	70	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vcoubard	28:041dac1366b2	71	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vcoubard	28:041dac1366b2	72	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vcoubard	28:041dac1366b2	73	*
vcoubard	28:041dac1366b2	74	*
vcoubard	28:041dac1366b2	75	*******************************************************************************************************/
vcoubard	28:041dac1366b2	76
vcoubard	28:041dac1366b2	77
vcoubard	28:041dac1366b2	78
vcoubard	28:041dac1366b2	79	/** @addtogroup Nordic Semiconductor
vcoubard	28:041dac1366b2	80	* @{
vcoubard	28:041dac1366b2	81	*/
vcoubard	28:041dac1366b2	82
vcoubard	28:041dac1366b2	83	/** @addtogroup nrf51
vcoubard	28:041dac1366b2	84	* @{
vcoubard	28:041dac1366b2	85	*/
vcoubard	27:0fe148f1bca3	86
vcoubard	1:ebc0e0ef0a11	87	#ifndef NRF51_H
vcoubard	1:ebc0e0ef0a11	88	#define NRF51_H
vcoubard	1:ebc0e0ef0a11	89
vcoubard	1:ebc0e0ef0a11	90	#ifdef __cplusplus
vcoubard	1:ebc0e0ef0a11	91	extern "C" {
vcoubard	1:ebc0e0ef0a11	92	#endif
vcoubard	1:ebc0e0ef0a11	93
vcoubard	1:ebc0e0ef0a11	94
vcoubard	1:ebc0e0ef0a11	95	/* ------------------------- Interrupt Number Definition ------------------------ */
vcoubard	1:ebc0e0ef0a11	96
vcoubard	1:ebc0e0ef0a11	97	typedef enum {
vcoubard	1:ebc0e0ef0a11	98	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
vcoubard	1:ebc0e0ef0a11	99	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
vcoubard	1:ebc0e0ef0a11	100	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
vcoubard	1:ebc0e0ef0a11	101	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
vcoubard	1:ebc0e0ef0a11	102	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
vcoubard	1:ebc0e0ef0a11	103	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
vcoubard	1:ebc0e0ef0a11	104	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
vcoubard	1:ebc0e0ef0a11	105	SysTick_IRQn = -1, /!< 15 System Tick Timer /
vcoubard	1:ebc0e0ef0a11	106	/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
vcoubard	1:ebc0e0ef0a11	107	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
vcoubard	1:ebc0e0ef0a11	108	RADIO_IRQn = 1, /!< 1 RADIO /
vcoubard	1:ebc0e0ef0a11	109	UART0_IRQn = 2, /!< 2 UART0 /
vcoubard	1:ebc0e0ef0a11	110	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
vcoubard	1:ebc0e0ef0a11	111	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
vcoubard	1:ebc0e0ef0a11	112	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
vcoubard	1:ebc0e0ef0a11	113	ADC_IRQn = 7, /!< 7 ADC /
vcoubard	1:ebc0e0ef0a11	114	TIMER0_IRQn = 8, /!< 8 TIMER0 /
vcoubard	1:ebc0e0ef0a11	115	TIMER1_IRQn = 9, /!< 9 TIMER1 /
vcoubard	1:ebc0e0ef0a11	116	TIMER2_IRQn = 10, /!< 10 TIMER2 /
vcoubard	1:ebc0e0ef0a11	117	RTC0_IRQn = 11, /!< 11 RTC0 /
vcoubard	1:ebc0e0ef0a11	118	TEMP_IRQn = 12, /!< 12 TEMP /
vcoubard	1:ebc0e0ef0a11	119	RNG_IRQn = 13, /!< 13 RNG /
vcoubard	1:ebc0e0ef0a11	120	ECB_IRQn = 14, /!< 14 ECB /
vcoubard	1:ebc0e0ef0a11	121	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
vcoubard	1:ebc0e0ef0a11	122	WDT_IRQn = 16, /!< 16 WDT /
vcoubard	1:ebc0e0ef0a11	123	RTC1_IRQn = 17, /!< 17 RTC1 /
vcoubard	1:ebc0e0ef0a11	124	QDEC_IRQn = 18, /!< 18 QDEC /
vcoubard	1:ebc0e0ef0a11	125	LPCOMP_IRQn = 19, /!< 19 LPCOMP /
vcoubard	1:ebc0e0ef0a11	126	SWI0_IRQn = 20, /!< 20 SWI0 /
vcoubard	1:ebc0e0ef0a11	127	SWI1_IRQn = 21, /!< 21 SWI1 /
vcoubard	1:ebc0e0ef0a11	128	SWI2_IRQn = 22, /!< 22 SWI2 /
vcoubard	1:ebc0e0ef0a11	129	SWI3_IRQn = 23, /!< 23 SWI3 /
vcoubard	1:ebc0e0ef0a11	130	SWI4_IRQn = 24, /!< 24 SWI4 /
vcoubard	1:ebc0e0ef0a11	131	SWI5_IRQn = 25 /!< 25 SWI5 /
vcoubard	1:ebc0e0ef0a11	132	} IRQn_Type;
vcoubard	1:ebc0e0ef0a11	133
vcoubard	1:ebc0e0ef0a11	134
vcoubard	1:ebc0e0ef0a11	135	/** @addtogroup Configuration_of_CMSIS
vcoubard	1:ebc0e0ef0a11	136	* @{
vcoubard	1:ebc0e0ef0a11	137	*/
vcoubard	1:ebc0e0ef0a11	138
vcoubard	1:ebc0e0ef0a11	139
vcoubard	1:ebc0e0ef0a11	140	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	141	/* ================ Processor and Core Peripheral Section ================ */
vcoubard	1:ebc0e0ef0a11	142	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	143
vcoubard	1:ebc0e0ef0a11	144	/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
vcoubard	1:ebc0e0ef0a11	145	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
vcoubard	1:ebc0e0ef0a11	146	#define __MPU_PRESENT 0 /!< MPU present or not /
vcoubard	1:ebc0e0ef0a11	147	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
vcoubard	1:ebc0e0ef0a11	148	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
vcoubard	1:ebc0e0ef0a11	149	/** @} / / End of group Configuration_of_CMSIS */
vcoubard	1:ebc0e0ef0a11	150
vcoubard	1:ebc0e0ef0a11	151	#include "core_cm0.h" /!< Cortex-M0 processor and core peripherals /
vcoubard	1:ebc0e0ef0a11	152	#include "system_nrf51.h" /!< nrf51 System /
vcoubard	1:ebc0e0ef0a11	153
vcoubard	1:ebc0e0ef0a11	154
vcoubard	1:ebc0e0ef0a11	155	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	156	/* ================ Device Specific Peripheral Section ================ */
vcoubard	1:ebc0e0ef0a11	157	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	158
vcoubard	1:ebc0e0ef0a11	159
vcoubard	1:ebc0e0ef0a11	160	/** @addtogroup Device_Peripheral_Registers
vcoubard	1:ebc0e0ef0a11	161	* @{
vcoubard	1:ebc0e0ef0a11	162	*/
vcoubard	1:ebc0e0ef0a11	163
vcoubard	1:ebc0e0ef0a11	164
vcoubard	1:ebc0e0ef0a11	165	/* ------------------- Start of section using anonymous unions ------------------ */
vcoubard	1:ebc0e0ef0a11	166	#if defined(__CC_ARM)
vcoubard	1:ebc0e0ef0a11	167	#pragma push
vcoubard	1:ebc0e0ef0a11	168	#pragma anon_unions
vcoubard	1:ebc0e0ef0a11	169	#elif defined(__ICCARM__)
vcoubard	1:ebc0e0ef0a11	170	#pragma language=extended
vcoubard	1:ebc0e0ef0a11	171	#elif defined(__GNUC__)
vcoubard	1:ebc0e0ef0a11	172	/* anonymous unions are enabled by default */
vcoubard	1:ebc0e0ef0a11	173	#elif defined(__TMS470__)
vcoubard	1:ebc0e0ef0a11	174	/* anonymous unions are enabled by default */
vcoubard	1:ebc0e0ef0a11	175	#elif defined(__TASKING__)
vcoubard	1:ebc0e0ef0a11	176	#pragma warning 586
vcoubard	1:ebc0e0ef0a11	177	#else
vcoubard	1:ebc0e0ef0a11	178	#warning Not supported compiler type
vcoubard	1:ebc0e0ef0a11	179	#endif
vcoubard	1:ebc0e0ef0a11	180
vcoubard	1:ebc0e0ef0a11	181
vcoubard	1:ebc0e0ef0a11	182	typedef struct {
vcoubard	1:ebc0e0ef0a11	183	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
vcoubard	1:ebc0e0ef0a11	184	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
vcoubard	1:ebc0e0ef0a11	185	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
vcoubard	1:ebc0e0ef0a11	186	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
vcoubard	1:ebc0e0ef0a11	187	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
vcoubard	1:ebc0e0ef0a11	188	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
vcoubard	1:ebc0e0ef0a11	189	} AMLI_RAMPRI_Type;
vcoubard	1:ebc0e0ef0a11	190
vcoubard	1:ebc0e0ef0a11	191	typedef struct {
vcoubard	1:ebc0e0ef0a11	192	__IO uint32_t SCK; /!< Pin select for SCK. /
vcoubard	1:ebc0e0ef0a11	193	__IO uint32_t MOSI; /!< Pin select for MOSI. /
vcoubard	1:ebc0e0ef0a11	194	__IO uint32_t MISO; /!< Pin select for MISO. /
vcoubard	1:ebc0e0ef0a11	195	} SPIM_PSEL_Type;
vcoubard	1:ebc0e0ef0a11	196
vcoubard	1:ebc0e0ef0a11	197	typedef struct {
vcoubard	1:ebc0e0ef0a11	198	__IO uint32_t PTR; /!< Data pointer. /
vcoubard	1:ebc0e0ef0a11	199	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to receive. /
vcoubard	1:ebc0e0ef0a11	200	__I uint32_t AMOUNT; /!< Number of bytes received in the last transaction. /
vcoubard	1:ebc0e0ef0a11	201	} SPIM_RXD_Type;
vcoubard	1:ebc0e0ef0a11	202
vcoubard	1:ebc0e0ef0a11	203	typedef struct {
vcoubard	1:ebc0e0ef0a11	204	__IO uint32_t PTR; /!< Data pointer. /
vcoubard	1:ebc0e0ef0a11	205	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to send. /
vcoubard	1:ebc0e0ef0a11	206	__I uint32_t AMOUNT; /!< Number of bytes sent in the last transaction. /
vcoubard	1:ebc0e0ef0a11	207	} SPIM_TXD_Type;
vcoubard	1:ebc0e0ef0a11	208
vcoubard	1:ebc0e0ef0a11	209	typedef struct {
vcoubard	1:ebc0e0ef0a11	210	__O uint32_t EN; /!< Enable channel group. /
vcoubard	1:ebc0e0ef0a11	211	__O uint32_t DIS; /!< Disable channel group. /
vcoubard	1:ebc0e0ef0a11	212	} PPI_TASKS_CHG_Type;
vcoubard	1:ebc0e0ef0a11	213
vcoubard	1:ebc0e0ef0a11	214	typedef struct {
vcoubard	1:ebc0e0ef0a11	215	__IO uint32_t EEP; /!< Channel event end-point. /
vcoubard	1:ebc0e0ef0a11	216	__IO uint32_t TEP; /!< Channel task end-point. /
vcoubard	1:ebc0e0ef0a11	217	} PPI_CH_Type;
vcoubard	1:ebc0e0ef0a11	218
vcoubard	1:ebc0e0ef0a11	219
vcoubard	1:ebc0e0ef0a11	220	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	221	/* ================ POWER ================ */
vcoubard	1:ebc0e0ef0a11	222	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	223
vcoubard	1:ebc0e0ef0a11	224
vcoubard	1:ebc0e0ef0a11	225	/**
vcoubard	1:ebc0e0ef0a11	226	* @brief Power Control. (POWER)
vcoubard	1:ebc0e0ef0a11	227	*/
vcoubard	1:ebc0e0ef0a11	228
vcoubard	1:ebc0e0ef0a11	229	typedef struct { /!< POWER Structure /
vcoubard	1:ebc0e0ef0a11	230	__I uint32_t RESERVED0[30];
vcoubard	1:ebc0e0ef0a11	231	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
vcoubard	1:ebc0e0ef0a11	232	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
vcoubard	1:ebc0e0ef0a11	233	__I uint32_t RESERVED1[34];
vcoubard	1:ebc0e0ef0a11	234	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
vcoubard	1:ebc0e0ef0a11	235	__I uint32_t RESERVED2[126];
vcoubard	1:ebc0e0ef0a11	236	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	237	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	238	__I uint32_t RESERVED3[61];
vcoubard	1:ebc0e0ef0a11	239	__IO uint32_t RESETREAS; /!< Reset reason. /
vcoubard	1:ebc0e0ef0a11	240	__I uint32_t RESERVED4[9];
vcoubard	1:ebc0e0ef0a11	241	__I uint32_t RAMSTATUS; /!< Ram status register. /
vcoubard	1:ebc0e0ef0a11	242	__I uint32_t RESERVED5[53];
vcoubard	1:ebc0e0ef0a11	243	__O uint32_t SYSTEMOFF; /!< System off register. /
vcoubard	1:ebc0e0ef0a11	244	__I uint32_t RESERVED6[3];
vcoubard	1:ebc0e0ef0a11	245	__IO uint32_t POFCON; /!< Power failure configuration. /
vcoubard	1:ebc0e0ef0a11	246	__I uint32_t RESERVED7[2];
vcoubard	1:ebc0e0ef0a11	247	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
vcoubard	1:ebc0e0ef0a11	248	register. */
vcoubard	1:ebc0e0ef0a11	249	__I uint32_t RESERVED8;
vcoubard	1:ebc0e0ef0a11	250	__IO uint32_t RAMON; /!< Ram on/off. /
vcoubard	1:ebc0e0ef0a11	251	__I uint32_t RESERVED9[7];
vcoubard	1:ebc0e0ef0a11	252	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
vcoubard	1:ebc0e0ef0a11	253	is a retained register. */
vcoubard	1:ebc0e0ef0a11	254	__I uint32_t RESERVED10[3];
vcoubard	1:ebc0e0ef0a11	255	__IO uint32_t RAMONB; /!< Ram on/off. /
vcoubard	1:ebc0e0ef0a11	256	__I uint32_t RESERVED11[8];
vcoubard	1:ebc0e0ef0a11	257	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
vcoubard	1:ebc0e0ef0a11	258	__I uint32_t RESERVED12[291];
vcoubard	1:ebc0e0ef0a11	259	__IO uint32_t DCDCFORCE; /!< DCDC power-up force register. /
vcoubard	1:ebc0e0ef0a11	260	} NRF_POWER_Type;
vcoubard	1:ebc0e0ef0a11	261
vcoubard	1:ebc0e0ef0a11	262
vcoubard	1:ebc0e0ef0a11	263	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	264	/* ================ CLOCK ================ */
vcoubard	1:ebc0e0ef0a11	265	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	266
vcoubard	1:ebc0e0ef0a11	267
vcoubard	1:ebc0e0ef0a11	268	/**
vcoubard	1:ebc0e0ef0a11	269	* @brief Clock control. (CLOCK)
vcoubard	1:ebc0e0ef0a11	270	*/
vcoubard	1:ebc0e0ef0a11	271
vcoubard	1:ebc0e0ef0a11	272	typedef struct { /!< CLOCK Structure /
vcoubard	1:ebc0e0ef0a11	273	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
vcoubard	1:ebc0e0ef0a11	274	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
vcoubard	1:ebc0e0ef0a11	275	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
vcoubard	1:ebc0e0ef0a11	276	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
vcoubard	1:ebc0e0ef0a11	277	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
vcoubard	1:ebc0e0ef0a11	278	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
vcoubard	1:ebc0e0ef0a11	279	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
vcoubard	1:ebc0e0ef0a11	280	__I uint32_t RESERVED0[57];
vcoubard	1:ebc0e0ef0a11	281	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
vcoubard	1:ebc0e0ef0a11	282	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
vcoubard	1:ebc0e0ef0a11	283	__I uint32_t RESERVED1;
vcoubard	1:ebc0e0ef0a11	284	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator completed. /
vcoubard	1:ebc0e0ef0a11	285	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout. /
vcoubard	1:ebc0e0ef0a11	286	__I uint32_t RESERVED2[124];
vcoubard	1:ebc0e0ef0a11	287	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	288	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	289	__I uint32_t RESERVED3[63];
vcoubard	1:ebc0e0ef0a11	290	__I uint32_t HFCLKRUN; /!< Task HFCLKSTART trigger status. /
vcoubard	1:ebc0e0ef0a11	291	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
vcoubard	1:ebc0e0ef0a11	292	__I uint32_t RESERVED4;
vcoubard	1:ebc0e0ef0a11	293	__I uint32_t LFCLKRUN; /!< Task LFCLKSTART triggered status. /
vcoubard	1:ebc0e0ef0a11	294	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
vcoubard	1:ebc0e0ef0a11	295	__I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
vcoubard	1:ebc0e0ef0a11	296	triggered. */
vcoubard	1:ebc0e0ef0a11	297	__I uint32_t RESERVED5[62];
vcoubard	1:ebc0e0ef0a11	298	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
vcoubard	1:ebc0e0ef0a11	299	__I uint32_t RESERVED6[7];
vcoubard	1:ebc0e0ef0a11	300	__IO uint32_t CTIV; /!< Calibration timer interval. /
vcoubard	1:ebc0e0ef0a11	301	__I uint32_t RESERVED7[5];
vcoubard	1:ebc0e0ef0a11	302	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
vcoubard	1:ebc0e0ef0a11	303	} NRF_CLOCK_Type;
vcoubard	1:ebc0e0ef0a11	304
vcoubard	1:ebc0e0ef0a11	305
vcoubard	1:ebc0e0ef0a11	306	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	307	/* ================ MPU ================ */
vcoubard	1:ebc0e0ef0a11	308	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	309
vcoubard	1:ebc0e0ef0a11	310
vcoubard	1:ebc0e0ef0a11	311	/**
vcoubard	1:ebc0e0ef0a11	312	* @brief Memory Protection Unit. (MPU)
vcoubard	1:ebc0e0ef0a11	313	*/
vcoubard	1:ebc0e0ef0a11	314
vcoubard	1:ebc0e0ef0a11	315	typedef struct { /!< MPU Structure /
vcoubard	1:ebc0e0ef0a11	316	__I uint32_t RESERVED0[330];
vcoubard	1:ebc0e0ef0a11	317	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
vcoubard	1:ebc0e0ef0a11	318	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
vcoubard	1:ebc0e0ef0a11	319	__I uint32_t RESERVED1[52];
vcoubard	1:ebc0e0ef0a11	320	__IO uint32_t PROTENSET0; /!< Erase and write protection bit enable set register. /
vcoubard	1:ebc0e0ef0a11	321	__IO uint32_t PROTENSET1; /!< Erase and write protection bit enable set register. /
vcoubard	1:ebc0e0ef0a11	322	__IO uint32_t DISABLEINDEBUG; /!< Disable erase and write protection mechanism in debug mode. /
vcoubard	1:ebc0e0ef0a11	323	__IO uint32_t PROTBLOCKSIZE; /!< Erase and write protection block size. /
vcoubard	1:ebc0e0ef0a11	324	} NRF_MPU_Type;
vcoubard	1:ebc0e0ef0a11	325
vcoubard	1:ebc0e0ef0a11	326
vcoubard	1:ebc0e0ef0a11	327	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	328	/* ================ AMLI ================ */
vcoubard	1:ebc0e0ef0a11	329	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	330
vcoubard	1:ebc0e0ef0a11	331
vcoubard	1:ebc0e0ef0a11	332	/**
vcoubard	1:ebc0e0ef0a11	333	* @brief AHB Multi-Layer Interface. (AMLI)
vcoubard	1:ebc0e0ef0a11	334	*/
vcoubard	1:ebc0e0ef0a11	335
vcoubard	1:ebc0e0ef0a11	336	typedef struct { /!< AMLI Structure /
vcoubard	1:ebc0e0ef0a11	337	__I uint32_t RESERVED0[896];
vcoubard	1:ebc0e0ef0a11	338	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
vcoubard	1:ebc0e0ef0a11	339	} NRF_AMLI_Type;
vcoubard	1:ebc0e0ef0a11	340
vcoubard	1:ebc0e0ef0a11	341
vcoubard	1:ebc0e0ef0a11	342	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	343	/* ================ RADIO ================ */
vcoubard	1:ebc0e0ef0a11	344	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	345
vcoubard	1:ebc0e0ef0a11	346
vcoubard	1:ebc0e0ef0a11	347	/**
vcoubard	1:ebc0e0ef0a11	348	* @brief The radio. (RADIO)
vcoubard	1:ebc0e0ef0a11	349	*/
vcoubard	1:ebc0e0ef0a11	350
vcoubard	1:ebc0e0ef0a11	351	typedef struct { /!< RADIO Structure /
vcoubard	1:ebc0e0ef0a11	352	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
vcoubard	1:ebc0e0ef0a11	353	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
vcoubard	1:ebc0e0ef0a11	354	__O uint32_t TASKS_START; /!< Start radio. /
vcoubard	1:ebc0e0ef0a11	355	__O uint32_t TASKS_STOP; /!< Stop radio. /
vcoubard	1:ebc0e0ef0a11	356	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
vcoubard	1:ebc0e0ef0a11	357	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
vcoubard	1:ebc0e0ef0a11	358	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
vcoubard	1:ebc0e0ef0a11	359	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
vcoubard	1:ebc0e0ef0a11	360	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
vcoubard	1:ebc0e0ef0a11	361	__I uint32_t RESERVED0[55];
vcoubard	1:ebc0e0ef0a11	362	__IO uint32_t EVENTS_READY; /!< Ready event. /
vcoubard	1:ebc0e0ef0a11	363	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
vcoubard	1:ebc0e0ef0a11	364	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
vcoubard	1:ebc0e0ef0a11	365	__IO uint32_t EVENTS_END; /!< End event. /
vcoubard	1:ebc0e0ef0a11	366	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
vcoubard	1:ebc0e0ef0a11	367	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
vcoubard	1:ebc0e0ef0a11	368	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
vcoubard	1:ebc0e0ef0a11	369	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
vcoubard	1:ebc0e0ef0a11	370	sample is ready for readout at the RSSISAMPLE register. */
vcoubard	1:ebc0e0ef0a11	371	__I uint32_t RESERVED1[2];
vcoubard	1:ebc0e0ef0a11	372	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BCC register. /
vcoubard	1:ebc0e0ef0a11	373	__I uint32_t RESERVED2[53];
vcoubard	1:ebc0e0ef0a11	374	__IO uint32_t SHORTS; /!< Shortcuts for the radio. /
vcoubard	1:ebc0e0ef0a11	375	__I uint32_t RESERVED3[64];
vcoubard	1:ebc0e0ef0a11	376	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	377	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	378	__I uint32_t RESERVED4[61];
vcoubard	1:ebc0e0ef0a11	379	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
vcoubard	28:041dac1366b2	380	__I uint32_t RESERVED5;
vcoubard	1:ebc0e0ef0a11	381	__I uint32_t RXMATCH; /!< Received address. /
vcoubard	1:ebc0e0ef0a11	382	__I uint32_t RXCRC; /!< Received CRC. /
vcoubard	1:ebc0e0ef0a11	383	__I uint32_t DAI; /!< Device address match index. /
vcoubard	28:041dac1366b2	384	__I uint32_t RESERVED6[60];
vcoubard	1:ebc0e0ef0a11	385	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
vcoubard	1:ebc0e0ef0a11	386	__IO uint32_t FREQUENCY; /!< Frequency. /
vcoubard	1:ebc0e0ef0a11	387	__IO uint32_t TXPOWER; /!< Output power. /
vcoubard	1:ebc0e0ef0a11	388	__IO uint32_t MODE; /!< Data rate and modulation. /
vcoubard	1:ebc0e0ef0a11	389	__IO uint32_t PCNF0; /!< Packet configuration 0. /
vcoubard	1:ebc0e0ef0a11	390	__IO uint32_t PCNF1; /!< Packet configuration 1. /
vcoubard	1:ebc0e0ef0a11	391	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
vcoubard	1:ebc0e0ef0a11	392	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
vcoubard	1:ebc0e0ef0a11	393	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
vcoubard	1:ebc0e0ef0a11	394	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
vcoubard	1:ebc0e0ef0a11	395	__IO uint32_t TXADDRESS; /!< Transmit address select. /
vcoubard	1:ebc0e0ef0a11	396	__IO uint32_t RXADDRESSES; /!< Receive address select. /
vcoubard	1:ebc0e0ef0a11	397	__IO uint32_t CRCCNF; /!< CRC configuration. /
vcoubard	1:ebc0e0ef0a11	398	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
vcoubard	1:ebc0e0ef0a11	399	__IO uint32_t CRCINIT; /!< CRC initial value. /
vcoubard	1:ebc0e0ef0a11	400	__IO uint32_t TEST; /!< Test features enable register. /
vcoubard	1:ebc0e0ef0a11	401	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
vcoubard	1:ebc0e0ef0a11	402	__I uint32_t RSSISAMPLE; /!< RSSI sample. /
vcoubard	28:041dac1366b2	403	__I uint32_t RESERVED7;
vcoubard	1:ebc0e0ef0a11	404	__I uint32_t STATE; /!< Current radio state. /
vcoubard	1:ebc0e0ef0a11	405	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
vcoubard	28:041dac1366b2	406	__I uint32_t RESERVED8[2];
vcoubard	1:ebc0e0ef0a11	407	__IO uint32_t BCC; /!< Bit counter compare. /
vcoubard	28:041dac1366b2	408	__I uint32_t RESERVED9[39];
vcoubard	1:ebc0e0ef0a11	409	__IO uint32_t DAB[8]; /!< Device address base segment. /
vcoubard	1:ebc0e0ef0a11	410	__IO uint32_t DAP[8]; /!< Device address prefix. /
vcoubard	1:ebc0e0ef0a11	411	__IO uint32_t DACNF; /!< Device address match configuration. /
vcoubard	28:041dac1366b2	412	__I uint32_t RESERVED10[56];
vcoubard	1:ebc0e0ef0a11	413	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
vcoubard	1:ebc0e0ef0a11	414	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
vcoubard	1:ebc0e0ef0a11	415	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
vcoubard	1:ebc0e0ef0a11	416	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
vcoubard	1:ebc0e0ef0a11	417	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
vcoubard	28:041dac1366b2	418	__I uint32_t RESERVED11[561];
vcoubard	1:ebc0e0ef0a11	419	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	420	} NRF_RADIO_Type;
vcoubard	1:ebc0e0ef0a11	421
vcoubard	1:ebc0e0ef0a11	422
vcoubard	1:ebc0e0ef0a11	423	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	424	/* ================ UART ================ */
vcoubard	1:ebc0e0ef0a11	425	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	426
vcoubard	1:ebc0e0ef0a11	427
vcoubard	1:ebc0e0ef0a11	428	/**
vcoubard	1:ebc0e0ef0a11	429	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
vcoubard	1:ebc0e0ef0a11	430	*/
vcoubard	1:ebc0e0ef0a11	431
vcoubard	1:ebc0e0ef0a11	432	typedef struct { /!< UART Structure /
vcoubard	1:ebc0e0ef0a11	433	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
vcoubard	1:ebc0e0ef0a11	434	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
vcoubard	1:ebc0e0ef0a11	435	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
vcoubard	1:ebc0e0ef0a11	436	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
vcoubard	1:ebc0e0ef0a11	437	__I uint32_t RESERVED0[3];
vcoubard	1:ebc0e0ef0a11	438	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
vcoubard	1:ebc0e0ef0a11	439	__I uint32_t RESERVED1[56];
vcoubard	1:ebc0e0ef0a11	440	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
vcoubard	1:ebc0e0ef0a11	441	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
vcoubard	1:ebc0e0ef0a11	442	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
vcoubard	1:ebc0e0ef0a11	443	__I uint32_t RESERVED2[4];
vcoubard	1:ebc0e0ef0a11	444	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
vcoubard	1:ebc0e0ef0a11	445	__I uint32_t RESERVED3;
vcoubard	1:ebc0e0ef0a11	446	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
vcoubard	1:ebc0e0ef0a11	447	__I uint32_t RESERVED4[7];
vcoubard	1:ebc0e0ef0a11	448	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
vcoubard	28:041dac1366b2	449	__I uint32_t RESERVED5[46];
vcoubard	28:041dac1366b2	450	__IO uint32_t SHORTS; /!< Shortcuts for UART. /
vcoubard	28:041dac1366b2	451	__I uint32_t RESERVED6[64];
vcoubard	1:ebc0e0ef0a11	452	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	453	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	28:041dac1366b2	454	__I uint32_t RESERVED7[93];
vcoubard	1:ebc0e0ef0a11	455	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
vcoubard	28:041dac1366b2	456	__I uint32_t RESERVED8[31];
vcoubard	1:ebc0e0ef0a11	457	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
vcoubard	28:041dac1366b2	458	__I uint32_t RESERVED9;
vcoubard	1:ebc0e0ef0a11	459	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
vcoubard	1:ebc0e0ef0a11	460	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
vcoubard	1:ebc0e0ef0a11	461	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
vcoubard	1:ebc0e0ef0a11	462	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
vcoubard	1:ebc0e0ef0a11	463	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
vcoubard	1:ebc0e0ef0a11	464	Once read the character is consumed. If read when no character
vcoubard	1:ebc0e0ef0a11	465	available, the UART will stop working. */
vcoubard	1:ebc0e0ef0a11	466	__O uint32_t TXD; /!< TXD register. /
vcoubard	28:041dac1366b2	467	__I uint32_t RESERVED10;
vcoubard	1:ebc0e0ef0a11	468	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
vcoubard	28:041dac1366b2	469	__I uint32_t RESERVED11[17];
vcoubard	1:ebc0e0ef0a11	470	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
vcoubard	28:041dac1366b2	471	__I uint32_t RESERVED12[675];
vcoubard	1:ebc0e0ef0a11	472	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	473	} NRF_UART_Type;
vcoubard	1:ebc0e0ef0a11	474
vcoubard	1:ebc0e0ef0a11	475
vcoubard	1:ebc0e0ef0a11	476	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	477	/* ================ SPI ================ */
vcoubard	1:ebc0e0ef0a11	478	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	479
vcoubard	1:ebc0e0ef0a11	480
vcoubard	1:ebc0e0ef0a11	481	/**
vcoubard	1:ebc0e0ef0a11	482	* @brief SPI master 0. (SPI)
vcoubard	1:ebc0e0ef0a11	483	*/
vcoubard	1:ebc0e0ef0a11	484
vcoubard	1:ebc0e0ef0a11	485	typedef struct { /!< SPI Structure /
vcoubard	1:ebc0e0ef0a11	486	__I uint32_t RESERVED0[66];
vcoubard	1:ebc0e0ef0a11	487	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
vcoubard	1:ebc0e0ef0a11	488	__I uint32_t RESERVED1[126];
vcoubard	1:ebc0e0ef0a11	489	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	490	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	491	__I uint32_t RESERVED2[125];
vcoubard	1:ebc0e0ef0a11	492	__IO uint32_t ENABLE; /!< Enable SPI. /
vcoubard	1:ebc0e0ef0a11	493	__I uint32_t RESERVED3;
vcoubard	1:ebc0e0ef0a11	494	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
vcoubard	1:ebc0e0ef0a11	495	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
vcoubard	1:ebc0e0ef0a11	496	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
vcoubard	1:ebc0e0ef0a11	497	__I uint32_t RESERVED4;
vcoubard	1:ebc0e0ef0a11	498	__I uint32_t RXD; /!< RX data. /
vcoubard	1:ebc0e0ef0a11	499	__IO uint32_t TXD; /!< TX data. /
vcoubard	1:ebc0e0ef0a11	500	__I uint32_t RESERVED5;
vcoubard	1:ebc0e0ef0a11	501	__IO uint32_t FREQUENCY; /!< SPI frequency /
vcoubard	1:ebc0e0ef0a11	502	__I uint32_t RESERVED6[11];
vcoubard	1:ebc0e0ef0a11	503	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	1:ebc0e0ef0a11	504	__I uint32_t RESERVED7[681];
vcoubard	1:ebc0e0ef0a11	505	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	506	} NRF_SPI_Type;
vcoubard	1:ebc0e0ef0a11	507
vcoubard	1:ebc0e0ef0a11	508
vcoubard	1:ebc0e0ef0a11	509	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	510	/* ================ TWI ================ */
vcoubard	1:ebc0e0ef0a11	511	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	512
vcoubard	1:ebc0e0ef0a11	513
vcoubard	1:ebc0e0ef0a11	514	/**
vcoubard	1:ebc0e0ef0a11	515	* @brief Two-wire interface master 0. (TWI)
vcoubard	1:ebc0e0ef0a11	516	*/
vcoubard	1:ebc0e0ef0a11	517
vcoubard	1:ebc0e0ef0a11	518	typedef struct { /!< TWI Structure /
vcoubard	1:ebc0e0ef0a11	519	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
vcoubard	1:ebc0e0ef0a11	520	__I uint32_t RESERVED0;
vcoubard	1:ebc0e0ef0a11	521	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
vcoubard	1:ebc0e0ef0a11	522	__I uint32_t RESERVED1[2];
vcoubard	1:ebc0e0ef0a11	523	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
vcoubard	1:ebc0e0ef0a11	524	__I uint32_t RESERVED2;
vcoubard	1:ebc0e0ef0a11	525	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
vcoubard	1:ebc0e0ef0a11	526	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
vcoubard	1:ebc0e0ef0a11	527	__I uint32_t RESERVED3[56];
vcoubard	1:ebc0e0ef0a11	528	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
vcoubard	1:ebc0e0ef0a11	529	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
vcoubard	1:ebc0e0ef0a11	530	__I uint32_t RESERVED4[4];
vcoubard	1:ebc0e0ef0a11	531	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
vcoubard	1:ebc0e0ef0a11	532	__I uint32_t RESERVED5;
vcoubard	1:ebc0e0ef0a11	533	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
vcoubard	1:ebc0e0ef0a11	534	__I uint32_t RESERVED6[4];
vcoubard	1:ebc0e0ef0a11	535	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
vcoubard	1:ebc0e0ef0a11	536	__I uint32_t RESERVED7[3];
vcoubard	1:ebc0e0ef0a11	537	__IO uint32_t EVENTS_SUSPENDED; /!< Two-wire suspended. /
vcoubard	1:ebc0e0ef0a11	538	__I uint32_t RESERVED8[45];
vcoubard	1:ebc0e0ef0a11	539	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
vcoubard	1:ebc0e0ef0a11	540	__I uint32_t RESERVED9[64];
vcoubard	1:ebc0e0ef0a11	541	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	542	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	543	__I uint32_t RESERVED10[110];
vcoubard	1:ebc0e0ef0a11	544	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
vcoubard	1:ebc0e0ef0a11	545	__I uint32_t RESERVED11[14];
vcoubard	1:ebc0e0ef0a11	546	__IO uint32_t ENABLE; /!< Enable two-wire master. /
vcoubard	1:ebc0e0ef0a11	547	__I uint32_t RESERVED12;
vcoubard	1:ebc0e0ef0a11	548	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
vcoubard	1:ebc0e0ef0a11	549	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
vcoubard	1:ebc0e0ef0a11	550	__I uint32_t RESERVED13[2];
vcoubard	1:ebc0e0ef0a11	551	__I uint32_t RXD; /!< RX data register. /
vcoubard	1:ebc0e0ef0a11	552	__IO uint32_t TXD; /!< TX data register. /
vcoubard	1:ebc0e0ef0a11	553	__I uint32_t RESERVED14;
vcoubard	1:ebc0e0ef0a11	554	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
vcoubard	1:ebc0e0ef0a11	555	__I uint32_t RESERVED15[24];
vcoubard	1:ebc0e0ef0a11	556	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
vcoubard	1:ebc0e0ef0a11	557	__I uint32_t RESERVED16[668];
vcoubard	1:ebc0e0ef0a11	558	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	559	} NRF_TWI_Type;
vcoubard	1:ebc0e0ef0a11	560
vcoubard	1:ebc0e0ef0a11	561
vcoubard	1:ebc0e0ef0a11	562	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	563	/* ================ SPIS ================ */
vcoubard	1:ebc0e0ef0a11	564	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	565
vcoubard	1:ebc0e0ef0a11	566
vcoubard	1:ebc0e0ef0a11	567	/**
vcoubard	1:ebc0e0ef0a11	568	* @brief SPI slave 1. (SPIS)
vcoubard	1:ebc0e0ef0a11	569	*/
vcoubard	1:ebc0e0ef0a11	570
vcoubard	1:ebc0e0ef0a11	571	typedef struct { /!< SPIS Structure /
vcoubard	1:ebc0e0ef0a11	572	__I uint32_t RESERVED0[9];
vcoubard	1:ebc0e0ef0a11	573	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
vcoubard	1:ebc0e0ef0a11	574	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
vcoubard	1:ebc0e0ef0a11	575	__I uint32_t RESERVED1[54];
vcoubard	1:ebc0e0ef0a11	576	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
vcoubard	28:041dac1366b2	577	__I uint32_t RESERVED2[2];
vcoubard	28:041dac1366b2	578	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached /
vcoubard	28:041dac1366b2	579	__I uint32_t RESERVED3[5];
vcoubard	1:ebc0e0ef0a11	580	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
vcoubard	28:041dac1366b2	581	__I uint32_t RESERVED4[53];
vcoubard	1:ebc0e0ef0a11	582	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
vcoubard	28:041dac1366b2	583	__I uint32_t RESERVED5[64];
vcoubard	1:ebc0e0ef0a11	584	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	585	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	28:041dac1366b2	586	__I uint32_t RESERVED6[61];
vcoubard	1:ebc0e0ef0a11	587	__I uint32_t SEMSTAT; /!< Semaphore status. /
vcoubard	28:041dac1366b2	588	__I uint32_t RESERVED7[15];
vcoubard	1:ebc0e0ef0a11	589	__IO uint32_t STATUS; /!< Status from last transaction. /
vcoubard	28:041dac1366b2	590	__I uint32_t RESERVED8[47];
vcoubard	1:ebc0e0ef0a11	591	__IO uint32_t ENABLE; /!< Enable SPIS. /
vcoubard	28:041dac1366b2	592	__I uint32_t RESERVED9;
vcoubard	1:ebc0e0ef0a11	593	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
vcoubard	1:ebc0e0ef0a11	594	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
vcoubard	1:ebc0e0ef0a11	595	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
vcoubard	1:ebc0e0ef0a11	596	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
vcoubard	28:041dac1366b2	597	__I uint32_t RESERVED10[7];
vcoubard	1:ebc0e0ef0a11	598	__IO uint32_t RXDPTR; /!< RX data pointer. /
vcoubard	1:ebc0e0ef0a11	599	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
vcoubard	1:ebc0e0ef0a11	600	__I uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
vcoubard	28:041dac1366b2	601	__I uint32_t RESERVED11;
vcoubard	1:ebc0e0ef0a11	602	__IO uint32_t TXDPTR; /!< TX data pointer. /
vcoubard	1:ebc0e0ef0a11	603	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
vcoubard	1:ebc0e0ef0a11	604	__I uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
vcoubard	28:041dac1366b2	605	__I uint32_t RESERVED12;
vcoubard	1:ebc0e0ef0a11	606	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	28:041dac1366b2	607	__I uint32_t RESERVED13;
vcoubard	1:ebc0e0ef0a11	608	__IO uint32_t DEF; /!< Default character. /
vcoubard	28:041dac1366b2	609	__I uint32_t RESERVED14[24];
vcoubard	1:ebc0e0ef0a11	610	__IO uint32_t ORC; /!< Over-read character. /
vcoubard	28:041dac1366b2	611	__I uint32_t RESERVED15[654];
vcoubard	1:ebc0e0ef0a11	612	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	613	} NRF_SPIS_Type;
vcoubard	1:ebc0e0ef0a11	614
vcoubard	1:ebc0e0ef0a11	615
vcoubard	1:ebc0e0ef0a11	616	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	617	/* ================ SPIM ================ */
vcoubard	1:ebc0e0ef0a11	618	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	619
vcoubard	1:ebc0e0ef0a11	620
vcoubard	1:ebc0e0ef0a11	621	/**
vcoubard	1:ebc0e0ef0a11	622	* @brief SPI master with easyDMA 1. (SPIM)
vcoubard	1:ebc0e0ef0a11	623	*/
vcoubard	1:ebc0e0ef0a11	624
vcoubard	1:ebc0e0ef0a11	625	typedef struct { /!< SPIM Structure /
vcoubard	1:ebc0e0ef0a11	626	__I uint32_t RESERVED0[4];
vcoubard	1:ebc0e0ef0a11	627	__O uint32_t TASKS_START; /!< Start SPI transaction. /
vcoubard	1:ebc0e0ef0a11	628	__O uint32_t TASKS_STOP; /!< Stop SPI transaction. /
vcoubard	1:ebc0e0ef0a11	629	__I uint32_t RESERVED1;
vcoubard	1:ebc0e0ef0a11	630	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction. /
vcoubard	1:ebc0e0ef0a11	631	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction. /
vcoubard	1:ebc0e0ef0a11	632	__I uint32_t RESERVED2[56];
vcoubard	1:ebc0e0ef0a11	633	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped. /
vcoubard	1:ebc0e0ef0a11	634	__I uint32_t RESERVED3[2];
vcoubard	1:ebc0e0ef0a11	635	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached. /
vcoubard	28:041dac1366b2	636	__I uint32_t RESERVED4[3];
vcoubard	1:ebc0e0ef0a11	637	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached. /
vcoubard	28:041dac1366b2	638	__I uint32_t RESERVED5[10];
vcoubard	1:ebc0e0ef0a11	639	__IO uint32_t EVENTS_STARTED; /!< Transaction started. /
vcoubard	28:041dac1366b2	640	__I uint32_t RESERVED6[109];
vcoubard	1:ebc0e0ef0a11	641	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	642	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	28:041dac1366b2	643	__I uint32_t RESERVED7[125];
vcoubard	1:ebc0e0ef0a11	644	__IO uint32_t ENABLE; /!< Enable SPIM. /
vcoubard	28:041dac1366b2	645	__I uint32_t RESERVED8;
vcoubard	1:ebc0e0ef0a11	646	SPIM_PSEL_Type PSEL; /!< Pin select configuration. /
vcoubard	28:041dac1366b2	647	__I uint32_t RESERVED9[4];
vcoubard	1:ebc0e0ef0a11	648	__IO uint32_t FREQUENCY; /!< SPI frequency. /
vcoubard	28:041dac1366b2	649	__I uint32_t RESERVED10[3];
vcoubard	1:ebc0e0ef0a11	650	SPIM_RXD_Type RXD; /!< RXD EasyDMA configuration and status. /
vcoubard	28:041dac1366b2	651	__I uint32_t RESERVED11;
vcoubard	1:ebc0e0ef0a11	652	SPIM_TXD_Type TXD; /!< TXD EasyDMA configuration and status. /
vcoubard	28:041dac1366b2	653	__I uint32_t RESERVED12;
vcoubard	1:ebc0e0ef0a11	654	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	28:041dac1366b2	655	__I uint32_t RESERVED13[26];
vcoubard	1:ebc0e0ef0a11	656	__IO uint32_t ORC; /!< Over-read character. /
vcoubard	28:041dac1366b2	657	__I uint32_t RESERVED14[654];
vcoubard	1:ebc0e0ef0a11	658	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	659	} NRF_SPIM_Type;
vcoubard	1:ebc0e0ef0a11	660
vcoubard	1:ebc0e0ef0a11	661
vcoubard	1:ebc0e0ef0a11	662	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	663	/* ================ GPIOTE ================ */
vcoubard	1:ebc0e0ef0a11	664	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	665
vcoubard	1:ebc0e0ef0a11	666
vcoubard	1:ebc0e0ef0a11	667	/**
vcoubard	1:ebc0e0ef0a11	668	* @brief GPIO tasks and events. (GPIOTE)
vcoubard	1:ebc0e0ef0a11	669	*/
vcoubard	1:ebc0e0ef0a11	670
vcoubard	1:ebc0e0ef0a11	671	typedef struct { /!< GPIOTE Structure /
vcoubard	1:ebc0e0ef0a11	672	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
vcoubard	1:ebc0e0ef0a11	673	__I uint32_t RESERVED0[60];
vcoubard	1:ebc0e0ef0a11	674	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
vcoubard	1:ebc0e0ef0a11	675	__I uint32_t RESERVED1[27];
vcoubard	1:ebc0e0ef0a11	676	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
vcoubard	1:ebc0e0ef0a11	677	__I uint32_t RESERVED2[97];
vcoubard	1:ebc0e0ef0a11	678	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	679	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	680	__I uint32_t RESERVED3[129];
vcoubard	1:ebc0e0ef0a11	681	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
vcoubard	1:ebc0e0ef0a11	682	__I uint32_t RESERVED4[695];
vcoubard	1:ebc0e0ef0a11	683	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	684	} NRF_GPIOTE_Type;
vcoubard	1:ebc0e0ef0a11	685
vcoubard	1:ebc0e0ef0a11	686
vcoubard	1:ebc0e0ef0a11	687	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	688	/* ================ ADC ================ */
vcoubard	1:ebc0e0ef0a11	689	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	690
vcoubard	1:ebc0e0ef0a11	691
vcoubard	1:ebc0e0ef0a11	692	/**
vcoubard	1:ebc0e0ef0a11	693	* @brief Analog to digital converter. (ADC)
vcoubard	1:ebc0e0ef0a11	694	*/
vcoubard	1:ebc0e0ef0a11	695
vcoubard	1:ebc0e0ef0a11	696	typedef struct { /!< ADC Structure /
vcoubard	1:ebc0e0ef0a11	697	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
vcoubard	1:ebc0e0ef0a11	698	__O uint32_t TASKS_STOP; /!< Stop ADC. /
vcoubard	1:ebc0e0ef0a11	699	__I uint32_t RESERVED0[62];
vcoubard	1:ebc0e0ef0a11	700	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
vcoubard	1:ebc0e0ef0a11	701	__I uint32_t RESERVED1[128];
vcoubard	1:ebc0e0ef0a11	702	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	703	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	704	__I uint32_t RESERVED2[61];
vcoubard	1:ebc0e0ef0a11	705	__I uint32_t BUSY; /!< ADC busy register. /
vcoubard	1:ebc0e0ef0a11	706	__I uint32_t RESERVED3[63];
vcoubard	1:ebc0e0ef0a11	707	__IO uint32_t ENABLE; /!< ADC enable. /
vcoubard	1:ebc0e0ef0a11	708	__IO uint32_t CONFIG; /!< ADC configuration register. /
vcoubard	1:ebc0e0ef0a11	709	__I uint32_t RESULT; /!< Result of ADC conversion. /
vcoubard	1:ebc0e0ef0a11	710	__I uint32_t RESERVED4[700];
vcoubard	1:ebc0e0ef0a11	711	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	712	} NRF_ADC_Type;
vcoubard	1:ebc0e0ef0a11	713
vcoubard	1:ebc0e0ef0a11	714
vcoubard	1:ebc0e0ef0a11	715	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	716	/* ================ TIMER ================ */
vcoubard	1:ebc0e0ef0a11	717	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	718
vcoubard	1:ebc0e0ef0a11	719
vcoubard	1:ebc0e0ef0a11	720	/**
vcoubard	1:ebc0e0ef0a11	721	* @brief Timer 0. (TIMER)
vcoubard	1:ebc0e0ef0a11	722	*/
vcoubard	1:ebc0e0ef0a11	723
vcoubard	1:ebc0e0ef0a11	724	typedef struct { /!< TIMER Structure /
vcoubard	1:ebc0e0ef0a11	725	__O uint32_t TASKS_START; /!< Start Timer. /
vcoubard	1:ebc0e0ef0a11	726	__O uint32_t TASKS_STOP; /!< Stop Timer. /
vcoubard	1:ebc0e0ef0a11	727	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
vcoubard	1:ebc0e0ef0a11	728	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
vcoubard	1:ebc0e0ef0a11	729	__O uint32_t TASKS_SHUTDOWN; /!< Shutdown timer. /
vcoubard	1:ebc0e0ef0a11	730	__I uint32_t RESERVED0[11];
vcoubard	1:ebc0e0ef0a11	731	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
vcoubard	1:ebc0e0ef0a11	732	__I uint32_t RESERVED1[60];
vcoubard	1:ebc0e0ef0a11	733	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
vcoubard	1:ebc0e0ef0a11	734	__I uint32_t RESERVED2[44];
vcoubard	1:ebc0e0ef0a11	735	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
vcoubard	1:ebc0e0ef0a11	736	__I uint32_t RESERVED3[64];
vcoubard	1:ebc0e0ef0a11	737	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	738	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	739	__I uint32_t RESERVED4[126];
vcoubard	1:ebc0e0ef0a11	740	__IO uint32_t MODE; /!< Timer Mode selection. /
vcoubard	1:ebc0e0ef0a11	741	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
vcoubard	1:ebc0e0ef0a11	742	__I uint32_t RESERVED5;
vcoubard	1:ebc0e0ef0a11	743	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
vcoubard	1:ebc0e0ef0a11	744	clock frequency is divided by 2^SCALE. */
vcoubard	1:ebc0e0ef0a11	745	__I uint32_t RESERVED6[11];
vcoubard	1:ebc0e0ef0a11	746	__IO uint32_t CC[4]; /!< Capture/compare registers. /
vcoubard	1:ebc0e0ef0a11	747	__I uint32_t RESERVED7[683];
vcoubard	1:ebc0e0ef0a11	748	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	749	} NRF_TIMER_Type;
vcoubard	1:ebc0e0ef0a11	750
vcoubard	1:ebc0e0ef0a11	751
vcoubard	1:ebc0e0ef0a11	752	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	753	/* ================ RTC ================ */
vcoubard	1:ebc0e0ef0a11	754	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	755
vcoubard	1:ebc0e0ef0a11	756
vcoubard	1:ebc0e0ef0a11	757	/**
vcoubard	1:ebc0e0ef0a11	758	* @brief Real time counter 0. (RTC)
vcoubard	1:ebc0e0ef0a11	759	*/
vcoubard	1:ebc0e0ef0a11	760
vcoubard	1:ebc0e0ef0a11	761	typedef struct { /!< RTC Structure /
vcoubard	1:ebc0e0ef0a11	762	__O uint32_t TASKS_START; /!< Start RTC Counter. /
vcoubard	1:ebc0e0ef0a11	763	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
vcoubard	1:ebc0e0ef0a11	764	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
vcoubard	1:ebc0e0ef0a11	765	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
vcoubard	1:ebc0e0ef0a11	766	__I uint32_t RESERVED0[60];
vcoubard	1:ebc0e0ef0a11	767	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
vcoubard	1:ebc0e0ef0a11	768	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
vcoubard	1:ebc0e0ef0a11	769	__I uint32_t RESERVED1[14];
vcoubard	1:ebc0e0ef0a11	770	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
vcoubard	1:ebc0e0ef0a11	771	__I uint32_t RESERVED2[109];
vcoubard	1:ebc0e0ef0a11	772	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	773	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	774	__I uint32_t RESERVED3[13];
vcoubard	1:ebc0e0ef0a11	775	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
vcoubard	1:ebc0e0ef0a11	776	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
vcoubard	1:ebc0e0ef0a11	777	the value of EVTEN. */
vcoubard	1:ebc0e0ef0a11	778	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
vcoubard	1:ebc0e0ef0a11	779	gives the value of EVTEN. */
vcoubard	1:ebc0e0ef0a11	780	__I uint32_t RESERVED4[110];
vcoubard	1:ebc0e0ef0a11	781	__I uint32_t COUNTER; /!< Current COUNTER value. /
vcoubard	1:ebc0e0ef0a11	782	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
vcoubard	1:ebc0e0ef0a11	783	Must be written when RTC is STOPed. */
vcoubard	1:ebc0e0ef0a11	784	__I uint32_t RESERVED5[13];
vcoubard	1:ebc0e0ef0a11	785	__IO uint32_t CC[4]; /!< Capture/compare registers. /
vcoubard	1:ebc0e0ef0a11	786	__I uint32_t RESERVED6[683];
vcoubard	1:ebc0e0ef0a11	787	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	788	} NRF_RTC_Type;
vcoubard	1:ebc0e0ef0a11	789
vcoubard	1:ebc0e0ef0a11	790
vcoubard	1:ebc0e0ef0a11	791	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	792	/* ================ TEMP ================ */
vcoubard	1:ebc0e0ef0a11	793	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	794
vcoubard	1:ebc0e0ef0a11	795
vcoubard	1:ebc0e0ef0a11	796	/**
vcoubard	1:ebc0e0ef0a11	797	* @brief Temperature Sensor. (TEMP)
vcoubard	1:ebc0e0ef0a11	798	*/
vcoubard	1:ebc0e0ef0a11	799
vcoubard	1:ebc0e0ef0a11	800	typedef struct { /!< TEMP Structure /
vcoubard	1:ebc0e0ef0a11	801	__O uint32_t TASKS_START; /!< Start temperature measurement. /
vcoubard	1:ebc0e0ef0a11	802	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
vcoubard	1:ebc0e0ef0a11	803	__I uint32_t RESERVED0[62];
vcoubard	1:ebc0e0ef0a11	804	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
vcoubard	1:ebc0e0ef0a11	805	__I uint32_t RESERVED1[128];
vcoubard	1:ebc0e0ef0a11	806	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	807	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	808	__I uint32_t RESERVED2[127];
vcoubard	1:ebc0e0ef0a11	809	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
vcoubard	1:ebc0e0ef0a11	810	__I uint32_t RESERVED3[700];
vcoubard	1:ebc0e0ef0a11	811	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	812	} NRF_TEMP_Type;
vcoubard	1:ebc0e0ef0a11	813
vcoubard	1:ebc0e0ef0a11	814
vcoubard	1:ebc0e0ef0a11	815	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	816	/* ================ RNG ================ */
vcoubard	1:ebc0e0ef0a11	817	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	818
vcoubard	1:ebc0e0ef0a11	819
vcoubard	1:ebc0e0ef0a11	820	/**
vcoubard	1:ebc0e0ef0a11	821	* @brief Random Number Generator. (RNG)
vcoubard	1:ebc0e0ef0a11	822	*/
vcoubard	1:ebc0e0ef0a11	823
vcoubard	1:ebc0e0ef0a11	824	typedef struct { /!< RNG Structure /
vcoubard	1:ebc0e0ef0a11	825	__O uint32_t TASKS_START; /!< Start the random number generator. /
vcoubard	1:ebc0e0ef0a11	826	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
vcoubard	1:ebc0e0ef0a11	827	__I uint32_t RESERVED0[62];
vcoubard	1:ebc0e0ef0a11	828	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
vcoubard	1:ebc0e0ef0a11	829	__I uint32_t RESERVED1[63];
vcoubard	1:ebc0e0ef0a11	830	__IO uint32_t SHORTS; /!< Shortcuts for the RNG. /
vcoubard	1:ebc0e0ef0a11	831	__I uint32_t RESERVED2[64];
vcoubard	1:ebc0e0ef0a11	832	__IO uint32_t INTENSET; /!< Interrupt enable set register /
vcoubard	1:ebc0e0ef0a11	833	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
vcoubard	1:ebc0e0ef0a11	834	__I uint32_t RESERVED3[126];
vcoubard	1:ebc0e0ef0a11	835	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	1:ebc0e0ef0a11	836	__I uint32_t VALUE; /!< RNG random number. /
vcoubard	1:ebc0e0ef0a11	837	__I uint32_t RESERVED4[700];
vcoubard	1:ebc0e0ef0a11	838	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	839	} NRF_RNG_Type;
vcoubard	1:ebc0e0ef0a11	840
vcoubard	1:ebc0e0ef0a11	841
vcoubard	1:ebc0e0ef0a11	842	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	843	/* ================ ECB ================ */
vcoubard	1:ebc0e0ef0a11	844	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	845
vcoubard	1:ebc0e0ef0a11	846
vcoubard	1:ebc0e0ef0a11	847	/**
vcoubard	1:ebc0e0ef0a11	848	* @brief AES ECB Mode Encryption. (ECB)
vcoubard	1:ebc0e0ef0a11	849	*/
vcoubard	1:ebc0e0ef0a11	850
vcoubard	1:ebc0e0ef0a11	851	typedef struct { /!< ECB Structure /
vcoubard	1:ebc0e0ef0a11	852	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
vcoubard	1:ebc0e0ef0a11	853	will not initiate a new encryption and the ERRORECB event will
vcoubard	1:ebc0e0ef0a11	854	be triggered. */
vcoubard	1:ebc0e0ef0a11	855	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
vcoubard	1:ebc0e0ef0a11	856	this will will trigger the ERRORECB event. */
vcoubard	1:ebc0e0ef0a11	857	__I uint32_t RESERVED0[62];
vcoubard	1:ebc0e0ef0a11	858	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
vcoubard	1:ebc0e0ef0a11	859	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
vcoubard	1:ebc0e0ef0a11	860	error. */
vcoubard	1:ebc0e0ef0a11	861	__I uint32_t RESERVED1[127];
vcoubard	1:ebc0e0ef0a11	862	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	863	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	864	__I uint32_t RESERVED2[126];
vcoubard	1:ebc0e0ef0a11	865	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
vcoubard	1:ebc0e0ef0a11	866	__I uint32_t RESERVED3[701];
vcoubard	1:ebc0e0ef0a11	867	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	868	} NRF_ECB_Type;
vcoubard	1:ebc0e0ef0a11	869
vcoubard	1:ebc0e0ef0a11	870
vcoubard	1:ebc0e0ef0a11	871	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	872	/* ================ AAR ================ */
vcoubard	1:ebc0e0ef0a11	873	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	874
vcoubard	1:ebc0e0ef0a11	875
vcoubard	1:ebc0e0ef0a11	876	/**
vcoubard	1:ebc0e0ef0a11	877	* @brief Accelerated Address Resolver. (AAR)
vcoubard	1:ebc0e0ef0a11	878	*/
vcoubard	1:ebc0e0ef0a11	879
vcoubard	1:ebc0e0ef0a11	880	typedef struct { /!< AAR Structure /
vcoubard	1:ebc0e0ef0a11	881	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
vcoubard	1:ebc0e0ef0a11	882	data structure. */
vcoubard	1:ebc0e0ef0a11	883	__I uint32_t RESERVED0;
vcoubard	1:ebc0e0ef0a11	884	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
vcoubard	1:ebc0e0ef0a11	885	__I uint32_t RESERVED1[61];
vcoubard	1:ebc0e0ef0a11	886	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
vcoubard	1:ebc0e0ef0a11	887	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
vcoubard	1:ebc0e0ef0a11	888	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
vcoubard	1:ebc0e0ef0a11	889	__I uint32_t RESERVED2[126];
vcoubard	1:ebc0e0ef0a11	890	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	891	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	892	__I uint32_t RESERVED3[61];
vcoubard	1:ebc0e0ef0a11	893	__I uint32_t STATUS; /!< Resolution status. /
vcoubard	1:ebc0e0ef0a11	894	__I uint32_t RESERVED4[63];
vcoubard	1:ebc0e0ef0a11	895	__IO uint32_t ENABLE; /!< Enable AAR. /
vcoubard	1:ebc0e0ef0a11	896	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
vcoubard	1:ebc0e0ef0a11	897	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
vcoubard	1:ebc0e0ef0a11	898	__I uint32_t RESERVED5;
vcoubard	1:ebc0e0ef0a11	899	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
vcoubard	1:ebc0e0ef0a11	900	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
vcoubard	1:ebc0e0ef0a11	901	during resolution. A minimum of 3 bytes must be reserved. */
vcoubard	1:ebc0e0ef0a11	902	__I uint32_t RESERVED6[697];
vcoubard	1:ebc0e0ef0a11	903	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	904	} NRF_AAR_Type;
vcoubard	1:ebc0e0ef0a11	905
vcoubard	1:ebc0e0ef0a11	906
vcoubard	1:ebc0e0ef0a11	907	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	908	/* ================ CCM ================ */
vcoubard	1:ebc0e0ef0a11	909	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	910
vcoubard	1:ebc0e0ef0a11	911
vcoubard	1:ebc0e0ef0a11	912	/**
vcoubard	1:ebc0e0ef0a11	913	* @brief AES CCM Mode Encryption. (CCM)
vcoubard	1:ebc0e0ef0a11	914	*/
vcoubard	1:ebc0e0ef0a11	915
vcoubard	1:ebc0e0ef0a11	916	typedef struct { /!< CCM Structure /
vcoubard	1:ebc0e0ef0a11	917	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
vcoubard	1:ebc0e0ef0a11	918	itself when completed. */
vcoubard	1:ebc0e0ef0a11	919	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
vcoubard	1:ebc0e0ef0a11	920	completed. */
vcoubard	1:ebc0e0ef0a11	921	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
vcoubard	1:ebc0e0ef0a11	922	__I uint32_t RESERVED0[61];
vcoubard	1:ebc0e0ef0a11	923	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
vcoubard	1:ebc0e0ef0a11	924	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
vcoubard	1:ebc0e0ef0a11	925	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
vcoubard	1:ebc0e0ef0a11	926	__I uint32_t RESERVED1[61];
vcoubard	1:ebc0e0ef0a11	927	__IO uint32_t SHORTS; /!< Shortcuts for the CCM. /
vcoubard	1:ebc0e0ef0a11	928	__I uint32_t RESERVED2[64];
vcoubard	1:ebc0e0ef0a11	929	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	930	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	931	__I uint32_t RESERVED3[61];
vcoubard	1:ebc0e0ef0a11	932	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
vcoubard	1:ebc0e0ef0a11	933	__I uint32_t RESERVED4[63];
vcoubard	1:ebc0e0ef0a11	934	__IO uint32_t ENABLE; /!< CCM enable. /
vcoubard	1:ebc0e0ef0a11	935	__IO uint32_t MODE; /!< Operation mode. /
vcoubard	1:ebc0e0ef0a11	936	__IO uint32_t CNFPTR; /!< Pointer to a data structure holding AES key and NONCE vector. /
vcoubard	1:ebc0e0ef0a11	937	__IO uint32_t INPTR; /!< Pointer to the input packet. /
vcoubard	1:ebc0e0ef0a11	938	__IO uint32_t OUTPTR; /!< Pointer to the output packet. /
vcoubard	1:ebc0e0ef0a11	939	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
vcoubard	1:ebc0e0ef0a11	940	during resolution. A minimum of 43 bytes must be reserved. */
vcoubard	1:ebc0e0ef0a11	941	__I uint32_t RESERVED5[697];
vcoubard	1:ebc0e0ef0a11	942	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	943	} NRF_CCM_Type;
vcoubard	1:ebc0e0ef0a11	944
vcoubard	1:ebc0e0ef0a11	945
vcoubard	1:ebc0e0ef0a11	946	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	947	/* ================ WDT ================ */
vcoubard	1:ebc0e0ef0a11	948	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	949
vcoubard	1:ebc0e0ef0a11	950
vcoubard	1:ebc0e0ef0a11	951	/**
vcoubard	1:ebc0e0ef0a11	952	* @brief Watchdog Timer. (WDT)
vcoubard	1:ebc0e0ef0a11	953	*/
vcoubard	1:ebc0e0ef0a11	954
vcoubard	1:ebc0e0ef0a11	955	typedef struct { /!< WDT Structure /
vcoubard	1:ebc0e0ef0a11	956	__O uint32_t TASKS_START; /!< Start the watchdog. /
vcoubard	1:ebc0e0ef0a11	957	__I uint32_t RESERVED0[63];
vcoubard	1:ebc0e0ef0a11	958	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
vcoubard	1:ebc0e0ef0a11	959	__I uint32_t RESERVED1[128];
vcoubard	1:ebc0e0ef0a11	960	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	961	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	962	__I uint32_t RESERVED2[61];
vcoubard	1:ebc0e0ef0a11	963	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
vcoubard	1:ebc0e0ef0a11	964	__I uint32_t REQSTATUS; /!< Request status. /
vcoubard	1:ebc0e0ef0a11	965	__I uint32_t RESERVED3[63];
vcoubard	1:ebc0e0ef0a11	966	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
vcoubard	1:ebc0e0ef0a11	967	__IO uint32_t RREN; /!< Reload request enable. /
vcoubard	1:ebc0e0ef0a11	968	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	1:ebc0e0ef0a11	969	__I uint32_t RESERVED4[60];
vcoubard	1:ebc0e0ef0a11	970	__O uint32_t RR[8]; /!< Reload requests registers. /
vcoubard	1:ebc0e0ef0a11	971	__I uint32_t RESERVED5[631];
vcoubard	1:ebc0e0ef0a11	972	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	973	} NRF_WDT_Type;
vcoubard	1:ebc0e0ef0a11	974
vcoubard	1:ebc0e0ef0a11	975
vcoubard	1:ebc0e0ef0a11	976	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	977	/* ================ QDEC ================ */
vcoubard	1:ebc0e0ef0a11	978	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	979
vcoubard	1:ebc0e0ef0a11	980
vcoubard	1:ebc0e0ef0a11	981	/**
vcoubard	1:ebc0e0ef0a11	982	* @brief Rotary decoder. (QDEC)
vcoubard	1:ebc0e0ef0a11	983	*/
vcoubard	1:ebc0e0ef0a11	984
vcoubard	1:ebc0e0ef0a11	985	typedef struct { /!< QDEC Structure /
vcoubard	1:ebc0e0ef0a11	986	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
vcoubard	1:ebc0e0ef0a11	987	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
vcoubard	1:ebc0e0ef0a11	988	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
vcoubard	1:ebc0e0ef0a11	989	and clears the ACC registers. */
vcoubard	1:ebc0e0ef0a11	990	__I uint32_t RESERVED0[61];
vcoubard	1:ebc0e0ef0a11	991	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
vcoubard	1:ebc0e0ef0a11	992	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
vcoubard	1:ebc0e0ef0a11	993	ACC register different than zero. */
vcoubard	1:ebc0e0ef0a11	994	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
vcoubard	1:ebc0e0ef0a11	995	__I uint32_t RESERVED1[61];
vcoubard	1:ebc0e0ef0a11	996	__IO uint32_t SHORTS; /!< Shortcuts for the QDEC. /
vcoubard	1:ebc0e0ef0a11	997	__I uint32_t RESERVED2[64];
vcoubard	1:ebc0e0ef0a11	998	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	999	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	1000	__I uint32_t RESERVED3[125];
vcoubard	1:ebc0e0ef0a11	1001	__IO uint32_t ENABLE; /!< Enable the QDEC. /
vcoubard	1:ebc0e0ef0a11	1002	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
vcoubard	1:ebc0e0ef0a11	1003	__IO uint32_t SAMPLEPER; /!< Sample period. /
vcoubard	1:ebc0e0ef0a11	1004	__I int32_t SAMPLE; /!< Motion sample value. /
vcoubard	1:ebc0e0ef0a11	1005	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
vcoubard	1:ebc0e0ef0a11	1006	__I int32_t ACC; /!< Accumulated valid transitions register. /
vcoubard	1:ebc0e0ef0a11	1007	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
vcoubard	1:ebc0e0ef0a11	1008	task. */
vcoubard	1:ebc0e0ef0a11	1009	__IO uint32_t PSELLED; /!< Pin select for LED output. /
vcoubard	1:ebc0e0ef0a11	1010	__IO uint32_t PSELA; /!< Pin select for phase A input. /
vcoubard	1:ebc0e0ef0a11	1011	__IO uint32_t PSELB; /!< Pin select for phase B input. /
vcoubard	1:ebc0e0ef0a11	1012	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
vcoubard	1:ebc0e0ef0a11	1013	__I uint32_t RESERVED4[5];
vcoubard	1:ebc0e0ef0a11	1014	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
vcoubard	1:ebc0e0ef0a11	1015	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
vcoubard	1:ebc0e0ef0a11	1016	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
vcoubard	1:ebc0e0ef0a11	1017	task. */
vcoubard	1:ebc0e0ef0a11	1018	__I uint32_t RESERVED5[684];
vcoubard	1:ebc0e0ef0a11	1019	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	1020	} NRF_QDEC_Type;
vcoubard	1:ebc0e0ef0a11	1021
vcoubard	1:ebc0e0ef0a11	1022
vcoubard	1:ebc0e0ef0a11	1023	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1024	/* ================ LPCOMP ================ */
vcoubard	1:ebc0e0ef0a11	1025	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1026
vcoubard	1:ebc0e0ef0a11	1027
vcoubard	1:ebc0e0ef0a11	1028	/**
vcoubard	1:ebc0e0ef0a11	1029	* @brief Low power comparator. (LPCOMP)
vcoubard	1:ebc0e0ef0a11	1030	*/
vcoubard	1:ebc0e0ef0a11	1031
vcoubard	1:ebc0e0ef0a11	1032	typedef struct { /!< LPCOMP Structure /
vcoubard	1:ebc0e0ef0a11	1033	__O uint32_t TASKS_START; /!< Start the comparator. /
vcoubard	1:ebc0e0ef0a11	1034	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
vcoubard	1:ebc0e0ef0a11	1035	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
vcoubard	1:ebc0e0ef0a11	1036	__I uint32_t RESERVED0[61];
vcoubard	1:ebc0e0ef0a11	1037	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
vcoubard	1:ebc0e0ef0a11	1038	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
vcoubard	1:ebc0e0ef0a11	1039	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
vcoubard	1:ebc0e0ef0a11	1040	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
vcoubard	1:ebc0e0ef0a11	1041	__I uint32_t RESERVED1[60];
vcoubard	1:ebc0e0ef0a11	1042	__IO uint32_t SHORTS; /!< Shortcuts for the LPCOMP. /
vcoubard	1:ebc0e0ef0a11	1043	__I uint32_t RESERVED2[64];
vcoubard	1:ebc0e0ef0a11	1044	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	1045	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	1046	__I uint32_t RESERVED3[61];
vcoubard	1:ebc0e0ef0a11	1047	__I uint32_t RESULT; /!< Result of last compare. /
vcoubard	1:ebc0e0ef0a11	1048	__I uint32_t RESERVED4[63];
vcoubard	1:ebc0e0ef0a11	1049	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
vcoubard	1:ebc0e0ef0a11	1050	__IO uint32_t PSEL; /!< Input pin select. /
vcoubard	1:ebc0e0ef0a11	1051	__IO uint32_t REFSEL; /!< Reference select. /
vcoubard	1:ebc0e0ef0a11	1052	__IO uint32_t EXTREFSEL; /!< External reference select. /
vcoubard	1:ebc0e0ef0a11	1053	__I uint32_t RESERVED5[4];
vcoubard	1:ebc0e0ef0a11	1054	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
vcoubard	1:ebc0e0ef0a11	1055	__I uint32_t RESERVED6[694];
vcoubard	1:ebc0e0ef0a11	1056	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	1057	} NRF_LPCOMP_Type;
vcoubard	1:ebc0e0ef0a11	1058
vcoubard	1:ebc0e0ef0a11	1059
vcoubard	1:ebc0e0ef0a11	1060	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1061	/* ================ SWI ================ */
vcoubard	1:ebc0e0ef0a11	1062	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1063
vcoubard	1:ebc0e0ef0a11	1064
vcoubard	1:ebc0e0ef0a11	1065	/**
vcoubard	1:ebc0e0ef0a11	1066	* @brief SW Interrupts. (SWI)
vcoubard	1:ebc0e0ef0a11	1067	*/
vcoubard	1:ebc0e0ef0a11	1068
vcoubard	1:ebc0e0ef0a11	1069	typedef struct { /!< SWI Structure /
vcoubard	1:ebc0e0ef0a11	1070	__I uint32_t UNUSED; /!< Unused. /
vcoubard	1:ebc0e0ef0a11	1071	} NRF_SWI_Type;
vcoubard	1:ebc0e0ef0a11	1072
vcoubard	1:ebc0e0ef0a11	1073
vcoubard	1:ebc0e0ef0a11	1074	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1075	/* ================ NVMC ================ */
vcoubard	1:ebc0e0ef0a11	1076	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1077
vcoubard	1:ebc0e0ef0a11	1078
vcoubard	1:ebc0e0ef0a11	1079	/**
vcoubard	1:ebc0e0ef0a11	1080	* @brief Non Volatile Memory Controller. (NVMC)
vcoubard	1:ebc0e0ef0a11	1081	*/
vcoubard	1:ebc0e0ef0a11	1082
vcoubard	1:ebc0e0ef0a11	1083	typedef struct { /!< NVMC Structure /
vcoubard	1:ebc0e0ef0a11	1084	__I uint32_t RESERVED0[256];
vcoubard	1:ebc0e0ef0a11	1085	__I uint32_t READY; /!< Ready flag. /
vcoubard	1:ebc0e0ef0a11	1086	__I uint32_t RESERVED1[64];
vcoubard	1:ebc0e0ef0a11	1087	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	1:ebc0e0ef0a11	1088
vcoubard	1:ebc0e0ef0a11	1089	union {
vcoubard	1:ebc0e0ef0a11	1090	__IO uint32_t ERASEPCR1; /!< Register for erasing a non-protected non-volatile memory page. /
vcoubard	1:ebc0e0ef0a11	1091	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
vcoubard	1:ebc0e0ef0a11	1092	};
vcoubard	1:ebc0e0ef0a11	1093	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
vcoubard	1:ebc0e0ef0a11	1094	__IO uint32_t ERASEPCR0; /!< Register for erasing a protected non-volatile memory page. /
vcoubard	1:ebc0e0ef0a11	1095	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
vcoubard	1:ebc0e0ef0a11	1096	} NRF_NVMC_Type;
vcoubard	1:ebc0e0ef0a11	1097
vcoubard	1:ebc0e0ef0a11	1098
vcoubard	1:ebc0e0ef0a11	1099	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1100	/* ================ PPI ================ */
vcoubard	1:ebc0e0ef0a11	1101	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1102
vcoubard	1:ebc0e0ef0a11	1103
vcoubard	1:ebc0e0ef0a11	1104	/**
vcoubard	1:ebc0e0ef0a11	1105	* @brief PPI controller. (PPI)
vcoubard	1:ebc0e0ef0a11	1106	*/
vcoubard	1:ebc0e0ef0a11	1107
vcoubard	1:ebc0e0ef0a11	1108	typedef struct { /!< PPI Structure /
vcoubard	1:ebc0e0ef0a11	1109	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
vcoubard	1:ebc0e0ef0a11	1110	__I uint32_t RESERVED0[312];
vcoubard	1:ebc0e0ef0a11	1111	__IO uint32_t CHEN; /!< Channel enable. /
vcoubard	1:ebc0e0ef0a11	1112	__IO uint32_t CHENSET; /!< Channel enable set. /
vcoubard	1:ebc0e0ef0a11	1113	__IO uint32_t CHENCLR; /!< Channel enable clear. /
vcoubard	1:ebc0e0ef0a11	1114	__I uint32_t RESERVED1;
vcoubard	1:ebc0e0ef0a11	1115	PPI_CH_Type CH[16]; /!< PPI Channel. /
vcoubard	1:ebc0e0ef0a11	1116	__I uint32_t RESERVED2[156];
vcoubard	1:ebc0e0ef0a11	1117	__IO uint32_t CHG[4]; /!< Channel group configuration. /
vcoubard	1:ebc0e0ef0a11	1118	} NRF_PPI_Type;
vcoubard	1:ebc0e0ef0a11	1119
vcoubard	1:ebc0e0ef0a11	1120
vcoubard	1:ebc0e0ef0a11	1121	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1122	/* ================ FICR ================ */
vcoubard	1:ebc0e0ef0a11	1123	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1124
vcoubard	1:ebc0e0ef0a11	1125
vcoubard	1:ebc0e0ef0a11	1126	/**
vcoubard	1:ebc0e0ef0a11	1127	* @brief Factory Information Configuration. (FICR)
vcoubard	1:ebc0e0ef0a11	1128	*/
vcoubard	1:ebc0e0ef0a11	1129
vcoubard	1:ebc0e0ef0a11	1130	typedef struct { /!< FICR Structure /
vcoubard	1:ebc0e0ef0a11	1131	__I uint32_t RESERVED0[4];
vcoubard	1:ebc0e0ef0a11	1132	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
vcoubard	1:ebc0e0ef0a11	1133	__I uint32_t CODESIZE; /!< Code memory size in pages. /
vcoubard	1:ebc0e0ef0a11	1134	__I uint32_t RESERVED1[4];
vcoubard	1:ebc0e0ef0a11	1135	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
vcoubard	1:ebc0e0ef0a11	1136	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
vcoubard	1:ebc0e0ef0a11	1137	__I uint32_t RESERVED2;
vcoubard	1:ebc0e0ef0a11	1138	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
vcoubard	1:ebc0e0ef0a11	1139
vcoubard	1:ebc0e0ef0a11	1140	union {
vcoubard	1:ebc0e0ef0a11	1141	__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
vcoubard	1:ebc0e0ef0a11	1142	kept for backward compatinility purposes. Use SIZERAMBLOCKS
vcoubard	1:ebc0e0ef0a11	1143	instead. */
vcoubard	1:ebc0e0ef0a11	1144	__I uint32_t SIZERAMBLOCKS; /!< Size of RAM blocks in bytes. /
vcoubard	1:ebc0e0ef0a11	1145	};
vcoubard	1:ebc0e0ef0a11	1146	__I uint32_t RESERVED3[5];
vcoubard	1:ebc0e0ef0a11	1147	__I uint32_t CONFIGID; /!< Configuration identifier. /
vcoubard	1:ebc0e0ef0a11	1148	__I uint32_t DEVICEID[2]; /!< Device identifier. /
vcoubard	1:ebc0e0ef0a11	1149	__I uint32_t RESERVED4[6];
vcoubard	1:ebc0e0ef0a11	1150	__I uint32_t ER[4]; /!< Encryption root. /
vcoubard	1:ebc0e0ef0a11	1151	__I uint32_t IR[4]; /!< Identity root. /
vcoubard	1:ebc0e0ef0a11	1152	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
vcoubard	1:ebc0e0ef0a11	1153	__I uint32_t DEVICEADDR[2]; /!< Device address. /
vcoubard	1:ebc0e0ef0a11	1154	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
vcoubard	1:ebc0e0ef0a11	1155	__I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
vcoubard	1:ebc0e0ef0a11	1156	mode. */
vcoubard	1:ebc0e0ef0a11	1157	__I uint32_t RESERVED5[10];
vcoubard	1:ebc0e0ef0a11	1158	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
vcoubard	1:ebc0e0ef0a11	1159	mode. */
vcoubard	1:ebc0e0ef0a11	1160	} NRF_FICR_Type;
vcoubard	1:ebc0e0ef0a11	1161
vcoubard	1:ebc0e0ef0a11	1162
vcoubard	1:ebc0e0ef0a11	1163	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1164	/* ================ UICR ================ */
vcoubard	1:ebc0e0ef0a11	1165	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1166
vcoubard	1:ebc0e0ef0a11	1167
vcoubard	1:ebc0e0ef0a11	1168	/**
vcoubard	1:ebc0e0ef0a11	1169	* @brief User Information Configuration. (UICR)
vcoubard	1:ebc0e0ef0a11	1170	*/
vcoubard	1:ebc0e0ef0a11	1171
vcoubard	1:ebc0e0ef0a11	1172	typedef struct { /!< UICR Structure /
vcoubard	1:ebc0e0ef0a11	1173	__IO uint32_t CLENR0; /!< Length of code region 0. /
vcoubard	1:ebc0e0ef0a11	1174	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
vcoubard	1:ebc0e0ef0a11	1175	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
vcoubard	1:ebc0e0ef0a11	1176	__I uint32_t RESERVED0;
vcoubard	1:ebc0e0ef0a11	1177	__I uint32_t FWID; /!< Firmware ID. /
vcoubard	1:ebc0e0ef0a11	1178
vcoubard	1:ebc0e0ef0a11	1179	union {
vcoubard	1:ebc0e0ef0a11	1180	__IO uint32_t NRFFW[15]; /!< Reserved for Nordic firmware design. /
vcoubard	1:ebc0e0ef0a11	1181	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
vcoubard	1:ebc0e0ef0a11	1182	};
vcoubard	1:ebc0e0ef0a11	1183	__IO uint32_t NRFHW[12]; /!< Reserved for Nordic hardware design. /
vcoubard	1:ebc0e0ef0a11	1184	__IO uint32_t CUSTOMER[32]; /!< Reserved for customer. /
vcoubard	1:ebc0e0ef0a11	1185	} NRF_UICR_Type;
vcoubard	1:ebc0e0ef0a11	1186
vcoubard	1:ebc0e0ef0a11	1187
vcoubard	1:ebc0e0ef0a11	1188	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1189	/* ================ GPIO ================ */
vcoubard	1:ebc0e0ef0a11	1190	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1191
vcoubard	1:ebc0e0ef0a11	1192
vcoubard	1:ebc0e0ef0a11	1193	/**
vcoubard	1:ebc0e0ef0a11	1194	* @brief General purpose input and output. (GPIO)
vcoubard	1:ebc0e0ef0a11	1195	*/
vcoubard	1:ebc0e0ef0a11	1196
vcoubard	1:ebc0e0ef0a11	1197	typedef struct { /!< GPIO Structure /
vcoubard	1:ebc0e0ef0a11	1198	__I uint32_t RESERVED0[321];
vcoubard	1:ebc0e0ef0a11	1199	__IO uint32_t OUT; /!< Write GPIO port. /
vcoubard	1:ebc0e0ef0a11	1200	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
vcoubard	1:ebc0e0ef0a11	1201	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
vcoubard	1:ebc0e0ef0a11	1202	__I uint32_t IN; /!< Read GPIO port. /
vcoubard	1:ebc0e0ef0a11	1203	__IO uint32_t DIR; /!< Direction of GPIO pins. /
vcoubard	1:ebc0e0ef0a11	1204	__IO uint32_t DIRSET; /!< DIR set register. /
vcoubard	1:ebc0e0ef0a11	1205	__IO uint32_t DIRCLR; /!< DIR clear register. /
vcoubard	1:ebc0e0ef0a11	1206	__I uint32_t RESERVED1[120];
vcoubard	1:ebc0e0ef0a11	1207	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
vcoubard	1:ebc0e0ef0a11	1208	} NRF_GPIO_Type;
vcoubard	1:ebc0e0ef0a11	1209
vcoubard	1:ebc0e0ef0a11	1210
vcoubard	1:ebc0e0ef0a11	1211	/* -------------------- End of section using anonymous unions ------------------- */
vcoubard	1:ebc0e0ef0a11	1212	#if defined(__CC_ARM)
vcoubard	1:ebc0e0ef0a11	1213	#pragma pop
vcoubard	1:ebc0e0ef0a11	1214	#elif defined(__ICCARM__)
vcoubard	1:ebc0e0ef0a11	1215	/* leave anonymous unions enabled */
vcoubard	1:ebc0e0ef0a11	1216	#elif defined(__GNUC__)
vcoubard	1:ebc0e0ef0a11	1217	/* anonymous unions are enabled by default */
vcoubard	1:ebc0e0ef0a11	1218	#elif defined(__TMS470__)
vcoubard	1:ebc0e0ef0a11	1219	/* anonymous unions are enabled by default */
vcoubard	1:ebc0e0ef0a11	1220	#elif defined(__TASKING__)
vcoubard	1:ebc0e0ef0a11	1221	#pragma warning restore
vcoubard	1:ebc0e0ef0a11	1222	#else
vcoubard	1:ebc0e0ef0a11	1223	#warning Not supported compiler type
vcoubard	1:ebc0e0ef0a11	1224	#endif
vcoubard	1:ebc0e0ef0a11	1225
vcoubard	1:ebc0e0ef0a11	1226
vcoubard	1:ebc0e0ef0a11	1227
vcoubard	1:ebc0e0ef0a11	1228
vcoubard	1:ebc0e0ef0a11	1229	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1230	/* ================ Peripheral memory map ================ */
vcoubard	1:ebc0e0ef0a11	1231	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1232
vcoubard	1:ebc0e0ef0a11	1233	#define NRF_POWER_BASE 0x40000000UL
vcoubard	1:ebc0e0ef0a11	1234	#define NRF_CLOCK_BASE 0x40000000UL
vcoubard	1:ebc0e0ef0a11	1235	#define NRF_MPU_BASE 0x40000000UL
vcoubard	1:ebc0e0ef0a11	1236	#define NRF_AMLI_BASE 0x40000000UL
vcoubard	1:ebc0e0ef0a11	1237	#define NRF_RADIO_BASE 0x40001000UL
vcoubard	1:ebc0e0ef0a11	1238	#define NRF_UART0_BASE 0x40002000UL
vcoubard	1:ebc0e0ef0a11	1239	#define NRF_SPI0_BASE 0x40003000UL
vcoubard	1:ebc0e0ef0a11	1240	#define NRF_TWI0_BASE 0x40003000UL
vcoubard	1:ebc0e0ef0a11	1241	#define NRF_SPI1_BASE 0x40004000UL
vcoubard	1:ebc0e0ef0a11	1242	#define NRF_TWI1_BASE 0x40004000UL
vcoubard	1:ebc0e0ef0a11	1243	#define NRF_SPIS1_BASE 0x40004000UL
vcoubard	1:ebc0e0ef0a11	1244	#define NRF_SPIM1_BASE 0x40004000UL
vcoubard	1:ebc0e0ef0a11	1245	#define NRF_GPIOTE_BASE 0x40006000UL
vcoubard	1:ebc0e0ef0a11	1246	#define NRF_ADC_BASE 0x40007000UL
vcoubard	1:ebc0e0ef0a11	1247	#define NRF_TIMER0_BASE 0x40008000UL
vcoubard	1:ebc0e0ef0a11	1248	#define NRF_TIMER1_BASE 0x40009000UL
vcoubard	1:ebc0e0ef0a11	1249	#define NRF_TIMER2_BASE 0x4000A000UL
vcoubard	1:ebc0e0ef0a11	1250	#define NRF_RTC0_BASE 0x4000B000UL
vcoubard	1:ebc0e0ef0a11	1251	#define NRF_TEMP_BASE 0x4000C000UL
vcoubard	1:ebc0e0ef0a11	1252	#define NRF_RNG_BASE 0x4000D000UL
vcoubard	1:ebc0e0ef0a11	1253	#define NRF_ECB_BASE 0x4000E000UL
vcoubard	1:ebc0e0ef0a11	1254	#define NRF_AAR_BASE 0x4000F000UL
vcoubard	1:ebc0e0ef0a11	1255	#define NRF_CCM_BASE 0x4000F000UL
vcoubard	1:ebc0e0ef0a11	1256	#define NRF_WDT_BASE 0x40010000UL
vcoubard	1:ebc0e0ef0a11	1257	#define NRF_RTC1_BASE 0x40011000UL
vcoubard	1:ebc0e0ef0a11	1258	#define NRF_QDEC_BASE 0x40012000UL
vcoubard	1:ebc0e0ef0a11	1259	#define NRF_LPCOMP_BASE 0x40013000UL
vcoubard	1:ebc0e0ef0a11	1260	#define NRF_SWI_BASE 0x40014000UL
vcoubard	1:ebc0e0ef0a11	1261	#define NRF_NVMC_BASE 0x4001E000UL
vcoubard	1:ebc0e0ef0a11	1262	#define NRF_PPI_BASE 0x4001F000UL
vcoubard	1:ebc0e0ef0a11	1263	#define NRF_FICR_BASE 0x10000000UL
vcoubard	1:ebc0e0ef0a11	1264	#define NRF_UICR_BASE 0x10001000UL
vcoubard	1:ebc0e0ef0a11	1265	#define NRF_GPIO_BASE 0x50000000UL
vcoubard	1:ebc0e0ef0a11	1266
vcoubard	1:ebc0e0ef0a11	1267
vcoubard	1:ebc0e0ef0a11	1268	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1269	/* ================ Peripheral declaration ================ */
vcoubard	1:ebc0e0ef0a11	1270	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1271
vcoubard	1:ebc0e0ef0a11	1272	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
vcoubard	1:ebc0e0ef0a11	1273	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
vcoubard	1:ebc0e0ef0a11	1274	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
vcoubard	1:ebc0e0ef0a11	1275	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
vcoubard	1:ebc0e0ef0a11	1276	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
vcoubard	1:ebc0e0ef0a11	1277	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
vcoubard	1:ebc0e0ef0a11	1278	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
vcoubard	1:ebc0e0ef0a11	1279	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
vcoubard	1:ebc0e0ef0a11	1280	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
vcoubard	1:ebc0e0ef0a11	1281	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
vcoubard	1:ebc0e0ef0a11	1282	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
vcoubard	1:ebc0e0ef0a11	1283	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
vcoubard	1:ebc0e0ef0a11	1284	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
vcoubard	1:ebc0e0ef0a11	1285	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
vcoubard	1:ebc0e0ef0a11	1286	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
vcoubard	1:ebc0e0ef0a11	1287	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
vcoubard	1:ebc0e0ef0a11	1288	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
vcoubard	1:ebc0e0ef0a11	1289	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
vcoubard	1:ebc0e0ef0a11	1290	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
vcoubard	1:ebc0e0ef0a11	1291	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
vcoubard	1:ebc0e0ef0a11	1292	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
vcoubard	1:ebc0e0ef0a11	1293	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
vcoubard	1:ebc0e0ef0a11	1294	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
vcoubard	1:ebc0e0ef0a11	1295	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
vcoubard	1:ebc0e0ef0a11	1296	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
vcoubard	1:ebc0e0ef0a11	1297	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
vcoubard	1:ebc0e0ef0a11	1298	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
vcoubard	1:ebc0e0ef0a11	1299	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
vcoubard	1:ebc0e0ef0a11	1300	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
vcoubard	1:ebc0e0ef0a11	1301	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
vcoubard	1:ebc0e0ef0a11	1302	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
vcoubard	1:ebc0e0ef0a11	1303	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
vcoubard	1:ebc0e0ef0a11	1304	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
vcoubard	1:ebc0e0ef0a11	1305
vcoubard	1:ebc0e0ef0a11	1306
vcoubard	1:ebc0e0ef0a11	1307	/** @} / / End of group Device_Peripheral_Registers */
vcoubard	1:ebc0e0ef0a11	1308	/** @} / / End of group nrf51 */
vcoubard	1:ebc0e0ef0a11	1309	/** @} / / End of group Nordic Semiconductor */
vcoubard	1:ebc0e0ef0a11	1310
vcoubard	1:ebc0e0ef0a11	1311	#ifdef __cplusplus
vcoubard	1:ebc0e0ef0a11	1312	}
vcoubard	1:ebc0e0ef0a11	1313	#endif
vcoubard	1:ebc0e0ef0a11	1314
vcoubard	1:ebc0e0ef0a11	1315
vcoubard	1:ebc0e0ef0a11	1316	#endif /* nrf51_H */
vcoubard	1:ebc0e0ef0a11	1317

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Type:	Library
Created:	07 Aug 2016
Imports:	3
Forks:	0
Commits:	47
Dependents:	1
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Followers:	1

source/nordic_sdk/components/device/nrf51.h@29:286940b7ee5a, 2016-04-07 (annotated)

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