VL53L0X_Condensed - Condensed Version of Public VL53L0X

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Condensed Version of Public VL53L0X

VL53L0X.cpp@8:abea9638127a, 2019-03-24 (annotated)

Committer:: sepp_nepp
Date:: Sun Mar 24 18:36:37 2019 +0000
Revision:: 8:abea9638127a
Parent:: 7:41cbc431e1f4
Child:: 10:cd251e0fc2fd

still no compile, symbol multiply defined error . stupid

Who changed what in which revision?

User	Revision	Line number	New contents of line
nikapov	0:a1a69d32f310	1	/**
nikapov	0:a1a69d32f310	2	******************************************************************************
nikapov	0:a1a69d32f310	3	* @file VL53L0X_class.cpp
nikapov	0:a1a69d32f310	4	* @author IMG
nikapov	0:a1a69d32f310	5	* @version V0.0.1
nikapov	0:a1a69d32f310	6	* @date 28-June-2016
nikapov	0:a1a69d32f310	7	* @brief Implementation file for the VL53L0X driver class
nikapov	0:a1a69d32f310	8	******************************************************************************
nikapov	0:a1a69d32f310	9	* @attention
nikapov	0:a1a69d32f310	10	*
nikapov	0:a1a69d32f310	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
nikapov	0:a1a69d32f310	12	*
sepp_nepp	7:41cbc431e1f4	13	* Redistribution and use in source and binary forms,with or without modification,
nikapov	0:a1a69d32f310	14	* are permitted provided that the following conditions are met:
nikapov	0:a1a69d32f310	15	* 1. Redistributions of source code must retain the above copyright notice,
nikapov	0:a1a69d32f310	16	* this list of conditions and the following disclaimer.
nikapov	0:a1a69d32f310	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
nikapov	0:a1a69d32f310	18	* this list of conditions and the following disclaimer in the documentation
nikapov	0:a1a69d32f310	19	* and/or other materials provided with the distribution.
nikapov	0:a1a69d32f310	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
nikapov	0:a1a69d32f310	21	* may be used to endorse or promote products derived from this software
nikapov	0:a1a69d32f310	22	* without specific prior written permission.
nikapov	0:a1a69d32f310	23	*
nikapov	0:a1a69d32f310	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sepp_nepp	7:41cbc431e1f4	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE
nikapov	0:a1a69d32f310	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
nikapov	0:a1a69d32f310	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sepp_nepp	7:41cbc431e1f4	28	* FOR ANY DIRECT,INDIRECT,INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL
sepp_nepp	7:41cbc431e1f4	29	* DAMAGES (INCLUDING,BUT NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR
sepp_nepp	7:41cbc431e1f4	30	* SERVICES; LOSS OF USE,DATA,OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sepp_nepp	7:41cbc431e1f4	31	* CAUSED AND ON ANY THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,
nikapov	0:a1a69d32f310	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sepp_nepp	7:41cbc431e1f4	33	* OF THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
nikapov	0:a1a69d32f310	34	*
nikapov	0:a1a69d32f310	35	******************************************************************************
nikapov	0:a1a69d32f310	36	*/
nikapov	0:a1a69d32f310	37
sepp_nepp	7:41cbc431e1f4	38	// Some example regex that were used to replace useless macros
sepp_nepp	7:41cbc431e1f4	39	// \QVL53L0X_SETDEVICESPECIFICPARAMETER(\E([A-Z\d]+)[[:punct:]]([[:space:]]*)([A-Z\d_]+)\Q);\E
sepp_nepp	7:41cbc431e1f4	40	// _device->DeviceSpecificParameters.\1 = \3;
sepp_nepp	7:41cbc431e1f4	41
sepp_nepp	7:41cbc431e1f4	42	// \QVL53L0X_GETDEVICESPECIFICPARAMETER(\E([A-Z\d]+)\Q);\E
sepp_nepp	7:41cbc431e1f4	43	// _device->DeviceSpecificParameters.\1;
sepp_nepp	7:41cbc431e1f4	44
sepp_nepp	7:41cbc431e1f4	45	// \QVL53L0X_SETPARAMETERFIELD(\E([A-Z\d]+)[[:punct:]]([[:space:]]*)([A-Z\d_]+)\Q);\E
sepp_nepp	7:41cbc431e1f4	46	// _device->CurrentParameters.\1 = \3;
sepp_nepp	7:41cbc431e1f4	47
sepp_nepp	7:41cbc431e1f4	48	// \QVL53L0X_GETPARAMETERFIELD(\E([A-Z\d]+)[[:punct:]]([[:space:]]*)([A-Z\d_]+)\Q);\E
sepp_nepp	7:41cbc431e1f4	49	// \3 = _device->CurrentParameters.\1
sepp_nepp	7:41cbc431e1f4	50
sepp_nepp	7:41cbc431e1f4	51	// \QVL53L0X_SETARRAYPARAMETERFIELD(\E([A-Z\d]+)[[:punct:]](\s)([A-Z\d_]+)[[:punct:]](\s)([A-Z\d_]+)\Q);\E
sepp_nepp	7:41cbc431e1f4	52	// _device->CurrentParameters.\1[\3] = \5;
sepp_nepp	7:41cbc431e1f4	53	// is used to replace following macro for ex:
sepp_nepp	7:41cbc431e1f4	54	// #define VL53L0X_SETARRAYPARAMETERFIELD(field, index, value) \
sepp_nepp	7:41cbc431e1f4	55	//_device->CurrentParameters.field[index] = value
sepp_nepp	7:41cbc431e1f4	56
sepp_nepp	7:41cbc431e1f4	57	// \QVL53L0X_GETARRAYPARAMETERFIELD(\E([A-Z\d]+)[[:punct:]](\s)([A-Z\d_]+)[[:punct:]](\s)([A-Z\d_]+)\Q);\E
sepp_nepp	7:41cbc431e1f4	58	// \5 = _device->CurrentParameters.\1[\3]
sepp_nepp	7:41cbc431e1f4	59	// is used to replace following macro for ex:
sepp_nepp	7:41cbc431e1f4	60	// #define VL53L0X_GETARRAYPARAMETERFIELD(field, index, variable) \
sepp_nepp	7:41cbc431e1f4	61	// variable = _device-> CurrentParameters.field[index]
sepp_nepp	7:41cbc431e1f4	62
sepp_nepp	7:41cbc431e1f4	63	// \QPALDevDataSet(\E([A-Z\d]+)[[:punct:]]([[:space:]]*)([A-Z\d_]+)\Q);\E
sepp_nepp	7:41cbc431e1f4	64	// _device->\1 = \3;
sepp_nepp	7:41cbc431e1f4	65	// is used to replace:
sepp_nepp	7:41cbc431e1f4	66	// #define PALDevDataSet(field, data) (Dev->field)=(data)
sepp_nepp	7:41cbc431e1f4	67
nikapov	0:a1a69d32f310	68	/* Includes */
nikapov	0:a1a69d32f310	69	#include <stdlib.h>
nikapov	0:a1a69d32f310	70	#include "VL53L0X.h"
sepp_nepp	7:41cbc431e1f4	71
sepp_nepp	8:abea9638127a	72	#define REF_ARRAY_SPAD_0 0
sepp_nepp	8:abea9638127a	73	#define REF_ARRAY_SPAD_5 5
sepp_nepp	8:abea9638127a	74	#define REF_ARRAY_SPAD_10 10
sepp_nepp	8:abea9638127a	75
sepp_nepp	8:abea9638127a	76	uint32_t refArrayQuadrants[4] = {REF_ARRAY_SPAD_10,REF_ARRAY_SPAD_5,
sepp_nepp	8:abea9638127a	77	REF_ARRAY_SPAD_0,REF_ARRAY_SPAD_5 };
sepp_nepp	8:abea9638127a	78
sepp_nepp	8:abea9638127a	79
sepp_nepp	7:41cbc431e1f4	80	VL53L0X_Error VL53L0X::VL53L0X_device_read_strobe()
nikapov	0:a1a69d32f310	81	{
nikapov	0:a1a69d32f310	82	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	83	uint8_t strobe;
nikapov	0:a1a69d32f310	84	uint32_t loop_nb;
nikapov	0:a1a69d32f310	85
sepp_nepp	7:41cbc431e1f4	86	status \|= VL53L0X_write_byte(0x83,0x00);
nikapov	0:a1a69d32f310	87
nikapov	0:a1a69d32f310	88	/* polling
nikapov	0:a1a69d32f310	89	* use timeout to avoid deadlock*/
nikapov	0:a1a69d32f310	90	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	91	loop_nb = 0;
nikapov	0:a1a69d32f310	92	do {
sepp_nepp	7:41cbc431e1f4	93	status = VL53L0X_read_byte(0x83,&strobe);
nikapov	0:a1a69d32f310	94	if ((strobe != 0x00) \|\| status != VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	95	break;
nikapov	0:a1a69d32f310	96	}
nikapov	0:a1a69d32f310	97
nikapov	0:a1a69d32f310	98	loop_nb = loop_nb + 1;
nikapov	0:a1a69d32f310	99	} while (loop_nb < VL53L0X_DEFAULT_MAX_LOOP);
nikapov	0:a1a69d32f310	100
nikapov	0:a1a69d32f310	101	if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
nikapov	0:a1a69d32f310	102	status = VL53L0X_ERROR_TIME_OUT;
nikapov	0:a1a69d32f310	103	}
nikapov	0:a1a69d32f310	104	}
nikapov	0:a1a69d32f310	105
sepp_nepp	7:41cbc431e1f4	106	status \|= VL53L0X_write_byte(0x83,0x01);
nikapov	0:a1a69d32f310	107
nikapov	0:a1a69d32f310	108	return status;
nikapov	0:a1a69d32f310	109	}
nikapov	0:a1a69d32f310	110
sepp_nepp	7:41cbc431e1f4	111	VL53L0X_Error VL53L0X::VL53L0X_get_info_from_device(uint8_t option)
nikapov	0:a1a69d32f310	112	{
nikapov	0:a1a69d32f310	113	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	114	uint8_t byte;
nikapov	0:a1a69d32f310	115	uint32_t tmp_dword;
nikapov	0:a1a69d32f310	116	uint8_t module_id;
nikapov	0:a1a69d32f310	117	uint8_t revision;
nikapov	0:a1a69d32f310	118	uint8_t reference_spad_count = 0;
nikapov	0:a1a69d32f310	119	uint8_t reference_spad_type = 0;
nikapov	0:a1a69d32f310	120	uint32_t part_uid_upper = 0;
nikapov	0:a1a69d32f310	121	uint32_t part_uid_lower = 0;
nikapov	0:a1a69d32f310	122	uint32_t offset_fixed1104_mm = 0;
nikapov	0:a1a69d32f310	123	int16_t offset_micro_meters = 0;
nikapov	0:a1a69d32f310	124	uint32_t dist_meas_tgt_fixed1104_mm = 400 << 4;
nikapov	0:a1a69d32f310	125	uint32_t dist_meas_fixed1104_400_mm = 0;
nikapov	0:a1a69d32f310	126	uint32_t signal_rate_meas_fixed1104_400_mm = 0;
nikapov	0:a1a69d32f310	127	char product_id[19];
nikapov	0:a1a69d32f310	128	char *product_id_tmp;
nikapov	0:a1a69d32f310	129	uint8_t read_data_from_device_done;
nikapov	0:a1a69d32f310	130	FixPoint1616_t signal_rate_meas_fixed400_mm_fix = 0;
nikapov	0:a1a69d32f310	131	uint8_t nvm_ref_good_spad_map[VL53L0X_REF_SPAD_BUFFER_SIZE];
nikapov	0:a1a69d32f310	132	int i;
sepp_nepp	5:b95f6951f7d5	133
nikapov	0:a1a69d32f310	134
sepp_nepp	7:41cbc431e1f4	135	read_data_from_device_done = _device->DeviceSpecificParameters.ReadDataFromDeviceDone;
sepp_nepp	7:41cbc431e1f4	136	read_data_from_device_done = _device->DeviceSpecificParameters.ReadDataFromDeviceDone;
nikapov	0:a1a69d32f310	137
nikapov	0:a1a69d32f310	138	/* This access is done only once after that a GetDeviceInfo or
nikapov	0:a1a69d32f310	139	* datainit is done*/
nikapov	0:a1a69d32f310	140	if (read_data_from_device_done != 7) {
nikapov	0:a1a69d32f310	141
sepp_nepp	7:41cbc431e1f4	142	status \|= VL53L0X_write_byte(0x80,0x01);
sepp_nepp	7:41cbc431e1f4	143	status \|= VL53L0X_write_byte(0xFF,0x01);
sepp_nepp	7:41cbc431e1f4	144	status \|= VL53L0X_write_byte(0x00,0x00);
sepp_nepp	7:41cbc431e1f4	145
sepp_nepp	7:41cbc431e1f4	146	status \|= VL53L0X_write_byte(0xFF,0x06);
sepp_nepp	7:41cbc431e1f4	147	status \|= VL53L0X_read_byte(0x83,&byte);
sepp_nepp	7:41cbc431e1f4	148	status \|= VL53L0X_write_byte(0x83,byte \| 4);
sepp_nepp	7:41cbc431e1f4	149	status \|= VL53L0X_write_byte(0xFF,0x07);
sepp_nepp	7:41cbc431e1f4	150	status \|= VL53L0X_write_byte(0x81,0x01);
sepp_nepp	7:41cbc431e1f4	151
sepp_nepp	7:41cbc431e1f4	152	status \|= VL53L0X_polling_delay();
sepp_nepp	7:41cbc431e1f4	153
sepp_nepp	7:41cbc431e1f4	154	status \|= VL53L0X_write_byte(0x80,0x01);
nikapov	0:a1a69d32f310	155
nikapov	0:a1a69d32f310	156	if (((option & 1) == 1) &&
nikapov	0:a1a69d32f310	157	((read_data_from_device_done & 1) == 0)) {
sepp_nepp	7:41cbc431e1f4	158	status \|= VL53L0X_write_byte(0x94,0x6b);
sepp_nepp	7:41cbc431e1f4	159	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	160	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	161
sepp_nepp	8:abea9638127a	162	reference_spad_count = (uint8_t)((tmp_dword >> 8) & 0x7f);
nikapov	0:a1a69d32f310	163	reference_spad_type = (uint8_t)((tmp_dword >> 15) & 0x01);
nikapov	0:a1a69d32f310	164
sepp_nepp	7:41cbc431e1f4	165	status \|= VL53L0X_write_byte(0x94,0x24);
sepp_nepp	7:41cbc431e1f4	166	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	167	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	168
nikapov	0:a1a69d32f310	169
sepp_nepp	8:abea9638127a	170	nvm_ref_good_spad_map[0] = (uint8_t)((tmp_dword >> 24)& 0xff);
sepp_nepp	8:abea9638127a	171	nvm_ref_good_spad_map[1] = (uint8_t)((tmp_dword >> 16)& 0xff);
sepp_nepp	8:abea9638127a	172	nvm_ref_good_spad_map[2] = (uint8_t)((tmp_dword >> 8)& 0xff);
nikapov	0:a1a69d32f310	173	nvm_ref_good_spad_map[3] = (uint8_t)(tmp_dword & 0xff);
nikapov	0:a1a69d32f310	174
sepp_nepp	7:41cbc431e1f4	175	status \|= VL53L0X_write_byte(0x94,0x25);
sepp_nepp	7:41cbc431e1f4	176	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	177	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	178
sepp_nepp	8:abea9638127a	179	nvm_ref_good_spad_map[4] = (uint8_t)((tmp_dword >> 24)& 0xff);
sepp_nepp	8:abea9638127a	180	nvm_ref_good_spad_map[5] = (uint8_t)((tmp_dword >> 16)& 0xff);
nikapov	0:a1a69d32f310	181	}
nikapov	0:a1a69d32f310	182
nikapov	0:a1a69d32f310	183	if (((option & 2) == 2) &&
nikapov	0:a1a69d32f310	184	((read_data_from_device_done & 2) == 0)) {
nikapov	0:a1a69d32f310	185
sepp_nepp	7:41cbc431e1f4	186	status \|= VL53L0X_write_byte(0x94,0x02);
sepp_nepp	7:41cbc431e1f4	187	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	188	status \|= VL53L0X_read_byte(0x90,&module_id);
sepp_nepp	7:41cbc431e1f4	189
sepp_nepp	7:41cbc431e1f4	190	status \|= VL53L0X_write_byte(0x94,0x7B);
sepp_nepp	7:41cbc431e1f4	191	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	192	status \|= VL53L0X_read_byte(0x90,&revision);
sepp_nepp	7:41cbc431e1f4	193
sepp_nepp	7:41cbc431e1f4	194	status \|= VL53L0X_write_byte(0x94,0x77);
sepp_nepp	7:41cbc431e1f4	195	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	196	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	197
nikapov	0:a1a69d32f310	198	product_id[0] = (char)((tmp_dword >> 25) & 0x07f);
nikapov	0:a1a69d32f310	199	product_id[1] = (char)((tmp_dword >> 18) & 0x07f);
nikapov	0:a1a69d32f310	200	product_id[2] = (char)((tmp_dword >> 11) & 0x07f);
sepp_nepp	8:abea9638127a	201	product_id[3] = (char)((tmp_dword >> 4) & 0x07f);
nikapov	0:a1a69d32f310	202
nikapov	0:a1a69d32f310	203	byte = (uint8_t)((tmp_dword & 0x00f) << 3);
nikapov	0:a1a69d32f310	204
sepp_nepp	7:41cbc431e1f4	205	status \|= VL53L0X_write_byte(0x94,0x78);
sepp_nepp	7:41cbc431e1f4	206	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	207	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	208
nikapov	0:a1a69d32f310	209	product_id[4] = (char)(byte +
nikapov	0:a1a69d32f310	210	((tmp_dword >> 29) & 0x07f));
nikapov	0:a1a69d32f310	211	product_id[5] = (char)((tmp_dword >> 22) & 0x07f);
nikapov	0:a1a69d32f310	212	product_id[6] = (char)((tmp_dword >> 15) & 0x07f);
nikapov	0:a1a69d32f310	213	product_id[7] = (char)((tmp_dword >> 8) & 0x07f);
nikapov	0:a1a69d32f310	214	product_id[8] = (char)((tmp_dword >> 1) & 0x07f);
nikapov	0:a1a69d32f310	215
nikapov	0:a1a69d32f310	216	byte = (uint8_t)((tmp_dword & 0x001) << 6);
nikapov	0:a1a69d32f310	217
sepp_nepp	7:41cbc431e1f4	218	status \|= VL53L0X_write_byte(0x94,0x79);
sepp_nepp	7:41cbc431e1f4	219
sepp_nepp	7:41cbc431e1f4	220	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	221
sepp_nepp	7:41cbc431e1f4	222	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	223
nikapov	0:a1a69d32f310	224	product_id[9] = (char)(byte +
nikapov	0:a1a69d32f310	225	((tmp_dword >> 26) & 0x07f));
nikapov	0:a1a69d32f310	226	product_id[10] = (char)((tmp_dword >> 19) & 0x07f);
nikapov	0:a1a69d32f310	227	product_id[11] = (char)((tmp_dword >> 12) & 0x07f);
nikapov	0:a1a69d32f310	228	product_id[12] = (char)((tmp_dword >> 5) & 0x07f);
nikapov	0:a1a69d32f310	229
nikapov	0:a1a69d32f310	230	byte = (uint8_t)((tmp_dword & 0x01f) << 2);
nikapov	0:a1a69d32f310	231
sepp_nepp	7:41cbc431e1f4	232	status \|= VL53L0X_write_byte(0x94,0x7A);
sepp_nepp	7:41cbc431e1f4	233
sepp_nepp	7:41cbc431e1f4	234	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	235
sepp_nepp	7:41cbc431e1f4	236	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	237
nikapov	0:a1a69d32f310	238	product_id[13] = (char)(byte +
nikapov	0:a1a69d32f310	239	((tmp_dword >> 30) & 0x07f));
nikapov	0:a1a69d32f310	240	product_id[14] = (char)((tmp_dword >> 23) & 0x07f);
nikapov	0:a1a69d32f310	241	product_id[15] = (char)((tmp_dword >> 16) & 0x07f);
nikapov	0:a1a69d32f310	242	product_id[16] = (char)((tmp_dword >> 9) & 0x07f);
nikapov	0:a1a69d32f310	243	product_id[17] = (char)((tmp_dword >> 2) & 0x07f);
nikapov	0:a1a69d32f310	244	product_id[18] = '\0';
nikapov	0:a1a69d32f310	245
nikapov	0:a1a69d32f310	246	}
nikapov	0:a1a69d32f310	247
nikapov	0:a1a69d32f310	248	if (((option & 4) == 4) &&
nikapov	0:a1a69d32f310	249	((read_data_from_device_done & 4) == 0)) {
nikapov	0:a1a69d32f310	250
sepp_nepp	7:41cbc431e1f4	251	status \|= VL53L0X_write_byte(0x94,0x7B);
sepp_nepp	7:41cbc431e1f4	252	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	253	status \|= VL53L0X_read_dword(0x90,&part_uid_upper);
sepp_nepp	7:41cbc431e1f4	254
sepp_nepp	7:41cbc431e1f4	255	status \|= VL53L0X_write_byte(0x94,0x7C);
sepp_nepp	7:41cbc431e1f4	256	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	257	status \|= VL53L0X_read_dword(0x90,&part_uid_lower);
sepp_nepp	7:41cbc431e1f4	258
sepp_nepp	7:41cbc431e1f4	259	status \|= VL53L0X_write_byte(0x94,0x73);
sepp_nepp	7:41cbc431e1f4	260	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	261	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	262
nikapov	0:a1a69d32f310	263	signal_rate_meas_fixed1104_400_mm = (tmp_dword &
nikapov	0:a1a69d32f310	264	0x0000000ff) << 8;
nikapov	0:a1a69d32f310	265
sepp_nepp	7:41cbc431e1f4	266	status \|= VL53L0X_write_byte(0x94,0x74);
sepp_nepp	7:41cbc431e1f4	267	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	268	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	269
nikapov	0:a1a69d32f310	270	signal_rate_meas_fixed1104_400_mm \|= ((tmp_dword &
nikapov	0:a1a69d32f310	271	0xff000000) >> 24);
nikapov	0:a1a69d32f310	272
sepp_nepp	7:41cbc431e1f4	273	status \|= VL53L0X_write_byte(0x94,0x75);
sepp_nepp	7:41cbc431e1f4	274	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	275	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	276
nikapov	0:a1a69d32f310	277	dist_meas_fixed1104_400_mm = (tmp_dword & 0x0000000ff)
nikapov	0:a1a69d32f310	278	<< 8;
nikapov	0:a1a69d32f310	279
sepp_nepp	7:41cbc431e1f4	280	status \|= VL53L0X_write_byte(0x94,0x76);
sepp_nepp	7:41cbc431e1f4	281	status \|= VL53L0X_device_read_strobe();
sepp_nepp	7:41cbc431e1f4	282	status \|= VL53L0X_read_dword(0x90,&tmp_dword);
nikapov	0:a1a69d32f310	283
nikapov	0:a1a69d32f310	284	dist_meas_fixed1104_400_mm \|= ((tmp_dword & 0xff000000)
nikapov	0:a1a69d32f310	285	>> 24);
nikapov	0:a1a69d32f310	286	}
nikapov	0:a1a69d32f310	287
sepp_nepp	7:41cbc431e1f4	288	status \|= VL53L0X_write_byte(0x81,0x00);
sepp_nepp	7:41cbc431e1f4	289	status \|= VL53L0X_write_byte(0xFF,0x06);
sepp_nepp	7:41cbc431e1f4	290	status \|= VL53L0X_read_byte(0x83,&byte);
sepp_nepp	7:41cbc431e1f4	291	status \|= VL53L0X_write_byte(0x83,byte & 0xfb);
sepp_nepp	7:41cbc431e1f4	292	status \|= VL53L0X_write_byte(0xFF,0x01);
sepp_nepp	7:41cbc431e1f4	293	status \|= VL53L0X_write_byte(0x00,0x01);
sepp_nepp	7:41cbc431e1f4	294
sepp_nepp	7:41cbc431e1f4	295	status \|= VL53L0X_write_byte(0xFF,0x00);
sepp_nepp	7:41cbc431e1f4	296	status \|= VL53L0X_write_byte(0x80,0x00);
nikapov	0:a1a69d32f310	297	}
nikapov	0:a1a69d32f310	298
nikapov	0:a1a69d32f310	299	if ((status == VL53L0X_ERROR_NONE) &&
nikapov	0:a1a69d32f310	300	(read_data_from_device_done != 7)) {
nikapov	0:a1a69d32f310	301	/* Assign to variable if status is ok */
nikapov	0:a1a69d32f310	302	if (((option & 1) == 1) &&
nikapov	0:a1a69d32f310	303	((read_data_from_device_done & 1) == 0)) {
sepp_nepp	7:41cbc431e1f4	304	_device->DeviceSpecificParameters.ReferenceSpadCount=reference_spad_count;
sepp_nepp	8:abea9638127a	305	_device->DeviceSpecificParameters.ReferenceSpadType =reference_spad_type;
nikapov	0:a1a69d32f310	306	for (i = 0; i < VL53L0X_REF_SPAD_BUFFER_SIZE; i++) {
sepp_nepp	7:41cbc431e1f4	307	_device->SpadData.RefGoodSpadMap[i] =
nikapov	0:a1a69d32f310	308	nvm_ref_good_spad_map[i];
nikapov	0:a1a69d32f310	309	}
nikapov	0:a1a69d32f310	310	}
nikapov	0:a1a69d32f310	311
nikapov	0:a1a69d32f310	312	if (((option & 2) == 2) &&
nikapov	0:a1a69d32f310	313	((read_data_from_device_done & 2) == 0)) {
sepp_nepp	7:41cbc431e1f4	314	_device->DeviceSpecificParameters.ModuleId = module_id;
sepp_nepp	7:41cbc431e1f4	315	_device->DeviceSpecificParameters.Revision = revision;
sepp_nepp	7:41cbc431e1f4	316	product_id_tmp = _device->DeviceSpecificParameters.ProductId;
sepp_nepp	7:41cbc431e1f4	317	strcpy(product_id_tmp,product_id);
nikapov	0:a1a69d32f310	318
nikapov	0:a1a69d32f310	319	}
nikapov	0:a1a69d32f310	320
nikapov	0:a1a69d32f310	321	if (((option & 4) == 4) &&
nikapov	0:a1a69d32f310	322	((read_data_from_device_done & 4) == 0)) {
sepp_nepp	7:41cbc431e1f4	323	_device->DeviceSpecificParameters.PartUIDUpper = part_uid_upper;
sepp_nepp	7:41cbc431e1f4	324	_device->DeviceSpecificParameters.PartUIDLower = part_uid_lower;
nikapov	0:a1a69d32f310	325	signal_rate_meas_fixed400_mm_fix =
sepp_nepp	7:41cbc431e1f4	326	VL53L0X_FIXPOINT97TOFIXPOINT1616(signal_rate_meas_fixed1104_400_mm);
sepp_nepp	7:41cbc431e1f4	327	_device->DeviceSpecificParameters.SignalRateMeasFixed400mm = signal_rate_meas_fixed400_mm_fix;
sepp_nepp	7:41cbc431e1f4	328	_device->DeviceSpecificParameters.SignalRateMeasFixed400mm = signal_rate_meas_fixed400_mm_fix;
nikapov	0:a1a69d32f310	329
nikapov	0:a1a69d32f310	330	offset_micro_meters = 0;
nikapov	0:a1a69d32f310	331	if (dist_meas_fixed1104_400_mm != 0) {
nikapov	0:a1a69d32f310	332	offset_fixed1104_mm =
nikapov	0:a1a69d32f310	333	dist_meas_fixed1104_400_mm -
nikapov	0:a1a69d32f310	334	dist_meas_tgt_fixed1104_mm;
sepp_nepp	8:abea9638127a	335	offset_micro_meters = (offset_fixed1104_mm * 1000) >> 4;
nikapov	0:a1a69d32f310	336	offset_micro_meters *= -1;
nikapov	0:a1a69d32f310	337	}
sepp_nepp	7:41cbc431e1f4	338	_device->Part2PartOffsetAdjustmentNVMMicroMeter = offset_micro_meters;
nikapov	0:a1a69d32f310	339	}
nikapov	0:a1a69d32f310	340	byte = (uint8_t)(read_data_from_device_done \| option);
sepp_nepp	7:41cbc431e1f4	341	_device->DeviceSpecificParameters.ReadDataFromDeviceDone = byte;
nikapov	0:a1a69d32f310	342	}
nikapov	0:a1a69d32f310	343
sepp_nepp	5:b95f6951f7d5	344
nikapov	0:a1a69d32f310	345	return status;
nikapov	0:a1a69d32f310	346	}
nikapov	0:a1a69d32f310	347
sepp_nepp	7:41cbc431e1f4	348	VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_offset_calibration_data_micro_meter(int32_t *p_offset_calibration_data_micro_meter)
nikapov	0:a1a69d32f310	349	{
nikapov	0:a1a69d32f310	350	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	351	uint16_t range_offset_register;
nikapov	0:a1a69d32f310	352	int16_t c_max_offset = 2047;
nikapov	0:a1a69d32f310	353	int16_t c_offset_range = 4096;
nikapov	0:a1a69d32f310	354
nikapov	0:a1a69d32f310	355	/* Note that offset has 10.2 format */
nikapov	0:a1a69d32f310	356
sepp_nepp	7:41cbc431e1f4	357	status = VL53L0X_read_word(VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM,
nikapov	0:a1a69d32f310	358	&range_offset_register);
nikapov	0:a1a69d32f310	359
nikapov	0:a1a69d32f310	360	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	361	range_offset_register = (range_offset_register & 0x0fff);
nikapov	0:a1a69d32f310	362
nikapov	0:a1a69d32f310	363	/* Apply 12 bit 2's compliment conversion */
nikapov	0:a1a69d32f310	364	if (range_offset_register > c_max_offset) {
nikapov	0:a1a69d32f310	365	*p_offset_calibration_data_micro_meter =
nikapov	0:a1a69d32f310	366	(int16_t)(range_offset_register - c_offset_range)
nikapov	0:a1a69d32f310	367	* 250;
nikapov	0:a1a69d32f310	368	} else {
nikapov	0:a1a69d32f310	369	*p_offset_calibration_data_micro_meter =
nikapov	0:a1a69d32f310	370	(int16_t)range_offset_register * 250;
nikapov	0:a1a69d32f310	371	}
nikapov	0:a1a69d32f310	372
nikapov	0:a1a69d32f310	373	}
nikapov	0:a1a69d32f310	374
nikapov	0:a1a69d32f310	375	return status;
nikapov	0:a1a69d32f310	376	}
nikapov	0:a1a69d32f310	377
sepp_nepp	7:41cbc431e1f4	378	VL53L0X_Error VL53L0X::VL53L0X_get_offset_calibration_data_micro_meter(int32_t *p_offset_calibration_data_micro_meter)
nikapov	0:a1a69d32f310	379	{
nikapov	0:a1a69d32f310	380	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	381
nikapov	0:a1a69d32f310	382
sepp_nepp	7:41cbc431e1f4	383	status = wrapped_VL53L0X_get_offset_calibration_data_micro_meter(p_offset_calibration_data_micro_meter);
nikapov	0:a1a69d32f310	384
sepp_nepp	5:b95f6951f7d5	385
nikapov	0:a1a69d32f310	386	return status;
nikapov	0:a1a69d32f310	387	}
nikapov	0:a1a69d32f310	388
sepp_nepp	7:41cbc431e1f4	389	VL53L0X_Error VL53L0X::wrapped_VL53L0X_set_offset_calibration_data_micro_meter(int32_t offset_calibration_data_micro_meter)
nikapov	0:a1a69d32f310	390	{
nikapov	0:a1a69d32f310	391	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	392	int32_t c_max_offset_micro_meter = 511000;
nikapov	0:a1a69d32f310	393	int32_t c_min_offset_micro_meter = -512000;
nikapov	0:a1a69d32f310	394	int16_t c_offset_range = 4096;
nikapov	0:a1a69d32f310	395	uint32_t encoded_offset_val;
nikapov	0:a1a69d32f310	396
sepp_nepp	5:b95f6951f7d5	397
nikapov	0:a1a69d32f310	398
nikapov	0:a1a69d32f310	399	if (offset_calibration_data_micro_meter > c_max_offset_micro_meter) {
nikapov	0:a1a69d32f310	400	offset_calibration_data_micro_meter = c_max_offset_micro_meter;
nikapov	0:a1a69d32f310	401	} else {
nikapov	0:a1a69d32f310	402	if (offset_calibration_data_micro_meter < c_min_offset_micro_meter) {
Davidroid	2:d07edeaff6f1	403	offset_calibration_data_micro_meter = c_min_offset_micro_meter;
Davidroid	2:d07edeaff6f1	404	}
Davidroid	2:d07edeaff6f1	405	}
nikapov	0:a1a69d32f310	406
nikapov	0:a1a69d32f310	407	/* The offset register is 10.2 format and units are mm
nikapov	0:a1a69d32f310	408	* therefore conversion is applied by a division of
nikapov	0:a1a69d32f310	409	* 250.
nikapov	0:a1a69d32f310	410	*/
nikapov	0:a1a69d32f310	411	if (offset_calibration_data_micro_meter >= 0) {
nikapov	0:a1a69d32f310	412	encoded_offset_val =
nikapov	0:a1a69d32f310	413	offset_calibration_data_micro_meter / 250;
nikapov	0:a1a69d32f310	414	} else {
nikapov	0:a1a69d32f310	415	encoded_offset_val =
nikapov	0:a1a69d32f310	416	c_offset_range +
nikapov	0:a1a69d32f310	417	offset_calibration_data_micro_meter / 250;
nikapov	0:a1a69d32f310	418	}
nikapov	0:a1a69d32f310	419
sepp_nepp	7:41cbc431e1f4	420	status = VL53L0X_write_word(VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM,
nikapov	0:a1a69d32f310	421	encoded_offset_val);
nikapov	0:a1a69d32f310	422
sepp_nepp	5:b95f6951f7d5	423
nikapov	0:a1a69d32f310	424	return status;
nikapov	0:a1a69d32f310	425	}
nikapov	0:a1a69d32f310	426
sepp_nepp	7:41cbc431e1f4	427	VL53L0X_Error VL53L0X::VL53L0X_set_offset_calibration_data_micro_meter(int32_t offset_calibration_data_micro_meter)
nikapov	0:a1a69d32f310	428	{
nikapov	0:a1a69d32f310	429	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	430
nikapov	0:a1a69d32f310	431
sepp_nepp	7:41cbc431e1f4	432	status = wrapped_VL53L0X_set_offset_calibration_data_micro_meter(offset_calibration_data_micro_meter);
nikapov	0:a1a69d32f310	433
sepp_nepp	5:b95f6951f7d5	434
nikapov	0:a1a69d32f310	435	return status;
nikapov	0:a1a69d32f310	436	}
nikapov	0:a1a69d32f310	437
sepp_nepp	7:41cbc431e1f4	438	VL53L0X_Error VL53L0X::VL53L0X_apply_offset_adjustment()
nikapov	0:a1a69d32f310	439	{
nikapov	0:a1a69d32f310	440	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	441	int32_t corrected_offset_micro_meters;
nikapov	0:a1a69d32f310	442	int32_t current_offset_micro_meters;
nikapov	0:a1a69d32f310	443
nikapov	0:a1a69d32f310	444	/* if we run on this function we can read all the NVM info
nikapov	0:a1a69d32f310	445	* used by the API */
sepp_nepp	7:41cbc431e1f4	446	status = VL53L0X_get_info_from_device(7);
nikapov	0:a1a69d32f310	447
nikapov	0:a1a69d32f310	448	/* Read back current device offset */
nikapov	0:a1a69d32f310	449	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	450	status = VL53L0X_get_offset_calibration_data_micro_meter(&current_offset_micro_meters);
nikapov	0:a1a69d32f310	451	}
nikapov	0:a1a69d32f310	452
nikapov	0:a1a69d32f310	453	/* Apply Offset Adjustment derived from 400mm measurements */
nikapov	0:a1a69d32f310	454	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	455
nikapov	0:a1a69d32f310	456	/* Store initial device offset */
sepp_nepp	7:41cbc431e1f4	457	_device->Part2PartOffsetNVMMicroMeter = current_offset_micro_meters;
nikapov	0:a1a69d32f310	458
nikapov	0:a1a69d32f310	459	corrected_offset_micro_meters = current_offset_micro_meters +
sepp_nepp	7:41cbc431e1f4	460	(int32_t) _device->Part2PartOffsetAdjustmentNVMMicroMeter;
sepp_nepp	7:41cbc431e1f4	461
sepp_nepp	7:41cbc431e1f4	462	status = VL53L0X_set_offset_calibration_data_micro_meter(corrected_offset_micro_meters);
sepp_nepp	7:41cbc431e1f4	463
sepp_nepp	7:41cbc431e1f4	464	/* store current,adjusted offset */
nikapov	0:a1a69d32f310	465	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	466	_device->CurrentParameters.RangeOffsetMicroMeters = corrected_offset_micro_meters;
nikapov	0:a1a69d32f310	467	}
nikapov	0:a1a69d32f310	468	}
nikapov	0:a1a69d32f310	469
nikapov	0:a1a69d32f310	470	return status;
nikapov	0:a1a69d32f310	471	}
nikapov	0:a1a69d32f310	472
sepp_nepp	7:41cbc431e1f4	473	VL53L0X_Error VL53L0X::VL53L0X_get_device_mode(VL53L0X_DeviceModes *p_device_mode)
nikapov	0:a1a69d32f310	474	{
nikapov	0:a1a69d32f310	475	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	476
sepp_nepp	7:41cbc431e1f4	477	*p_device_mode = _device->CurrentParameters.DeviceMode;
sepp_nepp	5:b95f6951f7d5	478
nikapov	0:a1a69d32f310	479	return status;
nikapov	0:a1a69d32f310	480	}
nikapov	0:a1a69d32f310	481
sepp_nepp	7:41cbc431e1f4	482	VL53L0X_Error VL53L0X::VL53L0X_get_inter_measurement_period_milli_seconds(uint32_t *p_inter_measurement_period_milli_seconds)
nikapov	0:a1a69d32f310	483	{
nikapov	0:a1a69d32f310	484	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	485	uint16_t osc_calibrate_val;
nikapov	0:a1a69d32f310	486	uint32_t im_period_milli_seconds;
nikapov	0:a1a69d32f310	487
sepp_nepp	5:b95f6951f7d5	488
nikapov	0:a1a69d32f310	489
sepp_nepp	7:41cbc431e1f4	490	status = VL53L0X_read_word(VL53L0X_REG_OSC_CALIBRATE_VAL,
nikapov	0:a1a69d32f310	491	&osc_calibrate_val);
nikapov	0:a1a69d32f310	492
nikapov	0:a1a69d32f310	493	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	494	status = VL53L0X_read_dword(VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD,
nikapov	0:a1a69d32f310	495	&im_period_milli_seconds);
nikapov	0:a1a69d32f310	496	}
nikapov	0:a1a69d32f310	497
nikapov	0:a1a69d32f310	498	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	499	if (osc_calibrate_val != 0) {
nikapov	0:a1a69d32f310	500	*p_inter_measurement_period_milli_seconds =
nikapov	0:a1a69d32f310	501	im_period_milli_seconds / osc_calibrate_val;
nikapov	0:a1a69d32f310	502	}
sepp_nepp	7:41cbc431e1f4	503	_device->CurrentParameters.InterMeasurementPeriodMilliSeconds=
sepp_nepp	7:41cbc431e1f4	504	*p_inter_measurement_period_milli_seconds;
nikapov	0:a1a69d32f310	505	}
nikapov	0:a1a69d32f310	506
sepp_nepp	5:b95f6951f7d5	507
nikapov	0:a1a69d32f310	508	return status;
nikapov	0:a1a69d32f310	509	}
nikapov	0:a1a69d32f310	510
sepp_nepp	7:41cbc431e1f4	511	VL53L0X_Error VL53L0X::VL53L0X_get_x_talk_compensation_rate_mega_cps(FixPoint1616_t *p_xtalk_compensation_rate_mega_cps)
nikapov	0:a1a69d32f310	512	{
nikapov	0:a1a69d32f310	513	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	514	uint16_t value;
nikapov	0:a1a69d32f310	515	FixPoint1616_t temp_fix1616;
nikapov	0:a1a69d32f310	516
sepp_nepp	5:b95f6951f7d5	517
nikapov	0:a1a69d32f310	518
sepp_nepp	7:41cbc431e1f4	519	status = VL53L0X_read_word(VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS,(uint16_t *)&value);
nikapov	0:a1a69d32f310	520	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	521	if (value == 0) {
nikapov	0:a1a69d32f310	522	/* the Xtalk is disabled return value from memory */
sepp_nepp	7:41cbc431e1f4	523	temp_fix1616 = _device->CurrentParameters.XTalkCompensationRateMegaCps;
nikapov	0:a1a69d32f310	524	*p_xtalk_compensation_rate_mega_cps = temp_fix1616;
sepp_nepp	7:41cbc431e1f4	525	_device->CurrentParameters.XTalkCompensationEnable = 0;
nikapov	0:a1a69d32f310	526	} else {
nikapov	0:a1a69d32f310	527	temp_fix1616 = VL53L0X_FIXPOINT313TOFIXPOINT1616(value);
nikapov	0:a1a69d32f310	528	*p_xtalk_compensation_rate_mega_cps = temp_fix1616;
sepp_nepp	7:41cbc431e1f4	529	_device->CurrentParameters.XTalkCompensationRateMegaCps = temp_fix1616;
sepp_nepp	7:41cbc431e1f4	530	_device->CurrentParameters.XTalkCompensationEnable = 1;
nikapov	0:a1a69d32f310	531	}
nikapov	0:a1a69d32f310	532	}
nikapov	0:a1a69d32f310	533
sepp_nepp	5:b95f6951f7d5	534
nikapov	0:a1a69d32f310	535	return status;
nikapov	0:a1a69d32f310	536	}
nikapov	0:a1a69d32f310	537
sepp_nepp	7:41cbc431e1f4	538	VL53L0X_Error VL53L0X::VL53L0X_get_limit_check_value(uint16_t limit_check_id,
nikapov	0:a1a69d32f310	539	FixPoint1616_t *p_limit_check_value)
nikapov	0:a1a69d32f310	540	{
nikapov	0:a1a69d32f310	541	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	542	uint8_t enable_zero_value = 0;
nikapov	0:a1a69d32f310	543	uint16_t temp16;
nikapov	0:a1a69d32f310	544	FixPoint1616_t temp_fix1616;
nikapov	0:a1a69d32f310	545
sepp_nepp	5:b95f6951f7d5	546
nikapov	0:a1a69d32f310	547
nikapov	0:a1a69d32f310	548	switch (limit_check_id) {
nikapov	0:a1a69d32f310	549
nikapov	0:a1a69d32f310	550	case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
nikapov	0:a1a69d32f310	551	/* internal computation: */
sepp_nepp	7:41cbc431e1f4	552	temp_fix1616 = _device->CurrentParameters.LimitChecksValue[VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE];
nikapov	0:a1a69d32f310	553	enable_zero_value = 0;
nikapov	0:a1a69d32f310	554	break;
nikapov	0:a1a69d32f310	555
nikapov	0:a1a69d32f310	556	case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
sepp_nepp	7:41cbc431e1f4	557	status = VL53L0X_read_word(VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
nikapov	0:a1a69d32f310	558	&temp16);
Davidroid	3:e9269ff624ed	559	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	560	temp_fix1616 = VL53L0X_FIXPOINT97TOFIXPOINT1616(temp16);
Davidroid	3:e9269ff624ed	561	}
nikapov	0:a1a69d32f310	562
nikapov	0:a1a69d32f310	563
nikapov	0:a1a69d32f310	564	enable_zero_value = 1;
nikapov	0:a1a69d32f310	565	break;
nikapov	0:a1a69d32f310	566
nikapov	0:a1a69d32f310	567	case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
nikapov	0:a1a69d32f310	568	/* internal computation: */
sepp_nepp	7:41cbc431e1f4	569	temp_fix1616 = _device->CurrentParameters.LimitChecksValue[VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP];
nikapov	0:a1a69d32f310	570	enable_zero_value = 0;
nikapov	0:a1a69d32f310	571	break;
nikapov	0:a1a69d32f310	572
nikapov	0:a1a69d32f310	573	case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
nikapov	0:a1a69d32f310	574	/* internal computation: */
sepp_nepp	7:41cbc431e1f4	575	temp_fix1616 = _device->CurrentParameters.LimitChecksValue[VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD];
nikapov	0:a1a69d32f310	576	enable_zero_value = 0;
nikapov	0:a1a69d32f310	577	break;
nikapov	0:a1a69d32f310	578
nikapov	0:a1a69d32f310	579	case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
nikapov	0:a1a69d32f310	580	case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
sepp_nepp	7:41cbc431e1f4	581	status = VL53L0X_read_word(VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT,
nikapov	0:a1a69d32f310	582	&temp16);
Davidroid	3:e9269ff624ed	583	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	584	temp_fix1616 = VL53L0X_FIXPOINT97TOFIXPOINT1616(temp16);
Davidroid	3:e9269ff624ed	585	}
nikapov	0:a1a69d32f310	586
nikapov	0:a1a69d32f310	587
nikapov	0:a1a69d32f310	588	enable_zero_value = 0;
nikapov	0:a1a69d32f310	589	break;
nikapov	0:a1a69d32f310	590
nikapov	0:a1a69d32f310	591	default:
nikapov	0:a1a69d32f310	592	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	593
nikapov	0:a1a69d32f310	594	}
nikapov	0:a1a69d32f310	595
nikapov	0:a1a69d32f310	596	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	597
nikapov	0:a1a69d32f310	598	if (enable_zero_value == 1) {
nikapov	0:a1a69d32f310	599
nikapov	0:a1a69d32f310	600	if (temp_fix1616 == 0) {
nikapov	0:a1a69d32f310	601	/* disabled: return value from memory */
sepp_nepp	7:41cbc431e1f4	602	temp_fix1616 = _device->CurrentParameters.LimitChecksValue[limit_check_id];
nikapov	0:a1a69d32f310	603	*p_limit_check_value = temp_fix1616;
sepp_nepp	7:41cbc431e1f4	604	_device->CurrentParameters.LimitChecksEnable[limit_check_id] = 0;
sepp_nepp	7:41cbc431e1f4	605	_device->CurrentParameters.LimitChecksEnable[limit_check_id] = 0;
nikapov	0:a1a69d32f310	606	} else {
nikapov	0:a1a69d32f310	607	*p_limit_check_value = temp_fix1616;
sepp_nepp	7:41cbc431e1f4	608	_device->CurrentParameters.LimitChecksValue[limit_check_id] = temp_fix1616;
sepp_nepp	7:41cbc431e1f4	609	_device->CurrentParameters.LimitChecksEnable[limit_check_id] = 1;
nikapov	0:a1a69d32f310	610	}
nikapov	0:a1a69d32f310	611	} else {
nikapov	0:a1a69d32f310	612	*p_limit_check_value = temp_fix1616;
nikapov	0:a1a69d32f310	613	}
nikapov	0:a1a69d32f310	614	}
nikapov	0:a1a69d32f310	615
sepp_nepp	5:b95f6951f7d5	616
nikapov	0:a1a69d32f310	617	return status;
nikapov	0:a1a69d32f310	618
nikapov	0:a1a69d32f310	619	}
nikapov	0:a1a69d32f310	620
sepp_nepp	7:41cbc431e1f4	621	VL53L0X_Error VL53L0X::VL53L0X_get_limit_check_enable(uint16_t limit_check_id,
nikapov	0:a1a69d32f310	622	uint8_t *p_limit_check_enable)
nikapov	0:a1a69d32f310	623	{
nikapov	0:a1a69d32f310	624	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	625	uint8_t temp8;
nikapov	0:a1a69d32f310	626
sepp_nepp	5:b95f6951f7d5	627
nikapov	0:a1a69d32f310	628
nikapov	0:a1a69d32f310	629	if (limit_check_id >= VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS) {
nikapov	0:a1a69d32f310	630	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	631	*p_limit_check_enable = 0;
nikapov	0:a1a69d32f310	632	} else {
sepp_nepp	7:41cbc431e1f4	633	temp8 = _device->CurrentParameters.LimitChecksEnable[limit_check_id];
nikapov	0:a1a69d32f310	634	*p_limit_check_enable = temp8;
nikapov	0:a1a69d32f310	635	}
nikapov	0:a1a69d32f310	636
sepp_nepp	5:b95f6951f7d5	637
nikapov	0:a1a69d32f310	638	return status;
nikapov	0:a1a69d32f310	639	}
nikapov	0:a1a69d32f310	640
sepp_nepp	7:41cbc431e1f4	641	VL53L0X_Error VL53L0X::VL53L0X_get_wrap_around_check_enable(uint8_t *p_wrap_around_check_enable)
nikapov	0:a1a69d32f310	642	{
nikapov	0:a1a69d32f310	643	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	644	uint8_t data;
nikapov	0:a1a69d32f310	645
sepp_nepp	5:b95f6951f7d5	646
nikapov	0:a1a69d32f310	647
sepp_nepp	7:41cbc431e1f4	648	status = VL53L0X_read_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,&data);
nikapov	0:a1a69d32f310	649	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	650	_device->SequenceConfig = data;
Davidroid	3:e9269ff624ed	651	if (data & (0x01 << 7)) {
nikapov	0:a1a69d32f310	652	*p_wrap_around_check_enable = 0x01;
Davidroid	3:e9269ff624ed	653	} else {
nikapov	0:a1a69d32f310	654	*p_wrap_around_check_enable = 0x00;
Davidroid	3:e9269ff624ed	655	}
nikapov	0:a1a69d32f310	656	}
nikapov	0:a1a69d32f310	657	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	658	_device->CurrentParameters.WrapAroundCheckEnable=
sepp_nepp	7:41cbc431e1f4	659	*p_wrap_around_check_enable;
nikapov	0:a1a69d32f310	660	}
nikapov	0:a1a69d32f310	661
sepp_nepp	5:b95f6951f7d5	662
nikapov	0:a1a69d32f310	663	return status;
nikapov	0:a1a69d32f310	664	}
nikapov	0:a1a69d32f310	665
sepp_nepp	7:41cbc431e1f4	666	VL53L0X_Error VL53L0X::sequence_step_enabled(VL53L0X_SequenceStepId sequence_step_id,uint8_t sequence_config,
nikapov	0:a1a69d32f310	667	uint8_t *p_sequence_step_enabled)
nikapov	0:a1a69d32f310	668	{
nikapov	0:a1a69d32f310	669	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	670	*p_sequence_step_enabled = 0;
sepp_nepp	5:b95f6951f7d5	671
nikapov	0:a1a69d32f310	672
nikapov	0:a1a69d32f310	673	switch (sequence_step_id) {
nikapov	0:a1a69d32f310	674	case VL53L0X_SEQUENCESTEP_TCC:
nikapov	0:a1a69d32f310	675	*p_sequence_step_enabled = (sequence_config & 0x10) >> 4;
nikapov	0:a1a69d32f310	676	break;
nikapov	0:a1a69d32f310	677	case VL53L0X_SEQUENCESTEP_DSS:
nikapov	0:a1a69d32f310	678	*p_sequence_step_enabled = (sequence_config & 0x08) >> 3;
nikapov	0:a1a69d32f310	679	break;
nikapov	0:a1a69d32f310	680	case VL53L0X_SEQUENCESTEP_MSRC:
nikapov	0:a1a69d32f310	681	*p_sequence_step_enabled = (sequence_config & 0x04) >> 2;
nikapov	0:a1a69d32f310	682	break;
nikapov	0:a1a69d32f310	683	case VL53L0X_SEQUENCESTEP_PRE_RANGE:
nikapov	0:a1a69d32f310	684	*p_sequence_step_enabled = (sequence_config & 0x40) >> 6;
nikapov	0:a1a69d32f310	685	break;
nikapov	0:a1a69d32f310	686	case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
nikapov	0:a1a69d32f310	687	*p_sequence_step_enabled = (sequence_config & 0x80) >> 7;
nikapov	0:a1a69d32f310	688	break;
nikapov	0:a1a69d32f310	689	default:
nikapov	0:a1a69d32f310	690	Status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	691	}
nikapov	0:a1a69d32f310	692
sepp_nepp	5:b95f6951f7d5	693
nikapov	0:a1a69d32f310	694	return Status;
nikapov	0:a1a69d32f310	695	}
nikapov	0:a1a69d32f310	696
sepp_nepp	7:41cbc431e1f4	697	VL53L0X_Error VL53L0X::VL53L0X_get_sequence_step_enables(VL53L0X_SchedulerSequenceSteps_t *p_scheduler_sequence_steps)
nikapov	0:a1a69d32f310	698	{
nikapov	0:a1a69d32f310	699	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	700	uint8_t sequence_config = 0;
sepp_nepp	5:b95f6951f7d5	701
nikapov	0:a1a69d32f310	702
sepp_nepp	7:41cbc431e1f4	703	status = VL53L0X_read_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
nikapov	0:a1a69d32f310	704	&sequence_config);
nikapov	0:a1a69d32f310	705
nikapov	0:a1a69d32f310	706	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	707	status = sequence_step_enabled(VL53L0X_SEQUENCESTEP_TCC,sequence_config,
nikapov	0:a1a69d32f310	708	&p_scheduler_sequence_steps->TccOn);
nikapov	0:a1a69d32f310	709	}
nikapov	0:a1a69d32f310	710	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	711	status = sequence_step_enabled(VL53L0X_SEQUENCESTEP_DSS,sequence_config,
nikapov	0:a1a69d32f310	712	&p_scheduler_sequence_steps->DssOn);
nikapov	0:a1a69d32f310	713	}
nikapov	0:a1a69d32f310	714	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	715	status = sequence_step_enabled(VL53L0X_SEQUENCESTEP_MSRC,sequence_config,
nikapov	0:a1a69d32f310	716	&p_scheduler_sequence_steps->MsrcOn);
nikapov	0:a1a69d32f310	717	}
nikapov	0:a1a69d32f310	718	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	719	status = sequence_step_enabled(VL53L0X_SEQUENCESTEP_PRE_RANGE,sequence_config,
nikapov	0:a1a69d32f310	720	&p_scheduler_sequence_steps->PreRangeOn);
nikapov	0:a1a69d32f310	721	}
nikapov	0:a1a69d32f310	722	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	723	status = sequence_step_enabled(VL53L0X_SEQUENCESTEP_FINAL_RANGE,sequence_config,
nikapov	0:a1a69d32f310	724	&p_scheduler_sequence_steps->FinalRangeOn);
nikapov	0:a1a69d32f310	725	}
nikapov	0:a1a69d32f310	726
sepp_nepp	5:b95f6951f7d5	727
nikapov	0:a1a69d32f310	728	return status;
nikapov	0:a1a69d32f310	729	}
nikapov	0:a1a69d32f310	730
nikapov	0:a1a69d32f310	731	uint8_t VL53L0X::VL53L0X_decode_vcsel_period(uint8_t vcsel_period_reg)
nikapov	0:a1a69d32f310	732	{
nikapov	0:a1a69d32f310	733	/*!
nikapov	0:a1a69d32f310	734	* Converts the encoded VCSEL period register value into the real
nikapov	0:a1a69d32f310	735	* period in PLL clocks
nikapov	0:a1a69d32f310	736	*/
nikapov	0:a1a69d32f310	737
nikapov	0:a1a69d32f310	738	uint8_t vcsel_period_pclks = 0;
nikapov	0:a1a69d32f310	739
nikapov	0:a1a69d32f310	740	vcsel_period_pclks = (vcsel_period_reg + 1) << 1;
nikapov	0:a1a69d32f310	741
nikapov	0:a1a69d32f310	742	return vcsel_period_pclks;
nikapov	0:a1a69d32f310	743	}
nikapov	0:a1a69d32f310	744
nikapov	0:a1a69d32f310	745	uint8_t VL53L0X::lv53l0x_encode_vcsel_period(uint8_t vcsel_period_pclks)
nikapov	0:a1a69d32f310	746	{
nikapov	0:a1a69d32f310	747	/*!
nikapov	0:a1a69d32f310	748	* Converts the encoded VCSEL period register value into the real period
nikapov	0:a1a69d32f310	749	* in PLL clocks
nikapov	0:a1a69d32f310	750	*/
nikapov	0:a1a69d32f310	751
nikapov	0:a1a69d32f310	752	uint8_t vcsel_period_reg = 0;
nikapov	0:a1a69d32f310	753
nikapov	0:a1a69d32f310	754	vcsel_period_reg = (vcsel_period_pclks >> 1) - 1;
nikapov	0:a1a69d32f310	755
nikapov	0:a1a69d32f310	756	return vcsel_period_reg;
nikapov	0:a1a69d32f310	757	}
nikapov	0:a1a69d32f310	758
nikapov	0:a1a69d32f310	759
sepp_nepp	7:41cbc431e1f4	760	VL53L0X_Error VL53L0X::wrapped_VL53L0X_set_vcsel_pulse_period(VL53L0X_VcselPeriod vcsel_period_type,uint8_t vcsel_pulse_period_pclk)
nikapov	0:a1a69d32f310	761	{
nikapov	0:a1a69d32f310	762	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	763	uint8_t vcsel_period_reg;
nikapov	0:a1a69d32f310	764	uint8_t min_pre_vcsel_period_pclk = 12;
nikapov	0:a1a69d32f310	765	uint8_t max_pre_vcsel_period_pclk = 18;
nikapov	0:a1a69d32f310	766	uint8_t min_final_vcsel_period_pclk = 8;
nikapov	0:a1a69d32f310	767	uint8_t max_final_vcsel_period_pclk = 14;
nikapov	0:a1a69d32f310	768	uint32_t measurement_timing_budget_micro_seconds;
nikapov	0:a1a69d32f310	769	uint32_t final_range_timeout_micro_seconds;
nikapov	0:a1a69d32f310	770	uint32_t pre_range_timeout_micro_seconds;
nikapov	0:a1a69d32f310	771	uint32_t msrc_timeout_micro_seconds;
nikapov	0:a1a69d32f310	772	uint8_t phase_cal_int = 0;
nikapov	0:a1a69d32f310	773
nikapov	0:a1a69d32f310	774	/* Check if valid clock period requested */
nikapov	0:a1a69d32f310	775
nikapov	0:a1a69d32f310	776	if ((vcsel_pulse_period_pclk % 2) != 0) {
nikapov	0:a1a69d32f310	777	/* Value must be an even number */
nikapov	0:a1a69d32f310	778	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	779	} else if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_PRE_RANGE &&
nikapov	0:a1a69d32f310	780	(vcsel_pulse_period_pclk < min_pre_vcsel_period_pclk \|\|
nikapov	0:a1a69d32f310	781	vcsel_pulse_period_pclk > max_pre_vcsel_period_pclk)) {
nikapov	0:a1a69d32f310	782	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	783	} else if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_FINAL_RANGE &&
nikapov	0:a1a69d32f310	784	(vcsel_pulse_period_pclk < min_final_vcsel_period_pclk \|\|
nikapov	0:a1a69d32f310	785	vcsel_pulse_period_pclk > max_final_vcsel_period_pclk)) {
nikapov	0:a1a69d32f310	786
nikapov	0:a1a69d32f310	787	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	788	}
nikapov	0:a1a69d32f310	789
nikapov	0:a1a69d32f310	790	/* Apply specific settings for the requested clock period */
nikapov	0:a1a69d32f310	791
Davidroid	3:e9269ff624ed	792	if (status != VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	793	return status;
Davidroid	3:e9269ff624ed	794	}
nikapov	0:a1a69d32f310	795
nikapov	0:a1a69d32f310	796
nikapov	0:a1a69d32f310	797	if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_PRE_RANGE) {
nikapov	0:a1a69d32f310	798
nikapov	0:a1a69d32f310	799	/* Set phase check limits */
nikapov	0:a1a69d32f310	800	if (vcsel_pulse_period_pclk == 12) {
nikapov	0:a1a69d32f310	801
sepp_nepp	7:41cbc431e1f4	802	status = VL53L0X_write_byte(VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
nikapov	0:a1a69d32f310	803	0x18);
sepp_nepp	7:41cbc431e1f4	804	status = VL53L0X_write_byte(VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
nikapov	0:a1a69d32f310	805	0x08);
nikapov	0:a1a69d32f310	806	} else if (vcsel_pulse_period_pclk == 14) {
nikapov	0:a1a69d32f310	807
sepp_nepp	7:41cbc431e1f4	808	status = VL53L0X_write_byte(VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
nikapov	0:a1a69d32f310	809	0x30);
sepp_nepp	7:41cbc431e1f4	810	status = VL53L0X_write_byte(VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
nikapov	0:a1a69d32f310	811	0x08);
nikapov	0:a1a69d32f310	812	} else if (vcsel_pulse_period_pclk == 16) {
nikapov	0:a1a69d32f310	813
sepp_nepp	7:41cbc431e1f4	814	status = VL53L0X_write_byte(VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
nikapov	0:a1a69d32f310	815	0x40);
sepp_nepp	7:41cbc431e1f4	816	status = VL53L0X_write_byte(VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
nikapov	0:a1a69d32f310	817	0x08);
nikapov	0:a1a69d32f310	818	} else if (vcsel_pulse_period_pclk == 18) {
nikapov	0:a1a69d32f310	819
sepp_nepp	7:41cbc431e1f4	820	status = VL53L0X_write_byte(VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
nikapov	0:a1a69d32f310	821	0x50);
sepp_nepp	7:41cbc431e1f4	822	status = VL53L0X_write_byte(VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
nikapov	0:a1a69d32f310	823	0x08);
nikapov	0:a1a69d32f310	824	}
nikapov	0:a1a69d32f310	825	} else if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_FINAL_RANGE) {
nikapov	0:a1a69d32f310	826
nikapov	0:a1a69d32f310	827	if (vcsel_pulse_period_pclk == 8) {
nikapov	0:a1a69d32f310	828
sepp_nepp	7:41cbc431e1f4	829	status = VL53L0X_write_byte(VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
nikapov	0:a1a69d32f310	830	0x10);
sepp_nepp	7:41cbc431e1f4	831	status = VL53L0X_write_byte(VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
nikapov	0:a1a69d32f310	832	0x08);
nikapov	0:a1a69d32f310	833
sepp_nepp	7:41cbc431e1f4	834	status \|= VL53L0X_write_byte(VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH,0x02);
sepp_nepp	7:41cbc431e1f4	835	status \|= VL53L0X_write_byte(VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT,0x0C);
sepp_nepp	7:41cbc431e1f4	836
sepp_nepp	7:41cbc431e1f4	837	status \|= VL53L0X_write_byte(0xff,0x01);
sepp_nepp	7:41cbc431e1f4	838	status \|= VL53L0X_write_byte(VL53L0X_REG_ALGO_PHASECAL_LIM,
nikapov	0:a1a69d32f310	839	0x30);
sepp_nepp	7:41cbc431e1f4	840	status \|= VL53L0X_write_byte(0xff,0x00);
nikapov	0:a1a69d32f310	841	} else if (vcsel_pulse_period_pclk == 10) {
nikapov	0:a1a69d32f310	842
sepp_nepp	7:41cbc431e1f4	843	status = VL53L0X_write_byte(VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
nikapov	0:a1a69d32f310	844	0x28);
sepp_nepp	7:41cbc431e1f4	845	status = VL53L0X_write_byte(VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
nikapov	0:a1a69d32f310	846	0x08);
nikapov	0:a1a69d32f310	847
sepp_nepp	7:41cbc431e1f4	848	status \|= VL53L0X_write_byte(VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH,0x03);
sepp_nepp	7:41cbc431e1f4	849	status \|= VL53L0X_write_byte(VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT,0x09);
sepp_nepp	7:41cbc431e1f4	850
sepp_nepp	7:41cbc431e1f4	851	status \|= VL53L0X_write_byte(0xff,0x01);
sepp_nepp	7:41cbc431e1f4	852	status \|= VL53L0X_write_byte(VL53L0X_REG_ALGO_PHASECAL_LIM,
nikapov	0:a1a69d32f310	853	0x20);
sepp_nepp	7:41cbc431e1f4	854	status \|= VL53L0X_write_byte(0xff,0x00);
nikapov	0:a1a69d32f310	855	} else if (vcsel_pulse_period_pclk == 12) {
nikapov	0:a1a69d32f310	856
sepp_nepp	7:41cbc431e1f4	857	status = VL53L0X_write_byte(VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
nikapov	0:a1a69d32f310	858	0x38);
sepp_nepp	7:41cbc431e1f4	859	status = VL53L0X_write_byte(VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
nikapov	0:a1a69d32f310	860	0x08);
nikapov	0:a1a69d32f310	861
sepp_nepp	7:41cbc431e1f4	862	status \|= VL53L0X_write_byte(VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH,0x03);
sepp_nepp	7:41cbc431e1f4	863	status \|= VL53L0X_write_byte(VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT,0x08);
sepp_nepp	7:41cbc431e1f4	864
sepp_nepp	7:41cbc431e1f4	865	status \|= VL53L0X_write_byte(0xff,0x01);
sepp_nepp	7:41cbc431e1f4	866	status \|= VL53L0X_write_byte(VL53L0X_REG_ALGO_PHASECAL_LIM,
nikapov	0:a1a69d32f310	867	0x20);
sepp_nepp	7:41cbc431e1f4	868	status \|= VL53L0X_write_byte(0xff,0x00);
nikapov	0:a1a69d32f310	869	} else if (vcsel_pulse_period_pclk == 14) {
nikapov	0:a1a69d32f310	870
sepp_nepp	7:41cbc431e1f4	871	status = VL53L0X_write_byte(VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
nikapov	0:a1a69d32f310	872	0x048);
sepp_nepp	7:41cbc431e1f4	873	status = VL53L0X_write_byte(VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
nikapov	0:a1a69d32f310	874	0x08);
nikapov	0:a1a69d32f310	875
sepp_nepp	7:41cbc431e1f4	876	status \|= VL53L0X_write_byte(VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH,0x03);
sepp_nepp	7:41cbc431e1f4	877	status \|= VL53L0X_write_byte(VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT,0x07);
sepp_nepp	7:41cbc431e1f4	878
sepp_nepp	7:41cbc431e1f4	879	status \|= VL53L0X_write_byte(0xff,0x01);
sepp_nepp	7:41cbc431e1f4	880	status \|= VL53L0X_write_byte(VL53L0X_REG_ALGO_PHASECAL_LIM,
nikapov	0:a1a69d32f310	881	0x20);
sepp_nepp	7:41cbc431e1f4	882	status \|= VL53L0X_write_byte(0xff,0x00);
nikapov	0:a1a69d32f310	883	}
nikapov	0:a1a69d32f310	884	}
nikapov	0:a1a69d32f310	885
nikapov	0:a1a69d32f310	886
sepp_nepp	7:41cbc431e1f4	887	/* Re-calculate and apply timeouts,in macro periods */
nikapov	0:a1a69d32f310	888
nikapov	0:a1a69d32f310	889	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	890	vcsel_period_reg = lv53l0x_encode_vcsel_period((uint8_t)
nikapov	0:a1a69d32f310	891	vcsel_pulse_period_pclk);
nikapov	0:a1a69d32f310	892
nikapov	0:a1a69d32f310	893	/* When the VCSEL period for the pre or final range is changed,
nikapov	0:a1a69d32f310	894	* the corresponding timeout must be read from the device using
sepp_nepp	7:41cbc431e1f4	895	* the current VCSEL period,then the new VCSEL period can be
nikapov	0:a1a69d32f310	896	* applied. The timeout then must be written back to the device
nikapov	0:a1a69d32f310	897	* using the new VCSEL period.
nikapov	0:a1a69d32f310	898	*
sepp_nepp	7:41cbc431e1f4	899	* For the MSRC timeout,the same applies - this timeout being
nikapov	0:a1a69d32f310	900	* dependant on the pre-range vcsel period.
nikapov	0:a1a69d32f310	901	*/
nikapov	0:a1a69d32f310	902	switch (vcsel_period_type) {
nikapov	0:a1a69d32f310	903	case VL53L0X_VCSEL_PERIOD_PRE_RANGE:
sepp_nepp	7:41cbc431e1f4	904	status = get_sequence_step_timeout(VL53L0X_SEQUENCESTEP_PRE_RANGE,
nikapov	0:a1a69d32f310	905	&pre_range_timeout_micro_seconds);
nikapov	0:a1a69d32f310	906
nikapov	0:a1a69d32f310	907	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	908	status = get_sequence_step_timeout(VL53L0X_SEQUENCESTEP_MSRC,
nikapov	0:a1a69d32f310	909	&msrc_timeout_micro_seconds);
nikapov	0:a1a69d32f310	910
nikapov	0:a1a69d32f310	911	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	912	status = VL53L0X_write_byte(VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD,
nikapov	0:a1a69d32f310	913	vcsel_period_reg);
nikapov	0:a1a69d32f310	914
nikapov	0:a1a69d32f310	915
nikapov	0:a1a69d32f310	916	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	917	status = set_sequence_step_timeout(VL53L0X_SEQUENCESTEP_PRE_RANGE,
nikapov	0:a1a69d32f310	918	pre_range_timeout_micro_seconds);
nikapov	0:a1a69d32f310	919
nikapov	0:a1a69d32f310	920
nikapov	0:a1a69d32f310	921	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	922	status = set_sequence_step_timeout(VL53L0X_SEQUENCESTEP_MSRC,
nikapov	0:a1a69d32f310	923	msrc_timeout_micro_seconds);
nikapov	0:a1a69d32f310	924
sepp_nepp	7:41cbc431e1f4	925	_device->DeviceSpecificParameters.PreRangeVcselPulsePeriod = vcsel_pulse_period_pclk;
nikapov	0:a1a69d32f310	926	break;
nikapov	0:a1a69d32f310	927	case VL53L0X_VCSEL_PERIOD_FINAL_RANGE:
sepp_nepp	7:41cbc431e1f4	928	status = get_sequence_step_timeout(VL53L0X_SEQUENCESTEP_FINAL_RANGE,
nikapov	0:a1a69d32f310	929	&final_range_timeout_micro_seconds);
nikapov	0:a1a69d32f310	930
nikapov	0:a1a69d32f310	931	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	932	status = VL53L0X_write_byte(VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD,
nikapov	0:a1a69d32f310	933	vcsel_period_reg);
nikapov	0:a1a69d32f310	934
nikapov	0:a1a69d32f310	935
nikapov	0:a1a69d32f310	936	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	937	status = set_sequence_step_timeout(VL53L0X_SEQUENCESTEP_FINAL_RANGE,
nikapov	0:a1a69d32f310	938	final_range_timeout_micro_seconds);
nikapov	0:a1a69d32f310	939
sepp_nepp	7:41cbc431e1f4	940	_device->DeviceSpecificParameters.FinalRangeVcselPulsePeriod = vcsel_pulse_period_pclk;
nikapov	0:a1a69d32f310	941	break;
nikapov	0:a1a69d32f310	942	default:
nikapov	0:a1a69d32f310	943	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	944	}
nikapov	0:a1a69d32f310	945	}
nikapov	0:a1a69d32f310	946
sepp_nepp	7:41cbc431e1f4	947	/* Finally,the timing budget must be re-applied */
nikapov	0:a1a69d32f310	948	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	949	measurement_timing_budget_micro_seconds = _device->CurrentParameters.MeasurementTimingBudgetMicroSeconds;
sepp_nepp	7:41cbc431e1f4	950
sepp_nepp	7:41cbc431e1f4	951	status = VL53L0X_set_measurement_timing_budget_micro_seconds(measurement_timing_budget_micro_seconds);
nikapov	0:a1a69d32f310	952	}
nikapov	0:a1a69d32f310	953
nikapov	0:a1a69d32f310	954	/* Perform the phase calibration. This is needed after changing on
nikapov	0:a1a69d32f310	955	* vcsel period.
sepp_nepp	7:41cbc431e1f4	956	* get_data_enable = 0,restore_config = 1 */
nikapov	0:a1a69d32f310	957	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	958	status = VL53L0X_perform_phase_calibration(&phase_cal_int,0,1);
nikapov	0:a1a69d32f310	959
nikapov	0:a1a69d32f310	960	return status;
nikapov	0:a1a69d32f310	961	}
nikapov	0:a1a69d32f310	962
sepp_nepp	7:41cbc431e1f4	963	VL53L0X_Error VL53L0X::VL53L0X_set_vcsel_pulse_period(VL53L0X_VcselPeriod vcsel_period_type,uint8_t vcsel_pulse_period)
nikapov	0:a1a69d32f310	964	{
nikapov	0:a1a69d32f310	965	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	966
nikapov	0:a1a69d32f310	967
sepp_nepp	7:41cbc431e1f4	968	status = wrapped_VL53L0X_set_vcsel_pulse_period(vcsel_period_type,
nikapov	0:a1a69d32f310	969	vcsel_pulse_period);
nikapov	0:a1a69d32f310	970
sepp_nepp	5:b95f6951f7d5	971
nikapov	0:a1a69d32f310	972	return status;
nikapov	0:a1a69d32f310	973	}
nikapov	0:a1a69d32f310	974
sepp_nepp	7:41cbc431e1f4	975	VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_vcsel_pulse_period(VL53L0X_VcselPeriod vcsel_period_type,uint8_t *p_vcsel_pulse_period_pclk)
nikapov	0:a1a69d32f310	976	{
nikapov	0:a1a69d32f310	977	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	978	uint8_t vcsel_period_reg;
nikapov	0:a1a69d32f310	979
nikapov	0:a1a69d32f310	980	switch (vcsel_period_type) {
nikapov	0:a1a69d32f310	981	case VL53L0X_VCSEL_PERIOD_PRE_RANGE:
sepp_nepp	7:41cbc431e1f4	982	status = VL53L0X_read_byte(VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD,
nikapov	0:a1a69d32f310	983	&vcsel_period_reg);
nikapov	0:a1a69d32f310	984	break;
nikapov	0:a1a69d32f310	985	case VL53L0X_VCSEL_PERIOD_FINAL_RANGE:
sepp_nepp	7:41cbc431e1f4	986	status = VL53L0X_read_byte(VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD,
nikapov	0:a1a69d32f310	987	&vcsel_period_reg);
nikapov	0:a1a69d32f310	988	break;
nikapov	0:a1a69d32f310	989	default:
nikapov	0:a1a69d32f310	990	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	991	}
nikapov	0:a1a69d32f310	992
nikapov	0:a1a69d32f310	993	if (status == VL53L0X_ERROR_NONE)
nikapov	0:a1a69d32f310	994	*p_vcsel_pulse_period_pclk =
nikapov	0:a1a69d32f310	995	VL53L0X_decode_vcsel_period(vcsel_period_reg);
nikapov	0:a1a69d32f310	996
nikapov	0:a1a69d32f310	997	return status;
nikapov	0:a1a69d32f310	998	}
nikapov	0:a1a69d32f310	999
sepp_nepp	7:41cbc431e1f4	1000	VL53L0X_Error VL53L0X::VL53L0X_get_vcsel_pulse_period(VL53L0X_VcselPeriod vcsel_period_type,uint8_t *p_vcsel_pulse_period_pclk)
nikapov	0:a1a69d32f310	1001	{
nikapov	0:a1a69d32f310	1002	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	1003
nikapov	0:a1a69d32f310	1004
sepp_nepp	7:41cbc431e1f4	1005	status = wrapped_VL53L0X_get_vcsel_pulse_period(vcsel_period_type,
nikapov	0:a1a69d32f310	1006	p_vcsel_pulse_period_pclk);
nikapov	0:a1a69d32f310	1007
sepp_nepp	5:b95f6951f7d5	1008
nikapov	0:a1a69d32f310	1009	return status;
nikapov	0:a1a69d32f310	1010	}
nikapov	0:a1a69d32f310	1011
nikapov	0:a1a69d32f310	1012	uint32_t VL53L0X::VL53L0X_decode_timeout(uint16_t encoded_timeout)
nikapov	0:a1a69d32f310	1013	{
nikapov	0:a1a69d32f310	1014	/*!
nikapov	0:a1a69d32f310	1015	* Decode 16-bit timeout register value - format (LSByte * 2^MSByte) + 1
nikapov	0:a1a69d32f310	1016	*/
nikapov	0:a1a69d32f310	1017
nikapov	0:a1a69d32f310	1018	uint32_t timeout_macro_clks = 0;
nikapov	0:a1a69d32f310	1019
nikapov	0:a1a69d32f310	1020	timeout_macro_clks = ((uint32_t)(encoded_timeout & 0x00FF)
nikapov	0:a1a69d32f310	1021	<< (uint32_t)((encoded_timeout & 0xFF00) >> 8)) + 1;
nikapov	0:a1a69d32f310	1022
nikapov	0:a1a69d32f310	1023	return timeout_macro_clks;
nikapov	0:a1a69d32f310	1024	}
nikapov	0:a1a69d32f310	1025
sepp_nepp	7:41cbc431e1f4	1026	uint32_t VL53L0X::VL53L0X_calc_macro_period_ps(uint8_t vcsel_period_pclks)
nikapov	0:a1a69d32f310	1027	{
nikapov	0:a1a69d32f310	1028	uint64_t pll_period_ps;
nikapov	0:a1a69d32f310	1029	uint32_t macro_period_vclks;
nikapov	0:a1a69d32f310	1030	uint32_t macro_period_ps;
nikapov	0:a1a69d32f310	1031
sepp_nepp	5:b95f6951f7d5	1032
nikapov	0:a1a69d32f310	1033
nikapov	0:a1a69d32f310	1034	/* The above calculation will produce rounding errors,
nikapov	0:a1a69d32f310	1035	therefore set fixed value
nikapov	0:a1a69d32f310	1036	*/
nikapov	0:a1a69d32f310	1037	pll_period_ps = 1655;
nikapov	0:a1a69d32f310	1038
nikapov	0:a1a69d32f310	1039	macro_period_vclks = 2304;
nikapov	0:a1a69d32f310	1040	macro_period_ps = (uint32_t)(macro_period_vclks
nikapov	0:a1a69d32f310	1041	* vcsel_period_pclks * pll_period_ps);
nikapov	0:a1a69d32f310	1042	return macro_period_ps;
nikapov	0:a1a69d32f310	1043	}
nikapov	0:a1a69d32f310	1044
nikapov	0:a1a69d32f310	1045	/* To convert register value into us */
sepp_nepp	7:41cbc431e1f4	1046	uint32_t VL53L0X::VL53L0X_calc_timeout_us(uint16_t timeout_period_mclks,
nikapov	0:a1a69d32f310	1047	uint8_t vcsel_period_pclks)
nikapov	0:a1a69d32f310	1048	{
nikapov	0:a1a69d32f310	1049	uint32_t macro_period_ps;
nikapov	0:a1a69d32f310	1050	uint32_t macro_period_ns;
nikapov	0:a1a69d32f310	1051	uint32_t actual_timeout_period_us = 0;
nikapov	0:a1a69d32f310	1052
sepp_nepp	7:41cbc431e1f4	1053	macro_period_ps = VL53L0X_calc_macro_period_ps(vcsel_period_pclks);
nikapov	0:a1a69d32f310	1054	macro_period_ns = (macro_period_ps + 500) / 1000;
nikapov	0:a1a69d32f310	1055
nikapov	0:a1a69d32f310	1056	actual_timeout_period_us =
nikapov	0:a1a69d32f310	1057	((timeout_period_mclks * macro_period_ns) + 500) / 1000;
nikapov	0:a1a69d32f310	1058
nikapov	0:a1a69d32f310	1059	return actual_timeout_period_us;
nikapov	0:a1a69d32f310	1060	}
nikapov	0:a1a69d32f310	1061
sepp_nepp	7:41cbc431e1f4	1062	VL53L0X_Error VL53L0X::get_sequence_step_timeout(VL53L0X_SequenceStepId sequence_step_id,
nikapov	0:a1a69d32f310	1063	uint32_t *p_time_out_micro_secs)
nikapov	0:a1a69d32f310	1064	{
nikapov	0:a1a69d32f310	1065	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1066	uint8_t current_vcsel_pulse_period_p_clk;
nikapov	0:a1a69d32f310	1067	uint8_t encoded_time_out_byte = 0;
nikapov	0:a1a69d32f310	1068	uint32_t timeout_micro_seconds = 0;
nikapov	0:a1a69d32f310	1069	uint16_t pre_range_encoded_time_out = 0;
nikapov	0:a1a69d32f310	1070	uint16_t msrc_time_out_m_clks;
nikapov	0:a1a69d32f310	1071	uint16_t pre_range_time_out_m_clks;
nikapov	0:a1a69d32f310	1072	uint16_t final_range_time_out_m_clks = 0;
nikapov	0:a1a69d32f310	1073	uint16_t final_range_encoded_time_out;
nikapov	0:a1a69d32f310	1074	VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
nikapov	0:a1a69d32f310	1075
nikapov	0:a1a69d32f310	1076	if ((sequence_step_id == VL53L0X_SEQUENCESTEP_TCC) \|\|
nikapov	0:a1a69d32f310	1077	(sequence_step_id == VL53L0X_SEQUENCESTEP_DSS) \|\|
nikapov	0:a1a69d32f310	1078	(sequence_step_id == VL53L0X_SEQUENCESTEP_MSRC)) {
nikapov	0:a1a69d32f310	1079
sepp_nepp	7:41cbc431e1f4	1080	status = VL53L0X_get_vcsel_pulse_period(VL53L0X_VCSEL_PERIOD_PRE_RANGE,
nikapov	0:a1a69d32f310	1081	&current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	1082	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1083	status = VL53L0X_read_byte(VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP,
nikapov	0:a1a69d32f310	1084	&encoded_time_out_byte);
nikapov	0:a1a69d32f310	1085	}
nikapov	0:a1a69d32f310	1086	msrc_time_out_m_clks = VL53L0X_decode_timeout(encoded_time_out_byte);
nikapov	0:a1a69d32f310	1087
sepp_nepp	7:41cbc431e1f4	1088	timeout_micro_seconds = VL53L0X_calc_timeout_us(msrc_time_out_m_clks,
nikapov	0:a1a69d32f310	1089	current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	1090	} else if (sequence_step_id == VL53L0X_SEQUENCESTEP_PRE_RANGE) {
nikapov	0:a1a69d32f310	1091	/* Retrieve PRE-RANGE VCSEL Period */
sepp_nepp	7:41cbc431e1f4	1092	status = VL53L0X_get_vcsel_pulse_period(VL53L0X_VCSEL_PERIOD_PRE_RANGE,
nikapov	0:a1a69d32f310	1093	&current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	1094
nikapov	0:a1a69d32f310	1095	/* Retrieve PRE-RANGE Timeout in Macro periods (MCLKS) */
nikapov	0:a1a69d32f310	1096	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1097
nikapov	0:a1a69d32f310	1098	/* Retrieve PRE-RANGE VCSEL Period */
sepp_nepp	7:41cbc431e1f4	1099	status = VL53L0X_get_vcsel_pulse_period(VL53L0X_VCSEL_PERIOD_PRE_RANGE,
nikapov	0:a1a69d32f310	1100	&current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	1101
nikapov	0:a1a69d32f310	1102	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1103	status = VL53L0X_read_word(VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
nikapov	0:a1a69d32f310	1104	&pre_range_encoded_time_out);
nikapov	0:a1a69d32f310	1105	}
nikapov	0:a1a69d32f310	1106
sepp_nepp	7:41cbc431e1f4	1107	pre_range_time_out_m_clks = VL53L0X_decode_timeout(pre_range_encoded_time_out);
sepp_nepp	7:41cbc431e1f4	1108
sepp_nepp	7:41cbc431e1f4	1109	timeout_micro_seconds = VL53L0X_calc_timeout_us(pre_range_time_out_m_clks,
nikapov	0:a1a69d32f310	1110	current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	1111	}
nikapov	0:a1a69d32f310	1112	} else if (sequence_step_id == VL53L0X_SEQUENCESTEP_FINAL_RANGE) {
nikapov	0:a1a69d32f310	1113
sepp_nepp	7:41cbc431e1f4	1114	VL53L0X_get_sequence_step_enables(&scheduler_sequence_steps);
nikapov	0:a1a69d32f310	1115	pre_range_time_out_m_clks = 0;
nikapov	0:a1a69d32f310	1116
nikapov	0:a1a69d32f310	1117	if (scheduler_sequence_steps.PreRangeOn) {
nikapov	0:a1a69d32f310	1118	/* Retrieve PRE-RANGE VCSEL Period */
sepp_nepp	7:41cbc431e1f4	1119	status = VL53L0X_get_vcsel_pulse_period(VL53L0X_VCSEL_PERIOD_PRE_RANGE,
nikapov	0:a1a69d32f310	1120	&current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	1121
nikapov	0:a1a69d32f310	1122	/* Retrieve PRE-RANGE Timeout in Macro periods
nikapov	0:a1a69d32f310	1123	* (MCLKS) */
nikapov	0:a1a69d32f310	1124	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1125	status = VL53L0X_read_word(VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
nikapov	0:a1a69d32f310	1126	&pre_range_encoded_time_out);
sepp_nepp	7:41cbc431e1f4	1127	pre_range_time_out_m_clks = VL53L0X_decode_timeout(pre_range_encoded_time_out);
nikapov	0:a1a69d32f310	1128	}
nikapov	0:a1a69d32f310	1129	}
nikapov	0:a1a69d32f310	1130
nikapov	0:a1a69d32f310	1131	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1132	/* Retrieve FINAL-RANGE VCSEL Period */
sepp_nepp	7:41cbc431e1f4	1133	status = VL53L0X_get_vcsel_pulse_period(VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
nikapov	0:a1a69d32f310	1134	&current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	1135	}
nikapov	0:a1a69d32f310	1136
nikapov	0:a1a69d32f310	1137	/* Retrieve FINAL-RANGE Timeout in Macro periods (MCLKS) */
nikapov	0:a1a69d32f310	1138	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1139	status = VL53L0X_read_word(VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI,
nikapov	0:a1a69d32f310	1140	&final_range_encoded_time_out);
sepp_nepp	7:41cbc431e1f4	1141	final_range_time_out_m_clks = VL53L0X_decode_timeout(final_range_encoded_time_out);
nikapov	0:a1a69d32f310	1142	}
nikapov	0:a1a69d32f310	1143
nikapov	0:a1a69d32f310	1144	final_range_time_out_m_clks -= pre_range_time_out_m_clks;
sepp_nepp	7:41cbc431e1f4	1145	timeout_micro_seconds = VL53L0X_calc_timeout_us(final_range_time_out_m_clks,
nikapov	0:a1a69d32f310	1146	current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	1147	}
nikapov	0:a1a69d32f310	1148
nikapov	0:a1a69d32f310	1149	*p_time_out_micro_secs = timeout_micro_seconds;
nikapov	0:a1a69d32f310	1150
nikapov	0:a1a69d32f310	1151	return status;
nikapov	0:a1a69d32f310	1152	}
nikapov	0:a1a69d32f310	1153
sepp_nepp	7:41cbc431e1f4	1154	VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_measurement_timing_budget_micro_seconds(uint32_t *p_measurement_timing_budget_micro_seconds)
nikapov	0:a1a69d32f310	1155	{
nikapov	0:a1a69d32f310	1156	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1157	VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
nikapov	0:a1a69d32f310	1158	uint32_t final_range_timeout_micro_seconds;
nikapov	0:a1a69d32f310	1159	uint32_t msrc_dcc_tcc_timeout_micro_seconds = 2000;
nikapov	0:a1a69d32f310	1160	uint32_t start_overhead_micro_seconds = 1910;
nikapov	0:a1a69d32f310	1161	uint32_t end_overhead_micro_seconds = 960;
nikapov	0:a1a69d32f310	1162	uint32_t msrc_overhead_micro_seconds = 660;
nikapov	0:a1a69d32f310	1163	uint32_t tcc_overhead_micro_seconds = 590;
nikapov	0:a1a69d32f310	1164	uint32_t dss_overhead_micro_seconds = 690;
nikapov	0:a1a69d32f310	1165	uint32_t pre_range_overhead_micro_seconds = 660;
nikapov	0:a1a69d32f310	1166	uint32_t final_range_overhead_micro_seconds = 550;
nikapov	0:a1a69d32f310	1167	uint32_t pre_range_timeout_micro_seconds = 0;
nikapov	0:a1a69d32f310	1168
sepp_nepp	5:b95f6951f7d5	1169
nikapov	0:a1a69d32f310	1170
nikapov	0:a1a69d32f310	1171	/* Start and end overhead times always present */
nikapov	0:a1a69d32f310	1172	*p_measurement_timing_budget_micro_seconds
nikapov	0:a1a69d32f310	1173	= start_overhead_micro_seconds + end_overhead_micro_seconds;
nikapov	0:a1a69d32f310	1174
sepp_nepp	7:41cbc431e1f4	1175	status = VL53L0X_get_sequence_step_enables(&scheduler_sequence_steps);
nikapov	0:a1a69d32f310	1176
nikapov	0:a1a69d32f310	1177	if (status != VL53L0X_ERROR_NONE) {
sepp_nepp	5:b95f6951f7d5	1178
nikapov	0:a1a69d32f310	1179	return status;
nikapov	0:a1a69d32f310	1180	}
nikapov	0:a1a69d32f310	1181
nikapov	0:a1a69d32f310	1182
nikapov	0:a1a69d32f310	1183	if (scheduler_sequence_steps.TccOn \|\|
nikapov	0:a1a69d32f310	1184	scheduler_sequence_steps.MsrcOn \|\|
nikapov	0:a1a69d32f310	1185	scheduler_sequence_steps.DssOn) {
nikapov	0:a1a69d32f310	1186
sepp_nepp	7:41cbc431e1f4	1187	status = get_sequence_step_timeout(VL53L0X_SEQUENCESTEP_MSRC,
nikapov	0:a1a69d32f310	1188	&msrc_dcc_tcc_timeout_micro_seconds);
nikapov	0:a1a69d32f310	1189
nikapov	0:a1a69d32f310	1190	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1191	if (scheduler_sequence_steps.TccOn) {
nikapov	0:a1a69d32f310	1192	*p_measurement_timing_budget_micro_seconds +=
nikapov	0:a1a69d32f310	1193	msrc_dcc_tcc_timeout_micro_seconds +
nikapov	0:a1a69d32f310	1194	tcc_overhead_micro_seconds;
nikapov	0:a1a69d32f310	1195	}
nikapov	0:a1a69d32f310	1196
nikapov	0:a1a69d32f310	1197	if (scheduler_sequence_steps.DssOn) {
nikapov	0:a1a69d32f310	1198	*p_measurement_timing_budget_micro_seconds +=
nikapov	0:a1a69d32f310	1199	2 * (msrc_dcc_tcc_timeout_micro_seconds +
nikapov	0:a1a69d32f310	1200	dss_overhead_micro_seconds);
nikapov	0:a1a69d32f310	1201	} else if (scheduler_sequence_steps.MsrcOn) {
nikapov	0:a1a69d32f310	1202	*p_measurement_timing_budget_micro_seconds +=
nikapov	0:a1a69d32f310	1203	msrc_dcc_tcc_timeout_micro_seconds +
nikapov	0:a1a69d32f310	1204	msrc_overhead_micro_seconds;
nikapov	0:a1a69d32f310	1205	}
nikapov	0:a1a69d32f310	1206	}
nikapov	0:a1a69d32f310	1207	}
nikapov	0:a1a69d32f310	1208
nikapov	0:a1a69d32f310	1209	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1210	if (scheduler_sequence_steps.PreRangeOn) {
sepp_nepp	7:41cbc431e1f4	1211	status = get_sequence_step_timeout(VL53L0X_SEQUENCESTEP_PRE_RANGE,
nikapov	0:a1a69d32f310	1212	&pre_range_timeout_micro_seconds);
nikapov	0:a1a69d32f310	1213	*p_measurement_timing_budget_micro_seconds +=
nikapov	0:a1a69d32f310	1214	pre_range_timeout_micro_seconds +
nikapov	0:a1a69d32f310	1215	pre_range_overhead_micro_seconds;
nikapov	0:a1a69d32f310	1216	}
nikapov	0:a1a69d32f310	1217	}
nikapov	0:a1a69d32f310	1218
nikapov	0:a1a69d32f310	1219	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1220	if (scheduler_sequence_steps.FinalRangeOn) {
sepp_nepp	7:41cbc431e1f4	1221	status = get_sequence_step_timeout(VL53L0X_SEQUENCESTEP_FINAL_RANGE,
nikapov	0:a1a69d32f310	1222	&final_range_timeout_micro_seconds);
nikapov	0:a1a69d32f310	1223	*p_measurement_timing_budget_micro_seconds +=
nikapov	0:a1a69d32f310	1224	(final_range_timeout_micro_seconds +
nikapov	0:a1a69d32f310	1225	final_range_overhead_micro_seconds);
nikapov	0:a1a69d32f310	1226	}
nikapov	0:a1a69d32f310	1227	}
nikapov	0:a1a69d32f310	1228
nikapov	0:a1a69d32f310	1229	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1230	_device->CurrentParameters.MeasurementTimingBudgetMicroSeconds =
sepp_nepp	7:41cbc431e1f4	1231	*p_measurement_timing_budget_micro_seconds;
nikapov	0:a1a69d32f310	1232	}
nikapov	0:a1a69d32f310	1233
sepp_nepp	5:b95f6951f7d5	1234
nikapov	0:a1a69d32f310	1235	return status;
nikapov	0:a1a69d32f310	1236	}
nikapov	0:a1a69d32f310	1237
sepp_nepp	7:41cbc431e1f4	1238	VL53L0X_Error VL53L0X::VL53L0X_get_measurement_timing_budget_micro_seconds(uint32_t *p_measurement_timing_budget_micro_seconds)
nikapov	0:a1a69d32f310	1239	{
nikapov	0:a1a69d32f310	1240	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	1241
nikapov	0:a1a69d32f310	1242
sepp_nepp	7:41cbc431e1f4	1243	status = wrapped_VL53L0X_get_measurement_timing_budget_micro_seconds(p_measurement_timing_budget_micro_seconds);
nikapov	0:a1a69d32f310	1244
sepp_nepp	5:b95f6951f7d5	1245
nikapov	0:a1a69d32f310	1246	return status;
nikapov	0:a1a69d32f310	1247	}
nikapov	0:a1a69d32f310	1248
sepp_nepp	7:41cbc431e1f4	1249	VL53L0X_Error VL53L0X::VL53L0X_get_device_parameters(VL53L0X_DeviceParameters_t *p_device_parameters)
nikapov	0:a1a69d32f310	1250	{
nikapov	0:a1a69d32f310	1251	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1252	int i;
nikapov	0:a1a69d32f310	1253
sepp_nepp	5:b95f6951f7d5	1254
nikapov	0:a1a69d32f310	1255
sepp_nepp	7:41cbc431e1f4	1256	status = VL53L0X_get_device_mode(&(p_device_parameters->DeviceMode));
nikapov	0:a1a69d32f310	1257
nikapov	0:a1a69d32f310	1258	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	1259	status = VL53L0X_get_inter_measurement_period_milli_seconds(&(p_device_parameters->InterMeasurementPeriodMilliSeconds));
nikapov	0:a1a69d32f310	1260
nikapov	0:a1a69d32f310	1261
Davidroid	3:e9269ff624ed	1262	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1263	p_device_parameters->XTalkCompensationEnable = 0;
Davidroid	3:e9269ff624ed	1264	}
nikapov	0:a1a69d32f310	1265
nikapov	0:a1a69d32f310	1266	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	1267	status = VL53L0X_get_x_talk_compensation_rate_mega_cps(&(p_device_parameters->XTalkCompensationRateMegaCps));
nikapov	0:a1a69d32f310	1268
nikapov	0:a1a69d32f310	1269
nikapov	0:a1a69d32f310	1270	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	1271	status = VL53L0X_get_offset_calibration_data_micro_meter(&(p_device_parameters->RangeOffsetMicroMeters));
nikapov	0:a1a69d32f310	1272
nikapov	0:a1a69d32f310	1273
nikapov	0:a1a69d32f310	1274	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1275	for (i = 0; i < VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS; i++) {
sepp_nepp	7:41cbc431e1f4	1276	/* get first the values,then the enables.
nikapov	0:a1a69d32f310	1277	* VL53L0X_GetLimitCheckValue will modify the enable
nikapov	0:a1a69d32f310	1278	* flags
nikapov	0:a1a69d32f310	1279	*/
nikapov	0:a1a69d32f310	1280	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1281	status \|= VL53L0X_get_limit_check_value(i,
nikapov	0:a1a69d32f310	1282	&(p_device_parameters->LimitChecksValue[i]));
nikapov	0:a1a69d32f310	1283	} else {
nikapov	0:a1a69d32f310	1284	break;
nikapov	0:a1a69d32f310	1285	}
nikapov	0:a1a69d32f310	1286	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1287	status \|= VL53L0X_get_limit_check_enable(i,
nikapov	0:a1a69d32f310	1288	&(p_device_parameters->LimitChecksEnable[i]));
nikapov	0:a1a69d32f310	1289	} else {
nikapov	0:a1a69d32f310	1290	break;
nikapov	0:a1a69d32f310	1291	}
nikapov	0:a1a69d32f310	1292	}
nikapov	0:a1a69d32f310	1293	}
nikapov	0:a1a69d32f310	1294
nikapov	0:a1a69d32f310	1295	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1296	status = VL53L0X_get_wrap_around_check_enable(&(p_device_parameters->WrapAroundCheckEnable));
nikapov	0:a1a69d32f310	1297	}
nikapov	0:a1a69d32f310	1298
nikapov	0:a1a69d32f310	1299	/* Need to be done at the end as it uses VCSELPulsePeriod */
nikapov	0:a1a69d32f310	1300	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1301	status = VL53L0X_get_measurement_timing_budget_micro_seconds(&(p_device_parameters->MeasurementTimingBudgetMicroSeconds));
nikapov	0:a1a69d32f310	1302	}
nikapov	0:a1a69d32f310	1303
sepp_nepp	5:b95f6951f7d5	1304
nikapov	0:a1a69d32f310	1305	return status;
nikapov	0:a1a69d32f310	1306	}
nikapov	0:a1a69d32f310	1307
sepp_nepp	7:41cbc431e1f4	1308	VL53L0X_Error VL53L0X::VL53L0X_set_limit_check_value(uint16_t limit_check_id,
nikapov	0:a1a69d32f310	1309	FixPoint1616_t limit_check_value)
nikapov	0:a1a69d32f310	1310	{
nikapov	0:a1a69d32f310	1311	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1312	uint8_t temp8;
nikapov	0:a1a69d32f310	1313
sepp_nepp	5:b95f6951f7d5	1314
nikapov	0:a1a69d32f310	1315
sepp_nepp	7:41cbc431e1f4	1316	temp8 = _device->CurrentParameters.LimitChecksEnable[limit_check_id];
nikapov	0:a1a69d32f310	1317
nikapov	0:a1a69d32f310	1318	if (temp8 == 0) { /* disabled write only internal value */
sepp_nepp	7:41cbc431e1f4	1319	_device->CurrentParameters.LimitChecksValue[limit_check_id] = limit_check_value;
nikapov	0:a1a69d32f310	1320	} else {
nikapov	0:a1a69d32f310	1321
nikapov	0:a1a69d32f310	1322	switch (limit_check_id) {
nikapov	0:a1a69d32f310	1323
nikapov	0:a1a69d32f310	1324	case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
nikapov	0:a1a69d32f310	1325	/* internal computation: */
sepp_nepp	7:41cbc431e1f4	1326	_device->CurrentParameters.LimitChecksValue[VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE] = limit_check_value;
nikapov	0:a1a69d32f310	1327	break;
nikapov	0:a1a69d32f310	1328
nikapov	0:a1a69d32f310	1329	case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
nikapov	0:a1a69d32f310	1330
sepp_nepp	7:41cbc431e1f4	1331	status = VL53L0X_write_word(VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
sepp_nepp	7:41cbc431e1f4	1332	VL53L0X_FIXPOINT1616TOFIXPOINT97(limit_check_value));
nikapov	0:a1a69d32f310	1333
nikapov	0:a1a69d32f310	1334	break;
nikapov	0:a1a69d32f310	1335
nikapov	0:a1a69d32f310	1336	case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
nikapov	0:a1a69d32f310	1337
nikapov	0:a1a69d32f310	1338	/* internal computation: */
sepp_nepp	7:41cbc431e1f4	1339	_device->CurrentParameters.LimitChecksValue[VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP] = limit_check_value;
nikapov	0:a1a69d32f310	1340
nikapov	0:a1a69d32f310	1341	break;
nikapov	0:a1a69d32f310	1342
nikapov	0:a1a69d32f310	1343	case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
nikapov	0:a1a69d32f310	1344
nikapov	0:a1a69d32f310	1345	/* internal computation: */
sepp_nepp	7:41cbc431e1f4	1346	_device->CurrentParameters.LimitChecksValue[VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD] = limit_check_value;
nikapov	0:a1a69d32f310	1347
nikapov	0:a1a69d32f310	1348	break;
nikapov	0:a1a69d32f310	1349
nikapov	0:a1a69d32f310	1350	case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
nikapov	0:a1a69d32f310	1351	case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
nikapov	0:a1a69d32f310	1352
sepp_nepp	7:41cbc431e1f4	1353	status = VL53L0X_write_word(VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT,
sepp_nepp	7:41cbc431e1f4	1354	VL53L0X_FIXPOINT1616TOFIXPOINT97(limit_check_value));
nikapov	0:a1a69d32f310	1355
nikapov	0:a1a69d32f310	1356	break;
nikapov	0:a1a69d32f310	1357
nikapov	0:a1a69d32f310	1358	default:
nikapov	0:a1a69d32f310	1359	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	1360
nikapov	0:a1a69d32f310	1361	}
nikapov	0:a1a69d32f310	1362
nikapov	0:a1a69d32f310	1363	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1364	_device->CurrentParameters.LimitChecksValue[limit_check_id] = limit_check_value;
nikapov	0:a1a69d32f310	1365	}
nikapov	0:a1a69d32f310	1366	}
nikapov	0:a1a69d32f310	1367
sepp_nepp	5:b95f6951f7d5	1368
nikapov	0:a1a69d32f310	1369	return status;
nikapov	0:a1a69d32f310	1370	}
nikapov	0:a1a69d32f310	1371
sepp_nepp	7:41cbc431e1f4	1372	VL53L0X_Error VL53L0X::VL53L0X_data_init()
nikapov	0:a1a69d32f310	1373	{
nikapov	0:a1a69d32f310	1374	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1375	VL53L0X_DeviceParameters_t CurrentParameters;
nikapov	0:a1a69d32f310	1376	int i;
nikapov	0:a1a69d32f310	1377	uint8_t StopVariable;
nikapov	0:a1a69d32f310	1378
sepp_nepp	5:b95f6951f7d5	1379
nikapov	0:a1a69d32f310	1380
nikapov	0:a1a69d32f310	1381	/* by default the I2C is running at 1V8 if you want to change it you
nikapov	0:a1a69d32f310	1382	* need to include this define at compilation level. */
nikapov	0:a1a69d32f310	1383	#ifdef USE_I2C_2V8
sepp_nepp	7:41cbc431e1f4	1384	Status = VL53L0X_UpdateByte(VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV,
nikapov	0:a1a69d32f310	1385	0xFE,
nikapov	0:a1a69d32f310	1386	0x01);
nikapov	0:a1a69d32f310	1387	#endif
nikapov	0:a1a69d32f310	1388
nikapov	0:a1a69d32f310	1389	/* Set I2C standard mode */
Davidroid	3:e9269ff624ed	1390	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1391	status = VL53L0X_write_byte(0x88,0x00);
sepp_nepp	7:41cbc431e1f4	1392	}
sepp_nepp	7:41cbc431e1f4	1393
sepp_nepp	7:41cbc431e1f4	1394	_device->DeviceSpecificParameters.ReadDataFromDeviceDone = 0;
sepp_nepp	7:41cbc431e1f4	1395	_device->DeviceSpecificParameters.ReadDataFromDeviceDone = 0;
nikapov	0:a1a69d32f310	1396
nikapov	0:a1a69d32f310	1397	#ifdef USE_IQC_STATION
Davidroid	3:e9269ff624ed	1398	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1399	Status = VL53L0X_apply_offset_adjustment();
Davidroid	3:e9269ff624ed	1400	}
nikapov	0:a1a69d32f310	1401	#endif
nikapov	0:a1a69d32f310	1402
nikapov	0:a1a69d32f310	1403	/* Default value is 1000 for Linearity Corrective Gain */
sepp_nepp	7:41cbc431e1f4	1404	_device->LinearityCorrectiveGain = 1000;
nikapov	0:a1a69d32f310	1405
nikapov	0:a1a69d32f310	1406	/* Dmax default Parameter */
sepp_nepp	7:41cbc431e1f4	1407	_device->DmaxCalRangeMilliMeter = 400;
sepp_nepp	7:41cbc431e1f4	1408	_device->DmaxCalSignalRateRtnMegaCps = (FixPoint1616_t)((0x00016B85)); /* 1.42 No Cover Glass*/
nikapov	0:a1a69d32f310	1409
nikapov	0:a1a69d32f310	1410	/* Set Default static parameters
nikapov	0:a1a69d32f310	1411	set first temporary values 9.44MHz 65536 = 618660 */
sepp_nepp	7:41cbc431e1f4	1412	_device->DeviceSpecificParameters.OscFrequencyMHz = 618660;
nikapov	0:a1a69d32f310	1413
nikapov	0:a1a69d32f310	1414	/* Set Default XTalkCompensationRateMegaCps to 0 */
sepp_nepp	7:41cbc431e1f4	1415	_device->CurrentParameters.XTalkCompensationRateMegaCps = 0;
nikapov	0:a1a69d32f310	1416
nikapov	0:a1a69d32f310	1417	/* Get default parameters */
sepp_nepp	7:41cbc431e1f4	1418	status = VL53L0X_get_device_parameters(&CurrentParameters);
nikapov	0:a1a69d32f310	1419	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1420	/* initialize PAL values */
nikapov	0:a1a69d32f310	1421	CurrentParameters.DeviceMode = VL53L0X_DEVICEMODE_SINGLE_RANGING;
nikapov	0:a1a69d32f310	1422	CurrentParameters.HistogramMode = VL53L0X_HISTOGRAMMODE_DISABLED;
sepp_nepp	7:41cbc431e1f4	1423	_device->CurrentParameters = CurrentParameters;
nikapov	0:a1a69d32f310	1424	}
nikapov	0:a1a69d32f310	1425
nikapov	0:a1a69d32f310	1426	/* Sigma estimator variable */
sepp_nepp	7:41cbc431e1f4	1427	_device->SigmaEstRefArray = 100;
sepp_nepp	7:41cbc431e1f4	1428	_device->SigmaEstEffPulseWidth = 900;
sepp_nepp	7:41cbc431e1f4	1429	_device->SigmaEstEffAmbWidth = 500;
sepp_nepp	7:41cbc431e1f4	1430	_device->targetRefRate = 0x0A00; /* 20 MCPS in 9:7 format */
nikapov	0:a1a69d32f310	1431
nikapov	0:a1a69d32f310	1432	/* Use internal default settings */
sepp_nepp	7:41cbc431e1f4	1433	_device->UseInternalTuningSettings = 1;
sepp_nepp	7:41cbc431e1f4	1434
sepp_nepp	7:41cbc431e1f4	1435	status \|= VL53L0X_write_byte(0x80,0x01);
sepp_nepp	7:41cbc431e1f4	1436	status \|= VL53L0X_write_byte(0xFF,0x01);
sepp_nepp	7:41cbc431e1f4	1437	status \|= VL53L0X_write_byte(0x00,0x00);
sepp_nepp	7:41cbc431e1f4	1438	status \|= VL53L0X_read_byte(0x91,&StopVariable);
sepp_nepp	7:41cbc431e1f4	1439	_device->StopVariable = StopVariable;
sepp_nepp	7:41cbc431e1f4	1440	status \|= VL53L0X_write_byte(0x00,0x01);
sepp_nepp	7:41cbc431e1f4	1441	status \|= VL53L0X_write_byte(0xFF,0x00);
sepp_nepp	7:41cbc431e1f4	1442	status \|= VL53L0X_write_byte(0x80,0x00);
nikapov	0:a1a69d32f310	1443
nikapov	0:a1a69d32f310	1444	/* Enable all check */
nikapov	0:a1a69d32f310	1445	for (i = 0; i < VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS; i++) {
Davidroid	3:e9269ff624ed	1446	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1447	status \|= VL53L0X_set_limit_check_enable(i,1);
Davidroid	3:e9269ff624ed	1448	} else {
nikapov	0:a1a69d32f310	1449	break;
Davidroid	3:e9269ff624ed	1450	}
nikapov	0:a1a69d32f310	1451
nikapov	0:a1a69d32f310	1452	}
nikapov	0:a1a69d32f310	1453
nikapov	0:a1a69d32f310	1454	/* Disable the following checks */
nikapov	0:a1a69d32f310	1455	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	1456	status = VL53L0X_set_limit_check_enable(VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,0);
nikapov	0:a1a69d32f310	1457
nikapov	0:a1a69d32f310	1458	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	1459	status = VL53L0X_set_limit_check_enable(VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,0);
nikapov	0:a1a69d32f310	1460
nikapov	0:a1a69d32f310	1461	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	1462	status = VL53L0X_set_limit_check_enable(VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC,0);
nikapov	0:a1a69d32f310	1463
nikapov	0:a1a69d32f310	1464	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	1465	status = VL53L0X_set_limit_check_enable(VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE,0);
nikapov	0:a1a69d32f310	1466
nikapov	0:a1a69d32f310	1467	/* Limit default values */
nikapov	0:a1a69d32f310	1468	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1469	status = VL53L0X_set_limit_check_value(VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
nikapov	0:a1a69d32f310	1470	(FixPoint1616_t)(18 * 65536));
nikapov	0:a1a69d32f310	1471	}
nikapov	0:a1a69d32f310	1472	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1473	status = VL53L0X_set_limit_check_value(VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
nikapov	0:a1a69d32f310	1474	(FixPoint1616_t)(25 * 65536 / 100));
nikapov	0:a1a69d32f310	1475	/* 0.25 * 65536 */
nikapov	0:a1a69d32f310	1476	}
nikapov	0:a1a69d32f310	1477
nikapov	0:a1a69d32f310	1478	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1479	status = VL53L0X_set_limit_check_value(VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
nikapov	0:a1a69d32f310	1480	(FixPoint1616_t)(35 * 65536));
nikapov	0:a1a69d32f310	1481	}
nikapov	0:a1a69d32f310	1482
nikapov	0:a1a69d32f310	1483	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1484	status = VL53L0X_set_limit_check_value(VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
nikapov	0:a1a69d32f310	1485	(FixPoint1616_t)(0 * 65536));
nikapov	0:a1a69d32f310	1486	}
nikapov	0:a1a69d32f310	1487
nikapov	0:a1a69d32f310	1488	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1489
sepp_nepp	7:41cbc431e1f4	1490	_device->SequenceConfig = 0xFF;
sepp_nepp	7:41cbc431e1f4	1491	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
nikapov	0:a1a69d32f310	1492	0xFF);
nikapov	0:a1a69d32f310	1493
nikapov	0:a1a69d32f310	1494	/* Set PAL state to tell that we are waiting for call to
nikapov	0:a1a69d32f310	1495	* VL53L0X_StaticInit */
sepp_nepp	7:41cbc431e1f4	1496	_device->PalState = VL53L0X_STATE_WAIT_STATICINIT;
nikapov	0:a1a69d32f310	1497	}
nikapov	0:a1a69d32f310	1498
Davidroid	3:e9269ff624ed	1499	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1500	_device->DeviceSpecificParameters.RefSpadsInitialised = 0;
Davidroid	3:e9269ff624ed	1501	}
nikapov	0:a1a69d32f310	1502
nikapov	0:a1a69d32f310	1503
sepp_nepp	5:b95f6951f7d5	1504
nikapov	0:a1a69d32f310	1505	return status;
nikapov	0:a1a69d32f310	1506	}
nikapov	0:a1a69d32f310	1507
sepp_nepp	7:41cbc431e1f4	1508	VL53L0X_Error VL53L0X::VL53L0X_check_part_used(uint8_t *revision,
nikapov	0:a1a69d32f310	1509	VL53L0X_DeviceInfo_t *p_VL53L0X_device_info)
nikapov	0:a1a69d32f310	1510	{
nikapov	0:a1a69d32f310	1511	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1512	uint8_t module_id_int;
nikapov	0:a1a69d32f310	1513	char *product_id_tmp;
nikapov	0:a1a69d32f310	1514
sepp_nepp	5:b95f6951f7d5	1515
nikapov	0:a1a69d32f310	1516
sepp_nepp	7:41cbc431e1f4	1517	status = VL53L0X_get_info_from_device(2);
nikapov	0:a1a69d32f310	1518
nikapov	0:a1a69d32f310	1519	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1520	module_id_int = _device->DeviceSpecificParameters.ModuleId;
nikapov	0:a1a69d32f310	1521
nikapov	0:a1a69d32f310	1522	if (module_id_int == 0) {
nikapov	0:a1a69d32f310	1523	*revision = 0;
sepp_nepp	7:41cbc431e1f4	1524	strcpy(p_VL53L0X_device_info->ProductId,"");
nikapov	0:a1a69d32f310	1525	} else {
sepp_nepp	7:41cbc431e1f4	1526	*revision = _device->DeviceSpecificParameters.Revision;
sepp_nepp	7:41cbc431e1f4	1527	product_id_tmp = _device->DeviceSpecificParameters.ProductId;
sepp_nepp	7:41cbc431e1f4	1528	strcpy(p_VL53L0X_device_info->ProductId,product_id_tmp);
nikapov	0:a1a69d32f310	1529	}
nikapov	0:a1a69d32f310	1530	}
nikapov	0:a1a69d32f310	1531
sepp_nepp	5:b95f6951f7d5	1532
nikapov	0:a1a69d32f310	1533	return status;
nikapov	0:a1a69d32f310	1534	}
nikapov	0:a1a69d32f310	1535
sepp_nepp	7:41cbc431e1f4	1536	VL53L0X_Error VL53L0X::VL53L0X_get_device_info(VL53L0X_DeviceInfo_t *p_VL53L0X_device_info)
nikapov	0:a1a69d32f310	1537	{
nikapov	0:a1a69d32f310	1538	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1539	uint8_t revision_id;
nikapov	0:a1a69d32f310	1540	uint8_t revision;
nikapov	0:a1a69d32f310	1541
sepp_nepp	7:41cbc431e1f4	1542	status = VL53L0X_check_part_used(&revision,p_VL53L0X_device_info);
nikapov	0:a1a69d32f310	1543
nikapov	0:a1a69d32f310	1544	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1545	if (revision == 0) {
sepp_nepp	5:b95f6951f7d5	1546	strcpy(p_VL53L0X_device_info->Name,
nikapov	0:a1a69d32f310	1547	VL53L0X_STRING_DEVICE_INFO_NAME_TS0);
nikapov	0:a1a69d32f310	1548	} else if ((revision <= 34) && (revision != 32)) {
sepp_nepp	5:b95f6951f7d5	1549	strcpy(p_VL53L0X_device_info->Name,
nikapov	0:a1a69d32f310	1550	VL53L0X_STRING_DEVICE_INFO_NAME_TS1);
nikapov	0:a1a69d32f310	1551	} else if (revision < 39) {
sepp_nepp	5:b95f6951f7d5	1552	strcpy(p_VL53L0X_device_info->Name,
nikapov	0:a1a69d32f310	1553	VL53L0X_STRING_DEVICE_INFO_NAME_TS2);
nikapov	0:a1a69d32f310	1554	} else {
sepp_nepp	5:b95f6951f7d5	1555	strcpy(p_VL53L0X_device_info->Name,
nikapov	0:a1a69d32f310	1556	VL53L0X_STRING_DEVICE_INFO_NAME_ES1);
nikapov	0:a1a69d32f310	1557	}
nikapov	0:a1a69d32f310	1558
sepp_nepp	7:41cbc431e1f4	1559	strcpy(p_VL53L0X_device_info->Type,VL53L0X_STRING_DEVICE_INFO_TYPE);
nikapov	0:a1a69d32f310	1560	}
nikapov	0:a1a69d32f310	1561
nikapov	0:a1a69d32f310	1562	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1563	status = VL53L0X_read_byte(VL53L0X_REG_IDENTIFICATION_MODEL_ID,
nikapov	0:a1a69d32f310	1564	&p_VL53L0X_device_info->ProductType);
nikapov	0:a1a69d32f310	1565	}
nikapov	0:a1a69d32f310	1566
nikapov	0:a1a69d32f310	1567	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1568	status = VL53L0X_read_byte(VL53L0X_REG_IDENTIFICATION_REVISION_ID,
nikapov	0:a1a69d32f310	1569	&revision_id);
nikapov	0:a1a69d32f310	1570	p_VL53L0X_device_info->ProductRevisionMajor = 1;
nikapov	0:a1a69d32f310	1571	p_VL53L0X_device_info->ProductRevisionMinor =
nikapov	0:a1a69d32f310	1572	(revision_id & 0xF0) >> 4;
nikapov	0:a1a69d32f310	1573	}
nikapov	0:a1a69d32f310	1574
nikapov	0:a1a69d32f310	1575	return status;
nikapov	0:a1a69d32f310	1576	}
nikapov	0:a1a69d32f310	1577
sepp_nepp	7:41cbc431e1f4	1578	VL53L0X_Error VL53L0X::VL53L0X_get_interrupt_mask_status(uint32_t *p_interrupt_mask_status)
nikapov	0:a1a69d32f310	1579	{
nikapov	0:a1a69d32f310	1580	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1581	uint8_t byte;
sepp_nepp	5:b95f6951f7d5	1582
nikapov	0:a1a69d32f310	1583
sepp_nepp	7:41cbc431e1f4	1584	status = VL53L0X_read_byte(VL53L0X_REG_RESULT_INTERRUPT_STATUS,&byte);
nikapov	0:a1a69d32f310	1585	*p_interrupt_mask_status = byte & 0x07;
nikapov	0:a1a69d32f310	1586
nikapov	0:a1a69d32f310	1587	if (byte & 0x18) {
nikapov	0:a1a69d32f310	1588	status = VL53L0X_ERROR_RANGE_ERROR;
nikapov	0:a1a69d32f310	1589	}
nikapov	0:a1a69d32f310	1590
sepp_nepp	5:b95f6951f7d5	1591
nikapov	0:a1a69d32f310	1592	return status;
nikapov	0:a1a69d32f310	1593	}
nikapov	0:a1a69d32f310	1594
sepp_nepp	7:41cbc431e1f4	1595	VL53L0X_Error VL53L0X::VL53L0X_get_measurement_data_ready(uint8_t *p_measurement_data_ready)
nikapov	0:a1a69d32f310	1596	{
nikapov	0:a1a69d32f310	1597	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1598	uint8_t sys_range_status_register;
nikapov	0:a1a69d32f310	1599	uint8_t interrupt_config;
nikapov	0:a1a69d32f310	1600	uint32_t interrupt_mask;
sepp_nepp	5:b95f6951f7d5	1601
nikapov	0:a1a69d32f310	1602
sepp_nepp	7:41cbc431e1f4	1603	interrupt_config = _device->DeviceSpecificParameters.Pin0GpioFunctionality;
nikapov	0:a1a69d32f310	1604
nikapov	0:a1a69d32f310	1605	if (interrupt_config ==
nikapov	0:a1a69d32f310	1606	VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY) {
sepp_nepp	7:41cbc431e1f4	1607	status = VL53L0X_get_interrupt_mask_status(&interrupt_mask);
nikapov	0:a1a69d32f310	1608	if (interrupt_mask ==
nikapov	0:a1a69d32f310	1609	VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY) {
nikapov	0:a1a69d32f310	1610	*p_measurement_data_ready = 1;
nikapov	0:a1a69d32f310	1611	} else {
nikapov	0:a1a69d32f310	1612	*p_measurement_data_ready = 0;
nikapov	0:a1a69d32f310	1613	}
nikapov	0:a1a69d32f310	1614	} else {
sepp_nepp	7:41cbc431e1f4	1615	status = VL53L0X_read_byte(VL53L0X_REG_RESULT_RANGE_STATUS,
nikapov	0:a1a69d32f310	1616	&sys_range_status_register);
nikapov	0:a1a69d32f310	1617	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1618	if (sys_range_status_register & 0x01) {
nikapov	0:a1a69d32f310	1619	*p_measurement_data_ready = 1;
nikapov	0:a1a69d32f310	1620	} else {
nikapov	0:a1a69d32f310	1621	*p_measurement_data_ready = 0;
nikapov	0:a1a69d32f310	1622	}
nikapov	0:a1a69d32f310	1623	}
nikapov	0:a1a69d32f310	1624	}
nikapov	0:a1a69d32f310	1625
nikapov	0:a1a69d32f310	1626	return status;
nikapov	0:a1a69d32f310	1627	}
nikapov	0:a1a69d32f310	1628
sepp_nepp	7:41cbc431e1f4	1629	VL53L0X_Error VL53L0X::VL53L0X_polling_delay()
sepp_nepp	6:1976f4afed97	1630	{
sepp_nepp	6:1976f4afed97	1631	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	6:1976f4afed97	1632
sepp_nepp	6:1976f4afed97	1633	// do nothing VL53L0X_OsDelay();
sepp_nepp	6:1976f4afed97	1634	return status;
sepp_nepp	6:1976f4afed97	1635	}
sepp_nepp	6:1976f4afed97	1636
sepp_nepp	7:41cbc431e1f4	1637	VL53L0X_Error VL53L0X::VL53L0X_measurement_poll_for_completion()
nikapov	0:a1a69d32f310	1638	{
nikapov	0:a1a69d32f310	1639	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1640	uint8_t new_data_ready = 0;
nikapov	0:a1a69d32f310	1641	uint32_t loop_nb;
nikapov	0:a1a69d32f310	1642
nikapov	0:a1a69d32f310	1643	loop_nb = 0;
sepp_nepp	5:b95f6951f7d5	1644
sepp_nepp	7:41cbc431e1f4	1645	status = VL53L0X_get_measurement_data_ready(&new_data_ready);
sepp_nepp	7:41cbc431e1f4	1646
sepp_nepp	7:41cbc431e1f4	1647	while ((status==0) && (new_data_ready != 1) &&
sepp_nepp	5:b95f6951f7d5	1648	(loop_nb < VL53L0X_DEFAULT_MAX_LOOP) )
sepp_nepp	5:b95f6951f7d5	1649	{
sepp_nepp	7:41cbc431e1f4	1650	VL53L0X_polling_delay();
sepp_nepp	7:41cbc431e1f4	1651	status = VL53L0X_get_measurement_data_ready(&new_data_ready);
sepp_nepp	5:b95f6951f7d5	1652	loop_nb++;
sepp_nepp	5:b95f6951f7d5	1653	} // while ;
sepp_nepp	5:b95f6951f7d5	1654
sepp_nepp	5:b95f6951f7d5	1655	if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) status = VL53L0X_ERROR_TIME_OUT;
sepp_nepp	5:b95f6951f7d5	1656
nikapov	0:a1a69d32f310	1657	return status;
nikapov	0:a1a69d32f310	1658	}
nikapov	0:a1a69d32f310	1659
nikapov	0:a1a69d32f310	1660	/* Group PAL Interrupt Functions */
sepp_nepp	7:41cbc431e1f4	1661	VL53L0X_Error VL53L0X::VL53L0X_clear_interrupt_mask(uint32_t interrupt_mask)
nikapov	0:a1a69d32f310	1662	{
nikapov	0:a1a69d32f310	1663	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1664	uint8_t loop_count;
nikapov	0:a1a69d32f310	1665	uint8_t byte;
sepp_nepp	5:b95f6951f7d5	1666
nikapov	0:a1a69d32f310	1667
sepp_nepp	7:41cbc431e1f4	1668	/* clear bit 0 range interrupt,bit 1 error interrupt */
nikapov	0:a1a69d32f310	1669	loop_count = 0;
nikapov	0:a1a69d32f310	1670	do {
sepp_nepp	7:41cbc431e1f4	1671	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR,0x01);
sepp_nepp	7:41cbc431e1f4	1672	status \|= VL53L0X_write_byte(VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR,0x00);
sepp_nepp	7:41cbc431e1f4	1673	status \|= VL53L0X_read_byte(VL53L0X_REG_RESULT_INTERRUPT_STATUS,&byte);
nikapov	0:a1a69d32f310	1674	loop_count++;
nikapov	0:a1a69d32f310	1675	} while (((byte & 0x07) != 0x00)
nikapov	0:a1a69d32f310	1676	&& (loop_count < 3)
nikapov	0:a1a69d32f310	1677	&& (status == VL53L0X_ERROR_NONE));
nikapov	0:a1a69d32f310	1678
nikapov	0:a1a69d32f310	1679
nikapov	0:a1a69d32f310	1680	if (loop_count >= 3) {
nikapov	0:a1a69d32f310	1681	status = VL53L0X_ERROR_INTERRUPT_NOT_CLEARED;
nikapov	0:a1a69d32f310	1682	}
nikapov	0:a1a69d32f310	1683
sepp_nepp	5:b95f6951f7d5	1684
nikapov	0:a1a69d32f310	1685	return status;
nikapov	0:a1a69d32f310	1686	}
nikapov	0:a1a69d32f310	1687
sepp_nepp	7:41cbc431e1f4	1688	VL53L0X_Error VL53L0X::VL53L0X_perform_single_ref_calibration(uint8_t vhv_init_byte)
nikapov	0:a1a69d32f310	1689	{
nikapov	0:a1a69d32f310	1690	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1691
nikapov	0:a1a69d32f310	1692	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1693	status = VL53L0X_write_byte(VL53L0X_REG_SYSRANGE_START,
nikapov	0:a1a69d32f310	1694	VL53L0X_REG_SYSRANGE_MODE_START_STOP \|
nikapov	0:a1a69d32f310	1695	vhv_init_byte);
nikapov	0:a1a69d32f310	1696	}
nikapov	0:a1a69d32f310	1697
nikapov	0:a1a69d32f310	1698	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1699	status = VL53L0X_measurement_poll_for_completion();
nikapov	0:a1a69d32f310	1700	}
nikapov	0:a1a69d32f310	1701
nikapov	0:a1a69d32f310	1702	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1703	status = VL53L0X_clear_interrupt_mask(0);
nikapov	0:a1a69d32f310	1704	}
nikapov	0:a1a69d32f310	1705
nikapov	0:a1a69d32f310	1706	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1707	status = VL53L0X_write_byte(VL53L0X_REG_SYSRANGE_START,0x00);
nikapov	0:a1a69d32f310	1708	}
nikapov	0:a1a69d32f310	1709
nikapov	0:a1a69d32f310	1710	return status;
nikapov	0:a1a69d32f310	1711	}
nikapov	0:a1a69d32f310	1712
sepp_nepp	7:41cbc431e1f4	1713	VL53L0X_Error VL53L0X::VL53L0X_ref_calibration_io(uint8_t read_not_write,
sepp_nepp	7:41cbc431e1f4	1714	uint8_t vhv_settings,uint8_t phase_cal,
sepp_nepp	7:41cbc431e1f4	1715	uint8_t p_vhv_settings,uint8_t p_phase_cal,
sepp_nepp	7:41cbc431e1f4	1716	const uint8_t vhv_enable,const uint8_t phase_enable)
nikapov	0:a1a69d32f310	1717	{
nikapov	0:a1a69d32f310	1718	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1719	uint8_t phase_calint = 0;
nikapov	0:a1a69d32f310	1720
nikapov	0:a1a69d32f310	1721	/* Read VHV from device */
sepp_nepp	7:41cbc431e1f4	1722	status \|= VL53L0X_write_byte(0xFF,0x01);
sepp_nepp	7:41cbc431e1f4	1723	status \|= VL53L0X_write_byte(0x00,0x00);
sepp_nepp	7:41cbc431e1f4	1724	status \|= VL53L0X_write_byte(0xFF,0x00);
nikapov	0:a1a69d32f310	1725
nikapov	0:a1a69d32f310	1726	if (read_not_write) {
nikapov	0:a1a69d32f310	1727	if (vhv_enable) {
sepp_nepp	7:41cbc431e1f4	1728	status \|= VL53L0X_read_byte(0xCB,p_vhv_settings);
nikapov	0:a1a69d32f310	1729	}
nikapov	0:a1a69d32f310	1730	if (phase_enable) {
sepp_nepp	7:41cbc431e1f4	1731	status \|= VL53L0X_read_byte(0xEE,&phase_calint);
nikapov	0:a1a69d32f310	1732	}
nikapov	0:a1a69d32f310	1733	} else {
nikapov	0:a1a69d32f310	1734	if (vhv_enable) {
sepp_nepp	7:41cbc431e1f4	1735	status \|= VL53L0X_write_byte(0xCB,vhv_settings);
nikapov	0:a1a69d32f310	1736	}
nikapov	0:a1a69d32f310	1737	if (phase_enable) {
sepp_nepp	7:41cbc431e1f4	1738	status \|= VL53L0X_update_byte(0xEE,0x80,phase_cal);
nikapov	0:a1a69d32f310	1739	}
nikapov	0:a1a69d32f310	1740	}
nikapov	0:a1a69d32f310	1741
sepp_nepp	7:41cbc431e1f4	1742	status \|= VL53L0X_write_byte(0xFF,0x01);
sepp_nepp	7:41cbc431e1f4	1743	status \|= VL53L0X_write_byte(0x00,0x01);
sepp_nepp	7:41cbc431e1f4	1744	status \|= VL53L0X_write_byte(0xFF,0x00);
nikapov	0:a1a69d32f310	1745
nikapov	0:a1a69d32f310	1746	*p_phase_cal = (uint8_t)(phase_calint & 0xEF);
nikapov	0:a1a69d32f310	1747
nikapov	0:a1a69d32f310	1748	return status;
nikapov	0:a1a69d32f310	1749	}
nikapov	0:a1a69d32f310	1750
sepp_nepp	7:41cbc431e1f4	1751	VL53L0X_Error VL53L0X::VL53L0X_perform_vhv_calibration(uint8_t *p_vhv_settings,const uint8_t get_data_enable,
nikapov	0:a1a69d32f310	1752	const uint8_t restore_config)
nikapov	0:a1a69d32f310	1753	{
nikapov	0:a1a69d32f310	1754	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1755	uint8_t sequence_config = 0;
nikapov	0:a1a69d32f310	1756	uint8_t vhv_settings = 0;
nikapov	0:a1a69d32f310	1757	uint8_t phase_cal = 0;
nikapov	0:a1a69d32f310	1758	uint8_t phase_cal_int = 0;
nikapov	0:a1a69d32f310	1759
nikapov	0:a1a69d32f310	1760	/* store the value of the sequence config,
nikapov	0:a1a69d32f310	1761	* this will be reset before the end of the function
nikapov	0:a1a69d32f310	1762	*/
sepp_nepp	7:41cbc431e1f4	1763	if (restore_config) {sequence_config = _device->SequenceConfig;}
nikapov	0:a1a69d32f310	1764
nikapov	0:a1a69d32f310	1765	/* Run VHV */
sepp_nepp	7:41cbc431e1f4	1766	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,0x01);
nikapov	0:a1a69d32f310	1767
nikapov	0:a1a69d32f310	1768	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1769	status = VL53L0X_perform_single_ref_calibration(0x40);
nikapov	0:a1a69d32f310	1770	}
nikapov	0:a1a69d32f310	1771
nikapov	0:a1a69d32f310	1772	/* Read VHV from device */
nikapov	0:a1a69d32f310	1773	if ((status == VL53L0X_ERROR_NONE) && (get_data_enable == 1)) {
sepp_nepp	7:41cbc431e1f4	1774	status = VL53L0X_ref_calibration_io(1,
sepp_nepp	7:41cbc431e1f4	1775	vhv_settings,phase_cal,/* Not used here */
sepp_nepp	7:41cbc431e1f4	1776	p_vhv_settings,&phase_cal_int,
sepp_nepp	7:41cbc431e1f4	1777	1,0);
nikapov	0:a1a69d32f310	1778	} else {
nikapov	0:a1a69d32f310	1779	*p_vhv_settings = 0;
nikapov	0:a1a69d32f310	1780	}
nikapov	0:a1a69d32f310	1781
nikapov	0:a1a69d32f310	1782
nikapov	0:a1a69d32f310	1783	if ((status == VL53L0X_ERROR_NONE) && restore_config) {
nikapov	0:a1a69d32f310	1784	/* restore the previous Sequence Config */
sepp_nepp	7:41cbc431e1f4	1785	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
nikapov	0:a1a69d32f310	1786	sequence_config);
nikapov	0:a1a69d32f310	1787	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1788	_device->SequenceConfig = sequence_config;
nikapov	0:a1a69d32f310	1789	}
nikapov	0:a1a69d32f310	1790
nikapov	0:a1a69d32f310	1791	}
nikapov	0:a1a69d32f310	1792
nikapov	0:a1a69d32f310	1793	return status;
nikapov	0:a1a69d32f310	1794	}
nikapov	0:a1a69d32f310	1795
sepp_nepp	7:41cbc431e1f4	1796	VL53L0X_Error VL53L0X::VL53L0X_perform_phase_calibration(uint8_t *p_phase_cal,const uint8_t get_data_enable,
nikapov	0:a1a69d32f310	1797	const uint8_t restore_config)
nikapov	0:a1a69d32f310	1798	{
nikapov	0:a1a69d32f310	1799	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1800	uint8_t sequence_config = 0;
nikapov	0:a1a69d32f310	1801	uint8_t vhv_settings = 0;
nikapov	0:a1a69d32f310	1802	uint8_t phase_cal = 0;
nikapov	0:a1a69d32f310	1803	uint8_t vhv_settingsint;
nikapov	0:a1a69d32f310	1804
nikapov	0:a1a69d32f310	1805	/* store the value of the sequence config,
nikapov	0:a1a69d32f310	1806	* this will be reset before the end of the function
nikapov	0:a1a69d32f310	1807	*/
nikapov	0:a1a69d32f310	1808
Davidroid	3:e9269ff624ed	1809	if (restore_config) {
sepp_nepp	7:41cbc431e1f4	1810	sequence_config = _device-> SequenceConfig;
Davidroid	3:e9269ff624ed	1811	}
nikapov	0:a1a69d32f310	1812
nikapov	0:a1a69d32f310	1813	/* Run PhaseCal */
sepp_nepp	7:41cbc431e1f4	1814	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,0x02);
nikapov	0:a1a69d32f310	1815
nikapov	0:a1a69d32f310	1816	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1817	status = VL53L0X_perform_single_ref_calibration(0x0);
nikapov	0:a1a69d32f310	1818	}
nikapov	0:a1a69d32f310	1819
nikapov	0:a1a69d32f310	1820	/* Read PhaseCal from device */
nikapov	0:a1a69d32f310	1821	if ((status == VL53L0X_ERROR_NONE) && (get_data_enable == 1)) {
sepp_nepp	7:41cbc431e1f4	1822	status = VL53L0X_ref_calibration_io(1,
sepp_nepp	7:41cbc431e1f4	1823	vhv_settings,phase_cal,/* Not used here */
sepp_nepp	7:41cbc431e1f4	1824	&vhv_settingsint,p_phase_cal,
sepp_nepp	7:41cbc431e1f4	1825	0,1);
nikapov	0:a1a69d32f310	1826	} else {
nikapov	0:a1a69d32f310	1827	*p_phase_cal = 0;
nikapov	0:a1a69d32f310	1828	}
nikapov	0:a1a69d32f310	1829
nikapov	0:a1a69d32f310	1830
nikapov	0:a1a69d32f310	1831	if ((status == VL53L0X_ERROR_NONE) && restore_config) {
nikapov	0:a1a69d32f310	1832	/* restore the previous Sequence Config */
sepp_nepp	7:41cbc431e1f4	1833	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
nikapov	0:a1a69d32f310	1834	sequence_config);
nikapov	0:a1a69d32f310	1835	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1836	_device->SequenceConfig = sequence_config;
nikapov	0:a1a69d32f310	1837	}
nikapov	0:a1a69d32f310	1838
nikapov	0:a1a69d32f310	1839	}
nikapov	0:a1a69d32f310	1840
nikapov	0:a1a69d32f310	1841	return status;
nikapov	0:a1a69d32f310	1842	}
nikapov	0:a1a69d32f310	1843
sepp_nepp	7:41cbc431e1f4	1844	VL53L0X_Error VL53L0X::VL53L0X_perform_ref_calibration(uint8_t p_vhv_settings,uint8_t p_phase_cal,uint8_t get_data_enable)
nikapov	0:a1a69d32f310	1845	{
nikapov	0:a1a69d32f310	1846	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1847	uint8_t sequence_config = 0;
nikapov	0:a1a69d32f310	1848
nikapov	0:a1a69d32f310	1849	/* store the value of the sequence config,
nikapov	0:a1a69d32f310	1850	* this will be reset before the end of the function
nikapov	0:a1a69d32f310	1851	*/
nikapov	0:a1a69d32f310	1852
sepp_nepp	7:41cbc431e1f4	1853	sequence_config = _device-> SequenceConfig;
nikapov	0:a1a69d32f310	1854
nikapov	0:a1a69d32f310	1855	/* In the following function we don't save the config to optimize
nikapov	0:a1a69d32f310	1856	* writes on device. Config is saved and restored only once. */
sepp_nepp	7:41cbc431e1f4	1857	status = VL53L0X_perform_vhv_calibration(p_vhv_settings,get_data_enable,0);
nikapov	0:a1a69d32f310	1858
nikapov	0:a1a69d32f310	1859	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1860	status = VL53L0X_perform_phase_calibration(p_phase_cal,get_data_enable,0);
Davidroid	2:d07edeaff6f1	1861	}
nikapov	0:a1a69d32f310	1862
nikapov	0:a1a69d32f310	1863
nikapov	0:a1a69d32f310	1864	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	1865	/* restore the previous Sequence Config */
sepp_nepp	7:41cbc431e1f4	1866	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
nikapov	0:a1a69d32f310	1867	sequence_config);
nikapov	0:a1a69d32f310	1868	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	1869	_device->SequenceConfig = sequence_config;
nikapov	0:a1a69d32f310	1870	}
nikapov	0:a1a69d32f310	1871
nikapov	0:a1a69d32f310	1872	}
nikapov	0:a1a69d32f310	1873
nikapov	0:a1a69d32f310	1874	return status;
nikapov	0:a1a69d32f310	1875	}
nikapov	0:a1a69d32f310	1876
sepp_nepp	7:41cbc431e1f4	1877	void VL53L0X::get_next_good_spad(uint8_t good_spad_array[],uint32_t size,
sepp_nepp	7:41cbc431e1f4	1878	uint32_t curr,int32_t *p_next)
nikapov	0:a1a69d32f310	1879	{
nikapov	0:a1a69d32f310	1880	uint32_t start_index;
nikapov	0:a1a69d32f310	1881	uint32_t fine_offset;
nikapov	0:a1a69d32f310	1882	uint32_t c_spads_per_byte = 8;
nikapov	0:a1a69d32f310	1883	uint32_t coarse_index;
nikapov	0:a1a69d32f310	1884	uint32_t fine_index;
nikapov	0:a1a69d32f310	1885	uint8_t data_byte;
nikapov	0:a1a69d32f310	1886	uint8_t success = 0;
nikapov	0:a1a69d32f310	1887
nikapov	0:a1a69d32f310	1888	/*
sepp_nepp	7:41cbc431e1f4	1889	* Starting with the current good spad,loop through the array to find
nikapov	0:a1a69d32f310	1890	* the next. i.e. the next bit set in the sequence.
nikapov	0:a1a69d32f310	1891	*
nikapov	0:a1a69d32f310	1892	* The coarse index is the byte index of the array and the fine index is
nikapov	0:a1a69d32f310	1893	* the index of the bit within each byte.
nikapov	0:a1a69d32f310	1894	*/
nikapov	0:a1a69d32f310	1895
nikapov	0:a1a69d32f310	1896	*p_next = -1;
nikapov	0:a1a69d32f310	1897
nikapov	0:a1a69d32f310	1898	start_index = curr / c_spads_per_byte;
nikapov	0:a1a69d32f310	1899	fine_offset = curr % c_spads_per_byte;
nikapov	0:a1a69d32f310	1900
nikapov	0:a1a69d32f310	1901	for (coarse_index = start_index; ((coarse_index < size) && !success);
nikapov	0:a1a69d32f310	1902	coarse_index++) {
nikapov	0:a1a69d32f310	1903	fine_index = 0;
nikapov	0:a1a69d32f310	1904	data_byte = good_spad_array[coarse_index];
nikapov	0:a1a69d32f310	1905
nikapov	0:a1a69d32f310	1906	if (coarse_index == start_index) {
nikapov	0:a1a69d32f310	1907	/* locate the bit position of the provided current
nikapov	0:a1a69d32f310	1908	* spad bit before iterating */
nikapov	0:a1a69d32f310	1909	data_byte >>= fine_offset;
nikapov	0:a1a69d32f310	1910	fine_index = fine_offset;
nikapov	0:a1a69d32f310	1911	}
nikapov	0:a1a69d32f310	1912
nikapov	0:a1a69d32f310	1913	while (fine_index < c_spads_per_byte) {
nikapov	0:a1a69d32f310	1914	if ((data_byte & 0x1) == 1) {
nikapov	0:a1a69d32f310	1915	success = 1;
nikapov	0:a1a69d32f310	1916	p_next = coarse_index c_spads_per_byte + fine_index;
nikapov	0:a1a69d32f310	1917	break;
nikapov	0:a1a69d32f310	1918	}
nikapov	0:a1a69d32f310	1919	data_byte >>= 1;
nikapov	0:a1a69d32f310	1920	fine_index++;
nikapov	0:a1a69d32f310	1921	}
nikapov	0:a1a69d32f310	1922	}
nikapov	0:a1a69d32f310	1923	}
nikapov	0:a1a69d32f310	1924
nikapov	0:a1a69d32f310	1925	uint8_t VL53L0X::is_aperture(uint32_t spad_index)
nikapov	0:a1a69d32f310	1926	{
nikapov	0:a1a69d32f310	1927	/*
nikapov	0:a1a69d32f310	1928	* This function reports if a given spad index is an aperture SPAD by
nikapov	0:a1a69d32f310	1929	* deriving the quadrant.
nikapov	0:a1a69d32f310	1930	*/
nikapov	0:a1a69d32f310	1931	uint32_t quadrant;
nikapov	0:a1a69d32f310	1932	uint8_t is_aperture = 1;
nikapov	0:a1a69d32f310	1933	quadrant = spad_index >> 6;
nikapov	0:a1a69d32f310	1934	if (refArrayQuadrants[quadrant] == REF_ARRAY_SPAD_0) {
nikapov	0:a1a69d32f310	1935	is_aperture = 0;
Davidroid	2:d07edeaff6f1	1936	}
nikapov	0:a1a69d32f310	1937
nikapov	0:a1a69d32f310	1938	return is_aperture;
nikapov	0:a1a69d32f310	1939	}
nikapov	0:a1a69d32f310	1940
sepp_nepp	7:41cbc431e1f4	1941	VL53L0X_Error VL53L0X::enable_spad_bit(uint8_t spad_array[],uint32_t size,
nikapov	0:a1a69d32f310	1942	uint32_t spad_index)
nikapov	0:a1a69d32f310	1943	{
nikapov	0:a1a69d32f310	1944	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1945	uint32_t c_spads_per_byte = 8;
nikapov	0:a1a69d32f310	1946	uint32_t coarse_index;
nikapov	0:a1a69d32f310	1947	uint32_t fine_index;
nikapov	0:a1a69d32f310	1948
nikapov	0:a1a69d32f310	1949	coarse_index = spad_index / c_spads_per_byte;
nikapov	0:a1a69d32f310	1950	fine_index = spad_index % c_spads_per_byte;
nikapov	0:a1a69d32f310	1951	if (coarse_index >= size) {
nikapov	0:a1a69d32f310	1952	status = VL53L0X_ERROR_REF_SPAD_INIT;
nikapov	0:a1a69d32f310	1953	} else {
nikapov	0:a1a69d32f310	1954	spad_array[coarse_index] \|= (1 << fine_index);
nikapov	0:a1a69d32f310	1955	}
nikapov	0:a1a69d32f310	1956
nikapov	0:a1a69d32f310	1957	return status;
nikapov	0:a1a69d32f310	1958	}
nikapov	0:a1a69d32f310	1959
sepp_nepp	7:41cbc431e1f4	1960	VL53L0X_Error VL53L0X::set_ref_spad_map(uint8_t *p_ref_spad_array)
nikapov	0:a1a69d32f310	1961	{
sepp_nepp	7:41cbc431e1f4	1962	VL53L0X_Error status = VL53L0X_write_multi(VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0,
sepp_nepp	7:41cbc431e1f4	1963	p_ref_spad_array,6);
nikapov	0:a1a69d32f310	1964
nikapov	0:a1a69d32f310	1965	return status;
nikapov	0:a1a69d32f310	1966	}
nikapov	0:a1a69d32f310	1967
sepp_nepp	7:41cbc431e1f4	1968	VL53L0X_Error VL53L0X::get_ref_spad_map(uint8_t *p_ref_spad_array)
nikapov	0:a1a69d32f310	1969	{
sepp_nepp	7:41cbc431e1f4	1970	VL53L0X_Error status = VL53L0X_read_multi(VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0,
nikapov	0:a1a69d32f310	1971	p_ref_spad_array,
nikapov	0:a1a69d32f310	1972	6);
nikapov	0:a1a69d32f310	1973	// VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1974	// uint8_t count=0;
nikapov	0:a1a69d32f310	1975
nikapov	0:a1a69d32f310	1976	// for (count = 0; count < 6; count++)
sepp_nepp	7:41cbc431e1f4	1977	// status = VL53L0X_RdByte((VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0 + count),&refSpadArray[count]);
nikapov	0:a1a69d32f310	1978	return status;
nikapov	0:a1a69d32f310	1979	}
nikapov	0:a1a69d32f310	1980
sepp_nepp	7:41cbc431e1f4	1981	VL53L0X_Error VL53L0X::enable_ref_spads(uint8_t aperture_spads,
nikapov	0:a1a69d32f310	1982	uint8_t good_spad_array[],
nikapov	0:a1a69d32f310	1983	uint8_t spad_array[],
nikapov	0:a1a69d32f310	1984	uint32_t size,
nikapov	0:a1a69d32f310	1985	uint32_t start,
nikapov	0:a1a69d32f310	1986	uint32_t offset,
nikapov	0:a1a69d32f310	1987	uint32_t spad_count,
nikapov	0:a1a69d32f310	1988	uint32_t *p_last_spad)
nikapov	0:a1a69d32f310	1989	{
nikapov	0:a1a69d32f310	1990	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	1991	uint32_t index;
nikapov	0:a1a69d32f310	1992	uint32_t i;
nikapov	0:a1a69d32f310	1993	int32_t next_good_spad = offset;
nikapov	0:a1a69d32f310	1994	uint32_t current_spad;
nikapov	0:a1a69d32f310	1995	uint8_t check_spad_array[6];
nikapov	0:a1a69d32f310	1996
nikapov	0:a1a69d32f310	1997	/*
nikapov	0:a1a69d32f310	1998	* This function takes in a spad array which may or may not have SPADS
nikapov	0:a1a69d32f310	1999	* already enabled and appends from a given offset a requested number
nikapov	0:a1a69d32f310	2000	* of new SPAD enables. The 'good spad map' is applied to
nikapov	0:a1a69d32f310	2001	* determine the next SPADs to enable.
nikapov	0:a1a69d32f310	2002	*
nikapov	0:a1a69d32f310	2003	* This function applies to only aperture or only non-aperture spads.
nikapov	0:a1a69d32f310	2004	* Checks are performed to ensure this.
nikapov	0:a1a69d32f310	2005	*/
nikapov	0:a1a69d32f310	2006
nikapov	0:a1a69d32f310	2007	current_spad = offset;
nikapov	0:a1a69d32f310	2008	for (index = 0; index < spad_count; index++) {
sepp_nepp	7:41cbc431e1f4	2009	get_next_good_spad(good_spad_array,size,current_spad,
nikapov	0:a1a69d32f310	2010	&next_good_spad);
nikapov	0:a1a69d32f310	2011
nikapov	0:a1a69d32f310	2012	if (next_good_spad == -1) {
nikapov	0:a1a69d32f310	2013	status = VL53L0X_ERROR_REF_SPAD_INIT;
nikapov	0:a1a69d32f310	2014	break;
nikapov	0:a1a69d32f310	2015	}
nikapov	0:a1a69d32f310	2016
nikapov	0:a1a69d32f310	2017	/* Confirm that the next good SPAD is non-aperture */
nikapov	0:a1a69d32f310	2018	if (is_aperture(start + next_good_spad) != aperture_spads) {
nikapov	0:a1a69d32f310	2019	/* if we can't get the required number of good aperture
nikapov	0:a1a69d32f310	2020	* spads from the current quadrant then this is an error
nikapov	0:a1a69d32f310	2021	*/
nikapov	0:a1a69d32f310	2022	status = VL53L0X_ERROR_REF_SPAD_INIT;
nikapov	0:a1a69d32f310	2023	break;
nikapov	0:a1a69d32f310	2024	}
nikapov	0:a1a69d32f310	2025	current_spad = (uint32_t)next_good_spad;
sepp_nepp	7:41cbc431e1f4	2026	enable_spad_bit(spad_array,size,current_spad);
nikapov	0:a1a69d32f310	2027	current_spad++;
nikapov	0:a1a69d32f310	2028	}
nikapov	0:a1a69d32f310	2029	*p_last_spad = current_spad;
nikapov	0:a1a69d32f310	2030
nikapov	0:a1a69d32f310	2031	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	2032	status = set_ref_spad_map(spad_array);
nikapov	0:a1a69d32f310	2033	}
nikapov	0:a1a69d32f310	2034
nikapov	0:a1a69d32f310	2035
nikapov	0:a1a69d32f310	2036	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	2037	status = get_ref_spad_map(check_spad_array);
nikapov	0:a1a69d32f310	2038
nikapov	0:a1a69d32f310	2039	i = 0;
nikapov	0:a1a69d32f310	2040
nikapov	0:a1a69d32f310	2041	/* Compare spad maps. If not equal report error. */
nikapov	0:a1a69d32f310	2042	while (i < size) {
nikapov	0:a1a69d32f310	2043	if (spad_array[i] != check_spad_array[i]) {
nikapov	0:a1a69d32f310	2044	status = VL53L0X_ERROR_REF_SPAD_INIT;
nikapov	0:a1a69d32f310	2045	break;
nikapov	0:a1a69d32f310	2046	}
nikapov	0:a1a69d32f310	2047	i++;
nikapov	0:a1a69d32f310	2048	}
nikapov	0:a1a69d32f310	2049	}
nikapov	0:a1a69d32f310	2050	return status;
nikapov	0:a1a69d32f310	2051	}
nikapov	0:a1a69d32f310	2052
sepp_nepp	7:41cbc431e1f4	2053	VL53L0X_Error VL53L0X::VL53L0X_set_device_mode(VL53L0X_DeviceModes device_mode)
nikapov	0:a1a69d32f310	2054	{
nikapov	0:a1a69d32f310	2055	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2056
nikapov	0:a1a69d32f310	2057	switch (device_mode) {
nikapov	0:a1a69d32f310	2058	case VL53L0X_DEVICEMODE_SINGLE_RANGING:
nikapov	0:a1a69d32f310	2059	case VL53L0X_DEVICEMODE_CONTINUOUS_RANGING:
nikapov	0:a1a69d32f310	2060	case VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING:
nikapov	0:a1a69d32f310	2061	case VL53L0X_DEVICEMODE_GPIO_DRIVE:
nikapov	0:a1a69d32f310	2062	case VL53L0X_DEVICEMODE_GPIO_OSC:
nikapov	0:a1a69d32f310	2063	/* Supported modes */
sepp_nepp	7:41cbc431e1f4	2064	_device->CurrentParameters.DeviceMode = device_mode;
nikapov	0:a1a69d32f310	2065	break;
nikapov	0:a1a69d32f310	2066	default:
nikapov	0:a1a69d32f310	2067	/* Unsupported mode */
nikapov	0:a1a69d32f310	2068	status = VL53L0X_ERROR_MODE_NOT_SUPPORTED;
nikapov	0:a1a69d32f310	2069	}
nikapov	0:a1a69d32f310	2070
sepp_nepp	5:b95f6951f7d5	2071
nikapov	0:a1a69d32f310	2072	return status;
nikapov	0:a1a69d32f310	2073	}
nikapov	0:a1a69d32f310	2074
sepp_nepp	7:41cbc431e1f4	2075	VL53L0X_Error VL53L0X::VL53L0X_set_interrupt_thresholds(VL53L0X_DeviceModes device_mode,FixPoint1616_t threshold_low,
nikapov	0:a1a69d32f310	2076	FixPoint1616_t threshold_high)
nikapov	0:a1a69d32f310	2077	{
nikapov	0:a1a69d32f310	2078	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2079	uint16_t threshold16;
sepp_nepp	5:b95f6951f7d5	2080
sepp_nepp	5:b95f6951f7d5	2081
sepp_nepp	5:b95f6951f7d5	2082	/* no dependency on DeviceMode for FlightSense */
nikapov	0:a1a69d32f310	2083	/* Need to divide by 2 because the FW will apply a x2 */
nikapov	0:a1a69d32f310	2084	threshold16 = (uint16_t)((threshold_low >> 17) & 0x00fff);
sepp_nepp	7:41cbc431e1f4	2085	status = VL53L0X_write_word(VL53L0X_REG_SYSTEM_THRESH_LOW,threshold16);
nikapov	0:a1a69d32f310	2086
nikapov	0:a1a69d32f310	2087	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	2088	/* Need to divide by 2 because the FW will apply a x2 */
nikapov	0:a1a69d32f310	2089	threshold16 = (uint16_t)((threshold_high >> 17) & 0x00fff);
sepp_nepp	7:41cbc431e1f4	2090	status = VL53L0X_write_word(VL53L0X_REG_SYSTEM_THRESH_HIGH,
nikapov	0:a1a69d32f310	2091	threshold16);
nikapov	0:a1a69d32f310	2092	}
nikapov	0:a1a69d32f310	2093
sepp_nepp	5:b95f6951f7d5	2094
nikapov	0:a1a69d32f310	2095	return status;
nikapov	0:a1a69d32f310	2096	}
nikapov	0:a1a69d32f310	2097
sepp_nepp	7:41cbc431e1f4	2098	VL53L0X_Error VL53L0X::VL53L0X_get_interrupt_thresholds(VL53L0X_DeviceModes device_mode,FixPoint1616_t *p_threshold_low,
nikapov	0:a1a69d32f310	2099	FixPoint1616_t *p_threshold_high)
nikapov	0:a1a69d32f310	2100	{
nikapov	0:a1a69d32f310	2101	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2102	uint16_t threshold16;
sepp_nepp	5:b95f6951f7d5	2103
sepp_nepp	5:b95f6951f7d5	2104
sepp_nepp	5:b95f6951f7d5	2105	/* no dependency on DeviceMode for FlightSense */
nikapov	0:a1a69d32f310	2106
sepp_nepp	7:41cbc431e1f4	2107	status = VL53L0X_read_word(VL53L0X_REG_SYSTEM_THRESH_LOW,&threshold16);
nikapov	0:a1a69d32f310	2108	/* Need to multiply by 2 because the FW will apply a x2 */
nikapov	0:a1a69d32f310	2109	*p_threshold_low = (FixPoint1616_t)((0x00fff & threshold16) << 17);
nikapov	0:a1a69d32f310	2110
nikapov	0:a1a69d32f310	2111	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	2112	status = VL53L0X_read_word(VL53L0X_REG_SYSTEM_THRESH_HIGH,
nikapov	0:a1a69d32f310	2113	&threshold16);
nikapov	0:a1a69d32f310	2114	/* Need to multiply by 2 because the FW will apply a x2 */
nikapov	0:a1a69d32f310	2115	*p_threshold_high =
nikapov	0:a1a69d32f310	2116	(FixPoint1616_t)((0x00fff & threshold16) << 17);
nikapov	0:a1a69d32f310	2117	}
nikapov	0:a1a69d32f310	2118
sepp_nepp	5:b95f6951f7d5	2119
nikapov	0:a1a69d32f310	2120	return status;
nikapov	0:a1a69d32f310	2121	}
nikapov	0:a1a69d32f310	2122
sepp_nepp	7:41cbc431e1f4	2123	VL53L0X_Error VL53L0X::VL53L0X_load_tuning_settings(uint8_t *p_tuning_setting_buffer)
nikapov	0:a1a69d32f310	2124	{
nikapov	0:a1a69d32f310	2125	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2126	int i;
nikapov	0:a1a69d32f310	2127	int index;
nikapov	0:a1a69d32f310	2128	uint8_t msb;
nikapov	0:a1a69d32f310	2129	uint8_t lsb;
nikapov	0:a1a69d32f310	2130	uint8_t select_param;
nikapov	0:a1a69d32f310	2131	uint8_t number_of_writes;
nikapov	0:a1a69d32f310	2132	uint8_t address;
nikapov	0:a1a69d32f310	2133	uint8_t local_buffer[4]; /* max */
nikapov	0:a1a69d32f310	2134	uint16_t temp16;
nikapov	0:a1a69d32f310	2135
sepp_nepp	5:b95f6951f7d5	2136
nikapov	0:a1a69d32f310	2137
nikapov	0:a1a69d32f310	2138	index = 0;
nikapov	0:a1a69d32f310	2139
nikapov	0:a1a69d32f310	2140	while ((*(p_tuning_setting_buffer + index) != 0) &&
nikapov	0:a1a69d32f310	2141	(status == VL53L0X_ERROR_NONE)) {
nikapov	0:a1a69d32f310	2142	number_of_writes = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2143	index++;
nikapov	0:a1a69d32f310	2144	if (number_of_writes == 0xFF) {
nikapov	0:a1a69d32f310	2145	/* internal parameters */
nikapov	0:a1a69d32f310	2146	select_param = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2147	index++;
nikapov	0:a1a69d32f310	2148	switch (select_param) {
nikapov	0:a1a69d32f310	2149	case 0: /* uint16_t SigmaEstRefArray -> 2 bytes */
nikapov	0:a1a69d32f310	2150	msb = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2151	index++;
nikapov	0:a1a69d32f310	2152	lsb = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2153	index++;
sepp_nepp	7:41cbc431e1f4	2154	temp16 = VL53L0X_MAKEUINT16(lsb,msb);
sepp_nepp	7:41cbc431e1f4	2155	_device->SigmaEstRefArray = temp16;
nikapov	0:a1a69d32f310	2156	break;
nikapov	0:a1a69d32f310	2157	case 1: /* uint16_t SigmaEstEffPulseWidth -> 2 bytes */
nikapov	0:a1a69d32f310	2158	msb = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2159	index++;
nikapov	0:a1a69d32f310	2160	lsb = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2161	index++;
sepp_nepp	7:41cbc431e1f4	2162	temp16 = VL53L0X_MAKEUINT16(lsb,msb);
sepp_nepp	7:41cbc431e1f4	2163	_device->SigmaEstEffPulseWidth = temp16;
nikapov	0:a1a69d32f310	2164	break;
nikapov	0:a1a69d32f310	2165	case 2: /* uint16_t SigmaEstEffAmbWidth -> 2 bytes */
nikapov	0:a1a69d32f310	2166	msb = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2167	index++;
nikapov	0:a1a69d32f310	2168	lsb = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2169	index++;
sepp_nepp	7:41cbc431e1f4	2170	temp16 = VL53L0X_MAKEUINT16(lsb,msb);
sepp_nepp	7:41cbc431e1f4	2171	_device->SigmaEstEffAmbWidth = temp16;
nikapov	0:a1a69d32f310	2172	break;
nikapov	0:a1a69d32f310	2173	case 3: /* uint16_t targetRefRate -> 2 bytes */
nikapov	0:a1a69d32f310	2174	msb = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2175	index++;
nikapov	0:a1a69d32f310	2176	lsb = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2177	index++;
sepp_nepp	7:41cbc431e1f4	2178	temp16 = VL53L0X_MAKEUINT16(lsb,msb);
sepp_nepp	7:41cbc431e1f4	2179	_device->targetRefRate = temp16;
nikapov	0:a1a69d32f310	2180	break;
nikapov	0:a1a69d32f310	2181	default: /* invalid parameter */
nikapov	0:a1a69d32f310	2182	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	2183	}
nikapov	0:a1a69d32f310	2184
nikapov	0:a1a69d32f310	2185	} else if (number_of_writes <= 4) {
nikapov	0:a1a69d32f310	2186	address = *(p_tuning_setting_buffer + index);
nikapov	0:a1a69d32f310	2187	index++;
nikapov	0:a1a69d32f310	2188
nikapov	0:a1a69d32f310	2189	for (i = 0; i < number_of_writes; i++) {
nikapov	0:a1a69d32f310	2190	local_buffer[i] = *(p_tuning_setting_buffer +
nikapov	0:a1a69d32f310	2191	index);
nikapov	0:a1a69d32f310	2192	index++;
nikapov	0:a1a69d32f310	2193	}
nikapov	0:a1a69d32f310	2194
sepp_nepp	7:41cbc431e1f4	2195	status = VL53L0X_write_multi(address,local_buffer,
nikapov	0:a1a69d32f310	2196	number_of_writes);
nikapov	0:a1a69d32f310	2197
nikapov	0:a1a69d32f310	2198	} else {
nikapov	0:a1a69d32f310	2199	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	2200	}
nikapov	0:a1a69d32f310	2201	}
nikapov	0:a1a69d32f310	2202
sepp_nepp	5:b95f6951f7d5	2203
nikapov	0:a1a69d32f310	2204	return status;
nikapov	0:a1a69d32f310	2205	}
nikapov	0:a1a69d32f310	2206
sepp_nepp	7:41cbc431e1f4	2207	VL53L0X_Error VL53L0X::VL53L0X_check_and_load_interrupt_settings(uint8_t start_not_stopflag)
nikapov	0:a1a69d32f310	2208	{
nikapov	0:a1a69d32f310	2209	uint8_t interrupt_config;
nikapov	0:a1a69d32f310	2210	FixPoint1616_t threshold_low;
nikapov	0:a1a69d32f310	2211	FixPoint1616_t threshold_high;
nikapov	0:a1a69d32f310	2212	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2213
sepp_nepp	7:41cbc431e1f4	2214	interrupt_config = _device->DeviceSpecificParameters.Pin0GpioFunctionality;
nikapov	0:a1a69d32f310	2215
nikapov	0:a1a69d32f310	2216	if ((interrupt_config ==
nikapov	0:a1a69d32f310	2217	VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW) \|\|
nikapov	0:a1a69d32f310	2218	(interrupt_config ==
nikapov	0:a1a69d32f310	2219	VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH) \|\|
nikapov	0:a1a69d32f310	2220	(interrupt_config ==
nikapov	0:a1a69d32f310	2221	VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT)) {
nikapov	0:a1a69d32f310	2222
sepp_nepp	7:41cbc431e1f4	2223	status = VL53L0X_get_interrupt_thresholds(VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
sepp_nepp	7:41cbc431e1f4	2224	&threshold_low,&threshold_high);
nikapov	0:a1a69d32f310	2225
nikapov	0:a1a69d32f310	2226	if (((threshold_low > 255 * 65536) \|\|
nikapov	0:a1a69d32f310	2227	(threshold_high > 255 * 65536)) &&
nikapov	0:a1a69d32f310	2228	(status == VL53L0X_ERROR_NONE)) {
nikapov	0:a1a69d32f310	2229
nikapov	0:a1a69d32f310	2230	if (start_not_stopflag != 0) {
sepp_nepp	7:41cbc431e1f4	2231	status = VL53L0X_load_tuning_settings(InterruptThresholdSettings);
nikapov	0:a1a69d32f310	2232	} else {
sepp_nepp	7:41cbc431e1f4	2233	status \|= VL53L0X_write_byte(0xFF,0x04);
sepp_nepp	7:41cbc431e1f4	2234	status \|= VL53L0X_write_byte(0x70,0x00);
sepp_nepp	7:41cbc431e1f4	2235	status \|= VL53L0X_write_byte(0xFF,0x00);
sepp_nepp	7:41cbc431e1f4	2236	status \|= VL53L0X_write_byte(0x80,0x00);
nikapov	0:a1a69d32f310	2237	}
nikapov	0:a1a69d32f310	2238
nikapov	0:a1a69d32f310	2239	}
nikapov	0:a1a69d32f310	2240
nikapov	0:a1a69d32f310	2241
nikapov	0:a1a69d32f310	2242	}
nikapov	0:a1a69d32f310	2243
nikapov	0:a1a69d32f310	2244	return status;
nikapov	0:a1a69d32f310	2245
nikapov	0:a1a69d32f310	2246	}
nikapov	0:a1a69d32f310	2247
sepp_nepp	7:41cbc431e1f4	2248	VL53L0X_Error VL53L0X::VL53L0X_start_measurement()
nikapov	0:a1a69d32f310	2249	{
nikapov	0:a1a69d32f310	2250	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2251	VL53L0X_DeviceModes device_mode;
nikapov	0:a1a69d32f310	2252	uint8_t byte;
nikapov	0:a1a69d32f310	2253	uint8_t start_stop_byte = VL53L0X_REG_SYSRANGE_MODE_START_STOP;
nikapov	0:a1a69d32f310	2254	uint32_t loop_nb;
sepp_nepp	5:b95f6951f7d5	2255
nikapov	0:a1a69d32f310	2256
nikapov	0:a1a69d32f310	2257	/* Get Current DeviceMode */
sepp_nepp	7:41cbc431e1f4	2258	VL53L0X_get_device_mode(&device_mode);
sepp_nepp	7:41cbc431e1f4	2259
sepp_nepp	7:41cbc431e1f4	2260	status = VL53L0X_write_byte(0x80,0x01);
sepp_nepp	7:41cbc431e1f4	2261	status = VL53L0X_write_byte(0xFF,0x01);
sepp_nepp	7:41cbc431e1f4	2262	status = VL53L0X_write_byte(0x00,0x00);
sepp_nepp	7:41cbc431e1f4	2263	status = VL53L0X_write_byte(0x91,_device-> StopVariable);
sepp_nepp	7:41cbc431e1f4	2264	status = VL53L0X_write_byte(0x00,0x01);
sepp_nepp	7:41cbc431e1f4	2265	status = VL53L0X_write_byte(0xFF,0x00);
sepp_nepp	7:41cbc431e1f4	2266	status = VL53L0X_write_byte(0x80,0x00);
nikapov	0:a1a69d32f310	2267
nikapov	0:a1a69d32f310	2268	switch (device_mode) {
nikapov	0:a1a69d32f310	2269	case VL53L0X_DEVICEMODE_SINGLE_RANGING:
sepp_nepp	7:41cbc431e1f4	2270	status = VL53L0X_write_byte(VL53L0X_REG_SYSRANGE_START,0x01);
nikapov	0:a1a69d32f310	2271
nikapov	0:a1a69d32f310	2272	byte = start_stop_byte;
nikapov	0:a1a69d32f310	2273	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	2274	/* Wait until start bit has been cleared */
nikapov	0:a1a69d32f310	2275	loop_nb = 0;
nikapov	0:a1a69d32f310	2276	do {
nikapov	0:a1a69d32f310	2277	if (loop_nb > 0)
sepp_nepp	7:41cbc431e1f4	2278	status = VL53L0X_read_byte(VL53L0X_REG_SYSRANGE_START,&byte);
nikapov	0:a1a69d32f310	2279	loop_nb = loop_nb + 1;
nikapov	0:a1a69d32f310	2280	} while (((byte & start_stop_byte) == start_stop_byte)
nikapov	0:a1a69d32f310	2281	&& (status == VL53L0X_ERROR_NONE)
nikapov	0:a1a69d32f310	2282	&& (loop_nb < VL53L0X_DEFAULT_MAX_LOOP));
nikapov	0:a1a69d32f310	2283
Davidroid	3:e9269ff624ed	2284	if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
nikapov	0:a1a69d32f310	2285	status = VL53L0X_ERROR_TIME_OUT;
Davidroid	3:e9269ff624ed	2286	}
nikapov	0:a1a69d32f310	2287
nikapov	0:a1a69d32f310	2288	}
nikapov	0:a1a69d32f310	2289
nikapov	0:a1a69d32f310	2290	break;
nikapov	0:a1a69d32f310	2291	case VL53L0X_DEVICEMODE_CONTINUOUS_RANGING:
nikapov	0:a1a69d32f310	2292	/* Back-to-back mode */
nikapov	0:a1a69d32f310	2293
nikapov	0:a1a69d32f310	2294	/* Check if need to apply interrupt settings */
Davidroid	3:e9269ff624ed	2295	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	2296	status = VL53L0X_check_and_load_interrupt_settings(1);
Davidroid	3:e9269ff624ed	2297	}
nikapov	0:a1a69d32f310	2298
sepp_nepp	7:41cbc431e1f4	2299	status = VL53L0X_write_byte(VL53L0X_REG_SYSRANGE_START,
nikapov	0:a1a69d32f310	2300	VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK);
nikapov	0:a1a69d32f310	2301	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	2302	/* Set PAL State to Running */
sepp_nepp	7:41cbc431e1f4	2303	_device->PalState = VL53L0X_STATE_RUNNING;
nikapov	0:a1a69d32f310	2304	}
nikapov	0:a1a69d32f310	2305	break;
nikapov	0:a1a69d32f310	2306	case VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING:
nikapov	0:a1a69d32f310	2307	/* Continuous mode */
nikapov	0:a1a69d32f310	2308	/* Check if need to apply interrupt settings */
Davidroid	3:e9269ff624ed	2309	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	2310	status = VL53L0X_check_and_load_interrupt_settings(1);
Davidroid	3:e9269ff624ed	2311	}
nikapov	0:a1a69d32f310	2312
sepp_nepp	7:41cbc431e1f4	2313	status = VL53L0X_write_byte(VL53L0X_REG_SYSRANGE_START,
nikapov	0:a1a69d32f310	2314	VL53L0X_REG_SYSRANGE_MODE_TIMED);
nikapov	0:a1a69d32f310	2315
nikapov	0:a1a69d32f310	2316	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	2317	/* Set PAL State to Running */
sepp_nepp	7:41cbc431e1f4	2318	_device->PalState = VL53L0X_STATE_RUNNING;
nikapov	0:a1a69d32f310	2319	}
nikapov	0:a1a69d32f310	2320	break;
nikapov	0:a1a69d32f310	2321	default:
nikapov	0:a1a69d32f310	2322	/* Selected mode not supported */
nikapov	0:a1a69d32f310	2323	status = VL53L0X_ERROR_MODE_NOT_SUPPORTED;
nikapov	0:a1a69d32f310	2324	}
nikapov	0:a1a69d32f310	2325
nikapov	0:a1a69d32f310	2326
sepp_nepp	5:b95f6951f7d5	2327
nikapov	0:a1a69d32f310	2328	return status;
nikapov	0:a1a69d32f310	2329	}
nikapov	0:a1a69d32f310	2330
nikapov	0:a1a69d32f310	2331	/* Group PAL Measurement Functions */
sepp_nepp	7:41cbc431e1f4	2332	VL53L0X_Error VL53L0X::VL53L0X_perform_single_measurement()
nikapov	0:a1a69d32f310	2333	{
nikapov	0:a1a69d32f310	2334	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2335	VL53L0X_DeviceModes device_mode;
nikapov	0:a1a69d32f310	2336
sepp_nepp	5:b95f6951f7d5	2337
nikapov	0:a1a69d32f310	2338
nikapov	0:a1a69d32f310	2339	/* Get Current DeviceMode */
sepp_nepp	7:41cbc431e1f4	2340	status = VL53L0X_get_device_mode(&device_mode);
nikapov	0:a1a69d32f310	2341
nikapov	0:a1a69d32f310	2342	/* Start immediately to run a single ranging measurement in case of
nikapov	0:a1a69d32f310	2343	* single ranging or single histogram */
nikapov	0:a1a69d32f310	2344	if (status == VL53L0X_ERROR_NONE
nikapov	0:a1a69d32f310	2345	&& device_mode == VL53L0X_DEVICEMODE_SINGLE_RANGING) {
sepp_nepp	7:41cbc431e1f4	2346	status = VL53L0X_start_measurement();
nikapov	0:a1a69d32f310	2347	}
nikapov	0:a1a69d32f310	2348
nikapov	0:a1a69d32f310	2349
nikapov	0:a1a69d32f310	2350	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	2351	status = VL53L0X_measurement_poll_for_completion();
nikapov	0:a1a69d32f310	2352	}
nikapov	0:a1a69d32f310	2353
nikapov	0:a1a69d32f310	2354
nikapov	0:a1a69d32f310	2355	/* Change PAL State in case of single ranging or single histogram */
nikapov	0:a1a69d32f310	2356	if (status == VL53L0X_ERROR_NONE
Davidroid	3:e9269ff624ed	2357	&& device_mode == VL53L0X_DEVICEMODE_SINGLE_RANGING) {
sepp_nepp	7:41cbc431e1f4	2358	_device->PalState = VL53L0X_STATE_IDLE;
Davidroid	3:e9269ff624ed	2359	}
nikapov	0:a1a69d32f310	2360
nikapov	0:a1a69d32f310	2361
sepp_nepp	5:b95f6951f7d5	2362
nikapov	0:a1a69d32f310	2363	return status;
nikapov	0:a1a69d32f310	2364	}
nikapov	0:a1a69d32f310	2365
sepp_nepp	7:41cbc431e1f4	2366	VL53L0X_Error VL53L0X::VL53L0X_get_x_talk_compensation_enable(uint8_t *p_x_talk_compensation_enable)
nikapov	0:a1a69d32f310	2367	{
nikapov	0:a1a69d32f310	2368	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2369	uint8_t temp8;
sepp_nepp	5:b95f6951f7d5	2370
nikapov	0:a1a69d32f310	2371
sepp_nepp	7:41cbc431e1f4	2372	temp8 = _device->CurrentParameters.XTalkCompensationEnable;
nikapov	0:a1a69d32f310	2373	*p_x_talk_compensation_enable = temp8;
nikapov	0:a1a69d32f310	2374
sepp_nepp	5:b95f6951f7d5	2375
nikapov	0:a1a69d32f310	2376	return status;
nikapov	0:a1a69d32f310	2377	}
nikapov	0:a1a69d32f310	2378
sepp_nepp	7:41cbc431e1f4	2379	VL53L0X_Error VL53L0X::VL53L0X_get_total_xtalk_rate(VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
nikapov	0:a1a69d32f310	2380	FixPoint1616_t *p_total_xtalk_rate_mcps)
nikapov	0:a1a69d32f310	2381	{
nikapov	0:a1a69d32f310	2382	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2383
nikapov	0:a1a69d32f310	2384	uint8_t xtalk_comp_enable;
nikapov	0:a1a69d32f310	2385	FixPoint1616_t total_xtalk_mega_cps;
nikapov	0:a1a69d32f310	2386	FixPoint1616_t xtalk_per_spad_mega_cps;
nikapov	0:a1a69d32f310	2387
nikapov	0:a1a69d32f310	2388	*p_total_xtalk_rate_mcps = 0;
nikapov	0:a1a69d32f310	2389
sepp_nepp	7:41cbc431e1f4	2390	status = VL53L0X_get_x_talk_compensation_enable(&xtalk_comp_enable);
nikapov	0:a1a69d32f310	2391	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	2392
nikapov	0:a1a69d32f310	2393	if (xtalk_comp_enable) {
nikapov	0:a1a69d32f310	2394
sepp_nepp	7:41cbc431e1f4	2395	xtalk_per_spad_mega_cps = _device->CurrentParameters.XTalkCompensationRateMegaCps;
nikapov	0:a1a69d32f310	2396
nikapov	0:a1a69d32f310	2397	/* FixPoint1616 * FixPoint 8:8 = FixPoint0824 */
nikapov	0:a1a69d32f310	2398	total_xtalk_mega_cps =
nikapov	0:a1a69d32f310	2399	p_ranging_measurement_data->EffectiveSpadRtnCount *
nikapov	0:a1a69d32f310	2400	xtalk_per_spad_mega_cps;
nikapov	0:a1a69d32f310	2401
nikapov	0:a1a69d32f310	2402	/* FixPoint0824 >> 8 = FixPoint1616 */
nikapov	0:a1a69d32f310	2403	*p_total_xtalk_rate_mcps =
nikapov	0:a1a69d32f310	2404	(total_xtalk_mega_cps + 0x80) >> 8;
nikapov	0:a1a69d32f310	2405	}
nikapov	0:a1a69d32f310	2406	}
nikapov	0:a1a69d32f310	2407
nikapov	0:a1a69d32f310	2408	return status;
nikapov	0:a1a69d32f310	2409	}
nikapov	0:a1a69d32f310	2410
sepp_nepp	7:41cbc431e1f4	2411	VL53L0X_Error VL53L0X::VL53L0X_get_total_signal_rate(VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
nikapov	0:a1a69d32f310	2412	FixPoint1616_t *p_total_signal_rate_mcps)
nikapov	0:a1a69d32f310	2413	{
nikapov	0:a1a69d32f310	2414	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2415	FixPoint1616_t total_xtalk_mega_cps;
nikapov	0:a1a69d32f310	2416
sepp_nepp	5:b95f6951f7d5	2417
nikapov	0:a1a69d32f310	2418
nikapov	0:a1a69d32f310	2419	*p_total_signal_rate_mcps =
nikapov	0:a1a69d32f310	2420	p_ranging_measurement_data->SignalRateRtnMegaCps;
nikapov	0:a1a69d32f310	2421
sepp_nepp	7:41cbc431e1f4	2422	status = VL53L0X_get_total_xtalk_rate(p_ranging_measurement_data,&total_xtalk_mega_cps);
nikapov	0:a1a69d32f310	2423
nikapov	0:a1a69d32f310	2424	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	2425	*p_total_signal_rate_mcps += total_xtalk_mega_cps;
nikapov	0:a1a69d32f310	2426	}
nikapov	0:a1a69d32f310	2427
nikapov	0:a1a69d32f310	2428	return status;
nikapov	0:a1a69d32f310	2429	}
nikapov	0:a1a69d32f310	2430
nikapov	0:a1a69d32f310	2431	/* To convert ms into register value */
sepp_nepp	7:41cbc431e1f4	2432	uint32_t VL53L0X::VL53L0X_calc_timeout_mclks(uint32_t timeout_period_us,
nikapov	0:a1a69d32f310	2433	uint8_t vcsel_period_pclks)
nikapov	0:a1a69d32f310	2434	{
nikapov	0:a1a69d32f310	2435	uint32_t macro_period_ps;
nikapov	0:a1a69d32f310	2436	uint32_t macro_period_ns;
nikapov	0:a1a69d32f310	2437	uint32_t timeout_period_mclks = 0;
nikapov	0:a1a69d32f310	2438
sepp_nepp	7:41cbc431e1f4	2439	macro_period_ps = VL53L0X_calc_macro_period_ps(vcsel_period_pclks);
nikapov	0:a1a69d32f310	2440	macro_period_ns = (macro_period_ps + 500) / 1000;
nikapov	0:a1a69d32f310	2441
nikapov	0:a1a69d32f310	2442	timeout_period_mclks =
nikapov	0:a1a69d32f310	2443	(uint32_t)(((timeout_period_us * 1000)
nikapov	0:a1a69d32f310	2444	+ (macro_period_ns / 2)) / macro_period_ns);
nikapov	0:a1a69d32f310	2445
nikapov	0:a1a69d32f310	2446	return timeout_period_mclks;
nikapov	0:a1a69d32f310	2447	}
nikapov	0:a1a69d32f310	2448
nikapov	0:a1a69d32f310	2449	uint32_t VL53L0X::VL53L0X_isqrt(uint32_t num)
nikapov	0:a1a69d32f310	2450	{
nikapov	0:a1a69d32f310	2451	/*
nikapov	0:a1a69d32f310	2452	* Implements an integer square root
nikapov	0:a1a69d32f310	2453	*
nikapov	0:a1a69d32f310	2454	* From: http://en.wikipedia.org/wiki/Methods_of_computing_square_roots
nikapov	0:a1a69d32f310	2455	*/
nikapov	0:a1a69d32f310	2456
nikapov	0:a1a69d32f310	2457	uint32_t res = 0;
nikapov	0:a1a69d32f310	2458	uint32_t bit = 1 << 30;
nikapov	0:a1a69d32f310	2459	/* The second-to-top bit is set:
sepp_nepp	7:41cbc431e1f4	2460	* 1 << 14 for 16-bits,1 << 30 for 32 bits */
nikapov	0:a1a69d32f310	2461
nikapov	0:a1a69d32f310	2462	/* "bit" starts at the highest power of four <= the argument. */
nikapov	0:a1a69d32f310	2463	while (bit > num) {
nikapov	0:a1a69d32f310	2464	bit >>= 2;
nikapov	0:a1a69d32f310	2465	}
nikapov	0:a1a69d32f310	2466
nikapov	0:a1a69d32f310	2467
nikapov	0:a1a69d32f310	2468	while (bit != 0) {
nikapov	0:a1a69d32f310	2469	if (num >= res + bit) {
nikapov	0:a1a69d32f310	2470	num -= res + bit;
nikapov	0:a1a69d32f310	2471	res = (res >> 1) + bit;
Davidroid	3:e9269ff624ed	2472	} else {
nikapov	0:a1a69d32f310	2473	res >>= 1;
Davidroid	3:e9269ff624ed	2474	}
nikapov	0:a1a69d32f310	2475
nikapov	0:a1a69d32f310	2476	bit >>= 2;
nikapov	0:a1a69d32f310	2477	}
nikapov	0:a1a69d32f310	2478
nikapov	0:a1a69d32f310	2479	return res;
nikapov	0:a1a69d32f310	2480	}
nikapov	0:a1a69d32f310	2481
sepp_nepp	7:41cbc431e1f4	2482	VL53L0X_Error VL53L0X::VL53L0X_calc_dmax(FixPoint1616_t total_signal_rate_mcps,
nikapov	0:a1a69d32f310	2483	FixPoint1616_t total_corr_signal_rate_mcps,
nikapov	0:a1a69d32f310	2484	FixPoint1616_t pw_mult,
nikapov	0:a1a69d32f310	2485	uint32_t sigma_estimate_p1,
nikapov	0:a1a69d32f310	2486	FixPoint1616_t sigma_estimate_p2,
nikapov	0:a1a69d32f310	2487	uint32_t peak_vcsel_duration_us,
nikapov	0:a1a69d32f310	2488	uint32_t *pd_max_mm)
nikapov	0:a1a69d32f310	2489	{
nikapov	0:a1a69d32f310	2490	const uint32_t c_sigma_limit = 18;
nikapov	0:a1a69d32f310	2491	const FixPoint1616_t c_signal_limit = 0x4000; /* 0.25 */
nikapov	0:a1a69d32f310	2492	const FixPoint1616_t c_sigma_est_ref = 0x00000042; /* 0.001 */
nikapov	0:a1a69d32f310	2493	const uint32_t c_amb_eff_width_sigma_est_ns = 6;
nikapov	0:a1a69d32f310	2494	const uint32_t c_amb_eff_width_d_max_ns = 7;
nikapov	0:a1a69d32f310	2495	uint32_t dmax_cal_range_mm;
nikapov	0:a1a69d32f310	2496	FixPoint1616_t dmax_cal_signal_rate_rtn_mcps;
nikapov	0:a1a69d32f310	2497	FixPoint1616_t min_signal_needed;
nikapov	0:a1a69d32f310	2498	FixPoint1616_t min_signal_needed_p1;
nikapov	0:a1a69d32f310	2499	FixPoint1616_t min_signal_needed_p2;
nikapov	0:a1a69d32f310	2500	FixPoint1616_t min_signal_needed_p3;
nikapov	0:a1a69d32f310	2501	FixPoint1616_t min_signal_needed_p4;
nikapov	0:a1a69d32f310	2502	FixPoint1616_t sigma_limit_tmp;
nikapov	0:a1a69d32f310	2503	FixPoint1616_t sigma_est_sq_tmp;
nikapov	0:a1a69d32f310	2504	FixPoint1616_t signal_limit_tmp;
nikapov	0:a1a69d32f310	2505	FixPoint1616_t signal_at0_mm;
nikapov	0:a1a69d32f310	2506	FixPoint1616_t dmax_dark;
nikapov	0:a1a69d32f310	2507	FixPoint1616_t dmax_ambient;
nikapov	0:a1a69d32f310	2508	FixPoint1616_t dmax_dark_tmp;
nikapov	0:a1a69d32f310	2509	FixPoint1616_t sigma_est_p2_tmp;
nikapov	0:a1a69d32f310	2510	uint32_t signal_rate_temp_mcps;
nikapov	0:a1a69d32f310	2511
nikapov	0:a1a69d32f310	2512	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2513
sepp_nepp	5:b95f6951f7d5	2514
nikapov	0:a1a69d32f310	2515
nikapov	0:a1a69d32f310	2516	dmax_cal_range_mm =
sepp_nepp	7:41cbc431e1f4	2517	_device-> DmaxCalRangeMilliMeter;
nikapov	0:a1a69d32f310	2518
nikapov	0:a1a69d32f310	2519	dmax_cal_signal_rate_rtn_mcps =
sepp_nepp	7:41cbc431e1f4	2520	_device-> DmaxCalSignalRateRtnMegaCps;
nikapov	0:a1a69d32f310	2521
nikapov	0:a1a69d32f310	2522	/* uint32 * FixPoint1616 = FixPoint1616 */
nikapov	0:a1a69d32f310	2523	signal_at0_mm = dmax_cal_range_mm * dmax_cal_signal_rate_rtn_mcps;
nikapov	0:a1a69d32f310	2524
nikapov	0:a1a69d32f310	2525	/* FixPoint1616 >> 8 = FixPoint2408 */
nikapov	0:a1a69d32f310	2526	signal_at0_mm = (signal_at0_mm + 0x80) >> 8;
nikapov	0:a1a69d32f310	2527	signal_at0_mm *= dmax_cal_range_mm;
nikapov	0:a1a69d32f310	2528
nikapov	0:a1a69d32f310	2529	min_signal_needed_p1 = 0;
nikapov	0:a1a69d32f310	2530	if (total_corr_signal_rate_mcps > 0) {
nikapov	0:a1a69d32f310	2531
nikapov	0:a1a69d32f310	2532	/* Shift by 10 bits to increase resolution prior to the
nikapov	0:a1a69d32f310	2533	* division */
nikapov	0:a1a69d32f310	2534	signal_rate_temp_mcps = total_signal_rate_mcps << 10;
nikapov	0:a1a69d32f310	2535
nikapov	0:a1a69d32f310	2536	/* Add rounding value prior to division */
nikapov	0:a1a69d32f310	2537	min_signal_needed_p1 = signal_rate_temp_mcps +
nikapov	0:a1a69d32f310	2538	(total_corr_signal_rate_mcps / 2);
nikapov	0:a1a69d32f310	2539
nikapov	0:a1a69d32f310	2540	/* FixPoint0626/FixPoint1616 = FixPoint2210 */
nikapov	0:a1a69d32f310	2541	min_signal_needed_p1 /= total_corr_signal_rate_mcps;
nikapov	0:a1a69d32f310	2542
nikapov	0:a1a69d32f310	2543	/* Apply a factored version of the speed of light.
nikapov	0:a1a69d32f310	2544	Correction to be applied at the end */
nikapov	0:a1a69d32f310	2545	min_signal_needed_p1 *= 3;
nikapov	0:a1a69d32f310	2546
nikapov	0:a1a69d32f310	2547	/* FixPoint2210 * FixPoint2210 = FixPoint1220 */
nikapov	0:a1a69d32f310	2548	min_signal_needed_p1 *= min_signal_needed_p1;
nikapov	0:a1a69d32f310	2549
nikapov	0:a1a69d32f310	2550	/* FixPoint1220 >> 16 = FixPoint2804 */
nikapov	0:a1a69d32f310	2551	min_signal_needed_p1 = (min_signal_needed_p1 + 0x8000) >> 16;
nikapov	0:a1a69d32f310	2552	}
nikapov	0:a1a69d32f310	2553
nikapov	0:a1a69d32f310	2554	min_signal_needed_p2 = pw_mult * sigma_estimate_p1;
nikapov	0:a1a69d32f310	2555
nikapov	0:a1a69d32f310	2556	/* FixPoint1616 >> 16 = uint32 */
nikapov	0:a1a69d32f310	2557	min_signal_needed_p2 = (min_signal_needed_p2 + 0x8000) >> 16;
nikapov	0:a1a69d32f310	2558
nikapov	0:a1a69d32f310	2559	/* uint32 * uint32 = uint32 */
nikapov	0:a1a69d32f310	2560	min_signal_needed_p2 *= min_signal_needed_p2;
nikapov	0:a1a69d32f310	2561
nikapov	0:a1a69d32f310	2562	/* Check sigmaEstimateP2
nikapov	0:a1a69d32f310	2563	* If this value is too high there is not enough signal rate
nikapov	0:a1a69d32f310	2564	* to calculate dmax value so set a suitable value to ensure
nikapov	0:a1a69d32f310	2565	* a very small dmax.
nikapov	0:a1a69d32f310	2566	*/
nikapov	0:a1a69d32f310	2567	sigma_est_p2_tmp = (sigma_estimate_p2 + 0x8000) >> 16;
nikapov	0:a1a69d32f310	2568	sigma_est_p2_tmp = (sigma_est_p2_tmp + c_amb_eff_width_sigma_est_ns / 2) /
nikapov	0:a1a69d32f310	2569	c_amb_eff_width_sigma_est_ns;
nikapov	0:a1a69d32f310	2570	sigma_est_p2_tmp *= c_amb_eff_width_d_max_ns;
nikapov	0:a1a69d32f310	2571
nikapov	0:a1a69d32f310	2572	if (sigma_est_p2_tmp > 0xffff) {
nikapov	0:a1a69d32f310	2573	min_signal_needed_p3 = 0xfff00000;
nikapov	0:a1a69d32f310	2574	} else {
nikapov	0:a1a69d32f310	2575
sepp_nepp	7:41cbc431e1f4	2576	/* DMAX uses a different ambient width from sigma,so apply
nikapov	0:a1a69d32f310	2577	* correction.
nikapov	0:a1a69d32f310	2578	* Perform division before multiplication to prevent overflow.
nikapov	0:a1a69d32f310	2579	*/
nikapov	0:a1a69d32f310	2580	sigma_estimate_p2 = (sigma_estimate_p2 + c_amb_eff_width_sigma_est_ns / 2) /
nikapov	0:a1a69d32f310	2581	c_amb_eff_width_sigma_est_ns;
nikapov	0:a1a69d32f310	2582	sigma_estimate_p2 *= c_amb_eff_width_d_max_ns;
nikapov	0:a1a69d32f310	2583
nikapov	0:a1a69d32f310	2584	/* FixPoint1616 >> 16 = uint32 */
nikapov	0:a1a69d32f310	2585	min_signal_needed_p3 = (sigma_estimate_p2 + 0x8000) >> 16;
nikapov	0:a1a69d32f310	2586
nikapov	0:a1a69d32f310	2587	min_signal_needed_p3 *= min_signal_needed_p3;
nikapov	0:a1a69d32f310	2588
nikapov	0:a1a69d32f310	2589	}
nikapov	0:a1a69d32f310	2590
nikapov	0:a1a69d32f310	2591	/* FixPoint1814 / uint32 = FixPoint1814 */
nikapov	0:a1a69d32f310	2592	sigma_limit_tmp = ((c_sigma_limit << 14) + 500) / 1000;
nikapov	0:a1a69d32f310	2593
nikapov	0:a1a69d32f310	2594	/* FixPoint1814 * FixPoint1814 = FixPoint3628 := FixPoint0428 */
nikapov	0:a1a69d32f310	2595	sigma_limit_tmp *= sigma_limit_tmp;
nikapov	0:a1a69d32f310	2596
nikapov	0:a1a69d32f310	2597	/* FixPoint1616 * FixPoint1616 = FixPoint3232 */
nikapov	0:a1a69d32f310	2598	sigma_est_sq_tmp = c_sigma_est_ref * c_sigma_est_ref;
nikapov	0:a1a69d32f310	2599
nikapov	0:a1a69d32f310	2600	/* FixPoint3232 >> 4 = FixPoint0428 */
nikapov	0:a1a69d32f310	2601	sigma_est_sq_tmp = (sigma_est_sq_tmp + 0x08) >> 4;
nikapov	0:a1a69d32f310	2602
nikapov	0:a1a69d32f310	2603	/* FixPoint0428 - FixPoint0428 = FixPoint0428 */
nikapov	0:a1a69d32f310	2604	sigma_limit_tmp -= sigma_est_sq_tmp;
nikapov	0:a1a69d32f310	2605
nikapov	0:a1a69d32f310	2606	/* uint32_t * FixPoint0428 = FixPoint0428 */
nikapov	0:a1a69d32f310	2607	min_signal_needed_p4 = 4 * 12 * sigma_limit_tmp;
nikapov	0:a1a69d32f310	2608
nikapov	0:a1a69d32f310	2609	/* FixPoint0428 >> 14 = FixPoint1814 */
nikapov	0:a1a69d32f310	2610	min_signal_needed_p4 = (min_signal_needed_p4 + 0x2000) >> 14;
nikapov	0:a1a69d32f310	2611
nikapov	0:a1a69d32f310	2612	/* uint32 + uint32 = uint32 */
nikapov	0:a1a69d32f310	2613	min_signal_needed = (min_signal_needed_p2 + min_signal_needed_p3);
nikapov	0:a1a69d32f310	2614
nikapov	0:a1a69d32f310	2615	/* uint32 / uint32 = uint32 */
nikapov	0:a1a69d32f310	2616	min_signal_needed += (peak_vcsel_duration_us / 2);
nikapov	0:a1a69d32f310	2617	min_signal_needed /= peak_vcsel_duration_us;
nikapov	0:a1a69d32f310	2618
nikapov	0:a1a69d32f310	2619	/* uint32 << 14 = FixPoint1814 */
nikapov	0:a1a69d32f310	2620	min_signal_needed <<= 14;
nikapov	0:a1a69d32f310	2621
nikapov	0:a1a69d32f310	2622	/* FixPoint1814 / FixPoint1814 = uint32 */
nikapov	0:a1a69d32f310	2623	min_signal_needed += (min_signal_needed_p4 / 2);
nikapov	0:a1a69d32f310	2624	min_signal_needed /= min_signal_needed_p4;
nikapov	0:a1a69d32f310	2625
nikapov	0:a1a69d32f310	2626	/* FixPoint3200 * FixPoint2804 := FixPoint2804*/
nikapov	0:a1a69d32f310	2627	min_signal_needed *= min_signal_needed_p1;
nikapov	0:a1a69d32f310	2628
nikapov	0:a1a69d32f310	2629	/* Apply correction by dividing by 1000000.
nikapov	0:a1a69d32f310	2630	* This assumes 10E16 on the numerator of the equation
nikapov	0:a1a69d32f310	2631	* and 10E-22 on the denominator.
nikapov	0:a1a69d32f310	2632	* We do this because 32bit fix point calculation can't
nikapov	0:a1a69d32f310	2633	* handle the larger and smaller elements of this equation,
nikapov	0:a1a69d32f310	2634	* i.e. speed of light and pulse widths.
nikapov	0:a1a69d32f310	2635	*/
nikapov	0:a1a69d32f310	2636	min_signal_needed = (min_signal_needed + 500) / 1000;
nikapov	0:a1a69d32f310	2637	min_signal_needed <<= 4;
nikapov	0:a1a69d32f310	2638
nikapov	0:a1a69d32f310	2639	min_signal_needed = (min_signal_needed + 500) / 1000;
nikapov	0:a1a69d32f310	2640
nikapov	0:a1a69d32f310	2641	/* FixPoint1616 >> 8 = FixPoint2408 */
nikapov	0:a1a69d32f310	2642	signal_limit_tmp = (c_signal_limit + 0x80) >> 8;
nikapov	0:a1a69d32f310	2643
nikapov	0:a1a69d32f310	2644	/* FixPoint2408/FixPoint2408 = uint32 */
nikapov	0:a1a69d32f310	2645	if (signal_limit_tmp != 0) {
nikapov	0:a1a69d32f310	2646	dmax_dark_tmp = (signal_at0_mm + (signal_limit_tmp / 2))
nikapov	0:a1a69d32f310	2647	/ signal_limit_tmp;
nikapov	0:a1a69d32f310	2648	} else {
nikapov	0:a1a69d32f310	2649	dmax_dark_tmp = 0;
nikapov	0:a1a69d32f310	2650	}
nikapov	0:a1a69d32f310	2651
nikapov	0:a1a69d32f310	2652	dmax_dark = VL53L0X_isqrt(dmax_dark_tmp);
nikapov	0:a1a69d32f310	2653
nikapov	0:a1a69d32f310	2654	/* FixPoint2408/FixPoint2408 = uint32 */
nikapov	0:a1a69d32f310	2655	if (min_signal_needed != 0) {
nikapov	0:a1a69d32f310	2656	dmax_ambient = (signal_at0_mm + min_signal_needed / 2)
nikapov	0:a1a69d32f310	2657	/ min_signal_needed;
nikapov	0:a1a69d32f310	2658	} else {
nikapov	0:a1a69d32f310	2659	dmax_ambient = 0;
nikapov	0:a1a69d32f310	2660	}
nikapov	0:a1a69d32f310	2661
nikapov	0:a1a69d32f310	2662	dmax_ambient = VL53L0X_isqrt(dmax_ambient);
nikapov	0:a1a69d32f310	2663
nikapov	0:a1a69d32f310	2664	*pd_max_mm = dmax_dark;
nikapov	0:a1a69d32f310	2665	if (dmax_dark > dmax_ambient) {
nikapov	0:a1a69d32f310	2666	*pd_max_mm = dmax_ambient;
nikapov	0:a1a69d32f310	2667	}
nikapov	0:a1a69d32f310	2668
sepp_nepp	5:b95f6951f7d5	2669
nikapov	0:a1a69d32f310	2670
nikapov	0:a1a69d32f310	2671	return status;
nikapov	0:a1a69d32f310	2672	}
nikapov	0:a1a69d32f310	2673
sepp_nepp	7:41cbc431e1f4	2674	VL53L0X_Error VL53L0X::VL53L0X_calc_sigma_estimate(VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
nikapov	0:a1a69d32f310	2675	FixPoint1616_t *p_sigma_estimate,
nikapov	0:a1a69d32f310	2676	uint32_t *p_dmax_mm)
nikapov	0:a1a69d32f310	2677	{
sepp_nepp	7:41cbc431e1f4	2678	/* Expressed in 100ths of a ns,i.e. centi-ns */
nikapov	0:a1a69d32f310	2679	const uint32_t c_pulse_effective_width_centi_ns = 800;
sepp_nepp	7:41cbc431e1f4	2680	/* Expressed in 100ths of a ns,i.e. centi-ns */
nikapov	0:a1a69d32f310	2681	const uint32_t c_ambient_effective_width_centi_ns = 600;
nikapov	0:a1a69d32f310	2682	const FixPoint1616_t c_dflt_final_range_integration_time_milli_secs = 0x00190000; /* 25ms */
nikapov	0:a1a69d32f310	2683	const uint32_t c_vcsel_pulse_width_ps = 4700; /* pico secs */
nikapov	0:a1a69d32f310	2684	const FixPoint1616_t c_sigma_est_max = 0x028F87AE;
nikapov	0:a1a69d32f310	2685	const FixPoint1616_t c_sigma_est_rtn_max = 0xF000;
nikapov	0:a1a69d32f310	2686	const FixPoint1616_t c_amb_to_signal_ratio_max = 0xF0000000 /
nikapov	0:a1a69d32f310	2687	c_ambient_effective_width_centi_ns;
nikapov	0:a1a69d32f310	2688	/* Time Of Flight per mm (6.6 pico secs) */
nikapov	0:a1a69d32f310	2689	const FixPoint1616_t c_tof_per_mm_ps = 0x0006999A;
nikapov	0:a1a69d32f310	2690	const uint32_t c_16bit_rounding_param = 0x00008000;
nikapov	0:a1a69d32f310	2691	const FixPoint1616_t c_max_x_talk_kcps = 0x00320000;
nikapov	0:a1a69d32f310	2692	const uint32_t c_pll_period_ps = 1655;
nikapov	0:a1a69d32f310	2693
nikapov	0:a1a69d32f310	2694	uint32_t vcsel_total_events_rtn;
nikapov	0:a1a69d32f310	2695	uint32_t final_range_timeout_micro_secs;
nikapov	0:a1a69d32f310	2696	uint32_t pre_range_timeout_micro_secs;
nikapov	0:a1a69d32f310	2697	uint32_t final_range_integration_time_milli_secs;
nikapov	0:a1a69d32f310	2698	FixPoint1616_t sigma_estimate_p1;
nikapov	0:a1a69d32f310	2699	FixPoint1616_t sigma_estimate_p2;
nikapov	0:a1a69d32f310	2700	FixPoint1616_t sigma_estimate_p3;
nikapov	0:a1a69d32f310	2701	FixPoint1616_t delta_t_ps;
nikapov	0:a1a69d32f310	2702	FixPoint1616_t pw_mult;
nikapov	0:a1a69d32f310	2703	FixPoint1616_t sigma_est_rtn;
nikapov	0:a1a69d32f310	2704	FixPoint1616_t sigma_estimate;
nikapov	0:a1a69d32f310	2705	FixPoint1616_t x_talk_correction;
nikapov	0:a1a69d32f310	2706	FixPoint1616_t ambient_rate_kcps;
nikapov	0:a1a69d32f310	2707	FixPoint1616_t peak_signal_rate_kcps;
nikapov	0:a1a69d32f310	2708	FixPoint1616_t x_talk_comp_rate_mcps;
nikapov	0:a1a69d32f310	2709	uint32_t x_talk_comp_rate_kcps;
nikapov	0:a1a69d32f310	2710	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2711	FixPoint1616_t diff1_mcps;
nikapov	0:a1a69d32f310	2712	FixPoint1616_t diff2_mcps;
nikapov	0:a1a69d32f310	2713	FixPoint1616_t sqr1;
nikapov	0:a1a69d32f310	2714	FixPoint1616_t sqr2;
nikapov	0:a1a69d32f310	2715	FixPoint1616_t sqr_sum;
nikapov	0:a1a69d32f310	2716	FixPoint1616_t sqrt_result_centi_ns;
nikapov	0:a1a69d32f310	2717	FixPoint1616_t sqrt_result;
nikapov	0:a1a69d32f310	2718	FixPoint1616_t total_signal_rate_mcps;
nikapov	0:a1a69d32f310	2719	FixPoint1616_t corrected_signal_rate_mcps;
nikapov	0:a1a69d32f310	2720	FixPoint1616_t sigma_est_ref;
nikapov	0:a1a69d32f310	2721	uint32_t vcsel_width;
nikapov	0:a1a69d32f310	2722	uint32_t final_range_macro_pclks;
nikapov	0:a1a69d32f310	2723	uint32_t pre_range_macro_pclks;
nikapov	0:a1a69d32f310	2724	uint32_t peak_vcsel_duration_us;
nikapov	0:a1a69d32f310	2725	uint8_t final_range_vcsel_pclks;
nikapov	0:a1a69d32f310	2726	uint8_t pre_range_vcsel_pclks;
nikapov	0:a1a69d32f310	2727	/*! \addtogroup calc_sigma_estimate
nikapov	0:a1a69d32f310	2728	* @{
nikapov	0:a1a69d32f310	2729	*
nikapov	0:a1a69d32f310	2730	* Estimates the range sigma
nikapov	0:a1a69d32f310	2731	*/
nikapov	0:a1a69d32f310	2732
sepp_nepp	5:b95f6951f7d5	2733
nikapov	0:a1a69d32f310	2734
sepp_nepp	7:41cbc431e1f4	2735	x_talk_comp_rate_mcps = _device->CurrentParameters.XTalkCompensationRateMegaCps;
nikapov	0:a1a69d32f310	2736
nikapov	0:a1a69d32f310	2737	/*
nikapov	0:a1a69d32f310	2738	* We work in kcps rather than mcps as this helps keep within the
nikapov	0:a1a69d32f310	2739	* confines of the 32 Fix1616 type.
nikapov	0:a1a69d32f310	2740	*/
nikapov	0:a1a69d32f310	2741
nikapov	0:a1a69d32f310	2742	ambient_rate_kcps =
nikapov	0:a1a69d32f310	2743	(p_ranging_measurement_data->AmbientRateRtnMegaCps * 1000) >> 16;
nikapov	0:a1a69d32f310	2744
nikapov	0:a1a69d32f310	2745	corrected_signal_rate_mcps =
nikapov	0:a1a69d32f310	2746	p_ranging_measurement_data->SignalRateRtnMegaCps;
nikapov	0:a1a69d32f310	2747
nikapov	0:a1a69d32f310	2748
sepp_nepp	7:41cbc431e1f4	2749	status = VL53L0X_get_total_signal_rate(p_ranging_measurement_data,&total_signal_rate_mcps);
sepp_nepp	7:41cbc431e1f4	2750	status = VL53L0X_get_total_xtalk_rate(p_ranging_measurement_data,&x_talk_comp_rate_mcps);
nikapov	0:a1a69d32f310	2751
nikapov	0:a1a69d32f310	2752
nikapov	0:a1a69d32f310	2753	/* Signal rate measurement provided by device is the
sepp_nepp	7:41cbc431e1f4	2754	* peak signal rate,not average.
nikapov	0:a1a69d32f310	2755	*/
nikapov	0:a1a69d32f310	2756	peak_signal_rate_kcps = (total_signal_rate_mcps * 1000);
nikapov	0:a1a69d32f310	2757	peak_signal_rate_kcps = (peak_signal_rate_kcps + 0x8000) >> 16;
nikapov	0:a1a69d32f310	2758
nikapov	0:a1a69d32f310	2759	x_talk_comp_rate_kcps = x_talk_comp_rate_mcps * 1000;
nikapov	0:a1a69d32f310	2760
nikapov	0:a1a69d32f310	2761	if (x_talk_comp_rate_kcps > c_max_x_talk_kcps) {
nikapov	0:a1a69d32f310	2762	x_talk_comp_rate_kcps = c_max_x_talk_kcps;
nikapov	0:a1a69d32f310	2763	}
nikapov	0:a1a69d32f310	2764
nikapov	0:a1a69d32f310	2765	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	2766
nikapov	0:a1a69d32f310	2767	/* Calculate final range macro periods */
sepp_nepp	7:41cbc431e1f4	2768	final_range_timeout_micro_secs = _device->DeviceSpecificParameters.FinalRangeTimeoutMicroSecs;
sepp_nepp	7:41cbc431e1f4	2769
sepp_nepp	7:41cbc431e1f4	2770	final_range_vcsel_pclks = _device->DeviceSpecificParameters.FinalRangeVcselPulsePeriod;
sepp_nepp	7:41cbc431e1f4	2771
sepp_nepp	7:41cbc431e1f4	2772	final_range_macro_pclks = VL53L0X_calc_timeout_mclks(final_range_timeout_micro_secs,final_range_vcsel_pclks);
nikapov	0:a1a69d32f310	2773
nikapov	0:a1a69d32f310	2774	/* Calculate pre-range macro periods */
sepp_nepp	7:41cbc431e1f4	2775	pre_range_timeout_micro_secs = _device->DeviceSpecificParameters.PreRangeTimeoutMicroSecs;
sepp_nepp	7:41cbc431e1f4	2776
sepp_nepp	7:41cbc431e1f4	2777	pre_range_vcsel_pclks = _device->DeviceSpecificParameters.PreRangeVcselPulsePeriod;
sepp_nepp	7:41cbc431e1f4	2778
sepp_nepp	7:41cbc431e1f4	2779	pre_range_macro_pclks = VL53L0X_calc_timeout_mclks(pre_range_timeout_micro_secs,pre_range_vcsel_pclks);
nikapov	0:a1a69d32f310	2780
nikapov	0:a1a69d32f310	2781	vcsel_width = 3;
nikapov	0:a1a69d32f310	2782	if (final_range_vcsel_pclks == 8) {
nikapov	0:a1a69d32f310	2783	vcsel_width = 2;
nikapov	0:a1a69d32f310	2784	}
nikapov	0:a1a69d32f310	2785
nikapov	0:a1a69d32f310	2786
nikapov	0:a1a69d32f310	2787	peak_vcsel_duration_us = vcsel_width * 2048 *
nikapov	0:a1a69d32f310	2788	(pre_range_macro_pclks + final_range_macro_pclks);
nikapov	0:a1a69d32f310	2789	peak_vcsel_duration_us = (peak_vcsel_duration_us + 500) / 1000;
nikapov	0:a1a69d32f310	2790	peak_vcsel_duration_us *= c_pll_period_ps;
nikapov	0:a1a69d32f310	2791	peak_vcsel_duration_us = (peak_vcsel_duration_us + 500) / 1000;
nikapov	0:a1a69d32f310	2792
nikapov	0:a1a69d32f310	2793	/* Fix1616 >> 8 = Fix2408 */
nikapov	0:a1a69d32f310	2794	total_signal_rate_mcps = (total_signal_rate_mcps + 0x80) >> 8;
nikapov	0:a1a69d32f310	2795
nikapov	0:a1a69d32f310	2796	/* Fix2408 * uint32 = Fix2408 */
nikapov	0:a1a69d32f310	2797	vcsel_total_events_rtn = total_signal_rate_mcps *
nikapov	0:a1a69d32f310	2798	peak_vcsel_duration_us;
nikapov	0:a1a69d32f310	2799
nikapov	0:a1a69d32f310	2800	/* Fix2408 >> 8 = uint32 */
nikapov	0:a1a69d32f310	2801	vcsel_total_events_rtn = (vcsel_total_events_rtn + 0x80) >> 8;
nikapov	0:a1a69d32f310	2802
nikapov	0:a1a69d32f310	2803	/* Fix2408 << 8 = Fix1616 = */
nikapov	0:a1a69d32f310	2804	total_signal_rate_mcps <<= 8;
nikapov	0:a1a69d32f310	2805	}
nikapov	0:a1a69d32f310	2806
nikapov	0:a1a69d32f310	2807	if (status != VL53L0X_ERROR_NONE) {
sepp_nepp	5:b95f6951f7d5	2808
nikapov	0:a1a69d32f310	2809	return status;
nikapov	0:a1a69d32f310	2810	}
nikapov	0:a1a69d32f310	2811
nikapov	0:a1a69d32f310	2812	if (peak_signal_rate_kcps == 0) {
nikapov	0:a1a69d32f310	2813	*p_sigma_estimate = c_sigma_est_max;
sepp_nepp	7:41cbc431e1f4	2814	_device->SigmaEstimate = c_sigma_est_max;
nikapov	0:a1a69d32f310	2815	*p_dmax_mm = 0;
nikapov	0:a1a69d32f310	2816	} else {
nikapov	0:a1a69d32f310	2817	if (vcsel_total_events_rtn < 1) {
nikapov	0:a1a69d32f310	2818	vcsel_total_events_rtn = 1;
nikapov	0:a1a69d32f310	2819	}
nikapov	0:a1a69d32f310	2820
nikapov	0:a1a69d32f310	2821	sigma_estimate_p1 = c_pulse_effective_width_centi_ns;
nikapov	0:a1a69d32f310	2822
nikapov	0:a1a69d32f310	2823	/* ((FixPoint1616 << 16)* uint32)/uint32 = FixPoint1616 */
nikapov	0:a1a69d32f310	2824	sigma_estimate_p2 = (ambient_rate_kcps << 16) / peak_signal_rate_kcps;
nikapov	0:a1a69d32f310	2825	if (sigma_estimate_p2 > c_amb_to_signal_ratio_max) {
nikapov	0:a1a69d32f310	2826	/* Clip to prevent overflow. Will ensure safe
nikapov	0:a1a69d32f310	2827	* max result. */
nikapov	0:a1a69d32f310	2828	sigma_estimate_p2 = c_amb_to_signal_ratio_max;
nikapov	0:a1a69d32f310	2829	}
nikapov	0:a1a69d32f310	2830	sigma_estimate_p2 *= c_ambient_effective_width_centi_ns;
nikapov	0:a1a69d32f310	2831
nikapov	0:a1a69d32f310	2832	sigma_estimate_p3 = 2 * VL53L0X_isqrt(vcsel_total_events_rtn * 12);
nikapov	0:a1a69d32f310	2833
nikapov	0:a1a69d32f310	2834	/* uint32 * FixPoint1616 = FixPoint1616 */
nikapov	0:a1a69d32f310	2835	delta_t_ps = p_ranging_measurement_data->RangeMilliMeter *
nikapov	0:a1a69d32f310	2836	c_tof_per_mm_ps;
nikapov	0:a1a69d32f310	2837
nikapov	0:a1a69d32f310	2838	/*
nikapov	0:a1a69d32f310	2839	* vcselRate - xtalkCompRate
nikapov	0:a1a69d32f310	2840	* (uint32 << 16) - FixPoint1616 = FixPoint1616.
nikapov	0:a1a69d32f310	2841	* Divide result by 1000 to convert to mcps.
nikapov	0:a1a69d32f310	2842	* 500 is added to ensure rounding when integer division
nikapov	0:a1a69d32f310	2843	* truncates.
nikapov	0:a1a69d32f310	2844	*/
nikapov	0:a1a69d32f310	2845	diff1_mcps = (((peak_signal_rate_kcps << 16) -
nikapov	0:a1a69d32f310	2846	2 * x_talk_comp_rate_kcps) + 500) / 1000;
nikapov	0:a1a69d32f310	2847
nikapov	0:a1a69d32f310	2848	/* vcselRate + xtalkCompRate */
nikapov	0:a1a69d32f310	2849	diff2_mcps = ((peak_signal_rate_kcps << 16) + 500) / 1000;
nikapov	0:a1a69d32f310	2850
nikapov	0:a1a69d32f310	2851	/* Shift by 8 bits to increase resolution prior to the
nikapov	0:a1a69d32f310	2852	* division */
nikapov	0:a1a69d32f310	2853	diff1_mcps <<= 8;
nikapov	0:a1a69d32f310	2854
nikapov	0:a1a69d32f310	2855	/* FixPoint0824/FixPoint1616 = FixPoint2408 */
nikapov	0:a1a69d32f310	2856	// xTalkCorrection = abs(diff1_mcps/diff2_mcps);
sepp_nepp	7:41cbc431e1f4	2857	// abs is causing compiler overloading isue in C++,but unsigned types. So,redundant call anyway!
nikapov	0:a1a69d32f310	2858	x_talk_correction = diff1_mcps / diff2_mcps;
nikapov	0:a1a69d32f310	2859
nikapov	0:a1a69d32f310	2860	/* FixPoint2408 << 8 = FixPoint1616 */
nikapov	0:a1a69d32f310	2861	x_talk_correction <<= 8;
nikapov	0:a1a69d32f310	2862
nikapov	0:a1a69d32f310	2863	if (p_ranging_measurement_data->RangeStatus != 0) {
nikapov	0:a1a69d32f310	2864	pw_mult = 1 << 16;
nikapov	0:a1a69d32f310	2865	} else {
nikapov	0:a1a69d32f310	2866	/* FixPoint1616/uint32 = FixPoint1616 */
nikapov	0:a1a69d32f310	2867	pw_mult = delta_t_ps / c_vcsel_pulse_width_ps; /* smaller than 1.0f */
nikapov	0:a1a69d32f310	2868
nikapov	0:a1a69d32f310	2869	/*
sepp_nepp	7:41cbc431e1f4	2870	* FixPoint1616 * FixPoint1616 = FixPoint3232,however both
nikapov	0:a1a69d32f310	2871	* values are small enough such that32 bits will not be
nikapov	0:a1a69d32f310	2872	* exceeded.
nikapov	0:a1a69d32f310	2873	*/
nikapov	0:a1a69d32f310	2874	pw_mult *= ((1 << 16) - x_talk_correction);
nikapov	0:a1a69d32f310	2875
nikapov	0:a1a69d32f310	2876	/* (FixPoint3232 >> 16) = FixPoint1616 */
nikapov	0:a1a69d32f310	2877	pw_mult = (pw_mult + c_16bit_rounding_param) >> 16;
nikapov	0:a1a69d32f310	2878
nikapov	0:a1a69d32f310	2879	/* FixPoint1616 + FixPoint1616 = FixPoint1616 */
nikapov	0:a1a69d32f310	2880	pw_mult += (1 << 16);
nikapov	0:a1a69d32f310	2881
nikapov	0:a1a69d32f310	2882	/*
sepp_nepp	7:41cbc431e1f4	2883	* At this point the value will be 1.xx,therefore if we square
nikapov	0:a1a69d32f310	2884	* the value this will exceed 32 bits. To address this perform
nikapov	0:a1a69d32f310	2885	* a single shift to the right before the multiplication.
nikapov	0:a1a69d32f310	2886	*/
nikapov	0:a1a69d32f310	2887	pw_mult >>= 1;
nikapov	0:a1a69d32f310	2888	/* FixPoint1715 * FixPoint1715 = FixPoint3430 */
nikapov	0:a1a69d32f310	2889	pw_mult = pw_mult * pw_mult;
nikapov	0:a1a69d32f310	2890
nikapov	0:a1a69d32f310	2891	/* (FixPoint3430 >> 14) = Fix1616 */
nikapov	0:a1a69d32f310	2892	pw_mult >>= 14;
nikapov	0:a1a69d32f310	2893	}
nikapov	0:a1a69d32f310	2894
nikapov	0:a1a69d32f310	2895	/* FixPoint1616 * uint32 = FixPoint1616 */
nikapov	0:a1a69d32f310	2896	sqr1 = pw_mult * sigma_estimate_p1;
nikapov	0:a1a69d32f310	2897
nikapov	0:a1a69d32f310	2898	/* (FixPoint1616 >> 16) = FixPoint3200 */
nikapov	0:a1a69d32f310	2899	sqr1 = (sqr1 + 0x8000) >> 16;
nikapov	0:a1a69d32f310	2900
nikapov	0:a1a69d32f310	2901	/* FixPoint3200 * FixPoint3200 = FixPoint6400 */
nikapov	0:a1a69d32f310	2902	sqr1 *= sqr1;
nikapov	0:a1a69d32f310	2903
nikapov	0:a1a69d32f310	2904	sqr2 = sigma_estimate_p2;
nikapov	0:a1a69d32f310	2905
nikapov	0:a1a69d32f310	2906	/* (FixPoint1616 >> 16) = FixPoint3200 */
nikapov	0:a1a69d32f310	2907	sqr2 = (sqr2 + 0x8000) >> 16;
nikapov	0:a1a69d32f310	2908
nikapov	0:a1a69d32f310	2909	/* FixPoint3200 * FixPoint3200 = FixPoint6400 */
nikapov	0:a1a69d32f310	2910	sqr2 *= sqr2;
nikapov	0:a1a69d32f310	2911
nikapov	0:a1a69d32f310	2912	/* FixPoint64000 + FixPoint6400 = FixPoint6400 */
nikapov	0:a1a69d32f310	2913	sqr_sum = sqr1 + sqr2;
nikapov	0:a1a69d32f310	2914
nikapov	0:a1a69d32f310	2915	/* SQRT(FixPoin6400) = FixPoint3200 */
nikapov	0:a1a69d32f310	2916	sqrt_result_centi_ns = VL53L0X_isqrt(sqr_sum);
nikapov	0:a1a69d32f310	2917
nikapov	0:a1a69d32f310	2918	/* (FixPoint3200 << 16) = FixPoint1616 */
nikapov	0:a1a69d32f310	2919	sqrt_result_centi_ns <<= 16;
nikapov	0:a1a69d32f310	2920
nikapov	0:a1a69d32f310	2921	/*
nikapov	0:a1a69d32f310	2922	* Note that the Speed Of Light is expressed in um per 1E-10
nikapov	0:a1a69d32f310	2923	* seconds (2997) Therefore to get mm/ns we have to divide by
nikapov	0:a1a69d32f310	2924	* 10000
nikapov	0:a1a69d32f310	2925	*/
nikapov	0:a1a69d32f310	2926	sigma_est_rtn = (((sqrt_result_centi_ns + 50) / 100) /
nikapov	0:a1a69d32f310	2927	sigma_estimate_p3);
nikapov	0:a1a69d32f310	2928	sigma_est_rtn *= VL53L0X_SPEED_OF_LIGHT_IN_AIR;
nikapov	0:a1a69d32f310	2929
nikapov	0:a1a69d32f310	2930	/* Add 5000 before dividing by 10000 to ensure rounding. */
nikapov	0:a1a69d32f310	2931	sigma_est_rtn += 5000;
nikapov	0:a1a69d32f310	2932	sigma_est_rtn /= 10000;
nikapov	0:a1a69d32f310	2933
nikapov	0:a1a69d32f310	2934	if (sigma_est_rtn > c_sigma_est_rtn_max) {
nikapov	0:a1a69d32f310	2935	/* Clip to prevent overflow. Will ensure safe
nikapov	0:a1a69d32f310	2936	* max result. */
nikapov	0:a1a69d32f310	2937	sigma_est_rtn = c_sigma_est_rtn_max;
nikapov	0:a1a69d32f310	2938	}
nikapov	0:a1a69d32f310	2939	final_range_integration_time_milli_secs =
nikapov	0:a1a69d32f310	2940	(final_range_timeout_micro_secs + pre_range_timeout_micro_secs + 500) / 1000;
nikapov	0:a1a69d32f310	2941
nikapov	0:a1a69d32f310	2942	/* sigmaEstRef = 1mm * 25ms/final range integration time (inc pre-range)
nikapov	0:a1a69d32f310	2943	* sqrt(FixPoint1616/int) = FixPoint2408)
nikapov	0:a1a69d32f310	2944	*/
nikapov	0:a1a69d32f310	2945	sigma_est_ref =
nikapov	0:a1a69d32f310	2946	VL53L0X_isqrt((c_dflt_final_range_integration_time_milli_secs +
nikapov	0:a1a69d32f310	2947	final_range_integration_time_milli_secs / 2) /
nikapov	0:a1a69d32f310	2948	final_range_integration_time_milli_secs);
nikapov	0:a1a69d32f310	2949
nikapov	0:a1a69d32f310	2950	/* FixPoint2408 << 8 = FixPoint1616 */
nikapov	0:a1a69d32f310	2951	sigma_est_ref <<= 8;
nikapov	0:a1a69d32f310	2952	sigma_est_ref = (sigma_est_ref + 500) / 1000;
nikapov	0:a1a69d32f310	2953
nikapov	0:a1a69d32f310	2954	/* FixPoint1616 * FixPoint1616 = FixPoint3232 */
nikapov	0:a1a69d32f310	2955	sqr1 = sigma_est_rtn * sigma_est_rtn;
nikapov	0:a1a69d32f310	2956	/* FixPoint1616 * FixPoint1616 = FixPoint3232 */
nikapov	0:a1a69d32f310	2957	sqr2 = sigma_est_ref * sigma_est_ref;
nikapov	0:a1a69d32f310	2958
nikapov	0:a1a69d32f310	2959	/* sqrt(FixPoint3232) = FixPoint1616 */
nikapov	0:a1a69d32f310	2960	sqrt_result = VL53L0X_isqrt((sqr1 + sqr2));
nikapov	0:a1a69d32f310	2961	/*
nikapov	0:a1a69d32f310	2962	* Note that the Shift by 4 bits increases resolution prior to
sepp_nepp	7:41cbc431e1f4	2963	* the sqrt,therefore the result must be shifted by 2 bits to
nikapov	0:a1a69d32f310	2964	* the right to revert back to the FixPoint1616 format.
nikapov	0:a1a69d32f310	2965	*/
nikapov	0:a1a69d32f310	2966
nikapov	0:a1a69d32f310	2967	sigma_estimate = 1000 * sqrt_result;
nikapov	0:a1a69d32f310	2968
nikapov	0:a1a69d32f310	2969	if ((peak_signal_rate_kcps < 1) \|\| (vcsel_total_events_rtn < 1) \|\|
nikapov	0:a1a69d32f310	2970	(sigma_estimate > c_sigma_est_max)) {
nikapov	0:a1a69d32f310	2971	sigma_estimate = c_sigma_est_max;
nikapov	0:a1a69d32f310	2972	}
nikapov	0:a1a69d32f310	2973
nikapov	0:a1a69d32f310	2974	*p_sigma_estimate = (uint32_t)(sigma_estimate);
sepp_nepp	7:41cbc431e1f4	2975	_device->SigmaEstimate = *p_sigma_estimate;
sepp_nepp	7:41cbc431e1f4	2976	status = VL53L0X_calc_dmax(total_signal_rate_mcps,
nikapov	0:a1a69d32f310	2977	corrected_signal_rate_mcps,
nikapov	0:a1a69d32f310	2978	pw_mult,
nikapov	0:a1a69d32f310	2979	sigma_estimate_p1,
nikapov	0:a1a69d32f310	2980	sigma_estimate_p2,
nikapov	0:a1a69d32f310	2981	peak_vcsel_duration_us,
nikapov	0:a1a69d32f310	2982	p_dmax_mm);
nikapov	0:a1a69d32f310	2983	}
nikapov	0:a1a69d32f310	2984
sepp_nepp	5:b95f6951f7d5	2985
nikapov	0:a1a69d32f310	2986	return status;
nikapov	0:a1a69d32f310	2987	}
nikapov	0:a1a69d32f310	2988
sepp_nepp	7:41cbc431e1f4	2989	VL53L0X_Error VL53L0X::VL53L0X_get_pal_range_status(uint8_t device_range_status,
nikapov	0:a1a69d32f310	2990	FixPoint1616_t signal_rate,
nikapov	0:a1a69d32f310	2991	uint16_t effective_spad_rtn_count,
nikapov	0:a1a69d32f310	2992	VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
nikapov	0:a1a69d32f310	2993	uint8_t *p_pal_range_status)
nikapov	0:a1a69d32f310	2994	{
nikapov	0:a1a69d32f310	2995	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	2996	uint8_t none_flag;
nikapov	0:a1a69d32f310	2997	uint8_t sigma_limitflag = 0;
nikapov	0:a1a69d32f310	2998	uint8_t signal_ref_clipflag = 0;
nikapov	0:a1a69d32f310	2999	uint8_t range_ignore_thresholdflag = 0;
nikapov	0:a1a69d32f310	3000	uint8_t sigma_limit_check_enable = 0;
nikapov	0:a1a69d32f310	3001	uint8_t signal_rate_final_range_limit_check_enable = 0;
nikapov	0:a1a69d32f310	3002	uint8_t signal_ref_clip_limit_check_enable = 0;
nikapov	0:a1a69d32f310	3003	uint8_t range_ignore_threshold_limit_check_enable = 0;
nikapov	0:a1a69d32f310	3004	FixPoint1616_t sigma_estimate;
nikapov	0:a1a69d32f310	3005	FixPoint1616_t sigma_limit_value;
nikapov	0:a1a69d32f310	3006	FixPoint1616_t signal_ref_clip_value;
nikapov	0:a1a69d32f310	3007	FixPoint1616_t range_ignore_threshold_value;
nikapov	0:a1a69d32f310	3008	FixPoint1616_t signal_rate_per_spad;
nikapov	0:a1a69d32f310	3009	uint8_t device_range_status_internal = 0;
nikapov	0:a1a69d32f310	3010	uint16_t tmp_word = 0;
nikapov	0:a1a69d32f310	3011	uint8_t temp8;
nikapov	0:a1a69d32f310	3012	uint32_t dmax_mm = 0;
nikapov	0:a1a69d32f310	3013	FixPoint1616_t last_signal_ref_mcps;
nikapov	0:a1a69d32f310	3014
sepp_nepp	5:b95f6951f7d5	3015
nikapov	0:a1a69d32f310	3016
nikapov	0:a1a69d32f310	3017
nikapov	0:a1a69d32f310	3018	/*
nikapov	0:a1a69d32f310	3019	* VL53L0X has a good ranging when the value of the
nikapov	0:a1a69d32f310	3020	* DeviceRangeStatus = 11. This function will replace the value 0 with
nikapov	0:a1a69d32f310	3021	* the value 11 in the DeviceRangeStatus.
sepp_nepp	7:41cbc431e1f4	3022	* In addition,the SigmaEstimator is not included in the VL53L0X
sepp_nepp	7:41cbc431e1f4	3023	* DeviceRangeStatus,this will be added in the PalRangeStatus.
nikapov	0:a1a69d32f310	3024	*/
nikapov	0:a1a69d32f310	3025
nikapov	0:a1a69d32f310	3026	device_range_status_internal = ((device_range_status & 0x78) >> 3);
nikapov	0:a1a69d32f310	3027
sepp_nepp	7:41cbc431e1f4	3028	if ( device_range_status_internal == 0 \|\|
nikapov	0:a1a69d32f310	3029	device_range_status_internal == 5 \|\|
nikapov	0:a1a69d32f310	3030	device_range_status_internal == 7 \|\|
nikapov	0:a1a69d32f310	3031	device_range_status_internal == 12 \|\|
nikapov	0:a1a69d32f310	3032	device_range_status_internal == 13 \|\|
nikapov	0:a1a69d32f310	3033	device_range_status_internal == 14 \|\|
nikapov	0:a1a69d32f310	3034	device_range_status_internal == 15
nikapov	0:a1a69d32f310	3035	) {
nikapov	0:a1a69d32f310	3036	none_flag = 1;
nikapov	0:a1a69d32f310	3037	} else {
nikapov	0:a1a69d32f310	3038	none_flag = 0;
nikapov	0:a1a69d32f310	3039	}
nikapov	0:a1a69d32f310	3040
nikapov	0:a1a69d32f310	3041	/*
sepp_nepp	7:41cbc431e1f4	3042	* Check if Sigma limit is enabled,if yes then do comparison with limit
nikapov	0:a1a69d32f310	3043	* value and put the result back into pPalRangeStatus.
nikapov	0:a1a69d32f310	3044	*/
nikapov	0:a1a69d32f310	3045	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3046	status = VL53L0X_get_limit_check_enable(VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
nikapov	0:a1a69d32f310	3047	&sigma_limit_check_enable);
Davidroid	2:d07edeaff6f1	3048	}
nikapov	0:a1a69d32f310	3049
nikapov	0:a1a69d32f310	3050	if ((sigma_limit_check_enable != 0) && (status == VL53L0X_ERROR_NONE)) {
nikapov	0:a1a69d32f310	3051	/*
nikapov	0:a1a69d32f310	3052	* compute the Sigma and check with limit
nikapov	0:a1a69d32f310	3053	*/
sepp_nepp	7:41cbc431e1f4	3054	status = VL53L0X_calc_sigma_estimate(p_ranging_measurement_data,
nikapov	0:a1a69d32f310	3055	&sigma_estimate,
nikapov	0:a1a69d32f310	3056	&dmax_mm);
nikapov	0:a1a69d32f310	3057	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3058	p_ranging_measurement_data->RangeDMaxMilliMeter = dmax_mm;
nikapov	0:a1a69d32f310	3059	}
nikapov	0:a1a69d32f310	3060
nikapov	0:a1a69d32f310	3061	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3062	status = VL53L0X_get_limit_check_value(VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
nikapov	0:a1a69d32f310	3063	&sigma_limit_value);
nikapov	0:a1a69d32f310	3064
nikapov	0:a1a69d32f310	3065	if ((sigma_limit_value > 0) &&
nikapov	0:a1a69d32f310	3066	(sigma_estimate > sigma_limit_value)) {
nikapov	0:a1a69d32f310	3067	/* Limit Fail */
nikapov	0:a1a69d32f310	3068	sigma_limitflag = 1;
nikapov	0:a1a69d32f310	3069	}
nikapov	0:a1a69d32f310	3070	}
nikapov	0:a1a69d32f310	3071	}
nikapov	0:a1a69d32f310	3072
nikapov	0:a1a69d32f310	3073	/*
sepp_nepp	7:41cbc431e1f4	3074	* Check if Signal ref clip limit is enabled,if yes then do comparison
nikapov	0:a1a69d32f310	3075	* with limit value and put the result back into pPalRangeStatus.
nikapov	0:a1a69d32f310	3076	*/
nikapov	0:a1a69d32f310	3077	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3078	status = VL53L0X_get_limit_check_enable(VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
nikapov	0:a1a69d32f310	3079	&signal_ref_clip_limit_check_enable);
nikapov	0:a1a69d32f310	3080	}
nikapov	0:a1a69d32f310	3081
nikapov	0:a1a69d32f310	3082	if ((signal_ref_clip_limit_check_enable != 0) &&
nikapov	0:a1a69d32f310	3083	(status == VL53L0X_ERROR_NONE)) {
nikapov	0:a1a69d32f310	3084
sepp_nepp	7:41cbc431e1f4	3085	status = VL53L0X_get_limit_check_value(VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
nikapov	0:a1a69d32f310	3086	&signal_ref_clip_value);
nikapov	0:a1a69d32f310	3087
nikapov	0:a1a69d32f310	3088	/* Read LastSignalRefMcps from device */
nikapov	0:a1a69d32f310	3089	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3090	status = VL53L0X_write_byte(0xFF,0x01);
nikapov	0:a1a69d32f310	3091	}
nikapov	0:a1a69d32f310	3092
nikapov	0:a1a69d32f310	3093	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3094	status = VL53L0X_read_word(VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF,
nikapov	0:a1a69d32f310	3095	&tmp_word);
nikapov	0:a1a69d32f310	3096	}
nikapov	0:a1a69d32f310	3097
nikapov	0:a1a69d32f310	3098	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3099	status = VL53L0X_write_byte(0xFF,0x00);
nikapov	0:a1a69d32f310	3100	}
nikapov	0:a1a69d32f310	3101
nikapov	0:a1a69d32f310	3102	last_signal_ref_mcps = VL53L0X_FIXPOINT97TOFIXPOINT1616(tmp_word);
sepp_nepp	7:41cbc431e1f4	3103	_device->LastSignalRefMcps = last_signal_ref_mcps;
nikapov	0:a1a69d32f310	3104
nikapov	0:a1a69d32f310	3105	if ((signal_ref_clip_value > 0) &&
nikapov	0:a1a69d32f310	3106	(last_signal_ref_mcps > signal_ref_clip_value)) {
nikapov	0:a1a69d32f310	3107	/* Limit Fail */
nikapov	0:a1a69d32f310	3108	signal_ref_clipflag = 1;
nikapov	0:a1a69d32f310	3109	}
nikapov	0:a1a69d32f310	3110	}
nikapov	0:a1a69d32f310	3111
nikapov	0:a1a69d32f310	3112	/*
sepp_nepp	7:41cbc431e1f4	3113	* Check if Signal ref clip limit is enabled,if yes then do comparison
nikapov	0:a1a69d32f310	3114	* with limit value and put the result back into pPalRangeStatus.
nikapov	0:a1a69d32f310	3115	* EffectiveSpadRtnCount has a format 8.8
nikapov	0:a1a69d32f310	3116	* If (Return signal rate < (1.5 x Xtalk x number of Spads)) : FAIL
nikapov	0:a1a69d32f310	3117	*/
Davidroid	2:d07edeaff6f1	3118	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3119	status = VL53L0X_get_limit_check_enable(VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
nikapov	0:a1a69d32f310	3120	&range_ignore_threshold_limit_check_enable);
Davidroid	2:d07edeaff6f1	3121	}
nikapov	0:a1a69d32f310	3122
nikapov	0:a1a69d32f310	3123	if ((range_ignore_threshold_limit_check_enable != 0) &&
nikapov	0:a1a69d32f310	3124	(status == VL53L0X_ERROR_NONE)) {
nikapov	0:a1a69d32f310	3125
nikapov	0:a1a69d32f310	3126	/* Compute the signal rate per spad */
nikapov	0:a1a69d32f310	3127	if (effective_spad_rtn_count == 0) {
nikapov	0:a1a69d32f310	3128	signal_rate_per_spad = 0;
nikapov	0:a1a69d32f310	3129	} else {
nikapov	0:a1a69d32f310	3130	signal_rate_per_spad = (FixPoint1616_t)((256 * signal_rate)
nikapov	0:a1a69d32f310	3131	/ effective_spad_rtn_count);
nikapov	0:a1a69d32f310	3132	}
nikapov	0:a1a69d32f310	3133
sepp_nepp	7:41cbc431e1f4	3134	status = VL53L0X_get_limit_check_value(VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
nikapov	0:a1a69d32f310	3135	&range_ignore_threshold_value);
nikapov	0:a1a69d32f310	3136
nikapov	0:a1a69d32f310	3137	if ((range_ignore_threshold_value > 0) &&
nikapov	0:a1a69d32f310	3138	(signal_rate_per_spad < range_ignore_threshold_value)) {
nikapov	0:a1a69d32f310	3139	/* Limit Fail add 2^6 to range status */
nikapov	0:a1a69d32f310	3140	range_ignore_thresholdflag = 1;
nikapov	0:a1a69d32f310	3141	}
nikapov	0:a1a69d32f310	3142	}
nikapov	0:a1a69d32f310	3143
nikapov	0:a1a69d32f310	3144	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3145	if (none_flag == 1) {
nikapov	0:a1a69d32f310	3146	p_pal_range_status = 255; / NONE */
nikapov	0:a1a69d32f310	3147	} else if (device_range_status_internal == 1 \|\|
nikapov	0:a1a69d32f310	3148	device_range_status_internal == 2 \|\|
nikapov	0:a1a69d32f310	3149	device_range_status_internal == 3) {
nikapov	0:a1a69d32f310	3150	p_pal_range_status = 5; / HW fail */
nikapov	0:a1a69d32f310	3151	} else if (device_range_status_internal == 6 \|\|
nikapov	0:a1a69d32f310	3152	device_range_status_internal == 9) {
nikapov	0:a1a69d32f310	3153	p_pal_range_status = 4; / Phase fail */
nikapov	0:a1a69d32f310	3154	} else if (device_range_status_internal == 8 \|\|
nikapov	0:a1a69d32f310	3155	device_range_status_internal == 10 \|\|
nikapov	0:a1a69d32f310	3156	signal_ref_clipflag == 1) {
nikapov	0:a1a69d32f310	3157	p_pal_range_status = 3; / Min range */
nikapov	0:a1a69d32f310	3158	} else if (device_range_status_internal == 4 \|\|
nikapov	0:a1a69d32f310	3159	range_ignore_thresholdflag == 1) {
nikapov	0:a1a69d32f310	3160	p_pal_range_status = 2; / Signal Fail */
nikapov	0:a1a69d32f310	3161	} else if (sigma_limitflag == 1) {
nikapov	0:a1a69d32f310	3162	p_pal_range_status = 1; / Sigma Fail */
nikapov	0:a1a69d32f310	3163	} else {
nikapov	0:a1a69d32f310	3164	p_pal_range_status = 0; / Range Valid */
nikapov	0:a1a69d32f310	3165	}
nikapov	0:a1a69d32f310	3166	}
nikapov	0:a1a69d32f310	3167
nikapov	0:a1a69d32f310	3168	/* DMAX only relevant during range error */
Davidroid	3:e9269ff624ed	3169	if (*p_pal_range_status == 0) {
nikapov	0:a1a69d32f310	3170	p_ranging_measurement_data->RangeDMaxMilliMeter = 0;
Davidroid	3:e9269ff624ed	3171	}
nikapov	0:a1a69d32f310	3172
nikapov	0:a1a69d32f310	3173	/* fill the Limit Check Status */
nikapov	0:a1a69d32f310	3174
sepp_nepp	7:41cbc431e1f4	3175	status = VL53L0X_get_limit_check_enable(VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
nikapov	0:a1a69d32f310	3176	&signal_rate_final_range_limit_check_enable);
nikapov	0:a1a69d32f310	3177
nikapov	0:a1a69d32f310	3178	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3179	if ((sigma_limit_check_enable == 0) \|\| (sigma_limitflag == 1)) {
nikapov	0:a1a69d32f310	3180	temp8 = 1;
nikapov	0:a1a69d32f310	3181	} else {
nikapov	0:a1a69d32f310	3182	temp8 = 0;
nikapov	0:a1a69d32f310	3183	}
sepp_nepp	7:41cbc431e1f4	3184	_device->CurrentParameters.LimitChecksStatus[VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE] = temp8;
nikapov	0:a1a69d32f310	3185
nikapov	0:a1a69d32f310	3186	if ((device_range_status_internal == 4) \|\|
nikapov	0:a1a69d32f310	3187	(signal_rate_final_range_limit_check_enable == 0)) {
nikapov	0:a1a69d32f310	3188	temp8 = 1;
nikapov	0:a1a69d32f310	3189	} else {
nikapov	0:a1a69d32f310	3190	temp8 = 0;
nikapov	0:a1a69d32f310	3191	}
sepp_nepp	7:41cbc431e1f4	3192	_device->CurrentParameters.LimitChecksStatus[VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE] = temp8;
nikapov	0:a1a69d32f310	3193
nikapov	0:a1a69d32f310	3194	if ((signal_ref_clip_limit_check_enable == 0) \|\|
nikapov	0:a1a69d32f310	3195	(signal_ref_clipflag == 1)) {
nikapov	0:a1a69d32f310	3196	temp8 = 1;
nikapov	0:a1a69d32f310	3197	} else {
nikapov	0:a1a69d32f310	3198	temp8 = 0;
nikapov	0:a1a69d32f310	3199	}
nikapov	0:a1a69d32f310	3200
sepp_nepp	7:41cbc431e1f4	3201	_device->CurrentParameters.LimitChecksStatus[VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP] = temp8;
nikapov	0:a1a69d32f310	3202
nikapov	0:a1a69d32f310	3203	if ((range_ignore_threshold_limit_check_enable == 0) \|\|
nikapov	0:a1a69d32f310	3204	(range_ignore_thresholdflag == 1)) {
nikapov	0:a1a69d32f310	3205	temp8 = 1;
nikapov	0:a1a69d32f310	3206	} else {
nikapov	0:a1a69d32f310	3207	temp8 = 0;
nikapov	0:a1a69d32f310	3208	}
nikapov	0:a1a69d32f310	3209
sepp_nepp	7:41cbc431e1f4	3210	_device->CurrentParameters.LimitChecksStatus[VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD] = temp8;
nikapov	0:a1a69d32f310	3211	}
nikapov	0:a1a69d32f310	3212
sepp_nepp	5:b95f6951f7d5	3213
nikapov	0:a1a69d32f310	3214	return status;
nikapov	0:a1a69d32f310	3215
nikapov	0:a1a69d32f310	3216	}
nikapov	0:a1a69d32f310	3217
sepp_nepp	7:41cbc431e1f4	3218	VL53L0X_Error VL53L0X::VL53L0X_get_ranging_measurement_data(VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data)
nikapov	0:a1a69d32f310	3219	{
nikapov	0:a1a69d32f310	3220	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	3221	uint8_t device_range_status;
nikapov	0:a1a69d32f310	3222	uint8_t range_fractional_enable;
nikapov	0:a1a69d32f310	3223	uint8_t pal_range_status;
nikapov	0:a1a69d32f310	3224	uint8_t x_talk_compensation_enable;
nikapov	0:a1a69d32f310	3225	uint16_t ambient_rate;
nikapov	0:a1a69d32f310	3226	FixPoint1616_t signal_rate;
nikapov	0:a1a69d32f310	3227	uint16_t x_talk_compensation_rate_mega_cps;
nikapov	0:a1a69d32f310	3228	uint16_t effective_spad_rtn_count;
nikapov	0:a1a69d32f310	3229	uint16_t tmpuint16;
nikapov	0:a1a69d32f310	3230	uint16_t xtalk_range_milli_meter;
nikapov	0:a1a69d32f310	3231	uint16_t linearity_corrective_gain;
nikapov	0:a1a69d32f310	3232	uint8_t localBuffer[12];
nikapov	0:a1a69d32f310	3233	VL53L0X_RangingMeasurementData_t last_range_data_buffer;
nikapov	0:a1a69d32f310	3234
sepp_nepp	5:b95f6951f7d5	3235
nikapov	0:a1a69d32f310	3236
nikapov	0:a1a69d32f310	3237	/*
sepp_nepp	7:41cbc431e1f4	3238	* use multi read even if some registers are not useful,result will
nikapov	0:a1a69d32f310	3239	* be more efficient
nikapov	0:a1a69d32f310	3240	* start reading at 0x14 dec20
nikapov	0:a1a69d32f310	3241	* end reading at 0x21 dec33 total 14 bytes to read
nikapov	0:a1a69d32f310	3242	*/
sepp_nepp	7:41cbc431e1f4	3243	status = VL53L0X_read_multi(0x14,localBuffer,12);
nikapov	0:a1a69d32f310	3244
nikapov	0:a1a69d32f310	3245	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3246
nikapov	0:a1a69d32f310	3247	p_ranging_measurement_data->ZoneId = 0; /* Only one zone */
nikapov	0:a1a69d32f310	3248	p_ranging_measurement_data->TimeStamp = 0; /* Not Implemented */
nikapov	0:a1a69d32f310	3249
sepp_nepp	7:41cbc431e1f4	3250	tmpuint16 = VL53L0X_MAKEUINT16(localBuffer[11],localBuffer[10]);
nikapov	0:a1a69d32f310	3251	/* cut1.1 if SYSTEM__RANGE_CONFIG if 1 range is 2bits fractional
nikapov	0:a1a69d32f310	3252	*(format 11.2) else no fractional
nikapov	0:a1a69d32f310	3253	*/
nikapov	0:a1a69d32f310	3254
nikapov	0:a1a69d32f310	3255	p_ranging_measurement_data->MeasurementTimeUsec = 0;
nikapov	0:a1a69d32f310	3256
sepp_nepp	7:41cbc431e1f4	3257	signal_rate = VL53L0X_FIXPOINT97TOFIXPOINT1616(VL53L0X_MAKEUINT16(localBuffer[7],localBuffer[6]));
nikapov	0:a1a69d32f310	3258	/* peak_signal_count_rate_rtn_mcps */
nikapov	0:a1a69d32f310	3259	p_ranging_measurement_data->SignalRateRtnMegaCps = signal_rate;
nikapov	0:a1a69d32f310	3260
sepp_nepp	7:41cbc431e1f4	3261	ambient_rate = VL53L0X_MAKEUINT16(localBuffer[9],localBuffer[8]);
nikapov	0:a1a69d32f310	3262	p_ranging_measurement_data->AmbientRateRtnMegaCps =
nikapov	0:a1a69d32f310	3263	VL53L0X_FIXPOINT97TOFIXPOINT1616(ambient_rate);
nikapov	0:a1a69d32f310	3264
nikapov	0:a1a69d32f310	3265	effective_spad_rtn_count = VL53L0X_MAKEUINT16(localBuffer[3],
nikapov	0:a1a69d32f310	3266	localBuffer[2]);
nikapov	0:a1a69d32f310	3267	/* EffectiveSpadRtnCount is 8.8 format */
nikapov	0:a1a69d32f310	3268	p_ranging_measurement_data->EffectiveSpadRtnCount =
nikapov	0:a1a69d32f310	3269	effective_spad_rtn_count;
nikapov	0:a1a69d32f310	3270
nikapov	0:a1a69d32f310	3271	device_range_status = localBuffer[0];
nikapov	0:a1a69d32f310	3272
nikapov	0:a1a69d32f310	3273	/* Get Linearity Corrective Gain */
sepp_nepp	7:41cbc431e1f4	3274	linearity_corrective_gain = _device->
sepp_nepp	7:41cbc431e1f4	3275	LinearityCorrectiveGain;
nikapov	0:a1a69d32f310	3276
nikapov	0:a1a69d32f310	3277	/* Get ranging configuration */
sepp_nepp	7:41cbc431e1f4	3278	range_fractional_enable = _device->
sepp_nepp	7:41cbc431e1f4	3279	RangeFractionalEnable;
nikapov	0:a1a69d32f310	3280
nikapov	0:a1a69d32f310	3281	if (linearity_corrective_gain != 1000) {
nikapov	0:a1a69d32f310	3282
nikapov	0:a1a69d32f310	3283	tmpuint16 = (uint16_t)((linearity_corrective_gain
nikapov	0:a1a69d32f310	3284	* tmpuint16 + 500) / 1000);
nikapov	0:a1a69d32f310	3285
nikapov	0:a1a69d32f310	3286	/* Implement Xtalk */
sepp_nepp	7:41cbc431e1f4	3287	x_talk_compensation_rate_mega_cps = _device->CurrentParameters.XTalkCompensationRateMegaCps;
sepp_nepp	7:41cbc431e1f4	3288	x_talk_compensation_enable = _device->CurrentParameters.XTalkCompensationEnable;
nikapov	0:a1a69d32f310	3289
nikapov	0:a1a69d32f310	3290	if (x_talk_compensation_enable) {
nikapov	0:a1a69d32f310	3291
nikapov	0:a1a69d32f310	3292	if ((signal_rate
nikapov	0:a1a69d32f310	3293	- ((x_talk_compensation_rate_mega_cps
nikapov	0:a1a69d32f310	3294	* effective_spad_rtn_count) >> 8))
nikapov	0:a1a69d32f310	3295	<= 0) {
nikapov	0:a1a69d32f310	3296	if (range_fractional_enable) {
nikapov	0:a1a69d32f310	3297	xtalk_range_milli_meter = 8888;
nikapov	0:a1a69d32f310	3298	} else {
nikapov	0:a1a69d32f310	3299	xtalk_range_milli_meter = 8888 << 2;
nikapov	0:a1a69d32f310	3300	}
nikapov	0:a1a69d32f310	3301	} else {
nikapov	0:a1a69d32f310	3302	xtalk_range_milli_meter =
nikapov	0:a1a69d32f310	3303	(tmpuint16 * signal_rate)
nikapov	0:a1a69d32f310	3304	/ (signal_rate
nikapov	0:a1a69d32f310	3305	- ((x_talk_compensation_rate_mega_cps
nikapov	0:a1a69d32f310	3306	* effective_spad_rtn_count)
nikapov	0:a1a69d32f310	3307	>> 8));
nikapov	0:a1a69d32f310	3308	}
nikapov	0:a1a69d32f310	3309
nikapov	0:a1a69d32f310	3310	tmpuint16 = xtalk_range_milli_meter;
nikapov	0:a1a69d32f310	3311	}
nikapov	0:a1a69d32f310	3312
nikapov	0:a1a69d32f310	3313	}
nikapov	0:a1a69d32f310	3314
nikapov	0:a1a69d32f310	3315	if (range_fractional_enable) {
nikapov	0:a1a69d32f310	3316	p_ranging_measurement_data->RangeMilliMeter =
nikapov	0:a1a69d32f310	3317	(uint16_t)((tmpuint16) >> 2);
nikapov	0:a1a69d32f310	3318	p_ranging_measurement_data->RangeFractionalPart =
nikapov	0:a1a69d32f310	3319	(uint8_t)((tmpuint16 & 0x03) << 6);
nikapov	0:a1a69d32f310	3320	} else {
nikapov	0:a1a69d32f310	3321	p_ranging_measurement_data->RangeMilliMeter = tmpuint16;
nikapov	0:a1a69d32f310	3322	p_ranging_measurement_data->RangeFractionalPart = 0;
nikapov	0:a1a69d32f310	3323	}
nikapov	0:a1a69d32f310	3324
nikapov	0:a1a69d32f310	3325	/*
sepp_nepp	7:41cbc431e1f4	3326	* For a standard definition of RangeStatus,this should
nikapov	0:a1a69d32f310	3327	* return 0 in case of good result after a ranging
nikapov	0:a1a69d32f310	3328	* The range status depends on the device so call a device
nikapov	0:a1a69d32f310	3329	* specific function to obtain the right Status.
nikapov	0:a1a69d32f310	3330	*/
sepp_nepp	7:41cbc431e1f4	3331	status \|= VL53L0X_get_pal_range_status(device_range_status,
sepp_nepp	7:41cbc431e1f4	3332	signal_rate,effective_spad_rtn_count,
sepp_nepp	7:41cbc431e1f4	3333	p_ranging_measurement_data,&pal_range_status);
nikapov	0:a1a69d32f310	3334
nikapov	0:a1a69d32f310	3335	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3336	p_ranging_measurement_data->RangeStatus = pal_range_status;
nikapov	0:a1a69d32f310	3337	}
nikapov	0:a1a69d32f310	3338
nikapov	0:a1a69d32f310	3339	}
nikapov	0:a1a69d32f310	3340
nikapov	0:a1a69d32f310	3341	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3342	/* Copy last read data into Dev buffer */
sepp_nepp	7:41cbc431e1f4	3343	last_range_data_buffer = _device-> LastRangeMeasure;
nikapov	0:a1a69d32f310	3344
nikapov	0:a1a69d32f310	3345	last_range_data_buffer.RangeMilliMeter =
nikapov	0:a1a69d32f310	3346	p_ranging_measurement_data->RangeMilliMeter;
nikapov	0:a1a69d32f310	3347	last_range_data_buffer.RangeFractionalPart =
nikapov	0:a1a69d32f310	3348	p_ranging_measurement_data->RangeFractionalPart;
nikapov	0:a1a69d32f310	3349	last_range_data_buffer.RangeDMaxMilliMeter =
nikapov	0:a1a69d32f310	3350	p_ranging_measurement_data->RangeDMaxMilliMeter;
nikapov	0:a1a69d32f310	3351	last_range_data_buffer.MeasurementTimeUsec =
nikapov	0:a1a69d32f310	3352	p_ranging_measurement_data->MeasurementTimeUsec;
nikapov	0:a1a69d32f310	3353	last_range_data_buffer.SignalRateRtnMegaCps =
nikapov	0:a1a69d32f310	3354	p_ranging_measurement_data->SignalRateRtnMegaCps;
nikapov	0:a1a69d32f310	3355	last_range_data_buffer.AmbientRateRtnMegaCps =
nikapov	0:a1a69d32f310	3356	p_ranging_measurement_data->AmbientRateRtnMegaCps;
nikapov	0:a1a69d32f310	3357	last_range_data_buffer.EffectiveSpadRtnCount =
nikapov	0:a1a69d32f310	3358	p_ranging_measurement_data->EffectiveSpadRtnCount;
nikapov	0:a1a69d32f310	3359	last_range_data_buffer.RangeStatus =
nikapov	0:a1a69d32f310	3360	p_ranging_measurement_data->RangeStatus;
nikapov	0:a1a69d32f310	3361
sepp_nepp	7:41cbc431e1f4	3362	_device->LastRangeMeasure = last_range_data_buffer;
nikapov	0:a1a69d32f310	3363	}
nikapov	0:a1a69d32f310	3364
sepp_nepp	5:b95f6951f7d5	3365
nikapov	0:a1a69d32f310	3366	return status;
nikapov	0:a1a69d32f310	3367	}
nikapov	0:a1a69d32f310	3368
sepp_nepp	7:41cbc431e1f4	3369	VL53L0X_Error VL53L0X::VL53L0X_perform_single_ranging_measurement(VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data)
nikapov	0:a1a69d32f310	3370	{
nikapov	0:a1a69d32f310	3371	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	3372
sepp_nepp	5:b95f6951f7d5	3373
nikapov	0:a1a69d32f310	3374
nikapov	0:a1a69d32f310	3375	/* This function will do a complete single ranging
nikapov	0:a1a69d32f310	3376	* Here we fix the mode! */
sepp_nepp	7:41cbc431e1f4	3377	status = VL53L0X_set_device_mode(VL53L0X_DEVICEMODE_SINGLE_RANGING);
nikapov	0:a1a69d32f310	3378
nikapov	0:a1a69d32f310	3379	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3380	status = VL53L0X_perform_single_measurement();
nikapov	0:a1a69d32f310	3381	}
nikapov	0:a1a69d32f310	3382
nikapov	0:a1a69d32f310	3383	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3384	status = VL53L0X_get_ranging_measurement_data(p_ranging_measurement_data);
nikapov	0:a1a69d32f310	3385	}
nikapov	0:a1a69d32f310	3386
nikapov	0:a1a69d32f310	3387	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3388	status = VL53L0X_clear_interrupt_mask(0);
nikapov	0:a1a69d32f310	3389	}
nikapov	0:a1a69d32f310	3390
sepp_nepp	5:b95f6951f7d5	3391
nikapov	0:a1a69d32f310	3392	return status;
nikapov	0:a1a69d32f310	3393	}
nikapov	0:a1a69d32f310	3394
sepp_nepp	7:41cbc431e1f4	3395	VL53L0X_Error VL53L0X::perform_ref_signal_measurement(uint16_t *p_ref_signal_rate)
nikapov	0:a1a69d32f310	3396	{
nikapov	0:a1a69d32f310	3397	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	3398	VL53L0X_RangingMeasurementData_t ranging_measurement_data;
nikapov	0:a1a69d32f310	3399
nikapov	0:a1a69d32f310	3400	uint8_t sequence_config = 0;
nikapov	0:a1a69d32f310	3401
nikapov	0:a1a69d32f310	3402	/* store the value of the sequence config,
nikapov	0:a1a69d32f310	3403	* this will be reset before the end of the function
nikapov	0:a1a69d32f310	3404	*/
nikapov	0:a1a69d32f310	3405
sepp_nepp	7:41cbc431e1f4	3406	sequence_config = _device-> SequenceConfig;
nikapov	0:a1a69d32f310	3407
nikapov	0:a1a69d32f310	3408	/*
nikapov	0:a1a69d32f310	3409	* This function performs a reference signal rate measurement.
nikapov	0:a1a69d32f310	3410	*/
nikapov	0:a1a69d32f310	3411	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3412	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,0xC0);
nikapov	0:a1a69d32f310	3413	}
nikapov	0:a1a69d32f310	3414
nikapov	0:a1a69d32f310	3415	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3416	status = VL53L0X_perform_single_ranging_measurement(&ranging_measurement_data);
nikapov	0:a1a69d32f310	3417	}
nikapov	0:a1a69d32f310	3418
nikapov	0:a1a69d32f310	3419	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3420	status = VL53L0X_write_byte(0xFF,0x01);
nikapov	0:a1a69d32f310	3421	}
nikapov	0:a1a69d32f310	3422
nikapov	0:a1a69d32f310	3423	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3424	status = VL53L0X_read_word(VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF,
nikapov	0:a1a69d32f310	3425	p_ref_signal_rate);
Davidroid	2:d07edeaff6f1	3426	}
nikapov	0:a1a69d32f310	3427
nikapov	0:a1a69d32f310	3428	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3429	status = VL53L0X_write_byte(0xFF,0x00);
Davidroid	2:d07edeaff6f1	3430	}
nikapov	0:a1a69d32f310	3431
nikapov	0:a1a69d32f310	3432	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3433	/* restore the previous Sequence Config */
sepp_nepp	7:41cbc431e1f4	3434	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
nikapov	0:a1a69d32f310	3435	sequence_config);
nikapov	0:a1a69d32f310	3436	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3437	_device->SequenceConfig = sequence_config;
nikapov	0:a1a69d32f310	3438	}
nikapov	0:a1a69d32f310	3439	}
nikapov	0:a1a69d32f310	3440
nikapov	0:a1a69d32f310	3441	return status;
nikapov	0:a1a69d32f310	3442	}
nikapov	0:a1a69d32f310	3443
sepp_nepp	7:41cbc431e1f4	3444	VL53L0X_Error VL53L0X::wrapped_VL53L0X_perform_ref_spad_management(uint32_t *ref_spad_count,
nikapov	0:a1a69d32f310	3445	uint8_t *is_aperture_spads)
nikapov	0:a1a69d32f310	3446	{
nikapov	0:a1a69d32f310	3447	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	3448	uint8_t last_spad_array[6];
nikapov	0:a1a69d32f310	3449	uint8_t start_select = 0xB4;
nikapov	0:a1a69d32f310	3450	uint32_t minimum_spad_count = 3;
nikapov	0:a1a69d32f310	3451	uint32_t max_spad_count = 44;
nikapov	0:a1a69d32f310	3452	uint32_t current_spad_index = 0;
nikapov	0:a1a69d32f310	3453	uint32_t last_spad_index = 0;
nikapov	0:a1a69d32f310	3454	int32_t next_good_spad = 0;
nikapov	0:a1a69d32f310	3455	uint16_t target_ref_rate = 0x0A00; /* 20 MCPS in 9:7 format */
nikapov	0:a1a69d32f310	3456	uint16_t peak_signal_rate_ref;
nikapov	0:a1a69d32f310	3457	uint32_t need_apt_spads = 0;
nikapov	0:a1a69d32f310	3458	uint32_t index = 0;
nikapov	0:a1a69d32f310	3459	uint32_t spad_array_size = 6;
nikapov	0:a1a69d32f310	3460	uint32_t signal_rate_diff = 0;
nikapov	0:a1a69d32f310	3461	uint32_t last_signal_rate_diff = 0;
nikapov	0:a1a69d32f310	3462	uint8_t complete = 0;
nikapov	0:a1a69d32f310	3463	uint8_t vhv_settings = 0;
nikapov	0:a1a69d32f310	3464	uint8_t phase_cal = 0;
nikapov	0:a1a69d32f310	3465	uint32_t ref_spad_count_int = 0;
nikapov	0:a1a69d32f310	3466	uint8_t is_aperture_spads_int = 0;
nikapov	0:a1a69d32f310	3467
nikapov	0:a1a69d32f310	3468	/*
nikapov	0:a1a69d32f310	3469	* The reference SPAD initialization procedure determines the minimum
nikapov	0:a1a69d32f310	3470	* amount of reference spads to be enables to achieve a target reference
nikapov	0:a1a69d32f310	3471	* signal rate and should be performed once during initialization.
nikapov	0:a1a69d32f310	3472	*
nikapov	0:a1a69d32f310	3473	* Either aperture or non-aperture spads are applied but never both.
sepp_nepp	7:41cbc431e1f4	3474	* Firstly non-aperture spads are set,begining with 5 spads,and
nikapov	0:a1a69d32f310	3475	* increased one spad at a time until the closest measurement to the
nikapov	0:a1a69d32f310	3476	* target rate is achieved.
nikapov	0:a1a69d32f310	3477	*
nikapov	0:a1a69d32f310	3478	* If the target rate is exceeded when 5 non-aperture spads are enabled,
nikapov	0:a1a69d32f310	3479	* initialization is performed instead with aperture spads.
nikapov	0:a1a69d32f310	3480	*
sepp_nepp	7:41cbc431e1f4	3481	* When setting spads,a 'Good Spad Map' is applied.
nikapov	0:a1a69d32f310	3482	*
nikapov	0:a1a69d32f310	3483	* This procedure operates within a SPAD window of interest of a maximum
nikapov	0:a1a69d32f310	3484	* 44 spads.
sepp_nepp	7:41cbc431e1f4	3485	* The start point is currently fixed to 180,which lies towards the end
nikapov	0:a1a69d32f310	3486	* of the non-aperture quadrant and runs in to the adjacent aperture
nikapov	0:a1a69d32f310	3487	* quadrant.
nikapov	0:a1a69d32f310	3488	*/
sepp_nepp	7:41cbc431e1f4	3489	target_ref_rate = _device-> targetRefRate;
nikapov	0:a1a69d32f310	3490
nikapov	0:a1a69d32f310	3491	/*
nikapov	0:a1a69d32f310	3492	* Initialize Spad arrays.
nikapov	0:a1a69d32f310	3493	* Currently the good spad map is initialised to 'All good'.
nikapov	0:a1a69d32f310	3494	* This is a short term implementation. The good spad map will be
nikapov	0:a1a69d32f310	3495	* provided as an input.
nikapov	0:a1a69d32f310	3496	* Note that there are 6 bytes. Only the first 44 bits will be used to
nikapov	0:a1a69d32f310	3497	* represent spads.
nikapov	0:a1a69d32f310	3498	*/
Davidroid	3:e9269ff624ed	3499	for (index = 0; index < spad_array_size; index++) {
sepp_nepp	7:41cbc431e1f4	3500	_device->SpadData.RefSpadEnables[index] = 0;
sepp_nepp	7:41cbc431e1f4	3501	}
sepp_nepp	7:41cbc431e1f4	3502
sepp_nepp	7:41cbc431e1f4	3503
sepp_nepp	7:41cbc431e1f4	3504	status = VL53L0X_write_byte(0xFF,0x01);
nikapov	0:a1a69d32f310	3505
nikapov	0:a1a69d32f310	3506	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3507	status = VL53L0X_write_byte(VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET,0x00);
nikapov	0:a1a69d32f310	3508	}
nikapov	0:a1a69d32f310	3509
nikapov	0:a1a69d32f310	3510	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3511	status = VL53L0X_write_byte(VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD,0x2C);
Davidroid	2:d07edeaff6f1	3512	}
nikapov	0:a1a69d32f310	3513
nikapov	0:a1a69d32f310	3514	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3515	status = VL53L0X_write_byte(0xFF,0x00);
nikapov	0:a1a69d32f310	3516	}
nikapov	0:a1a69d32f310	3517
nikapov	0:a1a69d32f310	3518	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3519	status = VL53L0X_write_byte(VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT,
nikapov	0:a1a69d32f310	3520	start_select);
Davidroid	2:d07edeaff6f1	3521	}
nikapov	0:a1a69d32f310	3522
nikapov	0:a1a69d32f310	3523	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3524	status = VL53L0X_write_byte(VL53L0X_REG_POWER_MANAGEMENT_GO1_POWER_FORCE,0);
Davidroid	2:d07edeaff6f1	3525	}
nikapov	0:a1a69d32f310	3526
nikapov	0:a1a69d32f310	3527	/* Perform ref calibration */
nikapov	0:a1a69d32f310	3528	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3529	status = VL53L0X_perform_ref_calibration(&vhv_settings,
sepp_nepp	7:41cbc431e1f4	3530	&phase_cal,0);
Davidroid	2:d07edeaff6f1	3531	}
nikapov	0:a1a69d32f310	3532
nikapov	0:a1a69d32f310	3533	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3534	/* Enable Minimum NON-APERTURE Spads */
nikapov	0:a1a69d32f310	3535	current_spad_index = 0;
nikapov	0:a1a69d32f310	3536	last_spad_index = current_spad_index;
nikapov	0:a1a69d32f310	3537	need_apt_spads = 0;
sepp_nepp	7:41cbc431e1f4	3538	status = enable_ref_spads(need_apt_spads,
sepp_nepp	7:41cbc431e1f4	3539	_device->SpadData.RefGoodSpadMap,
sepp_nepp	7:41cbc431e1f4	3540	_device->SpadData.RefSpadEnables,
nikapov	0:a1a69d32f310	3541	spad_array_size,
nikapov	0:a1a69d32f310	3542	start_select,
nikapov	0:a1a69d32f310	3543	current_spad_index,
nikapov	0:a1a69d32f310	3544	minimum_spad_count,
nikapov	0:a1a69d32f310	3545	&last_spad_index);
nikapov	0:a1a69d32f310	3546	}
nikapov	0:a1a69d32f310	3547
nikapov	0:a1a69d32f310	3548	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3549	current_spad_index = last_spad_index;
nikapov	0:a1a69d32f310	3550
sepp_nepp	7:41cbc431e1f4	3551	status = perform_ref_signal_measurement(&peak_signal_rate_ref);
nikapov	0:a1a69d32f310	3552	if ((status == VL53L0X_ERROR_NONE) &&
nikapov	0:a1a69d32f310	3553	(peak_signal_rate_ref > target_ref_rate)) {
nikapov	0:a1a69d32f310	3554	/* Signal rate measurement too high,
nikapov	0:a1a69d32f310	3555	* switch to APERTURE SPADs */
nikapov	0:a1a69d32f310	3556
nikapov	0:a1a69d32f310	3557	for (index = 0; index < spad_array_size; index++) {
sepp_nepp	7:41cbc431e1f4	3558	_device->SpadData.RefSpadEnables[index] = 0;
nikapov	0:a1a69d32f310	3559	}
nikapov	0:a1a69d32f310	3560
nikapov	0:a1a69d32f310	3561
nikapov	0:a1a69d32f310	3562	/* Increment to the first APERTURE spad */
nikapov	0:a1a69d32f310	3563	while ((is_aperture(start_select + current_spad_index)
nikapov	0:a1a69d32f310	3564	== 0) && (current_spad_index < max_spad_count)) {
nikapov	0:a1a69d32f310	3565	current_spad_index++;
nikapov	0:a1a69d32f310	3566	}
nikapov	0:a1a69d32f310	3567
nikapov	0:a1a69d32f310	3568	need_apt_spads = 1;
nikapov	0:a1a69d32f310	3569
sepp_nepp	7:41cbc431e1f4	3570	status = enable_ref_spads(need_apt_spads,
sepp_nepp	7:41cbc431e1f4	3571	_device->SpadData.RefGoodSpadMap,
sepp_nepp	7:41cbc431e1f4	3572	_device->SpadData.RefSpadEnables,
nikapov	0:a1a69d32f310	3573	spad_array_size,
nikapov	0:a1a69d32f310	3574	start_select,
nikapov	0:a1a69d32f310	3575	current_spad_index,
nikapov	0:a1a69d32f310	3576	minimum_spad_count,
nikapov	0:a1a69d32f310	3577	&last_spad_index);
nikapov	0:a1a69d32f310	3578
nikapov	0:a1a69d32f310	3579	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3580	current_spad_index = last_spad_index;
sepp_nepp	7:41cbc431e1f4	3581	status = perform_ref_signal_measurement(&peak_signal_rate_ref);
nikapov	0:a1a69d32f310	3582
nikapov	0:a1a69d32f310	3583	if ((status == VL53L0X_ERROR_NONE) &&
nikapov	0:a1a69d32f310	3584	(peak_signal_rate_ref > target_ref_rate)) {
nikapov	0:a1a69d32f310	3585	/* Signal rate still too high after
nikapov	0:a1a69d32f310	3586	* setting the minimum number of
nikapov	0:a1a69d32f310	3587	* APERTURE spads. Can do no more
nikapov	0:a1a69d32f310	3588	* therefore set the min number of
nikapov	0:a1a69d32f310	3589	* aperture spads as the result.
nikapov	0:a1a69d32f310	3590	*/
nikapov	0:a1a69d32f310	3591	is_aperture_spads_int = 1;
nikapov	0:a1a69d32f310	3592	ref_spad_count_int = minimum_spad_count;
nikapov	0:a1a69d32f310	3593	}
nikapov	0:a1a69d32f310	3594	}
nikapov	0:a1a69d32f310	3595	} else {
nikapov	0:a1a69d32f310	3596	need_apt_spads = 0;
nikapov	0:a1a69d32f310	3597	}
nikapov	0:a1a69d32f310	3598	}
nikapov	0:a1a69d32f310	3599
nikapov	0:a1a69d32f310	3600	if ((status == VL53L0X_ERROR_NONE) &&
nikapov	0:a1a69d32f310	3601	(peak_signal_rate_ref < target_ref_rate)) {
sepp_nepp	7:41cbc431e1f4	3602	/* At this point,the minimum number of either aperture
nikapov	0:a1a69d32f310	3603	* or non-aperture spads have been set. Proceed to add
nikapov	0:a1a69d32f310	3604	* spads and perform measurements until the target
nikapov	0:a1a69d32f310	3605	* reference is reached.
nikapov	0:a1a69d32f310	3606	*/
nikapov	0:a1a69d32f310	3607	is_aperture_spads_int = need_apt_spads;
nikapov	0:a1a69d32f310	3608	ref_spad_count_int = minimum_spad_count;
nikapov	0:a1a69d32f310	3609
sepp_nepp	7:41cbc431e1f4	3610	memcpy(last_spad_array,_device->SpadData.RefSpadEnables,
nikapov	0:a1a69d32f310	3611	spad_array_size);
nikapov	0:a1a69d32f310	3612	last_signal_rate_diff = abs(peak_signal_rate_ref -
nikapov	0:a1a69d32f310	3613	target_ref_rate);
nikapov	0:a1a69d32f310	3614	complete = 0;
nikapov	0:a1a69d32f310	3615
nikapov	0:a1a69d32f310	3616	while (!complete) {
sepp_nepp	7:41cbc431e1f4	3617	get_next_good_spad(_device->SpadData.RefGoodSpadMap,
sepp_nepp	7:41cbc431e1f4	3618	spad_array_size,current_spad_index,
nikapov	0:a1a69d32f310	3619	&next_good_spad);
nikapov	0:a1a69d32f310	3620
nikapov	0:a1a69d32f310	3621	if (next_good_spad == -1) {
nikapov	0:a1a69d32f310	3622	status = VL53L0X_ERROR_REF_SPAD_INIT;
nikapov	0:a1a69d32f310	3623	break;
nikapov	0:a1a69d32f310	3624	}
nikapov	0:a1a69d32f310	3625
sepp_nepp	7:41cbc431e1f4	3626	/* Cannot combine Aperture and Non-Aperture spads,so
nikapov	0:a1a69d32f310	3627	* ensure the current spad is of the correct type.
nikapov	0:a1a69d32f310	3628	*/
nikapov	0:a1a69d32f310	3629	if (is_aperture((uint32_t)start_select + next_good_spad) !=
nikapov	0:a1a69d32f310	3630	need_apt_spads) {
nikapov	0:a1a69d32f310	3631	/* At this point we have enabled the maximum
nikapov	0:a1a69d32f310	3632	* number of Aperture spads.
nikapov	0:a1a69d32f310	3633	*/
nikapov	0:a1a69d32f310	3634	complete = 1;
nikapov	0:a1a69d32f310	3635	break;
nikapov	0:a1a69d32f310	3636	}
nikapov	0:a1a69d32f310	3637
nikapov	0:a1a69d32f310	3638	(ref_spad_count_int)++;
nikapov	0:a1a69d32f310	3639
nikapov	0:a1a69d32f310	3640	current_spad_index = next_good_spad;
sepp_nepp	7:41cbc431e1f4	3641	status = enable_spad_bit(_device->SpadData.RefSpadEnables,
sepp_nepp	7:41cbc431e1f4	3642	spad_array_size,current_spad_index);
nikapov	0:a1a69d32f310	3643
nikapov	0:a1a69d32f310	3644	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3645	current_spad_index++;
nikapov	0:a1a69d32f310	3646	/* Proceed to apply the additional spad and
nikapov	0:a1a69d32f310	3647	* perform measurement. */
sepp_nepp	7:41cbc431e1f4	3648	status = set_ref_spad_map(_device->SpadData.RefSpadEnables);
nikapov	0:a1a69d32f310	3649	}
nikapov	0:a1a69d32f310	3650
nikapov	0:a1a69d32f310	3651	if (status != VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3652	break;
nikapov	0:a1a69d32f310	3653	}
nikapov	0:a1a69d32f310	3654
sepp_nepp	7:41cbc431e1f4	3655	status = perform_ref_signal_measurement(&peak_signal_rate_ref);
nikapov	0:a1a69d32f310	3656
nikapov	0:a1a69d32f310	3657	if (status != VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3658	break;
nikapov	0:a1a69d32f310	3659	}
nikapov	0:a1a69d32f310	3660
nikapov	0:a1a69d32f310	3661	signal_rate_diff = abs(peak_signal_rate_ref - target_ref_rate);
nikapov	0:a1a69d32f310	3662
nikapov	0:a1a69d32f310	3663	if (peak_signal_rate_ref > target_ref_rate) {
nikapov	0:a1a69d32f310	3664	/* Select the spad map that provides the
nikapov	0:a1a69d32f310	3665	* measurement closest to the target rate,
nikapov	0:a1a69d32f310	3666	* either above or below it.
nikapov	0:a1a69d32f310	3667	*/
nikapov	0:a1a69d32f310	3668	if (signal_rate_diff > last_signal_rate_diff) {
nikapov	0:a1a69d32f310	3669	/* Previous spad map produced a closer
sepp_nepp	7:41cbc431e1f4	3670	* measurement,so choose this. */
sepp_nepp	7:41cbc431e1f4	3671	status = set_ref_spad_map(last_spad_array);
sepp_nepp	7:41cbc431e1f4	3672	memcpy(_device->SpadData.RefSpadEnables,
sepp_nepp	7:41cbc431e1f4	3673	last_spad_array,spad_array_size);
nikapov	0:a1a69d32f310	3674
nikapov	0:a1a69d32f310	3675	(ref_spad_count_int)--;
nikapov	0:a1a69d32f310	3676	}
nikapov	0:a1a69d32f310	3677	complete = 1;
nikapov	0:a1a69d32f310	3678	} else {
nikapov	0:a1a69d32f310	3679	/* Continue to add spads */
nikapov	0:a1a69d32f310	3680	last_signal_rate_diff = signal_rate_diff;
nikapov	0:a1a69d32f310	3681	memcpy(last_spad_array,
sepp_nepp	7:41cbc431e1f4	3682	_device->SpadData.RefSpadEnables,
nikapov	0:a1a69d32f310	3683	spad_array_size);
nikapov	0:a1a69d32f310	3684	}
nikapov	0:a1a69d32f310	3685
nikapov	0:a1a69d32f310	3686	} /* while */
nikapov	0:a1a69d32f310	3687	}
nikapov	0:a1a69d32f310	3688
nikapov	0:a1a69d32f310	3689	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3690	*ref_spad_count = ref_spad_count_int;
nikapov	0:a1a69d32f310	3691	*is_aperture_spads = is_aperture_spads_int;
nikapov	0:a1a69d32f310	3692
sepp_nepp	7:41cbc431e1f4	3693	_device->DeviceSpecificParameters.RefSpadsInitialised = 1;
sepp_nepp	7:41cbc431e1f4	3694	_device->DeviceSpecificParameters.ReferenceSpadCount = (uint8_t)(*ref_spad_count);
sepp_nepp	7:41cbc431e1f4	3695	_device->DeviceSpecificParameters.ReferenceSpadType = *is_aperture_spads;
nikapov	0:a1a69d32f310	3696	}
nikapov	0:a1a69d32f310	3697
nikapov	0:a1a69d32f310	3698	return status;
nikapov	0:a1a69d32f310	3699	}
nikapov	0:a1a69d32f310	3700
sepp_nepp	7:41cbc431e1f4	3701	VL53L0X_Error VL53L0X::VL53L0X_set_reference_spads(uint32_t count,uint8_t is_aperture_spads)
nikapov	0:a1a69d32f310	3702	{
nikapov	0:a1a69d32f310	3703	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	3704	uint32_t current_spad_index = 0;
nikapov	0:a1a69d32f310	3705	uint8_t start_select = 0xB4;
nikapov	0:a1a69d32f310	3706	uint32_t spad_array_size = 6;
nikapov	0:a1a69d32f310	3707	uint32_t max_spad_count = 44;
nikapov	0:a1a69d32f310	3708	uint32_t last_spad_index;
nikapov	0:a1a69d32f310	3709	uint32_t index;
nikapov	0:a1a69d32f310	3710
nikapov	0:a1a69d32f310	3711	/*
sepp_nepp	7:41cbc431e1f4	3712	* This function applies a requested number of reference spads,either
nikapov	0:a1a69d32f310	3713	* aperture or
sepp_nepp	7:41cbc431e1f4	3714	* non-aperture,as requested.
nikapov	0:a1a69d32f310	3715	* The good spad map will be applied.
nikapov	0:a1a69d32f310	3716	*/
nikapov	0:a1a69d32f310	3717
sepp_nepp	7:41cbc431e1f4	3718	status = VL53L0X_write_byte(0xFF,0x01);
nikapov	0:a1a69d32f310	3719
nikapov	0:a1a69d32f310	3720	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3721	status = VL53L0X_write_byte(VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET,0x00);
Davidroid	2:d07edeaff6f1	3722	}
nikapov	0:a1a69d32f310	3723
nikapov	0:a1a69d32f310	3724	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3725	status = VL53L0X_write_byte(VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD,0x2C);
Davidroid	2:d07edeaff6f1	3726	}
nikapov	0:a1a69d32f310	3727
nikapov	0:a1a69d32f310	3728	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3729	status = VL53L0X_write_byte(0xFF,0x00);
Davidroid	2:d07edeaff6f1	3730	}
nikapov	0:a1a69d32f310	3731
nikapov	0:a1a69d32f310	3732	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3733	status = VL53L0X_write_byte(VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT,
nikapov	0:a1a69d32f310	3734	start_select);
Davidroid	2:d07edeaff6f1	3735	}
nikapov	0:a1a69d32f310	3736
nikapov	0:a1a69d32f310	3737	for (index = 0; index < spad_array_size; index++) {
sepp_nepp	7:41cbc431e1f4	3738	_device->SpadData.RefSpadEnables[index] = 0;
Davidroid	2:d07edeaff6f1	3739	}
nikapov	0:a1a69d32f310	3740
nikapov	0:a1a69d32f310	3741	if (is_aperture_spads) {
nikapov	0:a1a69d32f310	3742	/* Increment to the first APERTURE spad */
nikapov	0:a1a69d32f310	3743	while ((is_aperture(start_select + current_spad_index) == 0) &&
nikapov	0:a1a69d32f310	3744	(current_spad_index < max_spad_count)) {
nikapov	0:a1a69d32f310	3745	current_spad_index++;
nikapov	0:a1a69d32f310	3746	}
nikapov	0:a1a69d32f310	3747	}
sepp_nepp	7:41cbc431e1f4	3748	status = enable_ref_spads(is_aperture_spads,
sepp_nepp	7:41cbc431e1f4	3749	_device->SpadData.RefGoodSpadMap,
sepp_nepp	7:41cbc431e1f4	3750	_device->SpadData.RefSpadEnables,
nikapov	0:a1a69d32f310	3751	spad_array_size,
nikapov	0:a1a69d32f310	3752	start_select,
nikapov	0:a1a69d32f310	3753	current_spad_index,
nikapov	0:a1a69d32f310	3754	count,
nikapov	0:a1a69d32f310	3755	&last_spad_index);
nikapov	0:a1a69d32f310	3756
nikapov	0:a1a69d32f310	3757	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3758	_device->DeviceSpecificParameters.RefSpadsInitialised = 1;
sepp_nepp	7:41cbc431e1f4	3759	_device->DeviceSpecificParameters.ReferenceSpadCount = (uint8_t)(count);
sepp_nepp	7:41cbc431e1f4	3760	_device->DeviceSpecificParameters.ReferenceSpadType = is_aperture_spads;
nikapov	0:a1a69d32f310	3761	}
nikapov	0:a1a69d32f310	3762
nikapov	0:a1a69d32f310	3763	return status;
nikapov	0:a1a69d32f310	3764	}
nikapov	0:a1a69d32f310	3765
sepp_nepp	7:41cbc431e1f4	3766	VL53L0X_Error VL53L0X::VL53L0X_wait_device_booted()
nikapov	0:a1a69d32f310	3767	{
nikapov	0:a1a69d32f310	3768	VL53L0X_Error status = VL53L0X_ERROR_NOT_IMPLEMENTED;
sepp_nepp	5:b95f6951f7d5	3769
nikapov	0:a1a69d32f310	3770
nikapov	0:a1a69d32f310	3771	/* not implemented on VL53L0X */
nikapov	0:a1a69d32f310	3772
sepp_nepp	5:b95f6951f7d5	3773
nikapov	0:a1a69d32f310	3774	return status;
nikapov	0:a1a69d32f310	3775	}
nikapov	0:a1a69d32f310	3776
sepp_nepp	7:41cbc431e1f4	3777	VL53L0X_Error VL53L0X::VL53L0X_perform_ref_calibration(uint8_t *p_vhv_settings,
nikapov	0:a1a69d32f310	3778	uint8_t *p_phase_cal)
nikapov	0:a1a69d32f310	3779	{
nikapov	0:a1a69d32f310	3780	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	3781
nikapov	0:a1a69d32f310	3782
sepp_nepp	7:41cbc431e1f4	3783	status = VL53L0X_perform_ref_calibration(p_vhv_settings,
sepp_nepp	7:41cbc431e1f4	3784	p_phase_cal,1);
nikapov	0:a1a69d32f310	3785
sepp_nepp	5:b95f6951f7d5	3786
nikapov	0:a1a69d32f310	3787	return status;
nikapov	0:a1a69d32f310	3788	}
nikapov	0:a1a69d32f310	3789
sepp_nepp	7:41cbc431e1f4	3790	VL53L0X_Error VL53L0X::VL53L0X_perform_ref_spad_management(uint32_t ref_spad_count,uint8_t is_aperture_spads)
nikapov	0:a1a69d32f310	3791	{
nikapov	0:a1a69d32f310	3792	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	3793
nikapov	0:a1a69d32f310	3794
sepp_nepp	7:41cbc431e1f4	3795	status = wrapped_VL53L0X_perform_ref_spad_management(ref_spad_count,
nikapov	0:a1a69d32f310	3796	is_aperture_spads);
nikapov	0:a1a69d32f310	3797
sepp_nepp	5:b95f6951f7d5	3798
nikapov	0:a1a69d32f310	3799
nikapov	0:a1a69d32f310	3800	return status;
nikapov	0:a1a69d32f310	3801	}
nikapov	0:a1a69d32f310	3802
nikapov	0:a1a69d32f310	3803	/* Group PAL Init Functions */
sepp_nepp	7:41cbc431e1f4	3804	VL53L0X_Error VL53L0X::VL53L0X_set_device_address(uint8_t device_address)
nikapov	0:a1a69d32f310	3805	{
nikapov	0:a1a69d32f310	3806	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	3807
nikapov	0:a1a69d32f310	3808
sepp_nepp	7:41cbc431e1f4	3809	status = VL53L0X_write_byte(VL53L0X_REG_I2C_SLAVE_DEVICE_ADDRESS,
nikapov	0:a1a69d32f310	3810	device_address / 2);
nikapov	0:a1a69d32f310	3811
sepp_nepp	5:b95f6951f7d5	3812
nikapov	0:a1a69d32f310	3813	return status;
nikapov	0:a1a69d32f310	3814	}
nikapov	0:a1a69d32f310	3815
sepp_nepp	7:41cbc431e1f4	3816	VL53L0X_Error VL53L0X::VL53L0X_set_gpio_config(uint8_t pin,
sepp_nepp	7:41cbc431e1f4	3817	VL53L0X_DeviceModes device_mode,VL53L0X_GpioFunctionality functionality,
nikapov	0:a1a69d32f310	3818	VL53L0X_InterruptPolarity polarity)
nikapov	0:a1a69d32f310	3819	{
nikapov	0:a1a69d32f310	3820	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	3821	uint8_t data;
nikapov	0:a1a69d32f310	3822
sepp_nepp	5:b95f6951f7d5	3823
nikapov	0:a1a69d32f310	3824
nikapov	0:a1a69d32f310	3825	if (pin != 0) {
nikapov	0:a1a69d32f310	3826	status = VL53L0X_ERROR_GPIO_NOT_EXISTING;
nikapov	0:a1a69d32f310	3827	} else if (device_mode == VL53L0X_DEVICEMODE_GPIO_DRIVE) {
nikapov	0:a1a69d32f310	3828	if (polarity == VL53L0X_INTERRUPTPOLARITY_LOW) {
nikapov	0:a1a69d32f310	3829	data = 0x10;
nikapov	0:a1a69d32f310	3830	} else {
nikapov	0:a1a69d32f310	3831	data = 1;
nikapov	0:a1a69d32f310	3832	}
nikapov	0:a1a69d32f310	3833
sepp_nepp	7:41cbc431e1f4	3834	status = VL53L0X_write_byte(VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH,data);
nikapov	0:a1a69d32f310	3835
nikapov	0:a1a69d32f310	3836	} else {
Davidroid	2:d07edeaff6f1	3837	if (device_mode == VL53L0X_DEVICEMODE_GPIO_OSC) {
Davidroid	2:d07edeaff6f1	3838
sepp_nepp	7:41cbc431e1f4	3839	status \|= VL53L0X_write_byte(0xff,0x01);
sepp_nepp	7:41cbc431e1f4	3840	status \|= VL53L0X_write_byte(0x00,0x00);
sepp_nepp	7:41cbc431e1f4	3841
sepp_nepp	7:41cbc431e1f4	3842	status \|= VL53L0X_write_byte(0xff,0x00);
sepp_nepp	7:41cbc431e1f4	3843	status \|= VL53L0X_write_byte(0x80,0x01);
sepp_nepp	7:41cbc431e1f4	3844	status \|= VL53L0X_write_byte(0x85,0x02);
sepp_nepp	7:41cbc431e1f4	3845
sepp_nepp	7:41cbc431e1f4	3846	status \|= VL53L0X_write_byte(0xff,0x04);
sepp_nepp	7:41cbc431e1f4	3847	status \|= VL53L0X_write_byte(0xcd,0x00);
sepp_nepp	7:41cbc431e1f4	3848	status \|= VL53L0X_write_byte(0xcc,0x11);
sepp_nepp	7:41cbc431e1f4	3849
sepp_nepp	7:41cbc431e1f4	3850	status \|= VL53L0X_write_byte(0xff,0x07);
sepp_nepp	7:41cbc431e1f4	3851	status \|= VL53L0X_write_byte(0xbe,0x00);
sepp_nepp	7:41cbc431e1f4	3852
sepp_nepp	7:41cbc431e1f4	3853	status \|= VL53L0X_write_byte(0xff,0x06);
sepp_nepp	7:41cbc431e1f4	3854	status \|= VL53L0X_write_byte(0xcc,0x09);
sepp_nepp	7:41cbc431e1f4	3855
sepp_nepp	7:41cbc431e1f4	3856	status \|= VL53L0X_write_byte(0xff,0x00);
sepp_nepp	7:41cbc431e1f4	3857	status \|= VL53L0X_write_byte(0xff,0x01);
sepp_nepp	7:41cbc431e1f4	3858	status \|= VL53L0X_write_byte(0x00,0x00);
Davidroid	2:d07edeaff6f1	3859
Davidroid	2:d07edeaff6f1	3860	} else {
Davidroid	2:d07edeaff6f1	3861
Davidroid	2:d07edeaff6f1	3862	if (status == VL53L0X_ERROR_NONE) {
Davidroid	2:d07edeaff6f1	3863	switch (functionality) {
Davidroid	2:d07edeaff6f1	3864	case VL53L0X_GPIOFUNCTIONALITY_OFF:
Davidroid	2:d07edeaff6f1	3865	data = 0x00;
Davidroid	2:d07edeaff6f1	3866	break;
Davidroid	2:d07edeaff6f1	3867	case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW:
Davidroid	2:d07edeaff6f1	3868	data = 0x01;
Davidroid	2:d07edeaff6f1	3869	break;
Davidroid	2:d07edeaff6f1	3870	case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH:
Davidroid	2:d07edeaff6f1	3871	data = 0x02;
Davidroid	2:d07edeaff6f1	3872	break;
Davidroid	2:d07edeaff6f1	3873	case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT:
Davidroid	2:d07edeaff6f1	3874	data = 0x03;
Davidroid	2:d07edeaff6f1	3875	break;
Davidroid	2:d07edeaff6f1	3876	case VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY:
Davidroid	2:d07edeaff6f1	3877	data = 0x04;
Davidroid	2:d07edeaff6f1	3878	break;
Davidroid	2:d07edeaff6f1	3879	default:
Davidroid	2:d07edeaff6f1	3880	status =
Davidroid	2:d07edeaff6f1	3881	VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED;
Davidroid	2:d07edeaff6f1	3882	}
Davidroid	2:d07edeaff6f1	3883	}
Davidroid	2:d07edeaff6f1	3884
Davidroid	2:d07edeaff6f1	3885	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3886	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO,data);
Davidroid	2:d07edeaff6f1	3887	}
Davidroid	2:d07edeaff6f1	3888
Davidroid	2:d07edeaff6f1	3889	if (status == VL53L0X_ERROR_NONE) {
Davidroid	2:d07edeaff6f1	3890	if (polarity == VL53L0X_INTERRUPTPOLARITY_LOW) {
Davidroid	2:d07edeaff6f1	3891	data = 0;
Davidroid	2:d07edeaff6f1	3892	} else {
Davidroid	2:d07edeaff6f1	3893	data = (uint8_t)(1 << 4);
Davidroid	2:d07edeaff6f1	3894	}
sepp_nepp	7:41cbc431e1f4	3895	status = VL53L0X_update_byte(VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH,0xEF,data);
Davidroid	2:d07edeaff6f1	3896	}
Davidroid	2:d07edeaff6f1	3897
Davidroid	2:d07edeaff6f1	3898	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3899	_device->DeviceSpecificParameters.Pin0GpioFunctionality = functionality;
Davidroid	2:d07edeaff6f1	3900	}
Davidroid	2:d07edeaff6f1	3901
Davidroid	2:d07edeaff6f1	3902	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3903	status = VL53L0X_clear_interrupt_mask(0);
Davidroid	2:d07edeaff6f1	3904	}
Davidroid	2:d07edeaff6f1	3905	}
nikapov	0:a1a69d32f310	3906	}
sepp_nepp	5:b95f6951f7d5	3907
nikapov	0:a1a69d32f310	3908	return status;
nikapov	0:a1a69d32f310	3909	}
nikapov	0:a1a69d32f310	3910
sepp_nepp	7:41cbc431e1f4	3911	VL53L0X_Error VL53L0X::VL53L0X_get_fraction_enable(uint8_t *p_enabled)
nikapov	0:a1a69d32f310	3912	{
nikapov	0:a1a69d32f310	3913	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	3914
nikapov	0:a1a69d32f310	3915
sepp_nepp	7:41cbc431e1f4	3916	status = VL53L0X_read_byte(VL53L0X_REG_SYSTEM_RANGE_CONFIG,p_enabled);
nikapov	0:a1a69d32f310	3917
nikapov	0:a1a69d32f310	3918	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	3919	p_enabled = (p_enabled & 1);
nikapov	0:a1a69d32f310	3920	}
nikapov	0:a1a69d32f310	3921
sepp_nepp	5:b95f6951f7d5	3922
nikapov	0:a1a69d32f310	3923	return status;
nikapov	0:a1a69d32f310	3924	}
nikapov	0:a1a69d32f310	3925
nikapov	0:a1a69d32f310	3926	uint16_t VL53L0X::VL53L0X_encode_timeout(uint32_t timeout_macro_clks)
nikapov	0:a1a69d32f310	3927	{
nikapov	0:a1a69d32f310	3928	/*!
nikapov	0:a1a69d32f310	3929	* Encode timeout in macro periods in (LSByte * 2^MSByte) + 1 format
nikapov	0:a1a69d32f310	3930	*/
nikapov	0:a1a69d32f310	3931
nikapov	0:a1a69d32f310	3932	uint16_t encoded_timeout = 0;
nikapov	0:a1a69d32f310	3933	uint32_t ls_byte = 0;
nikapov	0:a1a69d32f310	3934	uint16_t ms_byte = 0;
nikapov	0:a1a69d32f310	3935
nikapov	0:a1a69d32f310	3936	if (timeout_macro_clks > 0) {
nikapov	0:a1a69d32f310	3937	ls_byte = timeout_macro_clks - 1;
nikapov	0:a1a69d32f310	3938
nikapov	0:a1a69d32f310	3939	while ((ls_byte & 0xFFFFFF00) > 0) {
nikapov	0:a1a69d32f310	3940	ls_byte = ls_byte >> 1;
nikapov	0:a1a69d32f310	3941	ms_byte++;
nikapov	0:a1a69d32f310	3942	}
nikapov	0:a1a69d32f310	3943
nikapov	0:a1a69d32f310	3944	encoded_timeout = (ms_byte << 8)
nikapov	0:a1a69d32f310	3945	+ (uint16_t)(ls_byte & 0x000000FF);
nikapov	0:a1a69d32f310	3946	}
nikapov	0:a1a69d32f310	3947
nikapov	0:a1a69d32f310	3948	return encoded_timeout;
nikapov	0:a1a69d32f310	3949
nikapov	0:a1a69d32f310	3950	}
nikapov	0:a1a69d32f310	3951
sepp_nepp	7:41cbc431e1f4	3952	VL53L0X_Error VL53L0X::set_sequence_step_timeout(VL53L0X_SequenceStepId sequence_step_id,
nikapov	0:a1a69d32f310	3953	uint32_t timeout_micro_secs)
nikapov	0:a1a69d32f310	3954	{
nikapov	0:a1a69d32f310	3955	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	3956	uint8_t current_vcsel_pulse_period_p_clk;
nikapov	0:a1a69d32f310	3957	uint8_t msrc_encoded_time_out;
nikapov	0:a1a69d32f310	3958	uint16_t pre_range_encoded_time_out;
nikapov	0:a1a69d32f310	3959	uint16_t pre_range_time_out_m_clks;
nikapov	0:a1a69d32f310	3960	uint16_t msrc_range_time_out_m_clks;
nikapov	0:a1a69d32f310	3961	uint32_t final_range_time_out_m_clks;
nikapov	0:a1a69d32f310	3962	uint16_t final_range_encoded_time_out;
nikapov	0:a1a69d32f310	3963	VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
nikapov	0:a1a69d32f310	3964
nikapov	0:a1a69d32f310	3965	if ((sequence_step_id == VL53L0X_SEQUENCESTEP_TCC) \|\|
nikapov	0:a1a69d32f310	3966	(sequence_step_id == VL53L0X_SEQUENCESTEP_DSS) \|\|
nikapov	0:a1a69d32f310	3967	(sequence_step_id == VL53L0X_SEQUENCESTEP_MSRC)) {
nikapov	0:a1a69d32f310	3968
sepp_nepp	7:41cbc431e1f4	3969	status = VL53L0X_get_vcsel_pulse_period(VL53L0X_VCSEL_PERIOD_PRE_RANGE,
nikapov	0:a1a69d32f310	3970	&current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	3971
nikapov	0:a1a69d32f310	3972	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3973	msrc_range_time_out_m_clks = VL53L0X_calc_timeout_mclks(timeout_micro_secs,
nikapov	0:a1a69d32f310	3974	(uint8_t)current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	3975
nikapov	0:a1a69d32f310	3976	if (msrc_range_time_out_m_clks > 256) {
nikapov	0:a1a69d32f310	3977	msrc_encoded_time_out = 255;
nikapov	0:a1a69d32f310	3978	} else {
nikapov	0:a1a69d32f310	3979	msrc_encoded_time_out =
nikapov	0:a1a69d32f310	3980	(uint8_t)msrc_range_time_out_m_clks - 1;
nikapov	0:a1a69d32f310	3981	}
nikapov	0:a1a69d32f310	3982
sepp_nepp	7:41cbc431e1f4	3983	_device->DeviceSpecificParameters.LastEncodedTimeout = msrc_encoded_time_out;
nikapov	0:a1a69d32f310	3984	}
nikapov	0:a1a69d32f310	3985
nikapov	0:a1a69d32f310	3986	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3987	status = VL53L0X_write_byte(VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP,
nikapov	0:a1a69d32f310	3988	msrc_encoded_time_out);
nikapov	0:a1a69d32f310	3989	}
nikapov	0:a1a69d32f310	3990	} else {
nikapov	0:a1a69d32f310	3991
nikapov	0:a1a69d32f310	3992	if (sequence_step_id == VL53L0X_SEQUENCESTEP_PRE_RANGE) {
nikapov	0:a1a69d32f310	3993
nikapov	0:a1a69d32f310	3994	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	3995	status = VL53L0X_get_vcsel_pulse_period(VL53L0X_VCSEL_PERIOD_PRE_RANGE,
nikapov	0:a1a69d32f310	3996	&current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	3997	pre_range_time_out_m_clks =
sepp_nepp	7:41cbc431e1f4	3998	VL53L0X_calc_timeout_mclks(timeout_micro_secs,
nikapov	0:a1a69d32f310	3999	(uint8_t)current_vcsel_pulse_period_p_clk);
sepp_nepp	7:41cbc431e1f4	4000	pre_range_encoded_time_out = VL53L0X_encode_timeout(pre_range_time_out_m_clks);
sepp_nepp	7:41cbc431e1f4	4001
sepp_nepp	7:41cbc431e1f4	4002	_device->DeviceSpecificParameters.LastEncodedTimeout = pre_range_encoded_time_out;
nikapov	0:a1a69d32f310	4003	}
nikapov	0:a1a69d32f310	4004
nikapov	0:a1a69d32f310	4005	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4006	status = VL53L0X_write_word(VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
nikapov	0:a1a69d32f310	4007	pre_range_encoded_time_out);
nikapov	0:a1a69d32f310	4008	}
nikapov	0:a1a69d32f310	4009
nikapov	0:a1a69d32f310	4010	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4011	_device->DeviceSpecificParameters.PreRangeTimeoutMicroSecs=timeout_micro_secs;
nikapov	0:a1a69d32f310	4012	}
nikapov	0:a1a69d32f310	4013	} else if (sequence_step_id == VL53L0X_SEQUENCESTEP_FINAL_RANGE) {
nikapov	0:a1a69d32f310	4014
sepp_nepp	7:41cbc431e1f4	4015	/* For the final range timeout,the pre-range timeout
nikapov	0:a1a69d32f310	4016	* must be added. To do this both final and pre-range
nikapov	0:a1a69d32f310	4017	* timeouts must be expressed in macro periods MClks
nikapov	0:a1a69d32f310	4018	* because they have different vcsel periods.
nikapov	0:a1a69d32f310	4019	*/
nikapov	0:a1a69d32f310	4020
sepp_nepp	7:41cbc431e1f4	4021	VL53L0X_get_sequence_step_enables(&scheduler_sequence_steps);
nikapov	0:a1a69d32f310	4022	pre_range_time_out_m_clks = 0;
nikapov	0:a1a69d32f310	4023	if (scheduler_sequence_steps.PreRangeOn) {
nikapov	0:a1a69d32f310	4024
nikapov	0:a1a69d32f310	4025	/* Retrieve PRE-RANGE VCSEL Period */
sepp_nepp	7:41cbc431e1f4	4026	status = VL53L0X_get_vcsel_pulse_period(VL53L0X_VCSEL_PERIOD_PRE_RANGE,
nikapov	0:a1a69d32f310	4027	&current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	4028
nikapov	0:a1a69d32f310	4029	/* Retrieve PRE-RANGE Timeout in Macro periods
nikapov	0:a1a69d32f310	4030	* (MCLKS) */
nikapov	0:a1a69d32f310	4031	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4032	status = VL53L0X_read_word(0x51,
nikapov	0:a1a69d32f310	4033	&pre_range_encoded_time_out);
nikapov	0:a1a69d32f310	4034	pre_range_time_out_m_clks =
sepp_nepp	7:41cbc431e1f4	4035	VL53L0X_decode_timeout(pre_range_encoded_time_out);
nikapov	0:a1a69d32f310	4036	}
nikapov	0:a1a69d32f310	4037	}
nikapov	0:a1a69d32f310	4038
nikapov	0:a1a69d32f310	4039	/* Calculate FINAL RANGE Timeout in Macro Periods
nikapov	0:a1a69d32f310	4040	* (MCLKS) and add PRE-RANGE value
nikapov	0:a1a69d32f310	4041	*/
nikapov	0:a1a69d32f310	4042	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4043	status = VL53L0X_get_vcsel_pulse_period(VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
nikapov	0:a1a69d32f310	4044	&current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	4045	}
nikapov	0:a1a69d32f310	4046	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4047	final_range_time_out_m_clks =
sepp_nepp	7:41cbc431e1f4	4048	VL53L0X_calc_timeout_mclks(timeout_micro_secs,
nikapov	0:a1a69d32f310	4049	(uint8_t) current_vcsel_pulse_period_p_clk);
nikapov	0:a1a69d32f310	4050
nikapov	0:a1a69d32f310	4051	final_range_time_out_m_clks += pre_range_time_out_m_clks;
nikapov	0:a1a69d32f310	4052
nikapov	0:a1a69d32f310	4053	final_range_encoded_time_out =
nikapov	0:a1a69d32f310	4054	VL53L0X_encode_timeout(final_range_time_out_m_clks);
nikapov	0:a1a69d32f310	4055
nikapov	0:a1a69d32f310	4056	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4057	status = VL53L0X_write_word(0x71,
nikapov	0:a1a69d32f310	4058	final_range_encoded_time_out);
nikapov	0:a1a69d32f310	4059	}
nikapov	0:a1a69d32f310	4060
nikapov	0:a1a69d32f310	4061	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4062	_device->DeviceSpecificParameters.FinalRangeTimeoutMicroSecs = timeout_micro_secs;
nikapov	0:a1a69d32f310	4063	}
nikapov	0:a1a69d32f310	4064	}
nikapov	0:a1a69d32f310	4065	} else {
nikapov	0:a1a69d32f310	4066	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4067	}
nikapov	0:a1a69d32f310	4068
nikapov	0:a1a69d32f310	4069	}
nikapov	0:a1a69d32f310	4070	return status;
nikapov	0:a1a69d32f310	4071	}
nikapov	0:a1a69d32f310	4072
sepp_nepp	7:41cbc431e1f4	4073	VL53L0X_Error VL53L0X::wrapped_VL53L0X_set_measurement_timing_budget_micro_seconds(uint32_t measurement_timing_budget_micro_seconds)
nikapov	0:a1a69d32f310	4074	{
nikapov	0:a1a69d32f310	4075	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	4076	uint32_t final_range_timing_budget_micro_seconds;
nikapov	0:a1a69d32f310	4077	VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
nikapov	0:a1a69d32f310	4078	uint32_t msrc_dcc_tcc_timeout_micro_seconds = 2000;
nikapov	0:a1a69d32f310	4079	uint32_t start_overhead_micro_seconds = 1910;
nikapov	0:a1a69d32f310	4080	uint32_t end_overhead_micro_seconds = 960;
nikapov	0:a1a69d32f310	4081	uint32_t msrc_overhead_micro_seconds = 660;
nikapov	0:a1a69d32f310	4082	uint32_t tcc_overhead_micro_seconds = 590;
nikapov	0:a1a69d32f310	4083	uint32_t dss_overhead_micro_seconds = 690;
nikapov	0:a1a69d32f310	4084	uint32_t pre_range_overhead_micro_seconds = 660;
nikapov	0:a1a69d32f310	4085	uint32_t final_range_overhead_micro_seconds = 550;
nikapov	0:a1a69d32f310	4086	uint32_t pre_range_timeout_micro_seconds = 0;
nikapov	0:a1a69d32f310	4087	uint32_t c_min_timing_budget_micro_seconds = 20000;
nikapov	0:a1a69d32f310	4088	uint32_t sub_timeout = 0;
nikapov	0:a1a69d32f310	4089
sepp_nepp	5:b95f6951f7d5	4090
nikapov	0:a1a69d32f310	4091
nikapov	0:a1a69d32f310	4092	if (measurement_timing_budget_micro_seconds
nikapov	0:a1a69d32f310	4093	< c_min_timing_budget_micro_seconds) {
nikapov	0:a1a69d32f310	4094	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4095	return status;
nikapov	0:a1a69d32f310	4096	}
nikapov	0:a1a69d32f310	4097
nikapov	0:a1a69d32f310	4098	final_range_timing_budget_micro_seconds =
nikapov	0:a1a69d32f310	4099	measurement_timing_budget_micro_seconds -
nikapov	0:a1a69d32f310	4100	(start_overhead_micro_seconds + end_overhead_micro_seconds);
nikapov	0:a1a69d32f310	4101
sepp_nepp	7:41cbc431e1f4	4102	status = VL53L0X_get_sequence_step_enables(&scheduler_sequence_steps);
nikapov	0:a1a69d32f310	4103
nikapov	0:a1a69d32f310	4104	if (status == VL53L0X_ERROR_NONE &&
nikapov	0:a1a69d32f310	4105	(scheduler_sequence_steps.TccOn \|\|
nikapov	0:a1a69d32f310	4106	scheduler_sequence_steps.MsrcOn \|\|
nikapov	0:a1a69d32f310	4107	scheduler_sequence_steps.DssOn)) {
nikapov	0:a1a69d32f310	4108
sepp_nepp	7:41cbc431e1f4	4109	/* TCC,MSRC and DSS all share the same timeout */
sepp_nepp	7:41cbc431e1f4	4110	status = get_sequence_step_timeout(VL53L0X_SEQUENCESTEP_MSRC,
nikapov	0:a1a69d32f310	4111	&msrc_dcc_tcc_timeout_micro_seconds);
nikapov	0:a1a69d32f310	4112
sepp_nepp	7:41cbc431e1f4	4113	/* Subtract the TCC,MSRC and DSS timeouts if they are
nikapov	0:a1a69d32f310	4114	* enabled. */
nikapov	0:a1a69d32f310	4115
nikapov	0:a1a69d32f310	4116	if (status != VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4117	return status;
nikapov	0:a1a69d32f310	4118	}
nikapov	0:a1a69d32f310	4119
nikapov	0:a1a69d32f310	4120	/* TCC */
nikapov	0:a1a69d32f310	4121	if (scheduler_sequence_steps.TccOn) {
nikapov	0:a1a69d32f310	4122
nikapov	0:a1a69d32f310	4123	sub_timeout = msrc_dcc_tcc_timeout_micro_seconds
nikapov	0:a1a69d32f310	4124	+ tcc_overhead_micro_seconds;
nikapov	0:a1a69d32f310	4125
nikapov	0:a1a69d32f310	4126	if (sub_timeout <
nikapov	0:a1a69d32f310	4127	final_range_timing_budget_micro_seconds) {
nikapov	0:a1a69d32f310	4128	final_range_timing_budget_micro_seconds -=
nikapov	0:a1a69d32f310	4129	sub_timeout;
nikapov	0:a1a69d32f310	4130	} else {
nikapov	0:a1a69d32f310	4131	/* Requested timeout too big. */
nikapov	0:a1a69d32f310	4132	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4133	}
nikapov	0:a1a69d32f310	4134	}
nikapov	0:a1a69d32f310	4135
nikapov	0:a1a69d32f310	4136	if (status != VL53L0X_ERROR_NONE) {
sepp_nepp	5:b95f6951f7d5	4137
nikapov	0:a1a69d32f310	4138	return status;
nikapov	0:a1a69d32f310	4139	}
nikapov	0:a1a69d32f310	4140
nikapov	0:a1a69d32f310	4141	/* DSS */
nikapov	0:a1a69d32f310	4142	if (scheduler_sequence_steps.DssOn) {
nikapov	0:a1a69d32f310	4143
nikapov	0:a1a69d32f310	4144	sub_timeout = 2 * (msrc_dcc_tcc_timeout_micro_seconds +
nikapov	0:a1a69d32f310	4145	dss_overhead_micro_seconds);
nikapov	0:a1a69d32f310	4146
nikapov	0:a1a69d32f310	4147	if (sub_timeout < final_range_timing_budget_micro_seconds) {
nikapov	0:a1a69d32f310	4148	final_range_timing_budget_micro_seconds
nikapov	0:a1a69d32f310	4149	-= sub_timeout;
nikapov	0:a1a69d32f310	4150	} else {
nikapov	0:a1a69d32f310	4151	/* Requested timeout too big. */
nikapov	0:a1a69d32f310	4152	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4153	}
nikapov	0:a1a69d32f310	4154	} else if (scheduler_sequence_steps.MsrcOn) {
nikapov	0:a1a69d32f310	4155	/* MSRC */
nikapov	0:a1a69d32f310	4156	sub_timeout = msrc_dcc_tcc_timeout_micro_seconds +
nikapov	0:a1a69d32f310	4157	msrc_overhead_micro_seconds;
nikapov	0:a1a69d32f310	4158
nikapov	0:a1a69d32f310	4159	if (sub_timeout < final_range_timing_budget_micro_seconds) {
nikapov	0:a1a69d32f310	4160	final_range_timing_budget_micro_seconds
nikapov	0:a1a69d32f310	4161	-= sub_timeout;
nikapov	0:a1a69d32f310	4162	} else {
nikapov	0:a1a69d32f310	4163	/* Requested timeout too big. */
nikapov	0:a1a69d32f310	4164	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4165	}
nikapov	0:a1a69d32f310	4166	}
nikapov	0:a1a69d32f310	4167
nikapov	0:a1a69d32f310	4168	}
nikapov	0:a1a69d32f310	4169
nikapov	0:a1a69d32f310	4170	if (status != VL53L0X_ERROR_NONE) {
sepp_nepp	5:b95f6951f7d5	4171
nikapov	0:a1a69d32f310	4172	return status;
nikapov	0:a1a69d32f310	4173	}
nikapov	0:a1a69d32f310	4174
nikapov	0:a1a69d32f310	4175	if (scheduler_sequence_steps.PreRangeOn) {
nikapov	0:a1a69d32f310	4176
nikapov	0:a1a69d32f310	4177	/* Subtract the Pre-range timeout if enabled. */
nikapov	0:a1a69d32f310	4178
sepp_nepp	7:41cbc431e1f4	4179	status = get_sequence_step_timeout(VL53L0X_SEQUENCESTEP_PRE_RANGE,
nikapov	0:a1a69d32f310	4180	&pre_range_timeout_micro_seconds);
nikapov	0:a1a69d32f310	4181
nikapov	0:a1a69d32f310	4182	sub_timeout = pre_range_timeout_micro_seconds +
nikapov	0:a1a69d32f310	4183	pre_range_overhead_micro_seconds;
nikapov	0:a1a69d32f310	4184
nikapov	0:a1a69d32f310	4185	if (sub_timeout < final_range_timing_budget_micro_seconds) {
nikapov	0:a1a69d32f310	4186	final_range_timing_budget_micro_seconds -= sub_timeout;
nikapov	0:a1a69d32f310	4187	} else {
nikapov	0:a1a69d32f310	4188	/* Requested timeout too big. */
nikapov	0:a1a69d32f310	4189	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4190	}
nikapov	0:a1a69d32f310	4191	}
nikapov	0:a1a69d32f310	4192
nikapov	0:a1a69d32f310	4193
nikapov	0:a1a69d32f310	4194	if (status == VL53L0X_ERROR_NONE &&
nikapov	0:a1a69d32f310	4195	scheduler_sequence_steps.FinalRangeOn) {
nikapov	0:a1a69d32f310	4196
nikapov	0:a1a69d32f310	4197	final_range_timing_budget_micro_seconds -=
nikapov	0:a1a69d32f310	4198	final_range_overhead_micro_seconds;
nikapov	0:a1a69d32f310	4199
nikapov	0:a1a69d32f310	4200	/* Final Range Timeout
nikapov	0:a1a69d32f310	4201	* Note that the final range timeout is determined by the timing
nikapov	0:a1a69d32f310	4202	* budget and the sum of all other timeouts within the sequence.
sepp_nepp	7:41cbc431e1f4	4203	* If there is no room for the final range timeout,then an error
nikapov	0:a1a69d32f310	4204	* will be set. Otherwise the remaining time will be applied to
nikapov	0:a1a69d32f310	4205	* the final range.
nikapov	0:a1a69d32f310	4206	*/
sepp_nepp	7:41cbc431e1f4	4207	status = set_sequence_step_timeout(VL53L0X_SEQUENCESTEP_FINAL_RANGE,
nikapov	0:a1a69d32f310	4208	final_range_timing_budget_micro_seconds);
nikapov	0:a1a69d32f310	4209
sepp_nepp	7:41cbc431e1f4	4210	_device->CurrentParameters.MeasurementTimingBudgetMicroSeconds = measurement_timing_budget_micro_seconds;
nikapov	0:a1a69d32f310	4211	}
nikapov	0:a1a69d32f310	4212
sepp_nepp	5:b95f6951f7d5	4213
nikapov	0:a1a69d32f310	4214
nikapov	0:a1a69d32f310	4215	return status;
nikapov	0:a1a69d32f310	4216	}
nikapov	0:a1a69d32f310	4217
sepp_nepp	7:41cbc431e1f4	4218	VL53L0X_Error VL53L0X::VL53L0X_set_measurement_timing_budget_micro_seconds(uint32_t measurement_timing_budget_micro_seconds)
nikapov	0:a1a69d32f310	4219	{
nikapov	0:a1a69d32f310	4220	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	4221
nikapov	0:a1a69d32f310	4222
sepp_nepp	7:41cbc431e1f4	4223	status = wrapped_VL53L0X_set_measurement_timing_budget_micro_seconds(measurement_timing_budget_micro_seconds);
nikapov	0:a1a69d32f310	4224
nikapov	0:a1a69d32f310	4225	return status;
nikapov	0:a1a69d32f310	4226	}
nikapov	0:a1a69d32f310	4227
sepp_nepp	7:41cbc431e1f4	4228	VL53L0X_Error VL53L0X::VL53L0X_set_sequence_step_enable(VL53L0X_SequenceStepId sequence_step_id,uint8_t sequence_step_enabled)
nikapov	0:a1a69d32f310	4229	{
nikapov	0:a1a69d32f310	4230	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	4231	uint8_t sequence_config = 0;
nikapov	0:a1a69d32f310	4232	uint8_t sequence_config_new = 0;
nikapov	0:a1a69d32f310	4233	uint32_t measurement_timing_budget_micro_seconds;
sepp_nepp	5:b95f6951f7d5	4234
nikapov	0:a1a69d32f310	4235
sepp_nepp	7:41cbc431e1f4	4236	status = VL53L0X_read_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
nikapov	0:a1a69d32f310	4237	&sequence_config);
nikapov	0:a1a69d32f310	4238
nikapov	0:a1a69d32f310	4239	sequence_config_new = sequence_config;
nikapov	0:a1a69d32f310	4240
nikapov	0:a1a69d32f310	4241	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4242	if (sequence_step_enabled == 1) {
nikapov	0:a1a69d32f310	4243
nikapov	0:a1a69d32f310	4244	/* Enable requested sequence step
nikapov	0:a1a69d32f310	4245	*/
nikapov	0:a1a69d32f310	4246	switch (sequence_step_id) {
nikapov	0:a1a69d32f310	4247	case VL53L0X_SEQUENCESTEP_TCC:
nikapov	0:a1a69d32f310	4248	sequence_config_new \|= 0x10;
nikapov	0:a1a69d32f310	4249	break;
nikapov	0:a1a69d32f310	4250	case VL53L0X_SEQUENCESTEP_DSS:
nikapov	0:a1a69d32f310	4251	sequence_config_new \|= 0x28;
nikapov	0:a1a69d32f310	4252	break;
nikapov	0:a1a69d32f310	4253	case VL53L0X_SEQUENCESTEP_MSRC:
nikapov	0:a1a69d32f310	4254	sequence_config_new \|= 0x04;
nikapov	0:a1a69d32f310	4255	break;
nikapov	0:a1a69d32f310	4256	case VL53L0X_SEQUENCESTEP_PRE_RANGE:
nikapov	0:a1a69d32f310	4257	sequence_config_new \|= 0x40;
nikapov	0:a1a69d32f310	4258	break;
nikapov	0:a1a69d32f310	4259	case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
nikapov	0:a1a69d32f310	4260	sequence_config_new \|= 0x80;
nikapov	0:a1a69d32f310	4261	break;
nikapov	0:a1a69d32f310	4262	default:
nikapov	0:a1a69d32f310	4263	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4264	}
nikapov	0:a1a69d32f310	4265	} else {
nikapov	0:a1a69d32f310	4266	/* Disable requested sequence step
nikapov	0:a1a69d32f310	4267	*/
nikapov	0:a1a69d32f310	4268	switch (sequence_step_id) {
nikapov	0:a1a69d32f310	4269	case VL53L0X_SEQUENCESTEP_TCC:
nikapov	0:a1a69d32f310	4270	sequence_config_new &= 0xef;
nikapov	0:a1a69d32f310	4271	break;
nikapov	0:a1a69d32f310	4272	case VL53L0X_SEQUENCESTEP_DSS:
nikapov	0:a1a69d32f310	4273	sequence_config_new &= 0xd7;
nikapov	0:a1a69d32f310	4274	break;
nikapov	0:a1a69d32f310	4275	case VL53L0X_SEQUENCESTEP_MSRC:
nikapov	0:a1a69d32f310	4276	sequence_config_new &= 0xfb;
nikapov	0:a1a69d32f310	4277	break;
nikapov	0:a1a69d32f310	4278	case VL53L0X_SEQUENCESTEP_PRE_RANGE:
nikapov	0:a1a69d32f310	4279	sequence_config_new &= 0xbf;
nikapov	0:a1a69d32f310	4280	break;
nikapov	0:a1a69d32f310	4281	case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
nikapov	0:a1a69d32f310	4282	sequence_config_new &= 0x7f;
nikapov	0:a1a69d32f310	4283	break;
nikapov	0:a1a69d32f310	4284	default:
nikapov	0:a1a69d32f310	4285	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4286	}
nikapov	0:a1a69d32f310	4287	}
nikapov	0:a1a69d32f310	4288	}
nikapov	0:a1a69d32f310	4289
nikapov	0:a1a69d32f310	4290	if (sequence_config_new != sequence_config) {
nikapov	0:a1a69d32f310	4291	/* Apply New Setting */
nikapov	0:a1a69d32f310	4292	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4293	status = VL53L0X_write_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,sequence_config_new);
nikapov	0:a1a69d32f310	4294	}
nikapov	0:a1a69d32f310	4295	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4296	_device->SequenceConfig = sequence_config_new;
nikapov	0:a1a69d32f310	4297	}
nikapov	0:a1a69d32f310	4298
nikapov	0:a1a69d32f310	4299
nikapov	0:a1a69d32f310	4300	/* Recalculate timing budget */
nikapov	0:a1a69d32f310	4301	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4302	measurement_timing_budget_micro_seconds = _device->CurrentParameters.MeasurementTimingBudgetMicroSeconds;
sepp_nepp	7:41cbc431e1f4	4303
sepp_nepp	7:41cbc431e1f4	4304	VL53L0X_set_measurement_timing_budget_micro_seconds(measurement_timing_budget_micro_seconds);
nikapov	0:a1a69d32f310	4305	}
nikapov	0:a1a69d32f310	4306	}
nikapov	0:a1a69d32f310	4307
sepp_nepp	5:b95f6951f7d5	4308
nikapov	0:a1a69d32f310	4309
nikapov	0:a1a69d32f310	4310	return status;
nikapov	0:a1a69d32f310	4311	}
nikapov	0:a1a69d32f310	4312
sepp_nepp	7:41cbc431e1f4	4313	VL53L0X_Error VL53L0X::VL53L0X_set_limit_check_enable(uint16_t limit_check_id,
nikapov	0:a1a69d32f310	4314	uint8_t limit_check_enable)
nikapov	0:a1a69d32f310	4315	{
nikapov	0:a1a69d32f310	4316	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	4317	FixPoint1616_t temp_fix1616 = 0;
nikapov	0:a1a69d32f310	4318	uint8_t limit_check_enable_int = 0;
nikapov	0:a1a69d32f310	4319	uint8_t limit_check_disable = 0;
nikapov	0:a1a69d32f310	4320	uint8_t temp8;
nikapov	0:a1a69d32f310	4321
sepp_nepp	5:b95f6951f7d5	4322
nikapov	0:a1a69d32f310	4323
nikapov	0:a1a69d32f310	4324	if (limit_check_id >= VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS) {
nikapov	0:a1a69d32f310	4325	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4326	} else {
nikapov	0:a1a69d32f310	4327	if (limit_check_enable == 0) {
nikapov	0:a1a69d32f310	4328	temp_fix1616 = 0;
nikapov	0:a1a69d32f310	4329	limit_check_enable_int = 0;
nikapov	0:a1a69d32f310	4330	limit_check_disable = 1;
nikapov	0:a1a69d32f310	4331
nikapov	0:a1a69d32f310	4332	} else {
sepp_nepp	7:41cbc431e1f4	4333	temp_fix1616 = _device->CurrentParameters.LimitChecksValue[limit_check_id];
nikapov	0:a1a69d32f310	4334	limit_check_disable = 0;
nikapov	0:a1a69d32f310	4335	/* this to be sure to have either 0 or 1 */
nikapov	0:a1a69d32f310	4336	limit_check_enable_int = 1;
nikapov	0:a1a69d32f310	4337	}
nikapov	0:a1a69d32f310	4338
nikapov	0:a1a69d32f310	4339	switch (limit_check_id) {
nikapov	0:a1a69d32f310	4340
nikapov	0:a1a69d32f310	4341	case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
nikapov	0:a1a69d32f310	4342	/* internal computation: */
sepp_nepp	7:41cbc431e1f4	4343	_device->CurrentParameters.LimitChecksEnable[VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE] = limit_check_enable_int;
nikapov	0:a1a69d32f310	4344
nikapov	0:a1a69d32f310	4345	break;
nikapov	0:a1a69d32f310	4346
nikapov	0:a1a69d32f310	4347	case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
nikapov	0:a1a69d32f310	4348
sepp_nepp	7:41cbc431e1f4	4349	status = VL53L0X_write_word(VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
nikapov	0:a1a69d32f310	4350	VL53L0X_FIXPOINT1616TOFIXPOINT97(temp_fix1616));
nikapov	0:a1a69d32f310	4351
nikapov	0:a1a69d32f310	4352	break;
nikapov	0:a1a69d32f310	4353
nikapov	0:a1a69d32f310	4354	case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
nikapov	0:a1a69d32f310	4355
nikapov	0:a1a69d32f310	4356	/* internal computation: */
sepp_nepp	7:41cbc431e1f4	4357	_device->CurrentParameters.LimitChecksEnable[VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP] = limit_check_enable_int;
nikapov	0:a1a69d32f310	4358
nikapov	0:a1a69d32f310	4359	break;
nikapov	0:a1a69d32f310	4360
nikapov	0:a1a69d32f310	4361	case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
nikapov	0:a1a69d32f310	4362
nikapov	0:a1a69d32f310	4363	/* internal computation: */
sepp_nepp	7:41cbc431e1f4	4364	_device->CurrentParameters.LimitChecksEnable[VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD] = limit_check_enable_int;
nikapov	0:a1a69d32f310	4365
nikapov	0:a1a69d32f310	4366	break;
nikapov	0:a1a69d32f310	4367
nikapov	0:a1a69d32f310	4368	case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
nikapov	0:a1a69d32f310	4369
nikapov	0:a1a69d32f310	4370	temp8 = (uint8_t)(limit_check_disable << 1);
sepp_nepp	7:41cbc431e1f4	4371	status = VL53L0X_update_byte(VL53L0X_REG_MSRC_CONFIG_CONTROL,
sepp_nepp	7:41cbc431e1f4	4372	0xFE,temp8);
nikapov	0:a1a69d32f310	4373
nikapov	0:a1a69d32f310	4374	break;
nikapov	0:a1a69d32f310	4375
nikapov	0:a1a69d32f310	4376	case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
nikapov	0:a1a69d32f310	4377
nikapov	0:a1a69d32f310	4378	temp8 = (uint8_t)(limit_check_disable << 4);
sepp_nepp	7:41cbc431e1f4	4379	status = VL53L0X_update_byte(VL53L0X_REG_MSRC_CONFIG_CONTROL,
sepp_nepp	7:41cbc431e1f4	4380	0xEF,temp8);
nikapov	0:a1a69d32f310	4381
nikapov	0:a1a69d32f310	4382	break;
nikapov	0:a1a69d32f310	4383
nikapov	0:a1a69d32f310	4384
nikapov	0:a1a69d32f310	4385	default:
nikapov	0:a1a69d32f310	4386	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4387
nikapov	0:a1a69d32f310	4388	}
nikapov	0:a1a69d32f310	4389
nikapov	0:a1a69d32f310	4390	}
nikapov	0:a1a69d32f310	4391
nikapov	0:a1a69d32f310	4392	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4393	if (limit_check_enable == 0) {
sepp_nepp	7:41cbc431e1f4	4394	_device->CurrentParameters.LimitChecksEnable[limit_check_id] = 0;
nikapov	0:a1a69d32f310	4395	} else {
sepp_nepp	7:41cbc431e1f4	4396	_device->CurrentParameters.LimitChecksEnable[limit_check_id] = 1;
nikapov	0:a1a69d32f310	4397	}
nikapov	0:a1a69d32f310	4398	}
nikapov	0:a1a69d32f310	4399
sepp_nepp	5:b95f6951f7d5	4400
nikapov	0:a1a69d32f310	4401	return status;
nikapov	0:a1a69d32f310	4402	}
nikapov	0:a1a69d32f310	4403
sepp_nepp	7:41cbc431e1f4	4404	VL53L0X_Error VL53L0X::VL53L0X_static_init()
nikapov	0:a1a69d32f310	4405	{
nikapov	0:a1a69d32f310	4406	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	4407	VL53L0X_DeviceParameters_t current_parameters = {0};
nikapov	0:a1a69d32f310	4408	uint8_t *p_tuning_setting_buffer;
nikapov	0:a1a69d32f310	4409	uint16_t tempword = 0;
nikapov	0:a1a69d32f310	4410	uint8_t tempbyte = 0;
nikapov	0:a1a69d32f310	4411	uint8_t use_internal_tuning_settings = 0;
nikapov	0:a1a69d32f310	4412	uint32_t count = 0;
nikapov	0:a1a69d32f310	4413	uint8_t is_aperture_spads = 0;
nikapov	0:a1a69d32f310	4414	uint32_t ref_spad_count = 0;
nikapov	0:a1a69d32f310	4415	uint8_t aperture_spads = 0;
nikapov	0:a1a69d32f310	4416	uint8_t vcsel_pulse_period_pclk;
nikapov	0:a1a69d32f310	4417	uint32_t seq_timeout_micro_secs;
nikapov	0:a1a69d32f310	4418
sepp_nepp	5:b95f6951f7d5	4419
nikapov	0:a1a69d32f310	4420
sepp_nepp	7:41cbc431e1f4	4421	status = VL53L0X_get_info_from_device(1);
nikapov	0:a1a69d32f310	4422
nikapov	0:a1a69d32f310	4423	/* set the ref spad from NVM */
sepp_nepp	7:41cbc431e1f4	4424	count = (uint32_t)_device->DeviceSpecificParameters.ReferenceSpadCount;
sepp_nepp	7:41cbc431e1f4	4425	aperture_spads = _device->DeviceSpecificParameters.ReferenceSpadType;
nikapov	0:a1a69d32f310	4426
nikapov	0:a1a69d32f310	4427	/* NVM value invalid */
nikapov	0:a1a69d32f310	4428	if ((aperture_spads > 1) \|\|
nikapov	0:a1a69d32f310	4429	((aperture_spads == 1) && (count > 32)) \|\|
nikapov	0:a1a69d32f310	4430	((aperture_spads == 0) && (count > 12))) {
sepp_nepp	7:41cbc431e1f4	4431	status = wrapped_VL53L0X_perform_ref_spad_management(&ref_spad_count,
nikapov	0:a1a69d32f310	4432	&is_aperture_spads);
nikapov	0:a1a69d32f310	4433	} else {
sepp_nepp	7:41cbc431e1f4	4434	status = VL53L0X_set_reference_spads(count,aperture_spads);
nikapov	0:a1a69d32f310	4435	}
nikapov	0:a1a69d32f310	4436
nikapov	0:a1a69d32f310	4437
nikapov	0:a1a69d32f310	4438	/* Initialize tuning settings buffer to prevent compiler warning. */
nikapov	0:a1a69d32f310	4439	p_tuning_setting_buffer = DefaultTuningSettings;
nikapov	0:a1a69d32f310	4440
nikapov	0:a1a69d32f310	4441	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4442	use_internal_tuning_settings = _device->UseInternalTuningSettings;
nikapov	0:a1a69d32f310	4443
nikapov	0:a1a69d32f310	4444	if (use_internal_tuning_settings == 0) {
sepp_nepp	7:41cbc431e1f4	4445	p_tuning_setting_buffer = _device->pTuningSettingsPointer;
nikapov	0:a1a69d32f310	4446	} else {
nikapov	0:a1a69d32f310	4447	p_tuning_setting_buffer = DefaultTuningSettings;
nikapov	0:a1a69d32f310	4448	}
nikapov	0:a1a69d32f310	4449
nikapov	0:a1a69d32f310	4450	}
nikapov	0:a1a69d32f310	4451
nikapov	0:a1a69d32f310	4452	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4453	status = VL53L0X_load_tuning_settings(p_tuning_setting_buffer);
nikapov	0:a1a69d32f310	4454	}
nikapov	0:a1a69d32f310	4455
nikapov	0:a1a69d32f310	4456
nikapov	0:a1a69d32f310	4457	/* Set interrupt config to new sample ready */
nikapov	0:a1a69d32f310	4458	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4459	status = VL53L0X_set_gpio_config(0,0,
nikapov	0:a1a69d32f310	4460	VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY,
nikapov	0:a1a69d32f310	4461	VL53L0X_INTERRUPTPOLARITY_LOW);
nikapov	0:a1a69d32f310	4462	}
nikapov	0:a1a69d32f310	4463
nikapov	0:a1a69d32f310	4464	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4465	status = VL53L0X_write_byte(0xFF,0x01);
sepp_nepp	7:41cbc431e1f4	4466	status \|= VL53L0X_read_word(0x84,&tempword);
sepp_nepp	7:41cbc431e1f4	4467	status \|= VL53L0X_write_byte(0xFF,0x00);
nikapov	0:a1a69d32f310	4468	}
nikapov	0:a1a69d32f310	4469
nikapov	0:a1a69d32f310	4470	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4471	_device->DeviceSpecificParameters.OscFrequencyMHz=
sepp_nepp	7:41cbc431e1f4	4472	VL53L0X_FIXPOINT412TOFIXPOINT1616(tempword);
sepp_nepp	7:41cbc431e1f4	4473	}
sepp_nepp	7:41cbc431e1f4	4474
sepp_nepp	7:41cbc431e1f4	4475	/* After static init,some device parameters may be changed,
nikapov	0:a1a69d32f310	4476	* so update them */
nikapov	0:a1a69d32f310	4477	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4478	status = VL53L0X_get_device_parameters(&current_parameters);
nikapov	0:a1a69d32f310	4479	}
nikapov	0:a1a69d32f310	4480
nikapov	0:a1a69d32f310	4481
nikapov	0:a1a69d32f310	4482	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4483	status = VL53L0X_get_fraction_enable(&tempbyte);
Davidroid	3:e9269ff624ed	4484	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4485	_device->RangeFractionalEnable = tempbyte;
Davidroid	3:e9269ff624ed	4486	}
nikapov	0:a1a69d32f310	4487
nikapov	0:a1a69d32f310	4488	}
nikapov	0:a1a69d32f310	4489
nikapov	0:a1a69d32f310	4490	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4491	_device->CurrentParameters = current_parameters;
nikapov	0:a1a69d32f310	4492	}
nikapov	0:a1a69d32f310	4493
nikapov	0:a1a69d32f310	4494
nikapov	0:a1a69d32f310	4495	/* read the sequence config and save it */
nikapov	0:a1a69d32f310	4496	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4497	status = VL53L0X_read_byte(VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,&tempbyte);
nikapov	0:a1a69d32f310	4498	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4499	_device->SequenceConfig = tempbyte;
nikapov	0:a1a69d32f310	4500	}
nikapov	0:a1a69d32f310	4501	}
nikapov	0:a1a69d32f310	4502
nikapov	0:a1a69d32f310	4503	/* Disable MSRC and TCC by default */
nikapov	0:a1a69d32f310	4504	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4505	status = VL53L0X_set_sequence_step_enable(VL53L0X_SEQUENCESTEP_TCC,0);
Davidroid	2:d07edeaff6f1	4506	}
nikapov	0:a1a69d32f310	4507
nikapov	0:a1a69d32f310	4508	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4509	status = VL53L0X_set_sequence_step_enable(VL53L0X_SEQUENCESTEP_MSRC,0);
Davidroid	2:d07edeaff6f1	4510	}
nikapov	0:a1a69d32f310	4511
nikapov	0:a1a69d32f310	4512	/* Set PAL State to standby */
nikapov	0:a1a69d32f310	4513	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4514	_device->PalState = VL53L0X_STATE_IDLE;
nikapov	0:a1a69d32f310	4515	}
nikapov	0:a1a69d32f310	4516
nikapov	0:a1a69d32f310	4517	/* Store pre-range vcsel period */
nikapov	0:a1a69d32f310	4518	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4519	status = VL53L0X_get_vcsel_pulse_period(
nikapov	0:a1a69d32f310	4520	VL53L0X_VCSEL_PERIOD_PRE_RANGE,
nikapov	0:a1a69d32f310	4521	&vcsel_pulse_period_pclk);
nikapov	0:a1a69d32f310	4522	}
nikapov	0:a1a69d32f310	4523
nikapov	0:a1a69d32f310	4524	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4525	_device->DeviceSpecificParameters.PreRangeVcselPulsePeriod = vcsel_pulse_period_pclk;
nikapov	0:a1a69d32f310	4526	}
nikapov	0:a1a69d32f310	4527
nikapov	0:a1a69d32f310	4528	/* Store final-range vcsel period */
nikapov	0:a1a69d32f310	4529	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4530	status = VL53L0X_get_vcsel_pulse_period(
nikapov	0:a1a69d32f310	4531	VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
nikapov	0:a1a69d32f310	4532	&vcsel_pulse_period_pclk);
nikapov	0:a1a69d32f310	4533	}
nikapov	0:a1a69d32f310	4534
nikapov	0:a1a69d32f310	4535	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4536	_device->DeviceSpecificParameters.FinalRangeVcselPulsePeriod = vcsel_pulse_period_pclk;
nikapov	0:a1a69d32f310	4537	}
nikapov	0:a1a69d32f310	4538
nikapov	0:a1a69d32f310	4539	/* Store pre-range timeout */
nikapov	0:a1a69d32f310	4540	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4541	status = get_sequence_step_timeout(
nikapov	0:a1a69d32f310	4542	VL53L0X_SEQUENCESTEP_PRE_RANGE,
nikapov	0:a1a69d32f310	4543	&seq_timeout_micro_secs);
nikapov	0:a1a69d32f310	4544	}
nikapov	0:a1a69d32f310	4545
nikapov	0:a1a69d32f310	4546	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4547	_device->DeviceSpecificParameters.PreRangeTimeoutMicroSecs = seq_timeout_micro_secs;
nikapov	0:a1a69d32f310	4548	}
nikapov	0:a1a69d32f310	4549
nikapov	0:a1a69d32f310	4550	/* Store final-range timeout */
nikapov	0:a1a69d32f310	4551	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4552	status = get_sequence_step_timeout(
nikapov	0:a1a69d32f310	4553	VL53L0X_SEQUENCESTEP_FINAL_RANGE,
nikapov	0:a1a69d32f310	4554	&seq_timeout_micro_secs);
nikapov	0:a1a69d32f310	4555	}
nikapov	0:a1a69d32f310	4556
nikapov	0:a1a69d32f310	4557	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4558	_device->DeviceSpecificParameters.FinalRangeTimeoutMicroSecs = seq_timeout_micro_secs;
nikapov	0:a1a69d32f310	4559	}
nikapov	0:a1a69d32f310	4560
sepp_nepp	5:b95f6951f7d5	4561
nikapov	0:a1a69d32f310	4562	return status;
nikapov	0:a1a69d32f310	4563	}
nikapov	0:a1a69d32f310	4564
nikapov	0:a1a69d32f310	4565
sepp_nepp	7:41cbc431e1f4	4566	VL53L0X_Error VL53L0X::VL53L0X_stop_measurement()
nikapov	0:a1a69d32f310	4567	{
nikapov	0:a1a69d32f310	4568	VL53L0X_Error status = VL53L0X_ERROR_NONE;
sepp_nepp	5:b95f6951f7d5	4569
nikapov	0:a1a69d32f310	4570
sepp_nepp	7:41cbc431e1f4	4571	status = VL53L0X_write_byte(VL53L0X_REG_SYSRANGE_START,
nikapov	0:a1a69d32f310	4572	VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT);
nikapov	0:a1a69d32f310	4573
sepp_nepp	7:41cbc431e1f4	4574	status = VL53L0X_write_byte(0xFF,0x01);
sepp_nepp	7:41cbc431e1f4	4575	status = VL53L0X_write_byte(0x00,0x00);
sepp_nepp	7:41cbc431e1f4	4576	status = VL53L0X_write_byte(0x91,0x00);
sepp_nepp	7:41cbc431e1f4	4577	status = VL53L0X_write_byte(0x00,0x01);
sepp_nepp	7:41cbc431e1f4	4578	status = VL53L0X_write_byte(0xFF,0x00);
nikapov	0:a1a69d32f310	4579
nikapov	0:a1a69d32f310	4580	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4581	/* Set PAL State to Idle */
sepp_nepp	7:41cbc431e1f4	4582	_device->PalState = VL53L0X_STATE_IDLE;
nikapov	0:a1a69d32f310	4583	}
nikapov	0:a1a69d32f310	4584
nikapov	0:a1a69d32f310	4585	/* Check if need to apply interrupt settings */
nikapov	0:a1a69d32f310	4586	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4587	status = VL53L0X_check_and_load_interrupt_settings(0);
nikapov	0:a1a69d32f310	4588	}
nikapov	0:a1a69d32f310	4589
sepp_nepp	5:b95f6951f7d5	4590
nikapov	0:a1a69d32f310	4591	return status;
nikapov	0:a1a69d32f310	4592	}
nikapov	0:a1a69d32f310	4593
sepp_nepp	7:41cbc431e1f4	4594	VL53L0X_Error VL53L0X::VL53L0X_get_stop_completed_status(uint32_t *p_stop_status)
nikapov	0:a1a69d32f310	4595	{
nikapov	0:a1a69d32f310	4596	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	4597	uint8_t byte = 0;
sepp_nepp	5:b95f6951f7d5	4598
nikapov	0:a1a69d32f310	4599
sepp_nepp	7:41cbc431e1f4	4600	status = VL53L0X_write_byte(0xFF,0x01);
nikapov	0:a1a69d32f310	4601
nikapov	0:a1a69d32f310	4602	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4603	status = VL53L0X_read_byte(0x04,&byte);
nikapov	0:a1a69d32f310	4604	}
nikapov	0:a1a69d32f310	4605
nikapov	0:a1a69d32f310	4606	if (status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4607	status = VL53L0X_write_byte(0xFF,0x0);
nikapov	0:a1a69d32f310	4608	}
nikapov	0:a1a69d32f310	4609
nikapov	0:a1a69d32f310	4610	*p_stop_status = byte;
nikapov	0:a1a69d32f310	4611
nikapov	0:a1a69d32f310	4612	if (byte == 0) {
sepp_nepp	7:41cbc431e1f4	4613	status = VL53L0X_write_byte(0x80,0x01);
sepp_nepp	7:41cbc431e1f4	4614	status = VL53L0X_write_byte(0xFF,0x01);
sepp_nepp	7:41cbc431e1f4	4615	status = VL53L0X_write_byte(0x00,0x00);
sepp_nepp	7:41cbc431e1f4	4616	status = VL53L0X_write_byte(0x91,_device->StopVariable);
sepp_nepp	7:41cbc431e1f4	4617	status = VL53L0X_write_byte(0x00,0x01);
sepp_nepp	7:41cbc431e1f4	4618	status = VL53L0X_write_byte(0xFF,0x00);
sepp_nepp	7:41cbc431e1f4	4619	status = VL53L0X_write_byte(0x80,0x00);
nikapov	0:a1a69d32f310	4620	}
nikapov	0:a1a69d32f310	4621
sepp_nepp	5:b95f6951f7d5	4622
nikapov	0:a1a69d32f310	4623	return status;
nikapov	0:a1a69d32f310	4624	}
nikapov	0:a1a69d32f310	4625
nikapov	0:a1a69d32f310	4626	/**************** Write and read functions from I2C ***********************/
nikapov	0:a1a69d32f310	4627
sepp_nepp	7:41cbc431e1f4	4628	VL53L0X_Error VL53L0X::VL53L0X_write_multi(uint8_t index,uint8_t *p_data,uint32_t count)
nikapov	0:a1a69d32f310	4629	{
nikapov	0:a1a69d32f310	4630	int status;
nikapov	0:a1a69d32f310	4631
sepp_nepp	7:41cbc431e1f4	4632	status = VL53L0X_i2c_write(index,p_data,(uint16_t)count);
nikapov	0:a1a69d32f310	4633	return status;
nikapov	0:a1a69d32f310	4634	}
nikapov	0:a1a69d32f310	4635
sepp_nepp	7:41cbc431e1f4	4636	VL53L0X_Error VL53L0X::VL53L0X_read_multi(uint8_t index,uint8_t *p_data,uint32_t count)
nikapov	0:a1a69d32f310	4637	{
nikapov	0:a1a69d32f310	4638	int status;
nikapov	0:a1a69d32f310	4639
nikapov	0:a1a69d32f310	4640	if (count >= VL53L0X_MAX_I2C_XFER_SIZE) {
nikapov	0:a1a69d32f310	4641	status = VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4642	}
nikapov	0:a1a69d32f310	4643
sepp_nepp	7:41cbc431e1f4	4644	status = VL53L0X_i2c_read(index,p_data,(uint16_t)count);
nikapov	0:a1a69d32f310	4645
nikapov	0:a1a69d32f310	4646	return status;
nikapov	0:a1a69d32f310	4647	}
nikapov	0:a1a69d32f310	4648
nikapov	0:a1a69d32f310	4649
sepp_nepp	7:41cbc431e1f4	4650	VL53L0X_Error VL53L0X::VL53L0X_write_byte(uint8_t index,uint8_t data)
nikapov	0:a1a69d32f310	4651	{
nikapov	0:a1a69d32f310	4652	int status;
nikapov	0:a1a69d32f310	4653
sepp_nepp	7:41cbc431e1f4	4654	status = VL53L0X_i2c_write(index,&data,1);
nikapov	0:a1a69d32f310	4655	return status;
nikapov	0:a1a69d32f310	4656	}
nikapov	0:a1a69d32f310	4657
sepp_nepp	7:41cbc431e1f4	4658	VL53L0X_Error VL53L0X::VL53L0X_write_word(uint8_t index,uint16_t data)
nikapov	0:a1a69d32f310	4659	{
nikapov	0:a1a69d32f310	4660	int status;
nikapov	0:a1a69d32f310	4661	uint8_t buffer[2];
nikapov	0:a1a69d32f310	4662
nikapov	0:a1a69d32f310	4663	buffer[0] = data >> 8;
nikapov	0:a1a69d32f310	4664	buffer[1] = data & 0x00FF;
sepp_nepp	7:41cbc431e1f4	4665	status = VL53L0X_i2c_write(index,(uint8_t *)buffer,2);
nikapov	0:a1a69d32f310	4666	return status;
nikapov	0:a1a69d32f310	4667	}
nikapov	0:a1a69d32f310	4668
sepp_nepp	7:41cbc431e1f4	4669	VL53L0X_Error VL53L0X::VL53L0X_write_dword(uint8_t index,uint32_t data)
nikapov	0:a1a69d32f310	4670	{
nikapov	0:a1a69d32f310	4671	int status;
nikapov	0:a1a69d32f310	4672	uint8_t buffer[4];
nikapov	0:a1a69d32f310	4673
nikapov	0:a1a69d32f310	4674	buffer[0] = (data >> 24) & 0xFF;
nikapov	0:a1a69d32f310	4675	buffer[1] = (data >> 16) & 0xFF;
nikapov	0:a1a69d32f310	4676	buffer[2] = (data >> 8) & 0xFF;
nikapov	0:a1a69d32f310	4677	buffer[3] = (data >> 0) & 0xFF;
sepp_nepp	7:41cbc431e1f4	4678	status = VL53L0X_i2c_write(index,(uint8_t *)buffer,4);
nikapov	0:a1a69d32f310	4679	return status;
nikapov	0:a1a69d32f310	4680	}
nikapov	0:a1a69d32f310	4681
nikapov	0:a1a69d32f310	4682
sepp_nepp	7:41cbc431e1f4	4683	VL53L0X_Error VL53L0X::VL53L0X_read_byte(uint8_t index,uint8_t *p_data)
nikapov	0:a1a69d32f310	4684	{
nikapov	0:a1a69d32f310	4685	int status;
nikapov	0:a1a69d32f310	4686
sepp_nepp	7:41cbc431e1f4	4687	status = VL53L0X_i2c_read(index,p_data,1);
nikapov	0:a1a69d32f310	4688
Davidroid	3:e9269ff624ed	4689	if (status) {
nikapov	0:a1a69d32f310	4690	return -1;
Davidroid	3:e9269ff624ed	4691	}
nikapov	0:a1a69d32f310	4692
nikapov	0:a1a69d32f310	4693	return 0;
nikapov	0:a1a69d32f310	4694	}
nikapov	0:a1a69d32f310	4695
sepp_nepp	7:41cbc431e1f4	4696	VL53L0X_Error VL53L0X::VL53L0X_read_word(uint8_t index,uint16_t *p_data)
nikapov	0:a1a69d32f310	4697	{
nikapov	0:a1a69d32f310	4698	int status;
sepp_nepp	7:41cbc431e1f4	4699	uint8_t buffer[2] = {0,0};
sepp_nepp	7:41cbc431e1f4	4700
sepp_nepp	7:41cbc431e1f4	4701	status = VL53L0X_i2c_read(index,buffer,2);
nikapov	0:a1a69d32f310	4702	if (!status) {
nikapov	0:a1a69d32f310	4703	*p_data = (buffer[0] << 8) + buffer[1];
nikapov	0:a1a69d32f310	4704	}
nikapov	0:a1a69d32f310	4705	return status;
nikapov	0:a1a69d32f310	4706
nikapov	0:a1a69d32f310	4707	}
nikapov	0:a1a69d32f310	4708
sepp_nepp	7:41cbc431e1f4	4709	VL53L0X_Error VL53L0X::VL53L0X_read_dword(uint8_t index,uint32_t *p_data)
nikapov	0:a1a69d32f310	4710	{
nikapov	0:a1a69d32f310	4711	int status;
sepp_nepp	7:41cbc431e1f4	4712	uint8_t buffer[4] = {0,0,0,0};
sepp_nepp	7:41cbc431e1f4	4713
sepp_nepp	7:41cbc431e1f4	4714	status = VL53L0X_i2c_read(index,buffer,4);
nikapov	0:a1a69d32f310	4715	if (!status) {
nikapov	0:a1a69d32f310	4716	*p_data = (buffer[0] << 24) + (buffer[1] << 16) + (buffer[2] << 8) + buffer[3];
nikapov	0:a1a69d32f310	4717	}
nikapov	0:a1a69d32f310	4718	return status;
nikapov	0:a1a69d32f310	4719
nikapov	0:a1a69d32f310	4720	}
nikapov	0:a1a69d32f310	4721
sepp_nepp	7:41cbc431e1f4	4722	VL53L0X_Error VL53L0X::VL53L0X_update_byte(uint8_t index,uint8_t and_data,uint8_t or_data)
nikapov	0:a1a69d32f310	4723	{
nikapov	0:a1a69d32f310	4724	int status;
nikapov	0:a1a69d32f310	4725	uint8_t buffer = 0;
nikapov	0:a1a69d32f310	4726
nikapov	0:a1a69d32f310	4727	/* read data direct onto buffer */
sepp_nepp	7:41cbc431e1f4	4728	status = VL53L0X_i2c_read(index,&buffer,1);
nikapov	0:a1a69d32f310	4729	if (!status) {
nikapov	0:a1a69d32f310	4730	buffer = (buffer & and_data) \| or_data;
sepp_nepp	7:41cbc431e1f4	4731	status = VL53L0X_i2c_write(index,&buffer,(uint8_t)1);
nikapov	0:a1a69d32f310	4732	}
nikapov	0:a1a69d32f310	4733	return status;
nikapov	0:a1a69d32f310	4734	}
nikapov	0:a1a69d32f310	4735
sepp_nepp	7:41cbc431e1f4	4736	VL53L0X_Error VL53L0X::VL53L0X_i2c_write(uint8_t RegisterAddr,uint8_t *p_data,
nikapov	0:a1a69d32f310	4737	uint16_t NumByteToWrite)
nikapov	0:a1a69d32f310	4738	{
nikapov	0:a1a69d32f310	4739	int ret;
nikapov	0:a1a69d32f310	4740
sepp_nepp	7:41cbc431e1f4	4741	ret = _dev_i2c->i2c_write(p_data,_device->I2cDevAddr,RegisterAddr,NumByteToWrite);
nikapov	0:a1a69d32f310	4742
nikapov	0:a1a69d32f310	4743	if (ret) {
nikapov	0:a1a69d32f310	4744	return -1;
nikapov	0:a1a69d32f310	4745	}
nikapov	0:a1a69d32f310	4746	return 0;
nikapov	0:a1a69d32f310	4747	}
nikapov	0:a1a69d32f310	4748
sepp_nepp	7:41cbc431e1f4	4749	VL53L0X_Error VL53L0X::VL53L0X_i2c_read(uint8_t RegisterAddr,uint8_t *p_data,
nikapov	0:a1a69d32f310	4750	uint16_t NumByteToRead)
nikapov	0:a1a69d32f310	4751	{
nikapov	0:a1a69d32f310	4752	int ret;
nikapov	0:a1a69d32f310	4753
sepp_nepp	7:41cbc431e1f4	4754	ret = _dev_i2c->i2c_read(p_data,_device->I2cDevAddr,RegisterAddr,NumByteToRead);
nikapov	0:a1a69d32f310	4755
nikapov	0:a1a69d32f310	4756	if (ret) {
nikapov	0:a1a69d32f310	4757	return -1;
nikapov	0:a1a69d32f310	4758	}
nikapov	0:a1a69d32f310	4759	return 0;
nikapov	0:a1a69d32f310	4760	}
nikapov	0:a1a69d32f310	4761
nikapov	0:a1a69d32f310	4762	int VL53L0X::read_id(uint8_t *id)
nikapov	0:a1a69d32f310	4763	{
nikapov	0:a1a69d32f310	4764	int status = 0;
nikapov	0:a1a69d32f310	4765	uint16_t rl_id = 0;
nikapov	0:a1a69d32f310	4766
sepp_nepp	7:41cbc431e1f4	4767	status = VL53L0X_read_word(VL53L0X_REG_IDENTIFICATION_MODEL_ID,&rl_id);
nikapov	0:a1a69d32f310	4768	if (rl_id == 0xEEAA) {
nikapov	0:a1a69d32f310	4769	return status;
nikapov	0:a1a69d32f310	4770	}
nikapov	0:a1a69d32f310	4771
nikapov	0:a1a69d32f310	4772	return -1;
nikapov	0:a1a69d32f310	4773	}
nikapov	0:a1a69d32f310	4774
nikapov	0:a1a69d32f310	4775
sepp_nepp	7:41cbc431e1f4	4776	VL53L0X_Error VL53L0X::wait_measurement_data_ready()
nikapov	0:a1a69d32f310	4777	{
nikapov	0:a1a69d32f310	4778	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	4779	uint8_t new_dat_ready = 0;
nikapov	0:a1a69d32f310	4780	uint32_t loop_nb;
nikapov	0:a1a69d32f310	4781
nikapov	0:a1a69d32f310	4782	// Wait until it finished
nikapov	0:a1a69d32f310	4783	// use timeout to avoid deadlock
nikapov	0:a1a69d32f310	4784	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4785	loop_nb = 0;
nikapov	0:a1a69d32f310	4786	do {
sepp_nepp	7:41cbc431e1f4	4787	status = VL53L0X_get_measurement_data_ready(&new_dat_ready);
nikapov	0:a1a69d32f310	4788	if ((new_dat_ready == 0x01) \|\| status != VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4789	break;
nikapov	0:a1a69d32f310	4790	}
nikapov	0:a1a69d32f310	4791	loop_nb = loop_nb + 1;
sepp_nepp	7:41cbc431e1f4	4792	VL53L0X_polling_delay();
nikapov	0:a1a69d32f310	4793	} while (loop_nb < VL53L0X_DEFAULT_MAX_LOOP);
nikapov	0:a1a69d32f310	4794
nikapov	0:a1a69d32f310	4795	if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
nikapov	0:a1a69d32f310	4796	status = VL53L0X_ERROR_TIME_OUT;
nikapov	0:a1a69d32f310	4797	}
nikapov	0:a1a69d32f310	4798	}
nikapov	0:a1a69d32f310	4799
nikapov	0:a1a69d32f310	4800	return status;
nikapov	0:a1a69d32f310	4801	}
nikapov	0:a1a69d32f310	4802
sepp_nepp	7:41cbc431e1f4	4803	VL53L0X_Error VL53L0X::wait_stop_completed()
nikapov	0:a1a69d32f310	4804	{
nikapov	0:a1a69d32f310	4805	VL53L0X_Error status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	4806	uint32_t stop_completed = 0;
nikapov	0:a1a69d32f310	4807	uint32_t loop_nb;
nikapov	0:a1a69d32f310	4808
nikapov	0:a1a69d32f310	4809	// Wait until it finished
nikapov	0:a1a69d32f310	4810	// use timeout to avoid deadlock
nikapov	0:a1a69d32f310	4811	if (status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4812	loop_nb = 0;
nikapov	0:a1a69d32f310	4813	do {
sepp_nepp	7:41cbc431e1f4	4814	status = VL53L0X_get_stop_completed_status(&stop_completed);
nikapov	0:a1a69d32f310	4815	if ((stop_completed == 0x00) \|\| status != VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4816	break;
nikapov	0:a1a69d32f310	4817	}
nikapov	0:a1a69d32f310	4818	loop_nb = loop_nb + 1;
sepp_nepp	7:41cbc431e1f4	4819	VL53L0X_polling_delay();
nikapov	0:a1a69d32f310	4820	} while (loop_nb < VL53L0X_DEFAULT_MAX_LOOP);
nikapov	0:a1a69d32f310	4821
nikapov	0:a1a69d32f310	4822	if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
nikapov	0:a1a69d32f310	4823	status = VL53L0X_ERROR_TIME_OUT;
nikapov	0:a1a69d32f310	4824	}
nikapov	0:a1a69d32f310	4825
nikapov	0:a1a69d32f310	4826	}
nikapov	0:a1a69d32f310	4827
nikapov	0:a1a69d32f310	4828	return status;
nikapov	0:a1a69d32f310	4829	}
nikapov	0:a1a69d32f310	4830
nikapov	0:a1a69d32f310	4831
nikapov	0:a1a69d32f310	4832	int VL53L0X::init_sensor(uint8_t new_addr)
nikapov	0:a1a69d32f310	4833	{
nikapov	0:a1a69d32f310	4834	int status;
nikapov	0:a1a69d32f310	4835
nikapov	0:a1a69d32f310	4836	VL53L0X_off();
nikapov	0:a1a69d32f310	4837	VL53L0X_on();
nikapov	0:a1a69d32f310	4838
sepp_nepp	7:41cbc431e1f4	4839	// status=VL53L0X_WaitDeviceBooted(ice);
nikapov	0:a1a69d32f310	4840	// if(status)
nikapov	0:a1a69d32f310	4841	// printf("WaitDeviceBooted fail\n\r");
nikapov	0:a1a69d32f310	4842	status = is_present();
nikapov	0:a1a69d32f310	4843	if (!status) {
nikapov	0:a1a69d32f310	4844	status = init(&_my_device);
nikapov	0:a1a69d32f310	4845	if (status != VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4846	printf("Failed to init VL53L0X sensor!\n\r");
nikapov	0:a1a69d32f310	4847	return status;
nikapov	0:a1a69d32f310	4848	}
nikapov	0:a1a69d32f310	4849
nikapov	0:a1a69d32f310	4850	// deduce silicon version
sepp_nepp	7:41cbc431e1f4	4851	status = VL53L0X_get_device_info(&_device_info);
nikapov	0:a1a69d32f310	4852
nikapov	0:a1a69d32f310	4853	status = prepare();
nikapov	0:a1a69d32f310	4854	if (status != VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4855	printf("Failed to prepare VL53L0X!\n\r");
nikapov	0:a1a69d32f310	4856	return status;
nikapov	0:a1a69d32f310	4857	}
nikapov	0:a1a69d32f310	4858
nikapov	1:834986cdde0a	4859	if (new_addr != VL53L0X_DEFAULT_ADDRESS) {
nikapov	0:a1a69d32f310	4860	status = set_device_address(new_addr);
nikapov	0:a1a69d32f310	4861	if (status) {
nikapov	0:a1a69d32f310	4862	printf("Failed to change I2C address!\n\r");
nikapov	0:a1a69d32f310	4863	return status;
nikapov	0:a1a69d32f310	4864	}
nikapov	0:a1a69d32f310	4865	} else {
nikapov	0:a1a69d32f310	4866	printf("Invalid new address!\n\r");
nikapov	0:a1a69d32f310	4867	return VL53L0X_ERROR_INVALID_PARAMS;
nikapov	0:a1a69d32f310	4868	}
nikapov	0:a1a69d32f310	4869	}
nikapov	0:a1a69d32f310	4870	return status;
nikapov	0:a1a69d32f310	4871	}
nikapov	0:a1a69d32f310	4872
nikapov	0:a1a69d32f310	4873	int VL53L0X::range_meas_int_continuous_mode(void (*fptr)(void))
nikapov	0:a1a69d32f310	4874	{
sepp_nepp	5:b95f6951f7d5	4875	int status;
nikapov	0:a1a69d32f310	4876
sepp_nepp	7:41cbc431e1f4	4877	status = VL53L0X_stop_measurement(); // it is safer to do this while sensor is stopped
sepp_nepp	7:41cbc431e1f4	4878
sepp_nepp	7:41cbc431e1f4	4879	status = VL53L0X_set_gpio_config(0,VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
nikapov	0:a1a69d32f310	4880	VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY,
nikapov	0:a1a69d32f310	4881	VL53L0X_INTERRUPTPOLARITY_HIGH);
nikapov	0:a1a69d32f310	4882
nikapov	0:a1a69d32f310	4883	if (!status) {
nikapov	0:a1a69d32f310	4884	attach_interrupt_measure_detection_irq(fptr);
nikapov	0:a1a69d32f310	4885	enable_interrupt_measure_detection_irq();
nikapov	0:a1a69d32f310	4886	}
nikapov	0:a1a69d32f310	4887
sepp_nepp	5:b95f6951f7d5	4888	clear_interrupt(VL53L0X_REG_RESULT_INTERRUPT_STATUS \| VL53L0X_REG_RESULT_RANGE_STATUS);
sepp_nepp	7:41cbc431e1f4	4889	// NB: return value was previously only passed to logging macro,but did not get passed back
nikapov	0:a1a69d32f310	4890
nikapov	0:a1a69d32f310	4891	if (!status) {
nikapov	0:a1a69d32f310	4892	status = range_start_continuous_mode();
nikapov	0:a1a69d32f310	4893	}
nikapov	0:a1a69d32f310	4894	return status;
nikapov	0:a1a69d32f310	4895	}
nikapov	0:a1a69d32f310	4896
nikapov	0:a1a69d32f310	4897
sepp_nepp	7:41cbc431e1f4	4898	int VL53L0X::start_measurement(OperatingMode operating_mode,void (*fptr)(void))
nikapov	0:a1a69d32f310	4899	{
nikapov	0:a1a69d32f310	4900	int Status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	4901
nikapov	0:a1a69d32f310	4902	uint8_t VhvSettings;
nikapov	0:a1a69d32f310	4903	uint8_t PhaseCal;
sepp_nepp	7:41cbc431e1f4	4904	// *** from mass market cube expansion v1.1,ranging with satellites.
sepp_nepp	7:41cbc431e1f4	4905	// default settings,for normal range.
nikapov	0:a1a69d32f310	4906	FixPoint1616_t signalLimit = (FixPoint1616_t)(0.25 * 65536);
nikapov	0:a1a69d32f310	4907	FixPoint1616_t sigmaLimit = (FixPoint1616_t)(18 * 65536);
nikapov	0:a1a69d32f310	4908	uint32_t timingBudget = 33000;
nikapov	0:a1a69d32f310	4909	uint8_t preRangeVcselPeriod = 14;
nikapov	0:a1a69d32f310	4910	uint8_t finalRangeVcselPeriod = 10;
nikapov	0:a1a69d32f310	4911
nikapov	0:a1a69d32f310	4912	if (operating_mode == range_continuous_interrupt) {
nikapov	0:a1a69d32f310	4913	if (_gpio1Int == NULL) {
nikapov	0:a1a69d32f310	4914	printf("GPIO1 Error\r\n");
nikapov	0:a1a69d32f310	4915	return 1;
nikapov	0:a1a69d32f310	4916	}
nikapov	0:a1a69d32f310	4917
sepp_nepp	7:41cbc431e1f4	4918	Status = VL53L0X_stop_measurement(); // it is safer to do this while sensor is stopped
sepp_nepp	7:41cbc431e1f4	4919
sepp_nepp	7:41cbc431e1f4	4920	Status = VL53L0X_set_gpio_config(0,VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
nikapov	0:a1a69d32f310	4921	VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY,
nikapov	0:a1a69d32f310	4922	VL53L0X_INTERRUPTPOLARITY_HIGH);
nikapov	0:a1a69d32f310	4923
nikapov	0:a1a69d32f310	4924	if (Status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4925	attach_interrupt_measure_detection_irq(fptr);
nikapov	0:a1a69d32f310	4926	enable_interrupt_measure_detection_irq();
nikapov	0:a1a69d32f310	4927	}
nikapov	0:a1a69d32f310	4928
sepp_nepp	5:b95f6951f7d5	4929	clear_interrupt(VL53L0X_REG_RESULT_INTERRUPT_STATUS \| VL53L0X_REG_RESULT_RANGE_STATUS);
sepp_nepp	7:41cbc431e1f4	4930	// NB: return value was previously only passed to logging macro,but did not get passed back
nikapov	0:a1a69d32f310	4931
nikapov	0:a1a69d32f310	4932	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4933	Status = VL53L0X_set_device_mode(VL53L0X_DEVICEMODE_CONTINUOUS_RANGING); // Setup in continuous ranging mode
nikapov	0:a1a69d32f310	4934	}
nikapov	0:a1a69d32f310	4935
nikapov	0:a1a69d32f310	4936	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4937	Status = VL53L0X_start_measurement();
nikapov	0:a1a69d32f310	4938	}
nikapov	0:a1a69d32f310	4939	}
nikapov	0:a1a69d32f310	4940
nikapov	0:a1a69d32f310	4941	if (operating_mode == range_single_shot_polling) {
sepp_nepp	7:41cbc431e1f4	4942	// singelshot,polled ranging
nikapov	0:a1a69d32f310	4943	if (Status == VL53L0X_ERROR_NONE) {
nikapov	0:a1a69d32f310	4944	// no need to do this when we use VL53L0X_PerformSingleRangingMeasurement
sepp_nepp	7:41cbc431e1f4	4945	Status = VL53L0X_set_device_mode(VL53L0X_DEVICEMODE_SINGLE_RANGING); // Setup in single ranging mode
nikapov	0:a1a69d32f310	4946	}
nikapov	0:a1a69d32f310	4947
nikapov	0:a1a69d32f310	4948	// Enable/Disable Sigma and Signal check
nikapov	0:a1a69d32f310	4949	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4950	Status = VL53L0X_set_limit_check_enable(
sepp_nepp	7:41cbc431e1f4	4951	VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,1);
nikapov	0:a1a69d32f310	4952	}
nikapov	0:a1a69d32f310	4953	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4954	Status = VL53L0X_set_limit_check_enable(
sepp_nepp	7:41cbc431e1f4	4955	VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,1);
nikapov	0:a1a69d32f310	4956	}
nikapov	0:a1a69d32f310	4957
sepp_nepp	7:41cbc431e1f4	4958	// *** from mass market cube expansion v1.1,ranging with satellites.
nikapov	0:a1a69d32f310	4959	/* Ranging configuration */
nikapov	0:a1a69d32f310	4960	//*
nikapov	0:a1a69d32f310	4961	// switch(rangingConfig) {
nikapov	0:a1a69d32f310	4962	// case LONG_RANGE:
nikapov	0:a1a69d32f310	4963	signalLimit = (FixPoint1616_t)(0.1 * 65536);
nikapov	0:a1a69d32f310	4964	sigmaLimit = (FixPoint1616_t)(60 * 65536);
nikapov	0:a1a69d32f310	4965	timingBudget = 33000;
nikapov	0:a1a69d32f310	4966	preRangeVcselPeriod = 18;
nikapov	0:a1a69d32f310	4967	finalRangeVcselPeriod = 14;
nikapov	0:a1a69d32f310	4968	/* break;
nikapov	0:a1a69d32f310	4969	case HIGH_ACCURACY:
nikapov	0:a1a69d32f310	4970	signalLimit = (FixPoint1616_t)(0.25*65536);
nikapov	0:a1a69d32f310	4971	sigmaLimit = (FixPoint1616_t)(18*65536);
nikapov	0:a1a69d32f310	4972	timingBudget = 200000;
nikapov	0:a1a69d32f310	4973	preRangeVcselPeriod = 14;
nikapov	0:a1a69d32f310	4974	finalRangeVcselPeriod = 10;
nikapov	0:a1a69d32f310	4975	break;
nikapov	0:a1a69d32f310	4976	case HIGH_SPEED:
nikapov	0:a1a69d32f310	4977	signalLimit = (FixPoint1616_t)(0.25*65536);
nikapov	0:a1a69d32f310	4978	sigmaLimit = (FixPoint1616_t)(32*65536);
nikapov	0:a1a69d32f310	4979	timingBudget = 20000;
nikapov	0:a1a69d32f310	4980	preRangeVcselPeriod = 14;
nikapov	0:a1a69d32f310	4981	finalRangeVcselPeriod = 10;
nikapov	0:a1a69d32f310	4982	break;
nikapov	0:a1a69d32f310	4983	default:
nikapov	0:a1a69d32f310	4984	debug_printf("Not Supported");
nikapov	0:a1a69d32f310	4985	}
nikapov	0:a1a69d32f310	4986	*/
nikapov	0:a1a69d32f310	4987
nikapov	0:a1a69d32f310	4988	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4989	Status = VL53L0X_set_limit_check_value(
sepp_nepp	7:41cbc431e1f4	4990	VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,signalLimit);
nikapov	0:a1a69d32f310	4991	}
nikapov	0:a1a69d32f310	4992
nikapov	0:a1a69d32f310	4993	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4994	Status = VL53L0X_set_limit_check_value(
sepp_nepp	7:41cbc431e1f4	4995	VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,sigmaLimit);
nikapov	0:a1a69d32f310	4996	}
nikapov	0:a1a69d32f310	4997
nikapov	0:a1a69d32f310	4998	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	4999	Status = VL53L0X_set_measurement_timing_budget_micro_seconds(timingBudget);
nikapov	0:a1a69d32f310	5000	}
nikapov	0:a1a69d32f310	5001
nikapov	0:a1a69d32f310	5002	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	5003	Status = VL53L0X_set_vcsel_pulse_period(
sepp_nepp	7:41cbc431e1f4	5004	VL53L0X_VCSEL_PERIOD_PRE_RANGE,preRangeVcselPeriod);
nikapov	0:a1a69d32f310	5005	}
nikapov	0:a1a69d32f310	5006
nikapov	0:a1a69d32f310	5007	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	5008	Status = VL53L0X_set_vcsel_pulse_period(
sepp_nepp	7:41cbc431e1f4	5009	VL53L0X_VCSEL_PERIOD_FINAL_RANGE,finalRangeVcselPeriod);
nikapov	0:a1a69d32f310	5010	}
nikapov	0:a1a69d32f310	5011
nikapov	0:a1a69d32f310	5012	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	5013	Status = VL53L0X_perform_ref_calibration(&VhvSettings,&PhaseCal);
nikapov	0:a1a69d32f310	5014	}
nikapov	0:a1a69d32f310	5015
nikapov	0:a1a69d32f310	5016	}
nikapov	0:a1a69d32f310	5017
nikapov	0:a1a69d32f310	5018	if (operating_mode == range_continuous_polling) {
nikapov	0:a1a69d32f310	5019	if (Status == VL53L0X_ERROR_NONE) {
nikapov	1:834986cdde0a	5020	//printf("Call of VL53L0X_SetDeviceMode\n");
sepp_nepp	7:41cbc431e1f4	5021	Status = VL53L0X_set_device_mode(VL53L0X_DEVICEMODE_CONTINUOUS_RANGING); // Setup in continuous ranging mode
nikapov	0:a1a69d32f310	5022	}
nikapov	0:a1a69d32f310	5023
nikapov	0:a1a69d32f310	5024	if (Status == VL53L0X_ERROR_NONE) {
nikapov	1:834986cdde0a	5025	//printf("Call of VL53L0X_StartMeasurement\n");
sepp_nepp	7:41cbc431e1f4	5026	Status = VL53L0X_start_measurement();
nikapov	0:a1a69d32f310	5027	}
nikapov	0:a1a69d32f310	5028	}
nikapov	0:a1a69d32f310	5029
nikapov	0:a1a69d32f310	5030	return Status;
nikapov	0:a1a69d32f310	5031	}
nikapov	0:a1a69d32f310	5032
nikapov	0:a1a69d32f310	5033
sepp_nepp	7:41cbc431e1f4	5034	int VL53L0X::get_measurement(OperatingMode operating_mode,VL53L0X_RangingMeasurementData_t *p_data)
nikapov	0:a1a69d32f310	5035	{
nikapov	0:a1a69d32f310	5036	int Status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	5037
nikapov	0:a1a69d32f310	5038	if (operating_mode == range_single_shot_polling) {
sepp_nepp	7:41cbc431e1f4	5039	Status = VL53L0X_perform_single_ranging_measurement(p_data);
nikapov	0:a1a69d32f310	5040	}
nikapov	0:a1a69d32f310	5041
nikapov	0:a1a69d32f310	5042	if (operating_mode == range_continuous_polling) {
Davidroid	3:e9269ff624ed	5043	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	5044	Status = VL53L0X_measurement_poll_for_completion();
Davidroid	3:e9269ff624ed	5045	}
nikapov	0:a1a69d32f310	5046
nikapov	0:a1a69d32f310	5047	if (Status == VL53L0X_ERROR_NONE) {
sepp_nepp	7:41cbc431e1f4	5048	Status = VL53L0X_get_ranging_measurement_data(p_data);
nikapov	0:a1a69d32f310	5049
nikapov	0:a1a69d32f310	5050	// Clear the interrupt
sepp_nepp	7:41cbc431e1f4	5051	VL53L0X_clear_interrupt_mask(VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY);
sepp_nepp	7:41cbc431e1f4	5052	VL53L0X_polling_delay();
nikapov	0:a1a69d32f310	5053	}
nikapov	0:a1a69d32f310	5054	}
nikapov	0:a1a69d32f310	5055
nikapov	0:a1a69d32f310	5056	if (operating_mode == range_continuous_interrupt) {
sepp_nepp	7:41cbc431e1f4	5057	Status = VL53L0X_get_ranging_measurement_data(p_data);
sepp_nepp	7:41cbc431e1f4	5058	VL53L0X_clear_interrupt_mask(VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR \| VL53L0X_REG_RESULT_INTERRUPT_STATUS);
nikapov	0:a1a69d32f310	5059	}
nikapov	0:a1a69d32f310	5060
nikapov	0:a1a69d32f310	5061	return Status;
nikapov	0:a1a69d32f310	5062	}
nikapov	0:a1a69d32f310	5063
nikapov	0:a1a69d32f310	5064
nikapov	0:a1a69d32f310	5065	int VL53L0X::stop_measurement(OperatingMode operating_mode)
nikapov	0:a1a69d32f310	5066	{
nikapov	0:a1a69d32f310	5067	int status = VL53L0X_ERROR_NONE;
nikapov	0:a1a69d32f310	5068
nikapov	0:a1a69d32f310	5069
nikapov	0:a1a69d32f310	5070	// don't need to stop for a singleshot range!
nikapov	0:a1a69d32f310	5071	if (operating_mode == range_single_shot_polling) {
nikapov	0:a1a69d32f310	5072	}
nikapov	0:a1a69d32f310	5073
nikapov	0:a1a69d32f310	5074	if (operating_mode == range_continuous_interrupt \|\| operating_mode == range_continuous_polling) {
nikapov	0:a1a69d32f310	5075	// continuous mode
nikapov	0:a1a69d32f310	5076	if (status == VL53L0X_ERROR_NONE) {
nikapov	1:834986cdde0a	5077	//printf("Call of VL53L0X_StopMeasurement\n");
sepp_nepp	7:41cbc431e1f4	5078	status = VL53L0X_stop_measurement();
nikapov	0:a1a69d32f310	5079	}
nikapov	0:a1a69d32f310	5080
nikapov	0:a1a69d32f310	5081	if (status == VL53L0X_ERROR_NONE) {
nikapov	1:834986cdde0a	5082	//printf("Wait Stop to be competed\n");
sepp_nepp	7:41cbc431e1f4	5083	status = wait_stop_completed();
nikapov	0:a1a69d32f310	5084	}
nikapov	0:a1a69d32f310	5085
nikapov	0:a1a69d32f310	5086	if (status == VL53L0X_ERROR_NONE)
sepp_nepp	7:41cbc431e1f4	5087	status = VL53L0X_clear_interrupt_mask(
nikapov	0:a1a69d32f310	5088	VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY);
nikapov	0:a1a69d32f310	5089	}
nikapov	0:a1a69d32f310	5090
nikapov	0:a1a69d32f310	5091	return status;
nikapov	0:a1a69d32f310	5092	}
nikapov	0:a1a69d32f310	5093
nikapov	0:a1a69d32f310	5094
sepp_nepp	7:41cbc431e1f4	5095	int VL53L0X::handle_irq(OperatingMode operating_mode,VL53L0X_RangingMeasurementData_t *data)
nikapov	0:a1a69d32f310	5096	{
nikapov	0:a1a69d32f310	5097	int status;
sepp_nepp	7:41cbc431e1f4	5098	status = get_measurement(operating_mode,data);
nikapov	0:a1a69d32f310	5099	enable_interrupt_measure_detection_irq();
nikapov	0:a1a69d32f310	5100	return status;
nikapov	0:a1a69d32f310	5101	}
nikapov	0:a1a69d32f310	5102
nikapov	0:a1a69d32f310	5103	/******************************************************************************/

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Type:	Library
Created:	23 Mar 2019
Imports:	20
Forks:	0
Commits:	13
Dependents:	1
Dependencies:	0
Followers:	2

VL53L0X.cpp@8:abea9638127a, 2019-03-24 (annotated)

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