Sinan Divarci / Mbed OS max4146x_comp

max4146x_comp

Dependencies:   MAX14690

USBDevice/USBDevice/USBRegs_STM32.h@0:0061165683ee, 2020-10-25 (annotated)

Committer:
sdivarci
Date:
Sun Oct 25 20:10:02 2020 +0000
Revision:
0:0061165683ee
sdivarci

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sdivarci 0:0061165683ee 1 /**
sdivarci 0:0061165683ee 2 ******************************************************************************
sdivarci 0:0061165683ee 3 * @file usb_regs.h
sdivarci 0:0061165683ee 4 * @author MCD Application Team
sdivarci 0:0061165683ee 5 * @version V2.1.0
sdivarci 0:0061165683ee 6 * @date 19-March-2012
sdivarci 0:0061165683ee 7 * @brief hardware registers
sdivarci 0:0061165683ee 8 ******************************************************************************
sdivarci 0:0061165683ee 9 * @attention
sdivarci 0:0061165683ee 10 *
sdivarci 0:0061165683ee 11 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
sdivarci 0:0061165683ee 12 *
sdivarci 0:0061165683ee 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
sdivarci 0:0061165683ee 14 * You may not use this file except in compliance with the License.
sdivarci 0:0061165683ee 15 * You may obtain a copy of the License at:
sdivarci 0:0061165683ee 16 *
sdivarci 0:0061165683ee 17 * http://www.st.com/software_license_agreement_liberty_v2
sdivarci 0:0061165683ee 18 *
sdivarci 0:0061165683ee 19 * Unless required by applicable law or agreed to in writing, software
sdivarci 0:0061165683ee 20 * distributed under the License is distributed on an "AS IS" BASIS,
sdivarci 0:0061165683ee 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sdivarci 0:0061165683ee 22 * See the License for the specific language governing permissions and
sdivarci 0:0061165683ee 23 * limitations under the License.
sdivarci 0:0061165683ee 24 *
sdivarci 0:0061165683ee 25 ******************************************************************************
sdivarci 0:0061165683ee 26 */
sdivarci 0:0061165683ee 27
sdivarci 0:0061165683ee 28 #ifndef __USB_OTG_REGS_H__
sdivarci 0:0061165683ee 29 #define __USB_OTG_REGS_H__
sdivarci 0:0061165683ee 30
sdivarci 0:0061165683ee 31 typedef struct //000h
sdivarci 0:0061165683ee 32 {
sdivarci 0:0061165683ee 33 __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
sdivarci 0:0061165683ee 34 __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
sdivarci 0:0061165683ee 35 __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
sdivarci 0:0061165683ee 36 __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
sdivarci 0:0061165683ee 37 __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
sdivarci 0:0061165683ee 38 __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
sdivarci 0:0061165683ee 39 __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
sdivarci 0:0061165683ee 40 __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
sdivarci 0:0061165683ee 41 __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
sdivarci 0:0061165683ee 42 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
sdivarci 0:0061165683ee 43 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
sdivarci 0:0061165683ee 44 __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
sdivarci 0:0061165683ee 45 uint32_t Reserved30[2]; /* Reserved 030h*/
sdivarci 0:0061165683ee 46 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
sdivarci 0:0061165683ee 47 __IO uint32_t CID; /* User ID Register 03Ch*/
sdivarci 0:0061165683ee 48 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
sdivarci 0:0061165683ee 49 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
sdivarci 0:0061165683ee 50 __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
sdivarci 0:0061165683ee 51 }
sdivarci 0:0061165683ee 52 USB_OTG_GREGS;
sdivarci 0:0061165683ee 53
sdivarci 0:0061165683ee 54 typedef struct // 800h
sdivarci 0:0061165683ee 55 {
sdivarci 0:0061165683ee 56 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
sdivarci 0:0061165683ee 57 __IO uint32_t DCTL; /* dev Control Register 804h*/
sdivarci 0:0061165683ee 58 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
sdivarci 0:0061165683ee 59 uint32_t Reserved0C; /* Reserved 80Ch*/
sdivarci 0:0061165683ee 60 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
sdivarci 0:0061165683ee 61 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
sdivarci 0:0061165683ee 62 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
sdivarci 0:0061165683ee 63 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
sdivarci 0:0061165683ee 64 uint32_t Reserved20; /* Reserved 820h*/
sdivarci 0:0061165683ee 65 uint32_t Reserved9; /* Reserved 824h*/
sdivarci 0:0061165683ee 66 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
sdivarci 0:0061165683ee 67 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
sdivarci 0:0061165683ee 68 __IO uint32_t DTHRCTL; /* dev thr 830h*/
sdivarci 0:0061165683ee 69 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
sdivarci 0:0061165683ee 70 }
sdivarci 0:0061165683ee 71 USB_OTG_DREGS;
sdivarci 0:0061165683ee 72
sdivarci 0:0061165683ee 73 typedef struct
sdivarci 0:0061165683ee 74 {
sdivarci 0:0061165683ee 75 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
sdivarci 0:0061165683ee 76 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
sdivarci 0:0061165683ee 77 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
sdivarci 0:0061165683ee 78 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
sdivarci 0:0061165683ee 79 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
sdivarci 0:0061165683ee 80 uint32_t Reserved14;
sdivarci 0:0061165683ee 81 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
sdivarci 0:0061165683ee 82 uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
sdivarci 0:0061165683ee 83 }
sdivarci 0:0061165683ee 84 USB_OTG_INEPREGS;
sdivarci 0:0061165683ee 85
sdivarci 0:0061165683ee 86 typedef struct
sdivarci 0:0061165683ee 87 {
sdivarci 0:0061165683ee 88 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
sdivarci 0:0061165683ee 89 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
sdivarci 0:0061165683ee 90 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
sdivarci 0:0061165683ee 91 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
sdivarci 0:0061165683ee 92 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
sdivarci 0:0061165683ee 93 uint32_t Reserved14[3];
sdivarci 0:0061165683ee 94 }
sdivarci 0:0061165683ee 95 USB_OTG_OUTEPREGS;
sdivarci 0:0061165683ee 96
sdivarci 0:0061165683ee 97 typedef struct
sdivarci 0:0061165683ee 98 {
sdivarci 0:0061165683ee 99 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
sdivarci 0:0061165683ee 100 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
sdivarci 0:0061165683ee 101 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
sdivarci 0:0061165683ee 102 uint32_t Reserved40C; /* Reserved 40Ch*/
sdivarci 0:0061165683ee 103 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
sdivarci 0:0061165683ee 104 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
sdivarci 0:0061165683ee 105 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
sdivarci 0:0061165683ee 106 }
sdivarci 0:0061165683ee 107 USB_OTG_HREGS;
sdivarci 0:0061165683ee 108
sdivarci 0:0061165683ee 109 typedef struct
sdivarci 0:0061165683ee 110 {
sdivarci 0:0061165683ee 111 __IO uint32_t HCCHAR;
sdivarci 0:0061165683ee 112 __IO uint32_t HCSPLT;
sdivarci 0:0061165683ee 113 __IO uint32_t HCINT;
sdivarci 0:0061165683ee 114 __IO uint32_t HCINTMSK;
sdivarci 0:0061165683ee 115 __IO uint32_t HCTSIZ;
sdivarci 0:0061165683ee 116 uint32_t Reserved[3];
sdivarci 0:0061165683ee 117 }
sdivarci 0:0061165683ee 118 USB_OTG_HC_REGS;
sdivarci 0:0061165683ee 119
sdivarci 0:0061165683ee 120 typedef struct
sdivarci 0:0061165683ee 121 {
sdivarci 0:0061165683ee 122 USB_OTG_GREGS GREGS;
sdivarci 0:0061165683ee 123 uint32_t RESERVED0[188];
sdivarci 0:0061165683ee 124 USB_OTG_HREGS HREGS;
sdivarci 0:0061165683ee 125 uint32_t RESERVED1[9];
sdivarci 0:0061165683ee 126 __IO uint32_t HPRT;
sdivarci 0:0061165683ee 127 uint32_t RESERVED2[47];
sdivarci 0:0061165683ee 128 USB_OTG_HC_REGS HC_REGS[8];
sdivarci 0:0061165683ee 129 uint32_t RESERVED3[128];
sdivarci 0:0061165683ee 130 USB_OTG_DREGS DREGS;
sdivarci 0:0061165683ee 131 uint32_t RESERVED4[50];
sdivarci 0:0061165683ee 132 USB_OTG_INEPREGS INEP_REGS[4];
sdivarci 0:0061165683ee 133 uint32_t RESERVED5[96];
sdivarci 0:0061165683ee 134 USB_OTG_OUTEPREGS OUTEP_REGS[4];
sdivarci 0:0061165683ee 135 uint32_t RESERVED6[160];
sdivarci 0:0061165683ee 136 __IO uint32_t PCGCCTL;
sdivarci 0:0061165683ee 137 uint32_t RESERVED7[127];
sdivarci 0:0061165683ee 138 __IO uint32_t FIFO[4][1024];
sdivarci 0:0061165683ee 139 }
sdivarci 0:0061165683ee 140 USB_OTG_CORE_REGS;
sdivarci 0:0061165683ee 141
sdivarci 0:0061165683ee 142
sdivarci 0:0061165683ee 143 #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
sdivarci 0:0061165683ee 144 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
sdivarci 0:0061165683ee 145
sdivarci 0:0061165683ee 146 #endif //__USB_OTG_REGS_H__
sdivarci 0:0061165683ee 147
sdivarci 0:0061165683ee 148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
sdivarci 0:0061165683ee 149