Sinan Divarci / Mbed OS max4146x_comp

max4146x_comp

Dependencies:   MAX14690

USBDevice/USBDevice/USBHAL_STM32F4.cpp@0:0061165683ee, 2020-10-25 (annotated)

Committer:
sdivarci
Date:
Sun Oct 25 20:10:02 2020 +0000
Revision:
0:0061165683ee
sdivarci

Who changed what in which revision?

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sdivarci 0:0061165683ee 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
sdivarci 0:0061165683ee 2 *
sdivarci 0:0061165683ee 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
sdivarci 0:0061165683ee 4 * and associated documentation files (the "Software"), to deal in the Software without
sdivarci 0:0061165683ee 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
sdivarci 0:0061165683ee 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
sdivarci 0:0061165683ee 7 * Software is furnished to do so, subject to the following conditions:
sdivarci 0:0061165683ee 8 *
sdivarci 0:0061165683ee 9 * The above copyright notice and this permission notice shall be included in all copies or
sdivarci 0:0061165683ee 10 * substantial portions of the Software.
sdivarci 0:0061165683ee 11 *
sdivarci 0:0061165683ee 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
sdivarci 0:0061165683ee 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
sdivarci 0:0061165683ee 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
sdivarci 0:0061165683ee 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
sdivarci 0:0061165683ee 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
sdivarci 0:0061165683ee 17 */
sdivarci 0:0061165683ee 18
sdivarci 0:0061165683ee 19 #if defined(TARGET_STM32F4)
sdivarci 0:0061165683ee 20
sdivarci 0:0061165683ee 21 #include "USBHAL.h"
sdivarci 0:0061165683ee 22 #include "USBRegs_STM32.h"
sdivarci 0:0061165683ee 23 #include "pinmap.h"
sdivarci 0:0061165683ee 24
sdivarci 0:0061165683ee 25 USBHAL * USBHAL::instance;
sdivarci 0:0061165683ee 26
sdivarci 0:0061165683ee 27 static volatile int epComplete = 0;
sdivarci 0:0061165683ee 28
sdivarci 0:0061165683ee 29 static uint32_t bufferEnd = 0;
sdivarci 0:0061165683ee 30 static const uint32_t rxFifoSize = 512;
sdivarci 0:0061165683ee 31 static uint32_t rxFifoCount = 0;
sdivarci 0:0061165683ee 32
sdivarci 0:0061165683ee 33 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
sdivarci 0:0061165683ee 34
sdivarci 0:0061165683ee 35 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
sdivarci 0:0061165683ee 36 return 0;
sdivarci 0:0061165683ee 37 }
sdivarci 0:0061165683ee 38
sdivarci 0:0061165683ee 39 USBHAL::USBHAL(void) {
sdivarci 0:0061165683ee 40 NVIC_DisableIRQ(OTG_FS_IRQn);
sdivarci 0:0061165683ee 41 epCallback[0] = &USBHAL::EP1_OUT_callback;
sdivarci 0:0061165683ee 42 epCallback[1] = &USBHAL::EP1_IN_callback;
sdivarci 0:0061165683ee 43 epCallback[2] = &USBHAL::EP2_OUT_callback;
sdivarci 0:0061165683ee 44 epCallback[3] = &USBHAL::EP2_IN_callback;
sdivarci 0:0061165683ee 45 epCallback[4] = &USBHAL::EP3_OUT_callback;
sdivarci 0:0061165683ee 46 epCallback[5] = &USBHAL::EP3_IN_callback;
sdivarci 0:0061165683ee 47
sdivarci 0:0061165683ee 48 // Enable power and clocking
sdivarci 0:0061165683ee 49 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
sdivarci 0:0061165683ee 50
sdivarci 0:0061165683ee 51 #if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F429ZI)
sdivarci 0:0061165683ee 52 pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
sdivarci 0:0061165683ee 53 pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS));
sdivarci 0:0061165683ee 54 pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
sdivarci 0:0061165683ee 55 pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
sdivarci 0:0061165683ee 56 pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
sdivarci 0:0061165683ee 57 #else
sdivarci 0:0061165683ee 58 pin_function(PA_8, STM_PIN_DATA(2, 10));
sdivarci 0:0061165683ee 59 pin_function(PA_9, STM_PIN_DATA(0, 0));
sdivarci 0:0061165683ee 60 pin_function(PA_10, STM_PIN_DATA(2, 10));
sdivarci 0:0061165683ee 61 pin_function(PA_11, STM_PIN_DATA(2, 10));
sdivarci 0:0061165683ee 62 pin_function(PA_12, STM_PIN_DATA(2, 10));
sdivarci 0:0061165683ee 63
sdivarci 0:0061165683ee 64 // Set ID pin to open drain with pull-up resistor
sdivarci 0:0061165683ee 65 pin_mode(PA_10, OpenDrain);
sdivarci 0:0061165683ee 66 GPIOA->PUPDR &= ~(0x3 << 20);
sdivarci 0:0061165683ee 67 GPIOA->PUPDR |= 1 << 20;
sdivarci 0:0061165683ee 68
sdivarci 0:0061165683ee 69 // Set VBUS pin to open drain
sdivarci 0:0061165683ee 70 pin_mode(PA_9, OpenDrain);
sdivarci 0:0061165683ee 71 #endif
sdivarci 0:0061165683ee 72
sdivarci 0:0061165683ee 73 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
sdivarci 0:0061165683ee 74
sdivarci 0:0061165683ee 75 // Enable interrupts
sdivarci 0:0061165683ee 76 OTG_FS->GREGS.GAHBCFG |= (1 << 0);
sdivarci 0:0061165683ee 77
sdivarci 0:0061165683ee 78 // Turnaround time to maximum value - too small causes packet loss
sdivarci 0:0061165683ee 79 OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
sdivarci 0:0061165683ee 80
sdivarci 0:0061165683ee 81 // Unmask global interrupts
sdivarci 0:0061165683ee 82 OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
sdivarci 0:0061165683ee 83 (1 << 4) | // RX FIFO not empty
sdivarci 0:0061165683ee 84 (1 << 12); // USB reset
sdivarci 0:0061165683ee 85
sdivarci 0:0061165683ee 86 OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
sdivarci 0:0061165683ee 87 (1 << 2); // Non-zero-length status OUT handshake
sdivarci 0:0061165683ee 88
sdivarci 0:0061165683ee 89 OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
sdivarci 0:0061165683ee 90 (1 << 16); // Power Up
sdivarci 0:0061165683ee 91
sdivarci 0:0061165683ee 92 instance = this;
sdivarci 0:0061165683ee 93 NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
sdivarci 0:0061165683ee 94 NVIC_SetPriority(OTG_FS_IRQn, 1);
sdivarci 0:0061165683ee 95 }
sdivarci 0:0061165683ee 96
sdivarci 0:0061165683ee 97 USBHAL::~USBHAL(void) {
sdivarci 0:0061165683ee 98 }
sdivarci 0:0061165683ee 99
sdivarci 0:0061165683ee 100 void USBHAL::connect(void) {
sdivarci 0:0061165683ee 101 NVIC_EnableIRQ(OTG_FS_IRQn);
sdivarci 0:0061165683ee 102 }
sdivarci 0:0061165683ee 103
sdivarci 0:0061165683ee 104 void USBHAL::disconnect(void) {
sdivarci 0:0061165683ee 105 NVIC_DisableIRQ(OTG_FS_IRQn);
sdivarci 0:0061165683ee 106 }
sdivarci 0:0061165683ee 107
sdivarci 0:0061165683ee 108 void USBHAL::configureDevice(void) {
sdivarci 0:0061165683ee 109 // Not needed
sdivarci 0:0061165683ee 110 }
sdivarci 0:0061165683ee 111
sdivarci 0:0061165683ee 112 void USBHAL::unconfigureDevice(void) {
sdivarci 0:0061165683ee 113 // Not needed
sdivarci 0:0061165683ee 114 }
sdivarci 0:0061165683ee 115
sdivarci 0:0061165683ee 116 void USBHAL::setAddress(uint8_t address) {
sdivarci 0:0061165683ee 117 OTG_FS->DREGS.DCFG |= (address << 4);
sdivarci 0:0061165683ee 118 EP0write(0, 0);
sdivarci 0:0061165683ee 119 }
sdivarci 0:0061165683ee 120
sdivarci 0:0061165683ee 121 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
sdivarci 0:0061165683ee 122 uint32_t flags) {
sdivarci 0:0061165683ee 123 uint32_t epIndex = endpoint >> 1;
sdivarci 0:0061165683ee 124
sdivarci 0:0061165683ee 125 uint32_t type;
sdivarci 0:0061165683ee 126 switch (endpoint) {
sdivarci 0:0061165683ee 127 case EP0IN:
sdivarci 0:0061165683ee 128 case EP0OUT:
sdivarci 0:0061165683ee 129 type = 0;
sdivarci 0:0061165683ee 130 break;
sdivarci 0:0061165683ee 131 case EPISO_IN:
sdivarci 0:0061165683ee 132 case EPISO_OUT:
sdivarci 0:0061165683ee 133 type = 1;
sdivarci 0:0061165683ee 134 case EPBULK_IN:
sdivarci 0:0061165683ee 135 case EPBULK_OUT:
sdivarci 0:0061165683ee 136 type = 2;
sdivarci 0:0061165683ee 137 break;
sdivarci 0:0061165683ee 138 case EPINT_IN:
sdivarci 0:0061165683ee 139 case EPINT_OUT:
sdivarci 0:0061165683ee 140 type = 3;
sdivarci 0:0061165683ee 141 break;
sdivarci 0:0061165683ee 142 }
sdivarci 0:0061165683ee 143
sdivarci 0:0061165683ee 144 // Generic in or out EP controls
sdivarci 0:0061165683ee 145 uint32_t control = (maxPacket << 0) | // Packet size
sdivarci 0:0061165683ee 146 (1 << 15) | // Active endpoint
sdivarci 0:0061165683ee 147 (type << 18); // Endpoint type
sdivarci 0:0061165683ee 148
sdivarci 0:0061165683ee 149 if (endpoint & 0x1) { // In Endpoint
sdivarci 0:0061165683ee 150 // Set up the Tx FIFO
sdivarci 0:0061165683ee 151 if (endpoint == EP0IN) {
sdivarci 0:0061165683ee 152 OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
sdivarci 0:0061165683ee 153 (bufferEnd << 0);
sdivarci 0:0061165683ee 154 }
sdivarci 0:0061165683ee 155 else {
sdivarci 0:0061165683ee 156 OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
sdivarci 0:0061165683ee 157 (bufferEnd << 0);
sdivarci 0:0061165683ee 158 }
sdivarci 0:0061165683ee 159 bufferEnd += maxPacket >> 2;
sdivarci 0:0061165683ee 160
sdivarci 0:0061165683ee 161 // Set the In EP specific control settings
sdivarci 0:0061165683ee 162 if (endpoint != EP0IN) {
sdivarci 0:0061165683ee 163 control |= (1 << 28); // SD0PID
sdivarci 0:0061165683ee 164 }
sdivarci 0:0061165683ee 165
sdivarci 0:0061165683ee 166 control |= (epIndex << 22) | // TxFIFO index
sdivarci 0:0061165683ee 167 (1 << 27); // SNAK
sdivarci 0:0061165683ee 168 OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
sdivarci 0:0061165683ee 169
sdivarci 0:0061165683ee 170 // Unmask the interrupt
sdivarci 0:0061165683ee 171 OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
sdivarci 0:0061165683ee 172 }
sdivarci 0:0061165683ee 173 else { // Out endpoint
sdivarci 0:0061165683ee 174 // Set the out EP specific control settings
sdivarci 0:0061165683ee 175 control |= (1 << 26); // CNAK
sdivarci 0:0061165683ee 176 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
sdivarci 0:0061165683ee 177
sdivarci 0:0061165683ee 178 // Unmask the interrupt
sdivarci 0:0061165683ee 179 OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
sdivarci 0:0061165683ee 180 }
sdivarci 0:0061165683ee 181 return true;
sdivarci 0:0061165683ee 182 }
sdivarci 0:0061165683ee 183
sdivarci 0:0061165683ee 184 // read setup packet
sdivarci 0:0061165683ee 185 void USBHAL::EP0setup(uint8_t *buffer) {
sdivarci 0:0061165683ee 186 memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
sdivarci 0:0061165683ee 187 }
sdivarci 0:0061165683ee 188
sdivarci 0:0061165683ee 189 void USBHAL::EP0readStage(void) {
sdivarci 0:0061165683ee 190 }
sdivarci 0:0061165683ee 191
sdivarci 0:0061165683ee 192 void USBHAL::EP0read(void) {
sdivarci 0:0061165683ee 193 }
sdivarci 0:0061165683ee 194
sdivarci 0:0061165683ee 195 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
sdivarci 0:0061165683ee 196 uint32_t* buffer32 = (uint32_t *) buffer;
sdivarci 0:0061165683ee 197 uint32_t length = rxFifoCount;
sdivarci 0:0061165683ee 198 for (uint32_t i = 0; i < length; i += 4) {
sdivarci 0:0061165683ee 199 buffer32[i >> 2] = OTG_FS->FIFO[0][0];
sdivarci 0:0061165683ee 200 }
sdivarci 0:0061165683ee 201
sdivarci 0:0061165683ee 202 rxFifoCount = 0;
sdivarci 0:0061165683ee 203 return length;
sdivarci 0:0061165683ee 204 }
sdivarci 0:0061165683ee 205
sdivarci 0:0061165683ee 206 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
sdivarci 0:0061165683ee 207 endpointWrite(0, buffer, size);
sdivarci 0:0061165683ee 208 }
sdivarci 0:0061165683ee 209
sdivarci 0:0061165683ee 210 void USBHAL::EP0getWriteResult(void) {
sdivarci 0:0061165683ee 211 }
sdivarci 0:0061165683ee 212
sdivarci 0:0061165683ee 213 void USBHAL::EP0stall(void) {
sdivarci 0:0061165683ee 214 // If we stall the out endpoint here then we have problems transferring
sdivarci 0:0061165683ee 215 // and setup requests after the (stalled) get device qualifier requests.
sdivarci 0:0061165683ee 216 // TODO: Find out if this is correct behavior, or whether we are doing
sdivarci 0:0061165683ee 217 // something else wrong
sdivarci 0:0061165683ee 218 stallEndpoint(EP0IN);
sdivarci 0:0061165683ee 219 // stallEndpoint(EP0OUT);
sdivarci 0:0061165683ee 220 }
sdivarci 0:0061165683ee 221
sdivarci 0:0061165683ee 222 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
sdivarci 0:0061165683ee 223 uint32_t epIndex = endpoint >> 1;
sdivarci 0:0061165683ee 224 uint32_t size = (1 << 19) | // 1 packet
sdivarci 0:0061165683ee 225 (maximumSize << 0); // Packet size
sdivarci 0:0061165683ee 226 // if (endpoint == EP0OUT) {
sdivarci 0:0061165683ee 227 size |= (1 << 29); // 1 setup packet
sdivarci 0:0061165683ee 228 // }
sdivarci 0:0061165683ee 229 OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
sdivarci 0:0061165683ee 230 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
sdivarci 0:0061165683ee 231 (1 << 26); // Clear NAK
sdivarci 0:0061165683ee 232
sdivarci 0:0061165683ee 233 epComplete &= ~(1 << endpoint);
sdivarci 0:0061165683ee 234 return EP_PENDING;
sdivarci 0:0061165683ee 235 }
sdivarci 0:0061165683ee 236
sdivarci 0:0061165683ee 237 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
sdivarci 0:0061165683ee 238 if (!(epComplete & (1 << endpoint))) {
sdivarci 0:0061165683ee 239 return EP_PENDING;
sdivarci 0:0061165683ee 240 }
sdivarci 0:0061165683ee 241
sdivarci 0:0061165683ee 242 uint32_t* buffer32 = (uint32_t *) buffer;
sdivarci 0:0061165683ee 243 uint32_t length = rxFifoCount;
sdivarci 0:0061165683ee 244 for (uint32_t i = 0; i < length; i += 4) {
sdivarci 0:0061165683ee 245 buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
sdivarci 0:0061165683ee 246 }
sdivarci 0:0061165683ee 247 rxFifoCount = 0;
sdivarci 0:0061165683ee 248 *bytesRead = length;
sdivarci 0:0061165683ee 249 return EP_COMPLETED;
sdivarci 0:0061165683ee 250 }
sdivarci 0:0061165683ee 251
sdivarci 0:0061165683ee 252 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
sdivarci 0:0061165683ee 253 uint32_t epIndex = endpoint >> 1;
sdivarci 0:0061165683ee 254 OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
sdivarci 0:0061165683ee 255 (size << 0); // Size of packet
sdivarci 0:0061165683ee 256 OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
sdivarci 0:0061165683ee 257 (1 << 26); // CNAK
sdivarci 0:0061165683ee 258 OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
sdivarci 0:0061165683ee 259
sdivarci 0:0061165683ee 260 while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
sdivarci 0:0061165683ee 261
sdivarci 0:0061165683ee 262 for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
sdivarci 0:0061165683ee 263 OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
sdivarci 0:0061165683ee 264 }
sdivarci 0:0061165683ee 265
sdivarci 0:0061165683ee 266 epComplete &= ~(1 << endpoint);
sdivarci 0:0061165683ee 267
sdivarci 0:0061165683ee 268 return EP_PENDING;
sdivarci 0:0061165683ee 269 }
sdivarci 0:0061165683ee 270
sdivarci 0:0061165683ee 271 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
sdivarci 0:0061165683ee 272 if (epComplete & (1 << endpoint)) {
sdivarci 0:0061165683ee 273 epComplete &= ~(1 << endpoint);
sdivarci 0:0061165683ee 274 return EP_COMPLETED;
sdivarci 0:0061165683ee 275 }
sdivarci 0:0061165683ee 276
sdivarci 0:0061165683ee 277 return EP_PENDING;
sdivarci 0:0061165683ee 278 }
sdivarci 0:0061165683ee 279
sdivarci 0:0061165683ee 280 void USBHAL::stallEndpoint(uint8_t endpoint) {
sdivarci 0:0061165683ee 281 if (endpoint & 0x1) { // In EP
sdivarci 0:0061165683ee 282 OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
sdivarci 0:0061165683ee 283 (1 << 21); // Stall
sdivarci 0:0061165683ee 284 }
sdivarci 0:0061165683ee 285 else { // Out EP
sdivarci 0:0061165683ee 286 OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
sdivarci 0:0061165683ee 287 OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
sdivarci 0:0061165683ee 288 (1 << 21); // Stall
sdivarci 0:0061165683ee 289 }
sdivarci 0:0061165683ee 290 }
sdivarci 0:0061165683ee 291
sdivarci 0:0061165683ee 292 void USBHAL::unstallEndpoint(uint8_t endpoint) {
sdivarci 0:0061165683ee 293
sdivarci 0:0061165683ee 294 }
sdivarci 0:0061165683ee 295
sdivarci 0:0061165683ee 296 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
sdivarci 0:0061165683ee 297 return false;
sdivarci 0:0061165683ee 298 }
sdivarci 0:0061165683ee 299
sdivarci 0:0061165683ee 300 void USBHAL::remoteWakeup(void) {
sdivarci 0:0061165683ee 301 }
sdivarci 0:0061165683ee 302
sdivarci 0:0061165683ee 303
sdivarci 0:0061165683ee 304 void USBHAL::_usbisr(void) {
sdivarci 0:0061165683ee 305 instance->usbisr();
sdivarci 0:0061165683ee 306 }
sdivarci 0:0061165683ee 307
sdivarci 0:0061165683ee 308
sdivarci 0:0061165683ee 309 void USBHAL::usbisr(void) {
sdivarci 0:0061165683ee 310 if (OTG_FS->GREGS.GINTSTS & (1 << 11)) { // USB Suspend
sdivarci 0:0061165683ee 311 suspendStateChanged(1);
sdivarci 0:0061165683ee 312 };
sdivarci 0:0061165683ee 313
sdivarci 0:0061165683ee 314 if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
sdivarci 0:0061165683ee 315 suspendStateChanged(0);
sdivarci 0:0061165683ee 316
sdivarci 0:0061165683ee 317 // Set SNAK bits
sdivarci 0:0061165683ee 318 OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
sdivarci 0:0061165683ee 319 OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
sdivarci 0:0061165683ee 320 OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
sdivarci 0:0061165683ee 321 OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
sdivarci 0:0061165683ee 322
sdivarci 0:0061165683ee 323 OTG_FS->DREGS.DIEPMSK = (1 << 0);
sdivarci 0:0061165683ee 324
sdivarci 0:0061165683ee 325 bufferEnd = 0;
sdivarci 0:0061165683ee 326
sdivarci 0:0061165683ee 327 // Set the receive FIFO size
sdivarci 0:0061165683ee 328 OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
sdivarci 0:0061165683ee 329 bufferEnd += rxFifoSize >> 2;
sdivarci 0:0061165683ee 330
sdivarci 0:0061165683ee 331 // Create the endpoints, and wait for setup packets on out EP0
sdivarci 0:0061165683ee 332 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
sdivarci 0:0061165683ee 333 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
sdivarci 0:0061165683ee 334 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
sdivarci 0:0061165683ee 335
sdivarci 0:0061165683ee 336 OTG_FS->GREGS.GINTSTS = (1 << 12);
sdivarci 0:0061165683ee 337 }
sdivarci 0:0061165683ee 338
sdivarci 0:0061165683ee 339 if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
sdivarci 0:0061165683ee 340 uint32_t status = OTG_FS->GREGS.GRXSTSP;
sdivarci 0:0061165683ee 341
sdivarci 0:0061165683ee 342 uint32_t endpoint = (status & 0xF) << 1;
sdivarci 0:0061165683ee 343 uint32_t length = (status >> 4) & 0x7FF;
sdivarci 0:0061165683ee 344 uint32_t type = (status >> 17) & 0xF;
sdivarci 0:0061165683ee 345
sdivarci 0:0061165683ee 346 rxFifoCount = length;
sdivarci 0:0061165683ee 347
sdivarci 0:0061165683ee 348 if (type == 0x6) {
sdivarci 0:0061165683ee 349 // Setup packet
sdivarci 0:0061165683ee 350 for (uint32_t i=0; i<length; i+=4) {
sdivarci 0:0061165683ee 351 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
sdivarci 0:0061165683ee 352 }
sdivarci 0:0061165683ee 353 rxFifoCount = 0;
sdivarci 0:0061165683ee 354 }
sdivarci 0:0061165683ee 355
sdivarci 0:0061165683ee 356 if (type == 0x4) {
sdivarci 0:0061165683ee 357 // Setup complete
sdivarci 0:0061165683ee 358 EP0setupCallback();
sdivarci 0:0061165683ee 359 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
sdivarci 0:0061165683ee 360 }
sdivarci 0:0061165683ee 361
sdivarci 0:0061165683ee 362 if (type == 0x2) {
sdivarci 0:0061165683ee 363 // Out packet
sdivarci 0:0061165683ee 364 if (endpoint == EP0OUT) {
sdivarci 0:0061165683ee 365 EP0out();
sdivarci 0:0061165683ee 366 }
sdivarci 0:0061165683ee 367 else {
sdivarci 0:0061165683ee 368 epComplete |= (1 << endpoint);
sdivarci 0:0061165683ee 369 if ((instance->*(epCallback[endpoint - 2]))()) {
sdivarci 0:0061165683ee 370 epComplete &= (1 << endpoint);
sdivarci 0:0061165683ee 371 }
sdivarci 0:0061165683ee 372 }
sdivarci 0:0061165683ee 373 }
sdivarci 0:0061165683ee 374
sdivarci 0:0061165683ee 375 for (uint32_t i=0; i<rxFifoCount; i+=4) {
sdivarci 0:0061165683ee 376 (void) OTG_FS->FIFO[0][0];
sdivarci 0:0061165683ee 377 }
sdivarci 0:0061165683ee 378 OTG_FS->GREGS.GINTSTS = (1 << 4);
sdivarci 0:0061165683ee 379 }
sdivarci 0:0061165683ee 380
sdivarci 0:0061165683ee 381 if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
sdivarci 0:0061165683ee 382 // Loop through the in endpoints
sdivarci 0:0061165683ee 383 for (uint32_t i=0; i<4; i++) {
sdivarci 0:0061165683ee 384 if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
sdivarci 0:0061165683ee 385
sdivarci 0:0061165683ee 386 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
sdivarci 0:0061165683ee 387 // If the Tx FIFO is empty on EP0 we need to send a further
sdivarci 0:0061165683ee 388 // packet, so call EP0in()
sdivarci 0:0061165683ee 389 if (i == 0) {
sdivarci 0:0061165683ee 390 EP0in();
sdivarci 0:0061165683ee 391 }
sdivarci 0:0061165683ee 392 // Clear the interrupt
sdivarci 0:0061165683ee 393 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
sdivarci 0:0061165683ee 394 // Stop firing Tx empty interrupts
sdivarci 0:0061165683ee 395 // Will get turned on again if another write is called
sdivarci 0:0061165683ee 396 OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
sdivarci 0:0061165683ee 397 }
sdivarci 0:0061165683ee 398
sdivarci 0:0061165683ee 399 // If the transfer is complete
sdivarci 0:0061165683ee 400 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
sdivarci 0:0061165683ee 401 epComplete |= (1 << (1 + (i << 1)));
sdivarci 0:0061165683ee 402 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
sdivarci 0:0061165683ee 403 }
sdivarci 0:0061165683ee 404 }
sdivarci 0:0061165683ee 405 }
sdivarci 0:0061165683ee 406 OTG_FS->GREGS.GINTSTS = (1 << 18);
sdivarci 0:0061165683ee 407 }
sdivarci 0:0061165683ee 408
sdivarci 0:0061165683ee 409 if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
sdivarci 0:0061165683ee 410 SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
sdivarci 0:0061165683ee 411 OTG_FS->GREGS.GINTSTS = (1 << 3);
sdivarci 0:0061165683ee 412 }
sdivarci 0:0061165683ee 413 }
sdivarci 0:0061165683ee 414
sdivarci 0:0061165683ee 415
sdivarci 0:0061165683ee 416 #endif