Sinan Divarci / Mbed OS max4146x_comp

max4146x_comp

Dependencies:   MAX14690

USBDevice/USBDevice/USBHAL_KL25Z.cpp@0:0061165683ee, 2020-10-25 (annotated)

Committer:
sdivarci
Date:
Sun Oct 25 20:10:02 2020 +0000
Revision:
0:0061165683ee
sdivarci

Who changed what in which revision?

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sdivarci 0:0061165683ee 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
sdivarci 0:0061165683ee 2 *
sdivarci 0:0061165683ee 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
sdivarci 0:0061165683ee 4 * and associated documentation files (the "Software"), to deal in the Software without
sdivarci 0:0061165683ee 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
sdivarci 0:0061165683ee 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
sdivarci 0:0061165683ee 7 * Software is furnished to do so, subject to the following conditions:
sdivarci 0:0061165683ee 8 *
sdivarci 0:0061165683ee 9 * The above copyright notice and this permission notice shall be included in all copies or
sdivarci 0:0061165683ee 10 * substantial portions of the Software.
sdivarci 0:0061165683ee 11 *
sdivarci 0:0061165683ee 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
sdivarci 0:0061165683ee 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
sdivarci 0:0061165683ee 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
sdivarci 0:0061165683ee 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
sdivarci 0:0061165683ee 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
sdivarci 0:0061165683ee 17 */
sdivarci 0:0061165683ee 18
sdivarci 0:0061165683ee 19 #if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
sdivarci 0:0061165683ee 20
sdivarci 0:0061165683ee 21 #include "USBHAL.h"
sdivarci 0:0061165683ee 22
sdivarci 0:0061165683ee 23 USBHAL * USBHAL::instance;
sdivarci 0:0061165683ee 24
sdivarci 0:0061165683ee 25 static volatile int epComplete = 0;
sdivarci 0:0061165683ee 26
sdivarci 0:0061165683ee 27 // Convert physical endpoint number to register bit
sdivarci 0:0061165683ee 28 #define EP(endpoint) (1<<(endpoint))
sdivarci 0:0061165683ee 29
sdivarci 0:0061165683ee 30 // Convert physical to logical
sdivarci 0:0061165683ee 31 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
sdivarci 0:0061165683ee 32
sdivarci 0:0061165683ee 33 // Get endpoint direction
sdivarci 0:0061165683ee 34 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
sdivarci 0:0061165683ee 35 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
sdivarci 0:0061165683ee 36
sdivarci 0:0061165683ee 37 #define BD_OWN_MASK (1<<7)
sdivarci 0:0061165683ee 38 #define BD_DATA01_MASK (1<<6)
sdivarci 0:0061165683ee 39 #define BD_KEEP_MASK (1<<5)
sdivarci 0:0061165683ee 40 #define BD_NINC_MASK (1<<4)
sdivarci 0:0061165683ee 41 #define BD_DTS_MASK (1<<3)
sdivarci 0:0061165683ee 42 #define BD_STALL_MASK (1<<2)
sdivarci 0:0061165683ee 43
sdivarci 0:0061165683ee 44 #define TX 1
sdivarci 0:0061165683ee 45 #define RX 0
sdivarci 0:0061165683ee 46 #define ODD 0
sdivarci 0:0061165683ee 47 #define EVEN 1
sdivarci 0:0061165683ee 48 // this macro waits a physical endpoint number
sdivarci 0:0061165683ee 49 #define EP_BDT_IDX(ep, dir, odd) (((ep * 4) + (2 * dir) + (1 * odd)))
sdivarci 0:0061165683ee 50
sdivarci 0:0061165683ee 51 #define SETUP_TOKEN 0x0D
sdivarci 0:0061165683ee 52 #define IN_TOKEN 0x09
sdivarci 0:0061165683ee 53 #define OUT_TOKEN 0x01
sdivarci 0:0061165683ee 54 #define TOK_PID(idx) ((bdt[idx].info >> 2) & 0x0F)
sdivarci 0:0061165683ee 55
sdivarci 0:0061165683ee 56 // for each endpt: 8 bytes
sdivarci 0:0061165683ee 57 typedef struct BDT {
sdivarci 0:0061165683ee 58 uint8_t info; // BD[0:7]
sdivarci 0:0061165683ee 59 uint8_t dummy; // RSVD: BD[8:15]
sdivarci 0:0061165683ee 60 uint16_t byte_count; // BD[16:32]
sdivarci 0:0061165683ee 61 uint32_t address; // Addr
sdivarci 0:0061165683ee 62 } BDT;
sdivarci 0:0061165683ee 63
sdivarci 0:0061165683ee 64
sdivarci 0:0061165683ee 65 // there are:
sdivarci 0:0061165683ee 66 // * 16 bidirectionnal endpt -> 32 physical endpt
sdivarci 0:0061165683ee 67 // * as there are ODD and EVEN buffer -> 32*2 bdt
sdivarci 0:0061165683ee 68 __attribute__((__aligned__(512))) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
sdivarci 0:0061165683ee 69 uint8_t * endpoint_buffer[(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2];
sdivarci 0:0061165683ee 70 uint8_t * endpoint_buffer_iso[2*2];
sdivarci 0:0061165683ee 71
sdivarci 0:0061165683ee 72 static uint8_t set_addr = 0;
sdivarci 0:0061165683ee 73 static uint8_t addr = 0;
sdivarci 0:0061165683ee 74
sdivarci 0:0061165683ee 75 static uint32_t Data1 = 0x55555555;
sdivarci 0:0061165683ee 76
sdivarci 0:0061165683ee 77 static uint32_t frameNumber() {
sdivarci 0:0061165683ee 78 return((USB0->FRMNUML | (USB0->FRMNUMH << 8)) & 0x07FF);
sdivarci 0:0061165683ee 79 }
sdivarci 0:0061165683ee 80
sdivarci 0:0061165683ee 81 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
sdivarci 0:0061165683ee 82 return 0;
sdivarci 0:0061165683ee 83 }
sdivarci 0:0061165683ee 84
sdivarci 0:0061165683ee 85 USBHAL::USBHAL(void) {
sdivarci 0:0061165683ee 86 // Disable IRQ
sdivarci 0:0061165683ee 87 NVIC_DisableIRQ(USB0_IRQn);
sdivarci 0:0061165683ee 88
sdivarci 0:0061165683ee 89 #if defined(TARGET_K64F)
sdivarci 0:0061165683ee 90 MPU->CESR=0;
sdivarci 0:0061165683ee 91 #endif
sdivarci 0:0061165683ee 92 // fill in callback array
sdivarci 0:0061165683ee 93 epCallback[0] = &USBHAL::EP1_OUT_callback;
sdivarci 0:0061165683ee 94 epCallback[1] = &USBHAL::EP1_IN_callback;
sdivarci 0:0061165683ee 95 epCallback[2] = &USBHAL::EP2_OUT_callback;
sdivarci 0:0061165683ee 96 epCallback[3] = &USBHAL::EP2_IN_callback;
sdivarci 0:0061165683ee 97 epCallback[4] = &USBHAL::EP3_OUT_callback;
sdivarci 0:0061165683ee 98 epCallback[5] = &USBHAL::EP3_IN_callback;
sdivarci 0:0061165683ee 99 epCallback[6] = &USBHAL::EP4_OUT_callback;
sdivarci 0:0061165683ee 100 epCallback[7] = &USBHAL::EP4_IN_callback;
sdivarci 0:0061165683ee 101 epCallback[8] = &USBHAL::EP5_OUT_callback;
sdivarci 0:0061165683ee 102 epCallback[9] = &USBHAL::EP5_IN_callback;
sdivarci 0:0061165683ee 103 epCallback[10] = &USBHAL::EP6_OUT_callback;
sdivarci 0:0061165683ee 104 epCallback[11] = &USBHAL::EP6_IN_callback;
sdivarci 0:0061165683ee 105 epCallback[12] = &USBHAL::EP7_OUT_callback;
sdivarci 0:0061165683ee 106 epCallback[13] = &USBHAL::EP7_IN_callback;
sdivarci 0:0061165683ee 107 epCallback[14] = &USBHAL::EP8_OUT_callback;
sdivarci 0:0061165683ee 108 epCallback[15] = &USBHAL::EP8_IN_callback;
sdivarci 0:0061165683ee 109 epCallback[16] = &USBHAL::EP9_OUT_callback;
sdivarci 0:0061165683ee 110 epCallback[17] = &USBHAL::EP9_IN_callback;
sdivarci 0:0061165683ee 111 epCallback[18] = &USBHAL::EP10_OUT_callback;
sdivarci 0:0061165683ee 112 epCallback[19] = &USBHAL::EP10_IN_callback;
sdivarci 0:0061165683ee 113 epCallback[20] = &USBHAL::EP11_OUT_callback;
sdivarci 0:0061165683ee 114 epCallback[21] = &USBHAL::EP11_IN_callback;
sdivarci 0:0061165683ee 115 epCallback[22] = &USBHAL::EP12_OUT_callback;
sdivarci 0:0061165683ee 116 epCallback[23] = &USBHAL::EP12_IN_callback;
sdivarci 0:0061165683ee 117 epCallback[24] = &USBHAL::EP13_OUT_callback;
sdivarci 0:0061165683ee 118 epCallback[25] = &USBHAL::EP13_IN_callback;
sdivarci 0:0061165683ee 119 epCallback[26] = &USBHAL::EP14_OUT_callback;
sdivarci 0:0061165683ee 120 epCallback[27] = &USBHAL::EP14_IN_callback;
sdivarci 0:0061165683ee 121 epCallback[28] = &USBHAL::EP15_OUT_callback;
sdivarci 0:0061165683ee 122 epCallback[29] = &USBHAL::EP15_IN_callback;
sdivarci 0:0061165683ee 123
sdivarci 0:0061165683ee 124 #if defined(TARGET_KL43Z)
sdivarci 0:0061165683ee 125 // enable USBFS clock
sdivarci 0:0061165683ee 126 SIM->SCGC4 |= SIM_SCGC4_USBFS_MASK;
sdivarci 0:0061165683ee 127
sdivarci 0:0061165683ee 128 // enable the IRC48M clock
sdivarci 0:0061165683ee 129 USB0->CLK_RECOVER_IRC_EN |= USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK;
sdivarci 0:0061165683ee 130
sdivarci 0:0061165683ee 131 // enable the USB clock recovery tuning
sdivarci 0:0061165683ee 132 USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
sdivarci 0:0061165683ee 133
sdivarci 0:0061165683ee 134 // choose usb src clock
sdivarci 0:0061165683ee 135 SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK;
sdivarci 0:0061165683ee 136 #else
sdivarci 0:0061165683ee 137 // choose usb src as PLL
sdivarci 0:0061165683ee 138 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
sdivarci 0:0061165683ee 139 SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | (1 << SIM_SOPT2_PLLFLLSEL_SHIFT));
sdivarci 0:0061165683ee 140
sdivarci 0:0061165683ee 141 // enable OTG clock
sdivarci 0:0061165683ee 142 SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
sdivarci 0:0061165683ee 143 #endif
sdivarci 0:0061165683ee 144
sdivarci 0:0061165683ee 145 // Attach IRQ
sdivarci 0:0061165683ee 146 instance = this;
sdivarci 0:0061165683ee 147 NVIC_SetVector(USB0_IRQn, (uint32_t)&_usbisr);
sdivarci 0:0061165683ee 148 NVIC_EnableIRQ(USB0_IRQn);
sdivarci 0:0061165683ee 149
sdivarci 0:0061165683ee 150 // USB Module Configuration
sdivarci 0:0061165683ee 151 // Reset USB Module
sdivarci 0:0061165683ee 152 USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
sdivarci 0:0061165683ee 153 while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
sdivarci 0:0061165683ee 154
sdivarci 0:0061165683ee 155 // Set BDT Base Register
sdivarci 0:0061165683ee 156 USB0->BDTPAGE1 = (uint8_t)((uint32_t)bdt>>8);
sdivarci 0:0061165683ee 157 USB0->BDTPAGE2 = (uint8_t)((uint32_t)bdt>>16);
sdivarci 0:0061165683ee 158 USB0->BDTPAGE3 = (uint8_t)((uint32_t)bdt>>24);
sdivarci 0:0061165683ee 159
sdivarci 0:0061165683ee 160 // Clear interrupt flag
sdivarci 0:0061165683ee 161 USB0->ISTAT = 0xff;
sdivarci 0:0061165683ee 162
sdivarci 0:0061165683ee 163 // USB Interrupt Enablers
sdivarci 0:0061165683ee 164 USB0->INTEN |= USB_INTEN_TOKDNEEN_MASK |
sdivarci 0:0061165683ee 165 USB_INTEN_SOFTOKEN_MASK |
sdivarci 0:0061165683ee 166 USB_INTEN_ERROREN_MASK |
sdivarci 0:0061165683ee 167 USB_INTEN_USBRSTEN_MASK;
sdivarci 0:0061165683ee 168
sdivarci 0:0061165683ee 169 // Disable weak pull downs
sdivarci 0:0061165683ee 170 USB0->USBCTRL &= ~(USB_USBCTRL_PDE_MASK | USB_USBCTRL_SUSP_MASK);
sdivarci 0:0061165683ee 171
sdivarci 0:0061165683ee 172 USB0->USBTRC0 |= 0x40;
sdivarci 0:0061165683ee 173 }
sdivarci 0:0061165683ee 174
sdivarci 0:0061165683ee 175 USBHAL::~USBHAL(void) { }
sdivarci 0:0061165683ee 176
sdivarci 0:0061165683ee 177 void USBHAL::connect(void) {
sdivarci 0:0061165683ee 178 // enable USB
sdivarci 0:0061165683ee 179 USB0->CTL |= USB_CTL_USBENSOFEN_MASK;
sdivarci 0:0061165683ee 180 // Pull up enable
sdivarci 0:0061165683ee 181 USB0->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
sdivarci 0:0061165683ee 182 }
sdivarci 0:0061165683ee 183
sdivarci 0:0061165683ee 184 void USBHAL::disconnect(void) {
sdivarci 0:0061165683ee 185 // disable USB
sdivarci 0:0061165683ee 186 USB0->CTL &= ~USB_CTL_USBENSOFEN_MASK;
sdivarci 0:0061165683ee 187 // Pull up disable
sdivarci 0:0061165683ee 188 USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
sdivarci 0:0061165683ee 189
sdivarci 0:0061165683ee 190 //Free buffers if required:
sdivarci 0:0061165683ee 191 for (int i = 0; i<(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2; i++) {
sdivarci 0:0061165683ee 192 free(endpoint_buffer[i]);
sdivarci 0:0061165683ee 193 endpoint_buffer[i] = NULL;
sdivarci 0:0061165683ee 194 }
sdivarci 0:0061165683ee 195 free(endpoint_buffer_iso[2]);
sdivarci 0:0061165683ee 196 endpoint_buffer_iso[2] = NULL;
sdivarci 0:0061165683ee 197 free(endpoint_buffer_iso[0]);
sdivarci 0:0061165683ee 198 endpoint_buffer_iso[0] = NULL;
sdivarci 0:0061165683ee 199 }
sdivarci 0:0061165683ee 200
sdivarci 0:0061165683ee 201 void USBHAL::configureDevice(void) {
sdivarci 0:0061165683ee 202 // not needed
sdivarci 0:0061165683ee 203 }
sdivarci 0:0061165683ee 204
sdivarci 0:0061165683ee 205 void USBHAL::unconfigureDevice(void) {
sdivarci 0:0061165683ee 206 // not needed
sdivarci 0:0061165683ee 207 }
sdivarci 0:0061165683ee 208
sdivarci 0:0061165683ee 209 void USBHAL::setAddress(uint8_t address) {
sdivarci 0:0061165683ee 210 // we don't set the address now otherwise the usb controller does not ack
sdivarci 0:0061165683ee 211 // we set a flag instead
sdivarci 0:0061165683ee 212 // see usbisr when an IN token is received
sdivarci 0:0061165683ee 213 set_addr = 1;
sdivarci 0:0061165683ee 214 addr = address;
sdivarci 0:0061165683ee 215 }
sdivarci 0:0061165683ee 216
sdivarci 0:0061165683ee 217 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
sdivarci 0:0061165683ee 218 uint32_t handshake_flag = 0;
sdivarci 0:0061165683ee 219 uint8_t * buf;
sdivarci 0:0061165683ee 220
sdivarci 0:0061165683ee 221 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
sdivarci 0:0061165683ee 222 return false;
sdivarci 0:0061165683ee 223 }
sdivarci 0:0061165683ee 224
sdivarci 0:0061165683ee 225 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
sdivarci 0:0061165683ee 226
sdivarci 0:0061165683ee 227 if ((flags & ISOCHRONOUS) == 0) {
sdivarci 0:0061165683ee 228 handshake_flag = USB_ENDPT_EPHSHK_MASK;
sdivarci 0:0061165683ee 229 if (IN_EP(endpoint)) {
sdivarci 0:0061165683ee 230 if (endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)] == NULL)
sdivarci 0:0061165683ee 231 endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)] = (uint8_t *) malloc (64);
sdivarci 0:0061165683ee 232 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)][0];
sdivarci 0:0061165683ee 233 } else {
sdivarci 0:0061165683ee 234 if (endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)] == NULL)
sdivarci 0:0061165683ee 235 endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)] = (uint8_t *) malloc (64);
sdivarci 0:0061165683ee 236 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)][0];
sdivarci 0:0061165683ee 237 }
sdivarci 0:0061165683ee 238 } else {
sdivarci 0:0061165683ee 239 if (IN_EP(endpoint)) {
sdivarci 0:0061165683ee 240 if (endpoint_buffer_iso[2] == NULL)
sdivarci 0:0061165683ee 241 endpoint_buffer_iso[2] = (uint8_t *) malloc (1023);
sdivarci 0:0061165683ee 242 buf = &endpoint_buffer_iso[2][0];
sdivarci 0:0061165683ee 243 } else {
sdivarci 0:0061165683ee 244 if (endpoint_buffer_iso[0] == NULL)
sdivarci 0:0061165683ee 245 endpoint_buffer_iso[0] = (uint8_t *) malloc (1023);
sdivarci 0:0061165683ee 246 buf = &endpoint_buffer_iso[0][0];
sdivarci 0:0061165683ee 247 }
sdivarci 0:0061165683ee 248 }
sdivarci 0:0061165683ee 249
sdivarci 0:0061165683ee 250 // IN endpt -> device to host (TX)
sdivarci 0:0061165683ee 251 if (IN_EP(endpoint)) {
sdivarci 0:0061165683ee 252 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
sdivarci 0:0061165683ee 253 USB_ENDPT_EPTXEN_MASK; // en TX (IN) tran
sdivarci 0:0061165683ee 254 bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].address = (uint32_t) buf;
sdivarci 0:0061165683ee 255 bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].address = 0;
sdivarci 0:0061165683ee 256 }
sdivarci 0:0061165683ee 257 // OUT endpt -> host to device (RX)
sdivarci 0:0061165683ee 258 else {
sdivarci 0:0061165683ee 259 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
sdivarci 0:0061165683ee 260 USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran.
sdivarci 0:0061165683ee 261 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = maxPacket;
sdivarci 0:0061165683ee 262 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf;
sdivarci 0:0061165683ee 263 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_OWN_MASK | BD_DTS_MASK;
sdivarci 0:0061165683ee 264 bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0;
sdivarci 0:0061165683ee 265 }
sdivarci 0:0061165683ee 266
sdivarci 0:0061165683ee 267 Data1 |= (1 << endpoint);
sdivarci 0:0061165683ee 268
sdivarci 0:0061165683ee 269 return true;
sdivarci 0:0061165683ee 270 }
sdivarci 0:0061165683ee 271
sdivarci 0:0061165683ee 272 // read setup packet
sdivarci 0:0061165683ee 273 void USBHAL::EP0setup(uint8_t *buffer) {
sdivarci 0:0061165683ee 274 uint32_t sz;
sdivarci 0:0061165683ee 275 endpointReadResult(EP0OUT, buffer, &sz);
sdivarci 0:0061165683ee 276 }
sdivarci 0:0061165683ee 277
sdivarci 0:0061165683ee 278 void USBHAL::EP0readStage(void) {
sdivarci 0:0061165683ee 279 Data1 &= ~1UL; // set DATA0
sdivarci 0:0061165683ee 280 bdt[0].info = (BD_DTS_MASK | BD_OWN_MASK);
sdivarci 0:0061165683ee 281 }
sdivarci 0:0061165683ee 282
sdivarci 0:0061165683ee 283 void USBHAL::EP0read(void) {
sdivarci 0:0061165683ee 284 uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0);
sdivarci 0:0061165683ee 285 bdt[idx].byte_count = MAX_PACKET_SIZE_EP0;
sdivarci 0:0061165683ee 286 }
sdivarci 0:0061165683ee 287
sdivarci 0:0061165683ee 288 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
sdivarci 0:0061165683ee 289 uint32_t sz;
sdivarci 0:0061165683ee 290 endpointReadResult(EP0OUT, buffer, &sz);
sdivarci 0:0061165683ee 291 return sz;
sdivarci 0:0061165683ee 292 }
sdivarci 0:0061165683ee 293
sdivarci 0:0061165683ee 294 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
sdivarci 0:0061165683ee 295 endpointWrite(EP0IN, buffer, size);
sdivarci 0:0061165683ee 296 }
sdivarci 0:0061165683ee 297
sdivarci 0:0061165683ee 298 void USBHAL::EP0getWriteResult(void) {
sdivarci 0:0061165683ee 299 }
sdivarci 0:0061165683ee 300
sdivarci 0:0061165683ee 301 void USBHAL::EP0stall(void) {
sdivarci 0:0061165683ee 302 stallEndpoint(EP0OUT);
sdivarci 0:0061165683ee 303 }
sdivarci 0:0061165683ee 304
sdivarci 0:0061165683ee 305 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
sdivarci 0:0061165683ee 306 endpoint = PHY_TO_LOG(endpoint);
sdivarci 0:0061165683ee 307 uint32_t idx = EP_BDT_IDX(endpoint, RX, 0);
sdivarci 0:0061165683ee 308 bdt[idx].byte_count = maximumSize;
sdivarci 0:0061165683ee 309 return EP_PENDING;
sdivarci 0:0061165683ee 310 }
sdivarci 0:0061165683ee 311
sdivarci 0:0061165683ee 312 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
sdivarci 0:0061165683ee 313 uint32_t n, sz, idx, setup = 0;
sdivarci 0:0061165683ee 314 uint8_t not_iso;
sdivarci 0:0061165683ee 315 uint8_t * ep_buf;
sdivarci 0:0061165683ee 316
sdivarci 0:0061165683ee 317 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
sdivarci 0:0061165683ee 318
sdivarci 0:0061165683ee 319 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
sdivarci 0:0061165683ee 320 return EP_INVALID;
sdivarci 0:0061165683ee 321 }
sdivarci 0:0061165683ee 322
sdivarci 0:0061165683ee 323 // if read on a IN endpoint -> error
sdivarci 0:0061165683ee 324 if (IN_EP(endpoint)) {
sdivarci 0:0061165683ee 325 return EP_INVALID;
sdivarci 0:0061165683ee 326 }
sdivarci 0:0061165683ee 327
sdivarci 0:0061165683ee 328 idx = EP_BDT_IDX(log_endpoint, RX, 0);
sdivarci 0:0061165683ee 329 sz = bdt[idx].byte_count;
sdivarci 0:0061165683ee 330 not_iso = USB0->ENDPOINT[log_endpoint].ENDPT & USB_ENDPT_EPHSHK_MASK;
sdivarci 0:0061165683ee 331
sdivarci 0:0061165683ee 332 //for isochronous endpoint, we don't wait an interrupt
sdivarci 0:0061165683ee 333 if ((log_endpoint != 0) && not_iso && !(epComplete & EP(endpoint))) {
sdivarci 0:0061165683ee 334 return EP_PENDING;
sdivarci 0:0061165683ee 335 }
sdivarci 0:0061165683ee 336
sdivarci 0:0061165683ee 337 if ((log_endpoint == 0) && (TOK_PID(idx) == SETUP_TOKEN)) {
sdivarci 0:0061165683ee 338 setup = 1;
sdivarci 0:0061165683ee 339 }
sdivarci 0:0061165683ee 340
sdivarci 0:0061165683ee 341 // non iso endpoint
sdivarci 0:0061165683ee 342 if (not_iso) {
sdivarci 0:0061165683ee 343 ep_buf = endpoint_buffer[idx];
sdivarci 0:0061165683ee 344 } else {
sdivarci 0:0061165683ee 345 ep_buf = endpoint_buffer_iso[0];
sdivarci 0:0061165683ee 346 }
sdivarci 0:0061165683ee 347
sdivarci 0:0061165683ee 348 for (n = 0; n < sz; n++) {
sdivarci 0:0061165683ee 349 buffer[n] = ep_buf[n];
sdivarci 0:0061165683ee 350 }
sdivarci 0:0061165683ee 351
sdivarci 0:0061165683ee 352 if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) {
sdivarci 0:0061165683ee 353 if (setup && (buffer[6] == 0)) // if no setup data stage,
sdivarci 0:0061165683ee 354 Data1 &= ~1UL; // set DATA0
sdivarci 0:0061165683ee 355 else
sdivarci 0:0061165683ee 356 Data1 ^= (1 << endpoint);
sdivarci 0:0061165683ee 357 }
sdivarci 0:0061165683ee 358
sdivarci 0:0061165683ee 359 if (((Data1 >> endpoint) & 1)) {
sdivarci 0:0061165683ee 360 bdt[idx].info = BD_DTS_MASK | BD_DATA01_MASK | BD_OWN_MASK;
sdivarci 0:0061165683ee 361 }
sdivarci 0:0061165683ee 362 else {
sdivarci 0:0061165683ee 363 bdt[idx].info = BD_DTS_MASK | BD_OWN_MASK;
sdivarci 0:0061165683ee 364 }
sdivarci 0:0061165683ee 365
sdivarci 0:0061165683ee 366 USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
sdivarci 0:0061165683ee 367 *bytesRead = sz;
sdivarci 0:0061165683ee 368
sdivarci 0:0061165683ee 369 epComplete &= ~EP(endpoint);
sdivarci 0:0061165683ee 370 return EP_COMPLETED;
sdivarci 0:0061165683ee 371 }
sdivarci 0:0061165683ee 372
sdivarci 0:0061165683ee 373 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
sdivarci 0:0061165683ee 374 uint32_t idx, n;
sdivarci 0:0061165683ee 375 uint8_t * ep_buf;
sdivarci 0:0061165683ee 376
sdivarci 0:0061165683ee 377 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
sdivarci 0:0061165683ee 378 return EP_INVALID;
sdivarci 0:0061165683ee 379 }
sdivarci 0:0061165683ee 380
sdivarci 0:0061165683ee 381 // if write on a OUT endpoint -> error
sdivarci 0:0061165683ee 382 if (OUT_EP(endpoint)) {
sdivarci 0:0061165683ee 383 return EP_INVALID;
sdivarci 0:0061165683ee 384 }
sdivarci 0:0061165683ee 385
sdivarci 0:0061165683ee 386 idx = EP_BDT_IDX(PHY_TO_LOG(endpoint), TX, 0);
sdivarci 0:0061165683ee 387 bdt[idx].byte_count = size;
sdivarci 0:0061165683ee 388
sdivarci 0:0061165683ee 389
sdivarci 0:0061165683ee 390 // non iso endpoint
sdivarci 0:0061165683ee 391 if (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPHSHK_MASK) {
sdivarci 0:0061165683ee 392 ep_buf = endpoint_buffer[idx];
sdivarci 0:0061165683ee 393 } else {
sdivarci 0:0061165683ee 394 ep_buf = endpoint_buffer_iso[2];
sdivarci 0:0061165683ee 395 }
sdivarci 0:0061165683ee 396
sdivarci 0:0061165683ee 397 for (n = 0; n < size; n++) {
sdivarci 0:0061165683ee 398 ep_buf[n] = data[n];
sdivarci 0:0061165683ee 399 }
sdivarci 0:0061165683ee 400
sdivarci 0:0061165683ee 401 if ((Data1 >> endpoint) & 1) {
sdivarci 0:0061165683ee 402 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK;
sdivarci 0:0061165683ee 403 } else {
sdivarci 0:0061165683ee 404 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
sdivarci 0:0061165683ee 405 }
sdivarci 0:0061165683ee 406
sdivarci 0:0061165683ee 407 Data1 ^= (1 << endpoint);
sdivarci 0:0061165683ee 408
sdivarci 0:0061165683ee 409 return EP_PENDING;
sdivarci 0:0061165683ee 410 }
sdivarci 0:0061165683ee 411
sdivarci 0:0061165683ee 412 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
sdivarci 0:0061165683ee 413 if (epComplete & EP(endpoint)) {
sdivarci 0:0061165683ee 414 epComplete &= ~EP(endpoint);
sdivarci 0:0061165683ee 415 return EP_COMPLETED;
sdivarci 0:0061165683ee 416 }
sdivarci 0:0061165683ee 417
sdivarci 0:0061165683ee 418 return EP_PENDING;
sdivarci 0:0061165683ee 419 }
sdivarci 0:0061165683ee 420
sdivarci 0:0061165683ee 421 void USBHAL::stallEndpoint(uint8_t endpoint) {
sdivarci 0:0061165683ee 422 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT |= USB_ENDPT_EPSTALL_MASK;
sdivarci 0:0061165683ee 423 }
sdivarci 0:0061165683ee 424
sdivarci 0:0061165683ee 425 void USBHAL::unstallEndpoint(uint8_t endpoint) {
sdivarci 0:0061165683ee 426 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
sdivarci 0:0061165683ee 427 }
sdivarci 0:0061165683ee 428
sdivarci 0:0061165683ee 429 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
sdivarci 0:0061165683ee 430 uint8_t stall = (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPSTALL_MASK);
sdivarci 0:0061165683ee 431 return (stall) ? true : false;
sdivarci 0:0061165683ee 432 }
sdivarci 0:0061165683ee 433
sdivarci 0:0061165683ee 434 void USBHAL::remoteWakeup(void) {
sdivarci 0:0061165683ee 435 // [TODO]
sdivarci 0:0061165683ee 436 }
sdivarci 0:0061165683ee 437
sdivarci 0:0061165683ee 438
sdivarci 0:0061165683ee 439 void USBHAL::_usbisr(void) {
sdivarci 0:0061165683ee 440 instance->usbisr();
sdivarci 0:0061165683ee 441 }
sdivarci 0:0061165683ee 442
sdivarci 0:0061165683ee 443
sdivarci 0:0061165683ee 444 void USBHAL::usbisr(void) {
sdivarci 0:0061165683ee 445 uint8_t i;
sdivarci 0:0061165683ee 446 uint8_t istat = USB0->ISTAT;
sdivarci 0:0061165683ee 447
sdivarci 0:0061165683ee 448 // reset interrupt
sdivarci 0:0061165683ee 449 if (istat & USB_ISTAT_USBRST_MASK) {
sdivarci 0:0061165683ee 450 // disable all endpt
sdivarci 0:0061165683ee 451 for(i = 0; i < 16; i++) {
sdivarci 0:0061165683ee 452 USB0->ENDPOINT[i].ENDPT = 0x00;
sdivarci 0:0061165683ee 453 }
sdivarci 0:0061165683ee 454
sdivarci 0:0061165683ee 455 // enable control endpoint
sdivarci 0:0061165683ee 456 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
sdivarci 0:0061165683ee 457 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
sdivarci 0:0061165683ee 458
sdivarci 0:0061165683ee 459 Data1 = 0x55555555;
sdivarci 0:0061165683ee 460 USB0->CTL |= USB_CTL_ODDRST_MASK;
sdivarci 0:0061165683ee 461
sdivarci 0:0061165683ee 462 USB0->ISTAT = 0xFF; // clear all interrupt status flags
sdivarci 0:0061165683ee 463 USB0->ERRSTAT = 0xFF; // clear all error flags
sdivarci 0:0061165683ee 464 USB0->ERREN = 0xFF; // enable error interrupt sources
sdivarci 0:0061165683ee 465 USB0->ADDR = 0x00; // set default address
sdivarci 0:0061165683ee 466
sdivarci 0:0061165683ee 467 return;
sdivarci 0:0061165683ee 468 }
sdivarci 0:0061165683ee 469
sdivarci 0:0061165683ee 470 // resume interrupt
sdivarci 0:0061165683ee 471 if (istat & USB_ISTAT_RESUME_MASK) {
sdivarci 0:0061165683ee 472 USB0->ISTAT = USB_ISTAT_RESUME_MASK;
sdivarci 0:0061165683ee 473 }
sdivarci 0:0061165683ee 474
sdivarci 0:0061165683ee 475 // SOF interrupt
sdivarci 0:0061165683ee 476 if (istat & USB_ISTAT_SOFTOK_MASK) {
sdivarci 0:0061165683ee 477 USB0->ISTAT = USB_ISTAT_SOFTOK_MASK;
sdivarci 0:0061165683ee 478 // SOF event, read frame number
sdivarci 0:0061165683ee 479 SOF(frameNumber());
sdivarci 0:0061165683ee 480 }
sdivarci 0:0061165683ee 481
sdivarci 0:0061165683ee 482 // stall interrupt
sdivarci 0:0061165683ee 483 if (istat & 1<<7) {
sdivarci 0:0061165683ee 484 if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK)
sdivarci 0:0061165683ee 485 USB0->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
sdivarci 0:0061165683ee 486 USB0->ISTAT |= USB_ISTAT_STALL_MASK;
sdivarci 0:0061165683ee 487 }
sdivarci 0:0061165683ee 488
sdivarci 0:0061165683ee 489 // token interrupt
sdivarci 0:0061165683ee 490 if (istat & 1<<3) {
sdivarci 0:0061165683ee 491 uint32_t num = (USB0->STAT >> 4) & 0x0F;
sdivarci 0:0061165683ee 492 uint32_t dir = (USB0->STAT >> 3) & 0x01;
sdivarci 0:0061165683ee 493 uint32_t ev_odd = (USB0->STAT >> 2) & 0x01;
sdivarci 0:0061165683ee 494 int endpoint = (num << 1) | dir;
sdivarci 0:0061165683ee 495
sdivarci 0:0061165683ee 496 // setup packet
sdivarci 0:0061165683ee 497 if ((num == 0) && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == SETUP_TOKEN)) {
sdivarci 0:0061165683ee 498 Data1 &= ~0x02;
sdivarci 0:0061165683ee 499 bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK;
sdivarci 0:0061165683ee 500 bdt[EP_BDT_IDX(0, TX, ODD)].info &= ~BD_OWN_MASK;
sdivarci 0:0061165683ee 501
sdivarci 0:0061165683ee 502 // EP0 SETUP event (SETUP data received)
sdivarci 0:0061165683ee 503 EP0setupCallback();
sdivarci 0:0061165683ee 504
sdivarci 0:0061165683ee 505 } else {
sdivarci 0:0061165683ee 506 // OUT packet
sdivarci 0:0061165683ee 507 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == OUT_TOKEN) {
sdivarci 0:0061165683ee 508 if (num == 0)
sdivarci 0:0061165683ee 509 EP0out();
sdivarci 0:0061165683ee 510 else {
sdivarci 0:0061165683ee 511 epComplete |= EP(endpoint);
sdivarci 0:0061165683ee 512 if ((instance->*(epCallback[endpoint - 2]))()) {
sdivarci 0:0061165683ee 513 epComplete &= ~EP(endpoint);
sdivarci 0:0061165683ee 514 }
sdivarci 0:0061165683ee 515 }
sdivarci 0:0061165683ee 516 }
sdivarci 0:0061165683ee 517
sdivarci 0:0061165683ee 518 // IN packet
sdivarci 0:0061165683ee 519 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == IN_TOKEN) {
sdivarci 0:0061165683ee 520 if (num == 0) {
sdivarci 0:0061165683ee 521 EP0in();
sdivarci 0:0061165683ee 522 if (set_addr == 1) {
sdivarci 0:0061165683ee 523 USB0->ADDR = addr & 0x7F;
sdivarci 0:0061165683ee 524 set_addr = 0;
sdivarci 0:0061165683ee 525 }
sdivarci 0:0061165683ee 526 }
sdivarci 0:0061165683ee 527 else {
sdivarci 0:0061165683ee 528 epComplete |= EP(endpoint);
sdivarci 0:0061165683ee 529 if ((instance->*(epCallback[endpoint - 2]))()) {
sdivarci 0:0061165683ee 530 epComplete &= ~EP(endpoint);
sdivarci 0:0061165683ee 531 }
sdivarci 0:0061165683ee 532 }
sdivarci 0:0061165683ee 533 }
sdivarci 0:0061165683ee 534 }
sdivarci 0:0061165683ee 535
sdivarci 0:0061165683ee 536 USB0->ISTAT = USB_ISTAT_TOKDNE_MASK;
sdivarci 0:0061165683ee 537 }
sdivarci 0:0061165683ee 538
sdivarci 0:0061165683ee 539 // sleep interrupt
sdivarci 0:0061165683ee 540 if (istat & 1<<4) {
sdivarci 0:0061165683ee 541 USB0->ISTAT |= USB_ISTAT_SLEEP_MASK;
sdivarci 0:0061165683ee 542 }
sdivarci 0:0061165683ee 543
sdivarci 0:0061165683ee 544 // error interrupt
sdivarci 0:0061165683ee 545 if (istat & USB_ISTAT_ERROR_MASK) {
sdivarci 0:0061165683ee 546 USB0->ERRSTAT = 0xFF;
sdivarci 0:0061165683ee 547 USB0->ISTAT |= USB_ISTAT_ERROR_MASK;
sdivarci 0:0061165683ee 548 }
sdivarci 0:0061165683ee 549 }
sdivarci 0:0061165683ee 550
sdivarci 0:0061165683ee 551
sdivarci 0:0061165683ee 552 #endif