Sinan Divarci / Mbed OS max4146x_comp

max4146x_comp

Dependencies:   MAX14690

USBDevice/USBDevice/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c@0:0061165683ee, 2020-10-25 (annotated)

Committer:
sdivarci
Date:
Sun Oct 25 20:10:02 2020 +0000
Revision:
0:0061165683ee
sdivarci

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sdivarci 0:0061165683ee 1 /*******************************************************************************
sdivarci 0:0061165683ee 2 * DISCLAIMER
sdivarci 0:0061165683ee 3 * This software is supplied by Renesas Electronics Corporation and is only
sdivarci 0:0061165683ee 4 * intended for use with Renesas products. No other uses are authorized. This
sdivarci 0:0061165683ee 5 * software is owned by Renesas Electronics Corporation and is protected under
sdivarci 0:0061165683ee 6 * all applicable laws, including copyright laws.
sdivarci 0:0061165683ee 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
sdivarci 0:0061165683ee 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
sdivarci 0:0061165683ee 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
sdivarci 0:0061165683ee 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
sdivarci 0:0061165683ee 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
sdivarci 0:0061165683ee 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
sdivarci 0:0061165683ee 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
sdivarci 0:0061165683ee 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
sdivarci 0:0061165683ee 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
sdivarci 0:0061165683ee 16 * Renesas reserves the right, without notice, to make changes to this software
sdivarci 0:0061165683ee 17 * and to discontinue the availability of this software. By using this software,
sdivarci 0:0061165683ee 18 * you agree to the additional terms and conditions found by accessing the
sdivarci 0:0061165683ee 19 * following link:
sdivarci 0:0061165683ee 20 * http://www.renesas.com/disclaimer
sdivarci 0:0061165683ee 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
sdivarci 0:0061165683ee 22 *******************************************************************************/
sdivarci 0:0061165683ee 23 /*******************************************************************************
sdivarci 0:0061165683ee 24 * File Name : usb0_function_dmacdrv.c
sdivarci 0:0061165683ee 25 * $Rev: 1116 $
sdivarci 0:0061165683ee 26 * $Date:: 2014-07-09 16:29:19 +0900#$
sdivarci 0:0061165683ee 27 * Device(s) : RZ/A1H
sdivarci 0:0061165683ee 28 * Tool-Chain :
sdivarci 0:0061165683ee 29 * OS : None
sdivarci 0:0061165683ee 30 * H/W Platform :
sdivarci 0:0061165683ee 31 * Description : RZ/A1H R7S72100 USB Sample Program
sdivarci 0:0061165683ee 32 * Operation :
sdivarci 0:0061165683ee 33 * Limitations :
sdivarci 0:0061165683ee 34 *******************************************************************************/
sdivarci 0:0061165683ee 35
sdivarci 0:0061165683ee 36
sdivarci 0:0061165683ee 37 /*******************************************************************************
sdivarci 0:0061165683ee 38 Includes <System Includes> , "Project Includes"
sdivarci 0:0061165683ee 39 *******************************************************************************/
sdivarci 0:0061165683ee 40 #include <stdio.h>
sdivarci 0:0061165683ee 41 #include "r_typedefs.h"
sdivarci 0:0061165683ee 42 #include "iodefine.h"
sdivarci 0:0061165683ee 43 #include "rza_io_regrw.h"
sdivarci 0:0061165683ee 44 #include "usb0_function_dmacdrv.h"
sdivarci 0:0061165683ee 45
sdivarci 0:0061165683ee 46
sdivarci 0:0061165683ee 47 /*******************************************************************************
sdivarci 0:0061165683ee 48 Typedef definitions
sdivarci 0:0061165683ee 49 *******************************************************************************/
sdivarci 0:0061165683ee 50
sdivarci 0:0061165683ee 51
sdivarci 0:0061165683ee 52 /*******************************************************************************
sdivarci 0:0061165683ee 53 Macro definitions
sdivarci 0:0061165683ee 54 *******************************************************************************/
sdivarci 0:0061165683ee 55 #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
sdivarci 0:0061165683ee 56
sdivarci 0:0061165683ee 57 /* ==== Request setting information for on-chip peripheral module ==== */
sdivarci 0:0061165683ee 58 typedef enum dmac_peri_req_reg_type
sdivarci 0:0061165683ee 59 {
sdivarci 0:0061165683ee 60 DMAC_REQ_MID,
sdivarci 0:0061165683ee 61 DMAC_REQ_RID,
sdivarci 0:0061165683ee 62 DMAC_REQ_AM,
sdivarci 0:0061165683ee 63 DMAC_REQ_LVL,
sdivarci 0:0061165683ee 64 DMAC_REQ_REQD
sdivarci 0:0061165683ee 65 } dmac_peri_req_reg_type_t;
sdivarci 0:0061165683ee 66
sdivarci 0:0061165683ee 67
sdivarci 0:0061165683ee 68 /*******************************************************************************
sdivarci 0:0061165683ee 69 Imported global variables and functions (from other files)
sdivarci 0:0061165683ee 70 *******************************************************************************/
sdivarci 0:0061165683ee 71
sdivarci 0:0061165683ee 72
sdivarci 0:0061165683ee 73 /*******************************************************************************
sdivarci 0:0061165683ee 74 Exported global variables and functions (to be accessed by other files)
sdivarci 0:0061165683ee 75 *******************************************************************************/
sdivarci 0:0061165683ee 76
sdivarci 0:0061165683ee 77
sdivarci 0:0061165683ee 78 /*******************************************************************************
sdivarci 0:0061165683ee 79 Private global variables and functions
sdivarci 0:0061165683ee 80 *******************************************************************************/
sdivarci 0:0061165683ee 81 /* ==== Prototype declaration ==== */
sdivarci 0:0061165683ee 82
sdivarci 0:0061165683ee 83 /* ==== Global variable ==== */
sdivarci 0:0061165683ee 84 /* On-chip peripheral module request setting table */
sdivarci 0:0061165683ee 85 static const uint8_t usb0_function_dmac_peri_req_init_table[8][5] =
sdivarci 0:0061165683ee 86 {
sdivarci 0:0061165683ee 87 /* MID,RID,AM,LVL,REQD */
sdivarci 0:0061165683ee 88 {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
sdivarci 0:0061165683ee 89 {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
sdivarci 0:0061165683ee 90 {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
sdivarci 0:0061165683ee 91 {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
sdivarci 0:0061165683ee 92 {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
sdivarci 0:0061165683ee 93 {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
sdivarci 0:0061165683ee 94 {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
sdivarci 0:0061165683ee 95 {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
sdivarci 0:0061165683ee 96 };
sdivarci 0:0061165683ee 97
sdivarci 0:0061165683ee 98
sdivarci 0:0061165683ee 99 /*******************************************************************************
sdivarci 0:0061165683ee 100 * Function Name: usb0_function_DMAC1_PeriReqInit
sdivarci 0:0061165683ee 101 * Description : Sets the register mode for DMA mode and the on-chip peripheral
sdivarci 0:0061165683ee 102 * : module request for transfer request for DMAC channel 1.
sdivarci 0:0061165683ee 103 * : Executes DMAC initial setting using the DMA information
sdivarci 0:0061165683ee 104 * : specified by the argument *trans_info and the enabled/disabled
sdivarci 0:0061165683ee 105 * : continuous transfer specified by the argument continuation.
sdivarci 0:0061165683ee 106 * : Registers DMAC channel 1 interrupt handler function and sets
sdivarci 0:0061165683ee 107 * : the interrupt priority level. Then enables transfer completion
sdivarci 0:0061165683ee 108 * : interrupt.
sdivarci 0:0061165683ee 109 * Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register
sdivarci 0:0061165683ee 110 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
sdivarci 0:0061165683ee 111 * : uint32_t continuation : Set continuous transfer to be valid
sdivarci 0:0061165683ee 112 * : after DMA transfer has been completed
sdivarci 0:0061165683ee 113 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
sdivarci 0:0061165683ee 114 * : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer
sdivarci 0:0061165683ee 115 * : uint32_t request_factor : Factor for on-chip peripheral module request
sdivarci 0:0061165683ee 116 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
sdivarci 0:0061165683ee 117 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
sdivarci 0:0061165683ee 118 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
sdivarci 0:0061165683ee 119 * : :
sdivarci 0:0061165683ee 120 * : uint32_t req_direction: Setting value of CHCFG_n register REQD bit
sdivarci 0:0061165683ee 121 * Return Value : none
sdivarci 0:0061165683ee 122 *******************************************************************************/
sdivarci 0:0061165683ee 123 void usb0_function_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info,
sdivarci 0:0061165683ee 124 uint32_t dmamode, uint32_t continuation,
sdivarci 0:0061165683ee 125 uint32_t request_factor, uint32_t req_direction)
sdivarci 0:0061165683ee 126 {
sdivarci 0:0061165683ee 127 /* ==== Register mode ==== */
sdivarci 0:0061165683ee 128 if (DMAC_MODE_REGISTER == dmamode)
sdivarci 0:0061165683ee 129 {
sdivarci 0:0061165683ee 130 /* ==== Next0 register set ==== */
sdivarci 0:0061165683ee 131 DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
sdivarci 0:0061165683ee 132 DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
sdivarci 0:0061165683ee 133 DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
sdivarci 0:0061165683ee 134
sdivarci 0:0061165683ee 135 /* DAD : Transfer destination address counting direction */
sdivarci 0:0061165683ee 136 /* SAD : Transfer source address counting direction */
sdivarci 0:0061165683ee 137 /* DDS : Transfer destination transfer size */
sdivarci 0:0061165683ee 138 /* SDS : Transfer source transfer size */
sdivarci 0:0061165683ee 139 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 140 trans_info->daddr_dir,
sdivarci 0:0061165683ee 141 DMAC1_CHCFG_n_DAD_SHIFT,
sdivarci 0:0061165683ee 142 DMAC1_CHCFG_n_DAD);
sdivarci 0:0061165683ee 143 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 144 trans_info->saddr_dir,
sdivarci 0:0061165683ee 145 DMAC1_CHCFG_n_SAD_SHIFT,
sdivarci 0:0061165683ee 146 DMAC1_CHCFG_n_SAD);
sdivarci 0:0061165683ee 147 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 148 trans_info->dst_size,
sdivarci 0:0061165683ee 149 DMAC1_CHCFG_n_DDS_SHIFT,
sdivarci 0:0061165683ee 150 DMAC1_CHCFG_n_DDS);
sdivarci 0:0061165683ee 151 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 152 trans_info->src_size,
sdivarci 0:0061165683ee 153 DMAC1_CHCFG_n_SDS_SHIFT,
sdivarci 0:0061165683ee 154 DMAC1_CHCFG_n_SDS);
sdivarci 0:0061165683ee 155
sdivarci 0:0061165683ee 156 /* DMS : Register mode */
sdivarci 0:0061165683ee 157 /* RSEL : Select Next0 register set */
sdivarci 0:0061165683ee 158 /* SBE : No discharge of buffer data when aborted */
sdivarci 0:0061165683ee 159 /* DEM : No DMA interrupt mask */
sdivarci 0:0061165683ee 160 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 161 0,
sdivarci 0:0061165683ee 162 DMAC1_CHCFG_n_DMS_SHIFT,
sdivarci 0:0061165683ee 163 DMAC1_CHCFG_n_DMS);
sdivarci 0:0061165683ee 164 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 165 0,
sdivarci 0:0061165683ee 166 DMAC1_CHCFG_n_RSEL_SHIFT,
sdivarci 0:0061165683ee 167 DMAC1_CHCFG_n_RSEL);
sdivarci 0:0061165683ee 168 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 169 0,
sdivarci 0:0061165683ee 170 DMAC1_CHCFG_n_SBE_SHIFT,
sdivarci 0:0061165683ee 171 DMAC1_CHCFG_n_SBE);
sdivarci 0:0061165683ee 172 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 173 0,
sdivarci 0:0061165683ee 174 DMAC1_CHCFG_n_DEM_SHIFT,
sdivarci 0:0061165683ee 175 DMAC1_CHCFG_n_DEM);
sdivarci 0:0061165683ee 176
sdivarci 0:0061165683ee 177 /* ---- Continuous transfer ---- */
sdivarci 0:0061165683ee 178 if (DMAC_SAMPLE_CONTINUATION == continuation)
sdivarci 0:0061165683ee 179 {
sdivarci 0:0061165683ee 180 /* REN : Execute continuous transfer */
sdivarci 0:0061165683ee 181 /* RSW : Change register set when DMA transfer is completed. */
sdivarci 0:0061165683ee 182 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 183 1,
sdivarci 0:0061165683ee 184 DMAC1_CHCFG_n_REN_SHIFT,
sdivarci 0:0061165683ee 185 DMAC1_CHCFG_n_REN);
sdivarci 0:0061165683ee 186 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 187 1,
sdivarci 0:0061165683ee 188 DMAC1_CHCFG_n_RSW_SHIFT,
sdivarci 0:0061165683ee 189 DMAC1_CHCFG_n_RSW);
sdivarci 0:0061165683ee 190 }
sdivarci 0:0061165683ee 191 /* ---- Single transfer ---- */
sdivarci 0:0061165683ee 192 else
sdivarci 0:0061165683ee 193 {
sdivarci 0:0061165683ee 194 /* REN : Do not execute continuous transfer */
sdivarci 0:0061165683ee 195 /* RSW : Do not change register set when DMA transfer is completed. */
sdivarci 0:0061165683ee 196 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 197 0,
sdivarci 0:0061165683ee 198 DMAC1_CHCFG_n_REN_SHIFT,
sdivarci 0:0061165683ee 199 DMAC1_CHCFG_n_REN);
sdivarci 0:0061165683ee 200 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 201 0,
sdivarci 0:0061165683ee 202 DMAC1_CHCFG_n_RSW_SHIFT,
sdivarci 0:0061165683ee 203 DMAC1_CHCFG_n_RSW);
sdivarci 0:0061165683ee 204 }
sdivarci 0:0061165683ee 205
sdivarci 0:0061165683ee 206 /* TM : Single transfer */
sdivarci 0:0061165683ee 207 /* SEL : Channel setting */
sdivarci 0:0061165683ee 208 /* HIEN, LOEN : On-chip peripheral module request */
sdivarci 0:0061165683ee 209 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 210 0,
sdivarci 0:0061165683ee 211 DMAC1_CHCFG_n_TM_SHIFT,
sdivarci 0:0061165683ee 212 DMAC1_CHCFG_n_TM);
sdivarci 0:0061165683ee 213 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 214 1,
sdivarci 0:0061165683ee 215 DMAC1_CHCFG_n_SEL_SHIFT,
sdivarci 0:0061165683ee 216 DMAC1_CHCFG_n_SEL);
sdivarci 0:0061165683ee 217 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 218 1,
sdivarci 0:0061165683ee 219 DMAC1_CHCFG_n_HIEN_SHIFT,
sdivarci 0:0061165683ee 220 DMAC1_CHCFG_n_HIEN);
sdivarci 0:0061165683ee 221 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 222 0,
sdivarci 0:0061165683ee 223 DMAC1_CHCFG_n_LOEN_SHIFT,
sdivarci 0:0061165683ee 224 DMAC1_CHCFG_n_LOEN);
sdivarci 0:0061165683ee 225
sdivarci 0:0061165683ee 226 /* ---- Set factor by specified on-chip peripheral module request ---- */
sdivarci 0:0061165683ee 227 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 228 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
sdivarci 0:0061165683ee 229 DMAC1_CHCFG_n_AM_SHIFT,
sdivarci 0:0061165683ee 230 DMAC1_CHCFG_n_AM);
sdivarci 0:0061165683ee 231 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 232 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
sdivarci 0:0061165683ee 233 DMAC1_CHCFG_n_LVL_SHIFT,
sdivarci 0:0061165683ee 234 DMAC1_CHCFG_n_LVL);
sdivarci 0:0061165683ee 235
sdivarci 0:0061165683ee 236 if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
sdivarci 0:0061165683ee 237 {
sdivarci 0:0061165683ee 238 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 239 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
sdivarci 0:0061165683ee 240 DMAC1_CHCFG_n_REQD_SHIFT,
sdivarci 0:0061165683ee 241 DMAC1_CHCFG_n_REQD);
sdivarci 0:0061165683ee 242 }
sdivarci 0:0061165683ee 243 else
sdivarci 0:0061165683ee 244 {
sdivarci 0:0061165683ee 245 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
sdivarci 0:0061165683ee 246 req_direction,
sdivarci 0:0061165683ee 247 DMAC1_CHCFG_n_REQD_SHIFT,
sdivarci 0:0061165683ee 248 DMAC1_CHCFG_n_REQD);
sdivarci 0:0061165683ee 249 }
sdivarci 0:0061165683ee 250
sdivarci 0:0061165683ee 251 RZA_IO_RegWrite_32(&DMAC01.DMARS,
sdivarci 0:0061165683ee 252 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
sdivarci 0:0061165683ee 253 DMAC01_DMARS_CH1_RID_SHIFT,
sdivarci 0:0061165683ee 254 DMAC01_DMARS_CH1_RID);
sdivarci 0:0061165683ee 255 RZA_IO_RegWrite_32(&DMAC01.DMARS,
sdivarci 0:0061165683ee 256 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
sdivarci 0:0061165683ee 257 DMAC01_DMARS_CH1_MID_SHIFT,
sdivarci 0:0061165683ee 258 DMAC01_DMARS_CH1_MID);
sdivarci 0:0061165683ee 259
sdivarci 0:0061165683ee 260 /* PR : Round robin mode */
sdivarci 0:0061165683ee 261 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
sdivarci 0:0061165683ee 262 1,
sdivarci 0:0061165683ee 263 DMAC07_DCTRL_0_7_PR_SHIFT,
sdivarci 0:0061165683ee 264 DMAC07_DCTRL_0_7_PR);
sdivarci 0:0061165683ee 265 }
sdivarci 0:0061165683ee 266 }
sdivarci 0:0061165683ee 267
sdivarci 0:0061165683ee 268 /*******************************************************************************
sdivarci 0:0061165683ee 269 * Function Name: usb0_function_DMAC1_Open
sdivarci 0:0061165683ee 270 * Description : Enables DMAC channel 1 transfer.
sdivarci 0:0061165683ee 271 * Arguments : uint32_t req : DMAC request mode
sdivarci 0:0061165683ee 272 * Return Value : 0 : Succeeded in enabling DMA transfer
sdivarci 0:0061165683ee 273 * : -1 : Failed to enable DMA transfer (due to DMA operation)
sdivarci 0:0061165683ee 274 *******************************************************************************/
sdivarci 0:0061165683ee 275 int32_t usb0_function_DMAC1_Open (uint32_t req)
sdivarci 0:0061165683ee 276 {
sdivarci 0:0061165683ee 277 int32_t ret;
sdivarci 0:0061165683ee 278 volatile uint8_t dummy;
sdivarci 0:0061165683ee 279
sdivarci 0:0061165683ee 280 /* Transferable? */
sdivarci 0:0061165683ee 281 if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
sdivarci 0:0061165683ee 282 DMAC1_CHSTAT_n_EN_SHIFT,
sdivarci 0:0061165683ee 283 DMAC1_CHSTAT_n_EN)) &&
sdivarci 0:0061165683ee 284 (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
sdivarci 0:0061165683ee 285 DMAC1_CHSTAT_n_TACT_SHIFT,
sdivarci 0:0061165683ee 286 DMAC1_CHSTAT_n_TACT)))
sdivarci 0:0061165683ee 287 {
sdivarci 0:0061165683ee 288 /* Clear Channel Status Register */
sdivarci 0:0061165683ee 289 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
sdivarci 0:0061165683ee 290 1,
sdivarci 0:0061165683ee 291 DMAC1_CHCTRL_n_SWRST_SHIFT,
sdivarci 0:0061165683ee 292 DMAC1_CHCTRL_n_SWRST);
sdivarci 0:0061165683ee 293 dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
sdivarci 0:0061165683ee 294 DMAC1_CHCTRL_n_SWRST_SHIFT,
sdivarci 0:0061165683ee 295 DMAC1_CHCTRL_n_SWRST);
sdivarci 0:0061165683ee 296 /* Enable DMA transfer */
sdivarci 0:0061165683ee 297 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
sdivarci 0:0061165683ee 298 1,
sdivarci 0:0061165683ee 299 DMAC1_CHCTRL_n_SETEN_SHIFT,
sdivarci 0:0061165683ee 300 DMAC1_CHCTRL_n_SETEN);
sdivarci 0:0061165683ee 301
sdivarci 0:0061165683ee 302 /* ---- Request by software ---- */
sdivarci 0:0061165683ee 303 if (DMAC_REQ_MODE_SOFT == req)
sdivarci 0:0061165683ee 304 {
sdivarci 0:0061165683ee 305 /* DMA transfer Request by software */
sdivarci 0:0061165683ee 306 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
sdivarci 0:0061165683ee 307 1,
sdivarci 0:0061165683ee 308 DMAC1_CHCTRL_n_STG_SHIFT,
sdivarci 0:0061165683ee 309 DMAC1_CHCTRL_n_STG);
sdivarci 0:0061165683ee 310 }
sdivarci 0:0061165683ee 311
sdivarci 0:0061165683ee 312 ret = 0;
sdivarci 0:0061165683ee 313 }
sdivarci 0:0061165683ee 314 else
sdivarci 0:0061165683ee 315 {
sdivarci 0:0061165683ee 316 ret = -1;
sdivarci 0:0061165683ee 317 }
sdivarci 0:0061165683ee 318
sdivarci 0:0061165683ee 319 return ret;
sdivarci 0:0061165683ee 320 }
sdivarci 0:0061165683ee 321
sdivarci 0:0061165683ee 322 /*******************************************************************************
sdivarci 0:0061165683ee 323 * Function Name: usb0_function_DMAC1_Close
sdivarci 0:0061165683ee 324 * Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
sdivarci 0:0061165683ee 325 * : byte count at the time of DMA transfer abort to the argument
sdivarci 0:0061165683ee 326 * : *remain.
sdivarci 0:0061165683ee 327 * Arguments : uint32_t * remain : Remaining transfer byte count when
sdivarci 0:0061165683ee 328 * : : DMA transfer is aborted
sdivarci 0:0061165683ee 329 * Return Value : none
sdivarci 0:0061165683ee 330 *******************************************************************************/
sdivarci 0:0061165683ee 331 void usb0_function_DMAC1_Close (uint32_t * remain)
sdivarci 0:0061165683ee 332 {
sdivarci 0:0061165683ee 333
sdivarci 0:0061165683ee 334 /* ==== Abort transfer ==== */
sdivarci 0:0061165683ee 335 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
sdivarci 0:0061165683ee 336 1,
sdivarci 0:0061165683ee 337 DMAC1_CHCTRL_n_CLREN_SHIFT,
sdivarci 0:0061165683ee 338 DMAC1_CHCTRL_n_CLREN);
sdivarci 0:0061165683ee 339
sdivarci 0:0061165683ee 340 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
sdivarci 0:0061165683ee 341 DMAC1_CHSTAT_n_TACT_SHIFT,
sdivarci 0:0061165683ee 342 DMAC1_CHSTAT_n_TACT))
sdivarci 0:0061165683ee 343 {
sdivarci 0:0061165683ee 344 /* Loop until transfer is aborted */
sdivarci 0:0061165683ee 345 }
sdivarci 0:0061165683ee 346
sdivarci 0:0061165683ee 347 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
sdivarci 0:0061165683ee 348 DMAC1_CHSTAT_n_EN_SHIFT,
sdivarci 0:0061165683ee 349 DMAC1_CHSTAT_n_EN))
sdivarci 0:0061165683ee 350 {
sdivarci 0:0061165683ee 351 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
sdivarci 0:0061165683ee 352 }
sdivarci 0:0061165683ee 353 /* ==== Obtain remaining transfer byte count ==== */
sdivarci 0:0061165683ee 354 *remain = DMAC1.CRTB_n;
sdivarci 0:0061165683ee 355 }
sdivarci 0:0061165683ee 356
sdivarci 0:0061165683ee 357 /*******************************************************************************
sdivarci 0:0061165683ee 358 * Function Name: usb0_function_DMAC1_Load_Set
sdivarci 0:0061165683ee 359 * Description : Sets the transfer source address, transfer destination
sdivarci 0:0061165683ee 360 * : address, and total transfer byte count respectively
sdivarci 0:0061165683ee 361 * : specified by the argument src_addr, dst_addr, and count to
sdivarci 0:0061165683ee 362 * : DMAC channel 1 as DMA transfer information.
sdivarci 0:0061165683ee 363 * : Sets the register set selected by the CHCFG_n register
sdivarci 0:0061165683ee 364 * : RSEL bit from the Next0 or Next1 register set.
sdivarci 0:0061165683ee 365 * : This function should be called when DMA transfer of DMAC
sdivarci 0:0061165683ee 366 * : channel 1 is aboted.
sdivarci 0:0061165683ee 367 * Arguments : uint32_t src_addr : Transfer source address
sdivarci 0:0061165683ee 368 * : uint32_t dst_addr : Transfer destination address
sdivarci 0:0061165683ee 369 * : uint32_t count : Total transfer byte count
sdivarci 0:0061165683ee 370 * Return Value : none
sdivarci 0:0061165683ee 371 *******************************************************************************/
sdivarci 0:0061165683ee 372 void usb0_function_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
sdivarci 0:0061165683ee 373 {
sdivarci 0:0061165683ee 374 uint8_t reg_set;
sdivarci 0:0061165683ee 375
sdivarci 0:0061165683ee 376 /* Obtain register set in use */
sdivarci 0:0061165683ee 377 reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
sdivarci 0:0061165683ee 378 DMAC1_CHSTAT_n_SR_SHIFT,
sdivarci 0:0061165683ee 379 DMAC1_CHSTAT_n_SR);
sdivarci 0:0061165683ee 380
sdivarci 0:0061165683ee 381 /* ==== Load ==== */
sdivarci 0:0061165683ee 382 if (0 == reg_set)
sdivarci 0:0061165683ee 383 {
sdivarci 0:0061165683ee 384 /* ---- Next0 Register Set ---- */
sdivarci 0:0061165683ee 385 DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
sdivarci 0:0061165683ee 386 DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
sdivarci 0:0061165683ee 387 DMAC1.N0TB_n = count; /* Total transfer byte count */
sdivarci 0:0061165683ee 388 }
sdivarci 0:0061165683ee 389 else
sdivarci 0:0061165683ee 390 {
sdivarci 0:0061165683ee 391 /* ---- Next1 Register Set ---- */
sdivarci 0:0061165683ee 392 DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
sdivarci 0:0061165683ee 393 DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
sdivarci 0:0061165683ee 394 DMAC1.N1TB_n = count; /* Total transfer byte count */
sdivarci 0:0061165683ee 395 }
sdivarci 0:0061165683ee 396 }
sdivarci 0:0061165683ee 397
sdivarci 0:0061165683ee 398 /*******************************************************************************
sdivarci 0:0061165683ee 399 * Function Name: usb0_function_DMAC2_PeriReqInit
sdivarci 0:0061165683ee 400 * Description : Sets the register mode for DMA mode and the on-chip peripheral
sdivarci 0:0061165683ee 401 * : module request for transfer request for DMAC channel 2.
sdivarci 0:0061165683ee 402 * : Executes DMAC initial setting using the DMA information
sdivarci 0:0061165683ee 403 * : specified by the argument *trans_info and the enabled/disabled
sdivarci 0:0061165683ee 404 * : continuous transfer specified by the argument continuation.
sdivarci 0:0061165683ee 405 * : Registers DMAC channel 2 interrupt handler function and sets
sdivarci 0:0061165683ee 406 * : the interrupt priority level. Then enables transfer completion
sdivarci 0:0061165683ee 407 * : interrupt.
sdivarci 0:0061165683ee 408 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
sdivarci 0:0061165683ee 409 * : : register
sdivarci 0:0061165683ee 410 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
sdivarci 0:0061165683ee 411 * : uint32_t continuation : Set continuous transfer to be valid
sdivarci 0:0061165683ee 412 * : : after DMA transfer has been completed
sdivarci 0:0061165683ee 413 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
sdivarci 0:0061165683ee 414 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
sdivarci 0:0061165683ee 415 * : : transfer
sdivarci 0:0061165683ee 416 * : uint32_t request_factor : Factor for on-chip peripheral module
sdivarci 0:0061165683ee 417 * : : request
sdivarci 0:0061165683ee 418 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
sdivarci 0:0061165683ee 419 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
sdivarci 0:0061165683ee 420 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
sdivarci 0:0061165683ee 421 * : :
sdivarci 0:0061165683ee 422 * : uint32_t req_direction : Setting value of CHCFG_n register
sdivarci 0:0061165683ee 423 * : : REQD bit
sdivarci 0:0061165683ee 424 *******************************************************************************/
sdivarci 0:0061165683ee 425 void usb0_function_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info,
sdivarci 0:0061165683ee 426 uint32_t dmamode, uint32_t continuation,
sdivarci 0:0061165683ee 427 uint32_t request_factor, uint32_t req_direction)
sdivarci 0:0061165683ee 428 {
sdivarci 0:0061165683ee 429 /* ==== Register mode ==== */
sdivarci 0:0061165683ee 430 if (DMAC_MODE_REGISTER == dmamode)
sdivarci 0:0061165683ee 431 {
sdivarci 0:0061165683ee 432 /* ==== Next0 register set ==== */
sdivarci 0:0061165683ee 433 DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
sdivarci 0:0061165683ee 434 DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
sdivarci 0:0061165683ee 435 DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
sdivarci 0:0061165683ee 436
sdivarci 0:0061165683ee 437 /* DAD : Transfer destination address counting direction */
sdivarci 0:0061165683ee 438 /* SAD : Transfer source address counting direction */
sdivarci 0:0061165683ee 439 /* DDS : Transfer destination transfer size */
sdivarci 0:0061165683ee 440 /* SDS : Transfer source transfer size */
sdivarci 0:0061165683ee 441 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 442 trans_info->daddr_dir,
sdivarci 0:0061165683ee 443 DMAC2_CHCFG_n_DAD_SHIFT,
sdivarci 0:0061165683ee 444 DMAC2_CHCFG_n_DAD);
sdivarci 0:0061165683ee 445 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 446 trans_info->saddr_dir,
sdivarci 0:0061165683ee 447 DMAC2_CHCFG_n_SAD_SHIFT,
sdivarci 0:0061165683ee 448 DMAC2_CHCFG_n_SAD);
sdivarci 0:0061165683ee 449 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 450 trans_info->dst_size,
sdivarci 0:0061165683ee 451 DMAC2_CHCFG_n_DDS_SHIFT,
sdivarci 0:0061165683ee 452 DMAC2_CHCFG_n_DDS);
sdivarci 0:0061165683ee 453 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 454 trans_info->src_size,
sdivarci 0:0061165683ee 455 DMAC2_CHCFG_n_SDS_SHIFT,
sdivarci 0:0061165683ee 456 DMAC2_CHCFG_n_SDS);
sdivarci 0:0061165683ee 457
sdivarci 0:0061165683ee 458 /* DMS : Register mode */
sdivarci 0:0061165683ee 459 /* RSEL : Select Next0 register set */
sdivarci 0:0061165683ee 460 /* SBE : No discharge of buffer data when aborted */
sdivarci 0:0061165683ee 461 /* DEM : No DMA interrupt mask */
sdivarci 0:0061165683ee 462 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 463 0,
sdivarci 0:0061165683ee 464 DMAC2_CHCFG_n_DMS_SHIFT,
sdivarci 0:0061165683ee 465 DMAC2_CHCFG_n_DMS);
sdivarci 0:0061165683ee 466 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 467 0,
sdivarci 0:0061165683ee 468 DMAC2_CHCFG_n_RSEL_SHIFT,
sdivarci 0:0061165683ee 469 DMAC2_CHCFG_n_RSEL);
sdivarci 0:0061165683ee 470 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 471 0,
sdivarci 0:0061165683ee 472 DMAC2_CHCFG_n_SBE_SHIFT,
sdivarci 0:0061165683ee 473 DMAC2_CHCFG_n_SBE);
sdivarci 0:0061165683ee 474 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 475 0,
sdivarci 0:0061165683ee 476 DMAC2_CHCFG_n_DEM_SHIFT,
sdivarci 0:0061165683ee 477 DMAC2_CHCFG_n_DEM);
sdivarci 0:0061165683ee 478
sdivarci 0:0061165683ee 479 /* ---- Continuous transfer ---- */
sdivarci 0:0061165683ee 480 if (DMAC_SAMPLE_CONTINUATION == continuation)
sdivarci 0:0061165683ee 481 {
sdivarci 0:0061165683ee 482 /* REN : Execute continuous transfer */
sdivarci 0:0061165683ee 483 /* RSW : Change register set when DMA transfer is completed. */
sdivarci 0:0061165683ee 484 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 485 1,
sdivarci 0:0061165683ee 486 DMAC2_CHCFG_n_REN_SHIFT,
sdivarci 0:0061165683ee 487 DMAC2_CHCFG_n_REN);
sdivarci 0:0061165683ee 488 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 489 1,
sdivarci 0:0061165683ee 490 DMAC2_CHCFG_n_RSW_SHIFT,
sdivarci 0:0061165683ee 491 DMAC2_CHCFG_n_RSW);
sdivarci 0:0061165683ee 492 }
sdivarci 0:0061165683ee 493 /* ---- Single transfer ---- */
sdivarci 0:0061165683ee 494 else
sdivarci 0:0061165683ee 495 {
sdivarci 0:0061165683ee 496 /* REN : Do not execute continuous transfer */
sdivarci 0:0061165683ee 497 /* RSW : Do not change register set when DMA transfer is completed. */
sdivarci 0:0061165683ee 498 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 499 0,
sdivarci 0:0061165683ee 500 DMAC2_CHCFG_n_REN_SHIFT,
sdivarci 0:0061165683ee 501 DMAC2_CHCFG_n_REN);
sdivarci 0:0061165683ee 502 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 503 0,
sdivarci 0:0061165683ee 504 DMAC2_CHCFG_n_RSW_SHIFT,
sdivarci 0:0061165683ee 505 DMAC2_CHCFG_n_RSW);
sdivarci 0:0061165683ee 506 }
sdivarci 0:0061165683ee 507
sdivarci 0:0061165683ee 508 /* TM : Single transfer */
sdivarci 0:0061165683ee 509 /* SEL : Channel setting */
sdivarci 0:0061165683ee 510 /* HIEN, LOEN : On-chip peripheral module request */
sdivarci 0:0061165683ee 511 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 512 0,
sdivarci 0:0061165683ee 513 DMAC2_CHCFG_n_TM_SHIFT,
sdivarci 0:0061165683ee 514 DMAC2_CHCFG_n_TM);
sdivarci 0:0061165683ee 515 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 516 2,
sdivarci 0:0061165683ee 517 DMAC2_CHCFG_n_SEL_SHIFT,
sdivarci 0:0061165683ee 518 DMAC2_CHCFG_n_SEL);
sdivarci 0:0061165683ee 519 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 520 1,
sdivarci 0:0061165683ee 521 DMAC2_CHCFG_n_HIEN_SHIFT,
sdivarci 0:0061165683ee 522 DMAC2_CHCFG_n_HIEN);
sdivarci 0:0061165683ee 523 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 524 0,
sdivarci 0:0061165683ee 525 DMAC2_CHCFG_n_LOEN_SHIFT,
sdivarci 0:0061165683ee 526 DMAC2_CHCFG_n_LOEN);
sdivarci 0:0061165683ee 527
sdivarci 0:0061165683ee 528 /* ---- Set factor by specified on-chip peripheral module request ---- */
sdivarci 0:0061165683ee 529 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 530 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
sdivarci 0:0061165683ee 531 DMAC2_CHCFG_n_AM_SHIFT,
sdivarci 0:0061165683ee 532 DMAC2_CHCFG_n_AM);
sdivarci 0:0061165683ee 533 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 534 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
sdivarci 0:0061165683ee 535 DMAC2_CHCFG_n_LVL_SHIFT,
sdivarci 0:0061165683ee 536 DMAC2_CHCFG_n_LVL);
sdivarci 0:0061165683ee 537 if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
sdivarci 0:0061165683ee 538 {
sdivarci 0:0061165683ee 539 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 540 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
sdivarci 0:0061165683ee 541 DMAC2_CHCFG_n_REQD_SHIFT,
sdivarci 0:0061165683ee 542 DMAC2_CHCFG_n_REQD);
sdivarci 0:0061165683ee 543 }
sdivarci 0:0061165683ee 544 else
sdivarci 0:0061165683ee 545 {
sdivarci 0:0061165683ee 546 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
sdivarci 0:0061165683ee 547 req_direction,
sdivarci 0:0061165683ee 548 DMAC2_CHCFG_n_REQD_SHIFT,
sdivarci 0:0061165683ee 549 DMAC2_CHCFG_n_REQD);
sdivarci 0:0061165683ee 550 }
sdivarci 0:0061165683ee 551 RZA_IO_RegWrite_32(&DMAC23.DMARS,
sdivarci 0:0061165683ee 552 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
sdivarci 0:0061165683ee 553 DMAC23_DMARS_CH2_RID_SHIFT,
sdivarci 0:0061165683ee 554 DMAC23_DMARS_CH2_RID);
sdivarci 0:0061165683ee 555 RZA_IO_RegWrite_32(&DMAC23.DMARS,
sdivarci 0:0061165683ee 556 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
sdivarci 0:0061165683ee 557 DMAC23_DMARS_CH2_MID_SHIFT,
sdivarci 0:0061165683ee 558 DMAC23_DMARS_CH2_MID);
sdivarci 0:0061165683ee 559
sdivarci 0:0061165683ee 560 /* PR : Round robin mode */
sdivarci 0:0061165683ee 561 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
sdivarci 0:0061165683ee 562 1,
sdivarci 0:0061165683ee 563 DMAC07_DCTRL_0_7_PR_SHIFT,
sdivarci 0:0061165683ee 564 DMAC07_DCTRL_0_7_PR);
sdivarci 0:0061165683ee 565 }
sdivarci 0:0061165683ee 566 }
sdivarci 0:0061165683ee 567
sdivarci 0:0061165683ee 568 /*******************************************************************************
sdivarci 0:0061165683ee 569 * Function Name: usb0_function_DMAC2_Open
sdivarci 0:0061165683ee 570 * Description : Enables DMAC channel 2 transfer.
sdivarci 0:0061165683ee 571 * Arguments : uint32_t req : DMAC request mode
sdivarci 0:0061165683ee 572 * Return Value : 0 : Succeeded in enabling DMA transfer
sdivarci 0:0061165683ee 573 * : -1 : Failed to enable DMA transfer (due to DMA operation)
sdivarci 0:0061165683ee 574 *******************************************************************************/
sdivarci 0:0061165683ee 575 int32_t usb0_function_DMAC2_Open (uint32_t req)
sdivarci 0:0061165683ee 576 {
sdivarci 0:0061165683ee 577 int32_t ret;
sdivarci 0:0061165683ee 578 volatile uint8_t dummy;
sdivarci 0:0061165683ee 579
sdivarci 0:0061165683ee 580 /* Transferable? */
sdivarci 0:0061165683ee 581 if ((0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2,
sdivarci 0:0061165683ee 582 DMAC2_CHSTAT_n_EN_SHIFT,
sdivarci 0:0061165683ee 583 DMAC2_CHSTAT_n_EN)) &&
sdivarci 0:0061165683ee 584 (0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2,
sdivarci 0:0061165683ee 585 DMAC2_CHSTAT_n_TACT_SHIFT,
sdivarci 0:0061165683ee 586 DMAC2_CHSTAT_n_TACT)))
sdivarci 0:0061165683ee 587 {
sdivarci 0:0061165683ee 588 /* Clear Channel Status Register */
sdivarci 0:0061165683ee 589 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
sdivarci 0:0061165683ee 590 1,
sdivarci 0:0061165683ee 591 DMAC2_CHCTRL_n_SWRST_SHIFT,
sdivarci 0:0061165683ee 592 DMAC2_CHCTRL_n_SWRST);
sdivarci 0:0061165683ee 593 dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
sdivarci 0:0061165683ee 594 DMAC2_CHCTRL_n_SWRST_SHIFT,
sdivarci 0:0061165683ee 595 DMAC2_CHCTRL_n_SWRST);
sdivarci 0:0061165683ee 596 /* Enable DMA transfer */
sdivarci 0:0061165683ee 597 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
sdivarci 0:0061165683ee 598 1,
sdivarci 0:0061165683ee 599 DMAC2_CHCTRL_n_SETEN_SHIFT,
sdivarci 0:0061165683ee 600 DMAC2_CHCTRL_n_SETEN);
sdivarci 0:0061165683ee 601
sdivarci 0:0061165683ee 602 /* ---- Request by software ---- */
sdivarci 0:0061165683ee 603 if (DMAC_REQ_MODE_SOFT == req)
sdivarci 0:0061165683ee 604 {
sdivarci 0:0061165683ee 605 /* DMA transfer Request by software */
sdivarci 0:0061165683ee 606 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
sdivarci 0:0061165683ee 607 1,
sdivarci 0:0061165683ee 608 DMAC2_CHCTRL_n_STG_SHIFT,
sdivarci 0:0061165683ee 609 DMAC2_CHCTRL_n_STG);
sdivarci 0:0061165683ee 610 }
sdivarci 0:0061165683ee 611
sdivarci 0:0061165683ee 612 ret = 0;
sdivarci 0:0061165683ee 613 }
sdivarci 0:0061165683ee 614 else
sdivarci 0:0061165683ee 615 {
sdivarci 0:0061165683ee 616 ret = -1;
sdivarci 0:0061165683ee 617 }
sdivarci 0:0061165683ee 618
sdivarci 0:0061165683ee 619 return ret;
sdivarci 0:0061165683ee 620 }
sdivarci 0:0061165683ee 621
sdivarci 0:0061165683ee 622 /*******************************************************************************
sdivarci 0:0061165683ee 623 * Function Name: usb0_function_DMAC2_Close
sdivarci 0:0061165683ee 624 * Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
sdivarci 0:0061165683ee 625 * : byte count at the time of DMA transfer abort to the argument
sdivarci 0:0061165683ee 626 * : *remain.
sdivarci 0:0061165683ee 627 * Arguments : uint32_t * remain : Remaining transfer byte count when
sdivarci 0:0061165683ee 628 * : : DMA transfer is aborted
sdivarci 0:0061165683ee 629 * Return Value : none
sdivarci 0:0061165683ee 630 *******************************************************************************/
sdivarci 0:0061165683ee 631 void usb0_function_DMAC2_Close (uint32_t * remain)
sdivarci 0:0061165683ee 632 {
sdivarci 0:0061165683ee 633
sdivarci 0:0061165683ee 634 /* ==== Abort transfer ==== */
sdivarci 0:0061165683ee 635 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
sdivarci 0:0061165683ee 636 1,
sdivarci 0:0061165683ee 637 DMAC2_CHCTRL_n_CLREN_SHIFT,
sdivarci 0:0061165683ee 638 DMAC2_CHCTRL_n_CLREN);
sdivarci 0:0061165683ee 639
sdivarci 0:0061165683ee 640 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
sdivarci 0:0061165683ee 641 DMAC2_CHSTAT_n_TACT_SHIFT,
sdivarci 0:0061165683ee 642 DMAC2_CHSTAT_n_TACT))
sdivarci 0:0061165683ee 643 {
sdivarci 0:0061165683ee 644 /* Loop until transfer is aborted */
sdivarci 0:0061165683ee 645 }
sdivarci 0:0061165683ee 646
sdivarci 0:0061165683ee 647 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
sdivarci 0:0061165683ee 648 DMAC2_CHSTAT_n_EN_SHIFT,
sdivarci 0:0061165683ee 649 DMAC2_CHSTAT_n_EN))
sdivarci 0:0061165683ee 650 {
sdivarci 0:0061165683ee 651 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
sdivarci 0:0061165683ee 652 }
sdivarci 0:0061165683ee 653 /* ==== Obtain remaining transfer byte count ==== */
sdivarci 0:0061165683ee 654 *remain = DMAC2.CRTB_n;
sdivarci 0:0061165683ee 655 }
sdivarci 0:0061165683ee 656
sdivarci 0:0061165683ee 657 /*******************************************************************************
sdivarci 0:0061165683ee 658 * Function Name: usb0_function_DMAC2_Load_Set
sdivarci 0:0061165683ee 659 * Description : Sets the transfer source address, transfer destination
sdivarci 0:0061165683ee 660 * : address, and total transfer byte count respectively
sdivarci 0:0061165683ee 661 * : specified by the argument src_addr, dst_addr, and count to
sdivarci 0:0061165683ee 662 * : DMAC channel 2 as DMA transfer information.
sdivarci 0:0061165683ee 663 * : Sets the register set selected by the CHCFG_n register
sdivarci 0:0061165683ee 664 * : RSEL bit from the Next0 or Next1 register set.
sdivarci 0:0061165683ee 665 * : This function should be called when DMA transfer of DMAC
sdivarci 0:0061165683ee 666 * : channel 2 is aboted.
sdivarci 0:0061165683ee 667 * Arguments : uint32_t src_addr : Transfer source address
sdivarci 0:0061165683ee 668 * : uint32_t dst_addr : Transfer destination address
sdivarci 0:0061165683ee 669 * : uint32_t count : Total transfer byte count
sdivarci 0:0061165683ee 670 * Return Value : none
sdivarci 0:0061165683ee 671 *******************************************************************************/
sdivarci 0:0061165683ee 672 void usb0_function_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
sdivarci 0:0061165683ee 673 {
sdivarci 0:0061165683ee 674 uint8_t reg_set;
sdivarci 0:0061165683ee 675
sdivarci 0:0061165683ee 676 /* Obtain register set in use */
sdivarci 0:0061165683ee 677 reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
sdivarci 0:0061165683ee 678 DMAC2_CHSTAT_n_SR_SHIFT,
sdivarci 0:0061165683ee 679 DMAC2_CHSTAT_n_SR);
sdivarci 0:0061165683ee 680
sdivarci 0:0061165683ee 681 /* ==== Load ==== */
sdivarci 0:0061165683ee 682 if (0 == reg_set)
sdivarci 0:0061165683ee 683 {
sdivarci 0:0061165683ee 684 /* ---- Next0 Register Set ---- */
sdivarci 0:0061165683ee 685 DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
sdivarci 0:0061165683ee 686 DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
sdivarci 0:0061165683ee 687 DMAC2.N0TB_n = count; /* Total transfer byte count */
sdivarci 0:0061165683ee 688 }
sdivarci 0:0061165683ee 689 else
sdivarci 0:0061165683ee 690 {
sdivarci 0:0061165683ee 691 /* ---- Next1 Register Set ---- */
sdivarci 0:0061165683ee 692 DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
sdivarci 0:0061165683ee 693 DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
sdivarci 0:0061165683ee 694 DMAC2.N1TB_n = count; /* Total transfer byte count */
sdivarci 0:0061165683ee 695 }
sdivarci 0:0061165683ee 696 }
sdivarci 0:0061165683ee 697
sdivarci 0:0061165683ee 698 /* End of File */