WAKE UP

Dependencies:   WakeUp mbed

Fork of NucleoStandbyTest by Michael Walker

Committer:
MichaelW
Date:
Sat May 07 12:23:15 2016 +0000
Revision:
1:085a87258f10
Parent:
0:1ecaa40f74d0
Code reduced to minimal working; Verified that ClearWakeUp is required. ; Standby uses lower power than deepsleep

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MichaelW 0:1ecaa40f74d0 1 #include "mbed.h"
MichaelW 0:1ecaa40f74d0 2 #include "WakeUp.h"
MichaelW 0:1ecaa40f74d0 3
MichaelW 0:1ecaa40f74d0 4 DigitalOut myled(LED1);
MichaelW 0:1ecaa40f74d0 5
MichaelW 0:1ecaa40f74d0 6 void ClearWakeUp(void);
MichaelW 0:1ecaa40f74d0 7
MichaelW 0:1ecaa40f74d0 8 int main()
MichaelW 0:1ecaa40f74d0 9 {
MichaelW 0:1ecaa40f74d0 10 myled = 1;
MichaelW 0:1ecaa40f74d0 11 wait(0.2);
MichaelW 0:1ecaa40f74d0 12 myled = 0;
MichaelW 0:1ecaa40f74d0 13 wait(0.2);
MichaelW 1:085a87258f10 14
MichaelW 0:1ecaa40f74d0 15 //The low-power oscillator can be quite inaccurate on some targets
MichaelW 0:1ecaa40f74d0 16 //this function calibrates it against the main clock
MichaelW 0:1ecaa40f74d0 17 WakeUp::calibrate();
MichaelW 0:1ecaa40f74d0 18
MichaelW 0:1ecaa40f74d0 19
MichaelW 1:085a87258f10 20 WakeUp::set_ms(5000);
MichaelW 0:1ecaa40f74d0 21 ClearWakeUp();
MichaelW 0:1ecaa40f74d0 22
MichaelW 1:085a87258f10 23 printf("Entering Standby Mode\r\n");
MichaelW 1:085a87258f10 24
MichaelW 0:1ecaa40f74d0 25 HAL_PWR_EnterSTANDBYMode();
MichaelW 1:085a87258f10 26
MichaelW 0:1ecaa40f74d0 27 //This will never be executed
MichaelW 0:1ecaa40f74d0 28 printf("After sleep\r\n");
MichaelW 1:085a87258f10 29
MichaelW 0:1ecaa40f74d0 30 }
MichaelW 1:085a87258f10 31 void ClearWakeUp(void)
MichaelW 1:085a87258f10 32 {
MichaelW 0:1ecaa40f74d0 33 PWR->CR |= PWR_CR_DBP; //Enable power domain
MichaelW 0:1ecaa40f74d0 34 RTC->WPR = 0xCA; //Disable RTC write protection
MichaelW 0:1ecaa40f74d0 35 RTC->WPR = 0x53;
MichaelW 0:1ecaa40f74d0 36
MichaelW 0:1ecaa40f74d0 37 __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
MichaelW 0:1ecaa40f74d0 38 __HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
MichaelW 0:1ecaa40f74d0 39
MichaelW 0:1ecaa40f74d0 40 RTC->WPR = 0xFF; //Enable RTC write protection
MichaelW 0:1ecaa40f74d0 41 PWR->CR &= ~PWR_CR_DBP; //Disable power domain
MichaelW 0:1ecaa40f74d0 42 }