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targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TMPM066.h@172:7d866c31b3c5, 2017-08-31 (annotated)

Committer:
AnnaBridge
Date:
Thu Aug 31 17:27:04 2017 +0100
Revision:
172:7d866c31b3c5
This updates the lib to the mbed lib v 150

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:7d866c31b3c5 1 /**
AnnaBridge 172:7d866c31b3c5 2 *******************************************************************************
AnnaBridge 172:7d866c31b3c5 3 * @file TMPM066.h
AnnaBridge 172:7d866c31b3c5 4 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for the
AnnaBridge 172:7d866c31b3c5 5 * TOSHIBA 'TMPM066' Device Series
AnnaBridge 172:7d866c31b3c5 6 * @version V2.0.2.2 (Tentative)
AnnaBridge 172:7d866c31b3c5 7 * @date 2016/02/15
AnnaBridge 172:7d866c31b3c5 8 *
AnnaBridge 172:7d866c31b3c5 9 *(C)Copyright TOSHIBA CORPORATION 2016 All rights reserved
AnnaBridge 172:7d866c31b3c5 10 *******************************************************************************
AnnaBridge 172:7d866c31b3c5 11 */
AnnaBridge 172:7d866c31b3c5 12
AnnaBridge 172:7d866c31b3c5 13 /** @addtogroup TOSHIBA_TX00_MICROCONTROLLER
AnnaBridge 172:7d866c31b3c5 14 * @{
AnnaBridge 172:7d866c31b3c5 15 */
AnnaBridge 172:7d866c31b3c5 16
AnnaBridge 172:7d866c31b3c5 17 /** @addtogroup TMPM066
AnnaBridge 172:7d866c31b3c5 18 * @{
AnnaBridge 172:7d866c31b3c5 19 */
AnnaBridge 172:7d866c31b3c5 20
AnnaBridge 172:7d866c31b3c5 21 #ifndef __TMPM066_H__
AnnaBridge 172:7d866c31b3c5 22 #define __TMPM066_H__
AnnaBridge 172:7d866c31b3c5 23
AnnaBridge 172:7d866c31b3c5 24 #ifdef __cplusplus
AnnaBridge 172:7d866c31b3c5 25 extern "C" {
AnnaBridge 172:7d866c31b3c5 26 #endif
AnnaBridge 172:7d866c31b3c5 27
AnnaBridge 172:7d866c31b3c5 28 /** @addtogroup Configuration_of_CMSIS
AnnaBridge 172:7d866c31b3c5 29 * @{
AnnaBridge 172:7d866c31b3c5 30 */
AnnaBridge 172:7d866c31b3c5 31
AnnaBridge 172:7d866c31b3c5 32 /** Interrupt Number Definition */
AnnaBridge 172:7d866c31b3c5 33 typedef enum IRQn {
AnnaBridge 172:7d866c31b3c5 34 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************************/
AnnaBridge 172:7d866c31b3c5 35 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 172:7d866c31b3c5 36 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
AnnaBridge 172:7d866c31b3c5 37 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
AnnaBridge 172:7d866c31b3c5 38 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
AnnaBridge 172:7d866c31b3c5 39 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
AnnaBridge 172:7d866c31b3c5 40
AnnaBridge 172:7d866c31b3c5 41 /****** TMPM066 Specific Interrupt Numbers *******************************************************************/
AnnaBridge 172:7d866c31b3c5 42 INT0_IRQn = 0, /*!< Interrupt Pin0 */
AnnaBridge 172:7d866c31b3c5 43 INT1_IRQn = 1, /*!< Interrupt Pin1 */
AnnaBridge 172:7d866c31b3c5 44 INT2_IRQn = 2, /*!< Interrupt Pin2 */
AnnaBridge 172:7d866c31b3c5 45 INT3_IRQn = 3, /*!< Interrupt Pin3 */
AnnaBridge 172:7d866c31b3c5 46 INT4_IRQn = 4, /*!< Interrupt Pin4 */
AnnaBridge 172:7d866c31b3c5 47 INT5_IRQn = 5, /*!< Interrupt Pin5 */
AnnaBridge 172:7d866c31b3c5 48 INTRX0_IRQn = 6, /*!< Serial reception interrupt(channel0) */
AnnaBridge 172:7d866c31b3c5 49 INTTX0_IRQn = 7, /*!< Serial transmission interrupt(channel0) */
AnnaBridge 172:7d866c31b3c5 50 INTRX1_IRQn = 8, /*!< Serial reception interrupt(channel1) */
AnnaBridge 172:7d866c31b3c5 51 INTTX1_IRQn = 9, /*!< Serial transmission interrupt(channel1) */
AnnaBridge 172:7d866c31b3c5 52 INTSPIRX_IRQn = 10, /*!< SPI serial reception interrupt */
AnnaBridge 172:7d866c31b3c5 53 INTSPITX_IRQn = 11, /*!< SPI serial transmission interrupt */
AnnaBridge 172:7d866c31b3c5 54 INTSPIERR_IRQn = 12, /*!< SPI serial error interrupt */
AnnaBridge 172:7d866c31b3c5 55 INTI2C0_IRQn = 13, /*!< Serial bus interface (channel.0) */
AnnaBridge 172:7d866c31b3c5 56 INTI2C1_IRQn = 14, /*!< Serial bus interface (channel.1) */
AnnaBridge 172:7d866c31b3c5 57 INTDMA_IRQn = 15, /*!< DMAC interrupt */
AnnaBridge 172:7d866c31b3c5 58 INT16A0_IRQn = 16, /*!< 16-bit TMR16A match detection (channel.0) */
AnnaBridge 172:7d866c31b3c5 59 INT16A1_IRQn = 17, /*!< 16-bit TMR16A match detection (channel.1) */
AnnaBridge 172:7d866c31b3c5 60 INTTB0_IRQn = 18, /*!< 16-bit TMRB interrupt(channel.0) */
AnnaBridge 172:7d866c31b3c5 61 INTTB1_IRQn = 19, /*!< 16-bit TMRB interrupt(channel.1) */
AnnaBridge 172:7d866c31b3c5 62 INTTB2_IRQn = 20, /*!< 16-bit TMRB interrupt(channel.2) */
AnnaBridge 172:7d866c31b3c5 63 INTTB3_IRQn = 21, /*!< 16-bit TMRB interrupt(channel.3) */
AnnaBridge 172:7d866c31b3c5 64 INTTB4_IRQn = 22, /*!< 16-bit TMRB interrupt(channel.4) */
AnnaBridge 172:7d866c31b3c5 65 INTTB5_IRQn = 23, /*!< 16-bit TMRB interrupt(channel.5) */
AnnaBridge 172:7d866c31b3c5 66 INTTB6_IRQn = 24, /*!< 16-bit TMRB interrupt(channel.6) */
AnnaBridge 172:7d866c31b3c5 67 INTTB7_IRQn = 25, /*!< 16-bit TMRB interrupt(channel.7) */
AnnaBridge 172:7d866c31b3c5 68 INTI2CS_IRQn = 26, /*!< Serial bus interface for Wakeup(channel.1) */
AnnaBridge 172:7d866c31b3c5 69 INTTMRD_IRQn = 27, /*!< TMRD interrupt */
AnnaBridge 172:7d866c31b3c5 70 INTUSB_IRQn = 28, /*!< USB interrupt */
AnnaBridge 172:7d866c31b3c5 71 INTUSBWKUP_IRQn = 29, /*!< USB wakeup interrupt */
AnnaBridge 172:7d866c31b3c5 72 INTADHP_IRQn = 30, /*!< High Priority A/D conversion interrupt */
AnnaBridge 172:7d866c31b3c5 73 INTAD_IRQn = 31 /*!< Normal A/D conversion completion interrupt */
AnnaBridge 172:7d866c31b3c5 74 } IRQn_Type;
AnnaBridge 172:7d866c31b3c5 75
AnnaBridge 172:7d866c31b3c5 76 /** Processor and Core Peripheral Section */
AnnaBridge 172:7d866c31b3c5 77
AnnaBridge 172:7d866c31b3c5 78 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
AnnaBridge 172:7d866c31b3c5 79 #define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */
AnnaBridge 172:7d866c31b3c5 80 #define __MPU_PRESENT 0 /*!< MPU present or not */
AnnaBridge 172:7d866c31b3c5 81 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
AnnaBridge 172:7d866c31b3c5 82 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 172:7d866c31b3c5 83
AnnaBridge 172:7d866c31b3c5 84 /** @} *//* End of group Configuration_of_CMSIS */
AnnaBridge 172:7d866c31b3c5 85
AnnaBridge 172:7d866c31b3c5 86 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
AnnaBridge 172:7d866c31b3c5 87 #include "system_TMPM066.h" /* TMPM066 System */
AnnaBridge 172:7d866c31b3c5 88
AnnaBridge 172:7d866c31b3c5 89 /** @addtogroup Device_Peripheral_registers
AnnaBridge 172:7d866c31b3c5 90 * @{
AnnaBridge 172:7d866c31b3c5 91 */
AnnaBridge 172:7d866c31b3c5 92
AnnaBridge 172:7d866c31b3c5 93 /** Device Specific Peripheral registers structures */
AnnaBridge 172:7d866c31b3c5 94
AnnaBridge 172:7d866c31b3c5 95 /**
AnnaBridge 172:7d866c31b3c5 96 * @brief UDC2 AHB Bridge
AnnaBridge 172:7d866c31b3c5 97 */
AnnaBridge 172:7d866c31b3c5 98 typedef struct {
AnnaBridge 172:7d866c31b3c5 99 __IO uint32_t INTSTS; /*!< Interrupt Status Register */
AnnaBridge 172:7d866c31b3c5 100 __IO uint32_t INTENB; /*!< Interrupt Enable Register */
AnnaBridge 172:7d866c31b3c5 101 __IO uint32_t MWTOUT; /*!< Master Write Timeout Register */
AnnaBridge 172:7d866c31b3c5 102 __IO uint32_t C2STSET; /*!< UDC2 setting */
AnnaBridge 172:7d866c31b3c5 103 __IO uint32_t MSTSET; /*!< DMAC setting */
AnnaBridge 172:7d866c31b3c5 104 __IO uint32_t DMACRDREQ; /*!< DMAC Read request */
AnnaBridge 172:7d866c31b3c5 105 __I uint32_t DMACRDVL; /*!< DMAC Read Value */
AnnaBridge 172:7d866c31b3c5 106 __IO uint32_t UDC2RDREQ; /*!< UDC2 Read Request */
AnnaBridge 172:7d866c31b3c5 107 __I uint32_t UDC2RDVL; /*!< UDC2 Read Value */
AnnaBridge 172:7d866c31b3c5 108 uint32_t RESERVED0[6];
AnnaBridge 172:7d866c31b3c5 109 __IO uint32_t ARBTSET; /*!< Arbiter Setting */
AnnaBridge 172:7d866c31b3c5 110 __IO uint32_t MWSADR; /*!< Master Write Start Address */
AnnaBridge 172:7d866c31b3c5 111 __IO uint32_t MWEADR; /*!< Master Write End Address */
AnnaBridge 172:7d866c31b3c5 112 __I uint32_t MWCADR; /*!< Master Write Current Address */
AnnaBridge 172:7d866c31b3c5 113 __I uint32_t MWAHBADR; /*!< Master Write AHB Address */
AnnaBridge 172:7d866c31b3c5 114 __IO uint32_t MRSADR; /*!< Master Read Start Address */
AnnaBridge 172:7d866c31b3c5 115 __IO uint32_t MREADR; /*!< Master Read End Address */
AnnaBridge 172:7d866c31b3c5 116 __I uint32_t MRCADR; /*!< Master Read Current Address */
AnnaBridge 172:7d866c31b3c5 117 __I uint32_t MRAHBADR; /*!< Master Read AHB Address */
AnnaBridge 172:7d866c31b3c5 118 uint32_t RESERVED1[8];
AnnaBridge 172:7d866c31b3c5 119 __IO uint32_t PWCTL; /*!< Power Detect Control */
AnnaBridge 172:7d866c31b3c5 120 __I uint32_t MSTSTS; /*!< Master Status */
AnnaBridge 172:7d866c31b3c5 121 __I uint32_t TOUTCNT; /*!< Timeout Count */
AnnaBridge 172:7d866c31b3c5 122 } TSB_UDFS_TypeDef;
AnnaBridge 172:7d866c31b3c5 123
AnnaBridge 172:7d866c31b3c5 124 /**
AnnaBridge 172:7d866c31b3c5 125 * @brief UDC2(USB -Spec2.0 Device contoller)
AnnaBridge 172:7d866c31b3c5 126 */
AnnaBridge 172:7d866c31b3c5 127 typedef struct {
AnnaBridge 172:7d866c31b3c5 128 __IO uint32_t ADR; /*!< UDC2 Address State */
AnnaBridge 172:7d866c31b3c5 129 __IO uint32_t FRM; /*!< UDC2 Frame */
AnnaBridge 172:7d866c31b3c5 130 uint32_t RESERVED0;
AnnaBridge 172:7d866c31b3c5 131 __IO uint32_t CMD; /*!< UDC2 Command */
AnnaBridge 172:7d866c31b3c5 132 __I uint32_t BRQ; /*!< UDC2 bRequest-bmRequest Type */
AnnaBridge 172:7d866c31b3c5 133 __I uint32_t WVL; /*!< UDC2 wValue */
AnnaBridge 172:7d866c31b3c5 134 __I uint32_t WIDX; /*!< UDC2 wIndex */
AnnaBridge 172:7d866c31b3c5 135 __I uint32_t WLGTH; /*!< UDC2 wLength */
AnnaBridge 172:7d866c31b3c5 136 __IO uint32_t INT; /*!< UDC2 INT */
AnnaBridge 172:7d866c31b3c5 137 __IO uint32_t INTEP; /*!< UDC2 INT_EP */
AnnaBridge 172:7d866c31b3c5 138 __IO uint32_t INTEPMSK; /*!< UDC2 INT_EP_MASK */
AnnaBridge 172:7d866c31b3c5 139 __IO uint32_t INTRX0; /*!< UDC2 INT RX DATA0 */
AnnaBridge 172:7d866c31b3c5 140 __IO uint32_t EP0MSZ; /*!< UDC2 EP0 Max Packet Size */
AnnaBridge 172:7d866c31b3c5 141 __I uint32_t EP0STS; /*!< UDC2 EP0 Status */
AnnaBridge 172:7d866c31b3c5 142 __I uint32_t EP0DSZ; /*!< UDC2 EP0 Data Size */
AnnaBridge 172:7d866c31b3c5 143 __IO uint32_t EP0FIFO; /*!< UDC2 EP0 FIFO */
AnnaBridge 172:7d866c31b3c5 144 __IO uint32_t EP1MSZ; /*!< UDC2 EP1 Max Packet Size */
AnnaBridge 172:7d866c31b3c5 145 __IO uint32_t EP1STS; /*!< UDC2 EP1 Status */
AnnaBridge 172:7d866c31b3c5 146 __I uint32_t EP1DSZ; /*!< UDC2 EP1 Data Size */
AnnaBridge 172:7d866c31b3c5 147 __IO uint32_t EP1FIFO; /*!< UDC2 EP1 FIFO */
AnnaBridge 172:7d866c31b3c5 148 __IO uint32_t EP2MSZ; /*!< UDC2 EP2 Max Packet Size */
AnnaBridge 172:7d866c31b3c5 149 __IO uint32_t EP2STS; /*!< UDC2 EP2 Status */
AnnaBridge 172:7d866c31b3c5 150 __I uint32_t EP2DSZ; /*!< UDC2 EP2 Data Size */
AnnaBridge 172:7d866c31b3c5 151 __IO uint32_t EP2FIFO; /*!< UDC2 EP2 FIFO */
AnnaBridge 172:7d866c31b3c5 152 __IO uint32_t EP3MSZ; /*!< UDC2 EP3 Max Packet Size */
AnnaBridge 172:7d866c31b3c5 153 __IO uint32_t EP3STS; /*!< UDC2 EP3 Status */
AnnaBridge 172:7d866c31b3c5 154 __I uint32_t EP3DSZ; /*!< UDC2 EP3 Data Size */
AnnaBridge 172:7d866c31b3c5 155 __IO uint32_t EP3FIFO; /*!< UDC2 EP3 FIFO */
AnnaBridge 172:7d866c31b3c5 156 __IO uint32_t EP4MSZ; /*!< UDC2 EP4 Max Packet Size */
AnnaBridge 172:7d866c31b3c5 157 __IO uint32_t EP4STS; /*!< UDC2 EP4 Status */
AnnaBridge 172:7d866c31b3c5 158 __I uint32_t EP4DSZ; /*!< UDC2 EP4 Data Size */
AnnaBridge 172:7d866c31b3c5 159 __IO uint32_t EP4FIFO; /*!< UDC2 EP4 FIFO */
AnnaBridge 172:7d866c31b3c5 160 uint32_t RESERVED1[44];
AnnaBridge 172:7d866c31b3c5 161 __IO uint32_t INTNAK; /*!< UDC2 INT NAK */
AnnaBridge 172:7d866c31b3c5 162 __IO uint32_t INTNAKMSK; /*!< UDC2 INT NAK MASK */
AnnaBridge 172:7d866c31b3c5 163 } TSB_UDFS2_TypeDef;
AnnaBridge 172:7d866c31b3c5 164
AnnaBridge 172:7d866c31b3c5 165 /**
AnnaBridge 172:7d866c31b3c5 166 * @brief AO Area register1
AnnaBridge 172:7d866c31b3c5 167 */
AnnaBridge 172:7d866c31b3c5 168 typedef struct {
AnnaBridge 172:7d866c31b3c5 169 uint8_t RESERVED0[32];
AnnaBridge 172:7d866c31b3c5 170 __IO uint8_t STOP2INT_032; /*!< STOP2INT I/F Control Register in AO Area */
AnnaBridge 172:7d866c31b3c5 171 __IO uint8_t STOP2INT_033; /*!< STOP2INT I/F Control Register in AO Area */
AnnaBridge 172:7d866c31b3c5 172 __IO uint8_t STOP2INT_034; /*!< STOP2INT I/F Control Register in AO Area */
AnnaBridge 172:7d866c31b3c5 173 __IO uint8_t STOP2INT_035; /*!< STOP2INT I/F Control Register in AO Area */
AnnaBridge 172:7d866c31b3c5 174 __IO uint8_t STOP2INT_036; /*!< STOP2INT I/F Control Register in AO Area */
AnnaBridge 172:7d866c31b3c5 175 __IO uint8_t STOP2INT_037; /*!< STOP2INT I/F Control Register in AO Area */
AnnaBridge 172:7d866c31b3c5 176 __IO uint8_t STOP2INT_038; /*!< STOP2INT I/F Control Register in AO Area */
AnnaBridge 172:7d866c31b3c5 177 __IO uint8_t STOP2INT_039; /*!< STOP2INT I/F Control Register in AO Area */
AnnaBridge 172:7d866c31b3c5 178 } TSB_INTIFAO_TypeDef;
AnnaBridge 172:7d866c31b3c5 179
AnnaBridge 172:7d866c31b3c5 180 /**
AnnaBridge 172:7d866c31b3c5 181 * @brief AO Area register2
AnnaBridge 172:7d866c31b3c5 182 */
AnnaBridge 172:7d866c31b3c5 183 typedef struct {
AnnaBridge 172:7d866c31b3c5 184 uint8_t RESERVED0[2];
AnnaBridge 172:7d866c31b3c5 185 __IO uint8_t RSTFLG; /*!< Reset Flag register */
AnnaBridge 172:7d866c31b3c5 186 __IO uint8_t RSTFLG1; /*!< Reset Flag1 register */
AnnaBridge 172:7d866c31b3c5 187 } TSB_AOREG_TypeDef;
AnnaBridge 172:7d866c31b3c5 188
AnnaBridge 172:7d866c31b3c5 189 /**
AnnaBridge 172:7d866c31b3c5 190 * @brief I2C Wakeup I/F register
AnnaBridge 172:7d866c31b3c5 191 */
AnnaBridge 172:7d866c31b3c5 192 typedef struct {
AnnaBridge 172:7d866c31b3c5 193 __IO uint8_t WUPCR1; /*!< I2C Wakeup control register1 */
AnnaBridge 172:7d866c31b3c5 194 __IO uint8_t WUPCR2; /*!< I2C Wakeup control register2 */
AnnaBridge 172:7d866c31b3c5 195 __IO uint8_t WUPCR3; /*!< I2C Wakeup control register3 */
AnnaBridge 172:7d866c31b3c5 196 __I uint8_t WUPSL; /*!< I2C Wakeup Status register */
AnnaBridge 172:7d866c31b3c5 197 } TSB_I2CS_TypeDef;
AnnaBridge 172:7d866c31b3c5 198
AnnaBridge 172:7d866c31b3c5 199 /**
AnnaBridge 172:7d866c31b3c5 200 * @brief DMA Controller
AnnaBridge 172:7d866c31b3c5 201 */
AnnaBridge 172:7d866c31b3c5 202 typedef struct {
AnnaBridge 172:7d866c31b3c5 203 __I uint32_t STATUS; /*!< DMA Status Register */
AnnaBridge 172:7d866c31b3c5 204 __O uint32_t CFG; /*!< DMA Configuration Register */
AnnaBridge 172:7d866c31b3c5 205 __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */
AnnaBridge 172:7d866c31b3c5 206 __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base
AnnaBridge 172:7d866c31b3c5 207 Pointer Register */
AnnaBridge 172:7d866c31b3c5 208 uint32_t RESERVED0;
AnnaBridge 172:7d866c31b3c5 209 __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */
AnnaBridge 172:7d866c31b3c5 210 __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */
AnnaBridge 172:7d866c31b3c5 211 __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */
AnnaBridge 172:7d866c31b3c5 212 __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */
AnnaBridge 172:7d866c31b3c5 213 __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */
AnnaBridge 172:7d866c31b3c5 214 __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */
AnnaBridge 172:7d866c31b3c5 215 __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */
AnnaBridge 172:7d866c31b3c5 216 __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */
AnnaBridge 172:7d866c31b3c5 217 __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */
AnnaBridge 172:7d866c31b3c5 218 __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */
AnnaBridge 172:7d866c31b3c5 219 __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */
AnnaBridge 172:7d866c31b3c5 220 uint32_t RESERVED1[3];
AnnaBridge 172:7d866c31b3c5 221 __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */
AnnaBridge 172:7d866c31b3c5 222 } TSB_DMA_TypeDef;
AnnaBridge 172:7d866c31b3c5 223
AnnaBridge 172:7d866c31b3c5 224 /**
AnnaBridge 172:7d866c31b3c5 225 * @brief Timer D (Unit0)
AnnaBridge 172:7d866c31b3c5 226 */
AnnaBridge 172:7d866c31b3c5 227 typedef struct {
AnnaBridge 172:7d866c31b3c5 228 __O uint32_t RUN; /*!< Timer Run Register (Unit0) */
AnnaBridge 172:7d866c31b3c5 229 __IO uint32_t CR; /*!< Timer Control Register (Unit0) */
AnnaBridge 172:7d866c31b3c5 230 __IO uint32_t MOD; /*!< Timer Mode Register (Unit0) */
AnnaBridge 172:7d866c31b3c5 231 __IO uint32_t DMA; /*!< DMA Request Enable Register (Unit0) */
AnnaBridge 172:7d866c31b3c5 232 uint32_t RESERVED0;
AnnaBridge 172:7d866c31b3c5 233 __IO uint32_t RG0; /*!< Timer Register0 (Unit0) */
AnnaBridge 172:7d866c31b3c5 234 __IO uint32_t RG1; /*!< Timer Register1 (Unit0) */
AnnaBridge 172:7d866c31b3c5 235 __IO uint32_t RG2; /*!< Timer Register2 (Unit0) */
AnnaBridge 172:7d866c31b3c5 236 __IO uint32_t RG3; /*!< Timer Register3 (Unit0) */
AnnaBridge 172:7d866c31b3c5 237 __IO uint32_t RG4; /*!< Timer Register4 (Unit0) */
AnnaBridge 172:7d866c31b3c5 238 __IO uint32_t RG5; /*!< Timer Register5 (Unit0) */
AnnaBridge 172:7d866c31b3c5 239 uint32_t RESERVED1[13];
AnnaBridge 172:7d866c31b3c5 240 __IO uint32_t HSWB0; /*!< H-SW Control Circuit Register Buffer0 (Unit0) */
AnnaBridge 172:7d866c31b3c5 241 __IO uint32_t HSWB1; /*!< H-SW Control Circuit Register Buffer1 (Unit0) */
AnnaBridge 172:7d866c31b3c5 242 uint32_t RESERVED2[43];
AnnaBridge 172:7d866c31b3c5 243 __I uint32_t CP0; /*!< Compare Register0 (Unit0) */
AnnaBridge 172:7d866c31b3c5 244 __I uint32_t CP1; /*!< Compare Register1 (Unit0) */
AnnaBridge 172:7d866c31b3c5 245 __I uint32_t CP2; /*!< Compare Register2 (Unit0) */
AnnaBridge 172:7d866c31b3c5 246 __I uint32_t CP3; /*!< Compare Register3 (Unit0) */
AnnaBridge 172:7d866c31b3c5 247 __I uint32_t CP4; /*!< Compare Register4 (Unit0) */
AnnaBridge 172:7d866c31b3c5 248 __I uint32_t CP5; /*!< Compare Register5 (Unit0) */
AnnaBridge 172:7d866c31b3c5 249 uint32_t RESERVED3[13];
AnnaBridge 172:7d866c31b3c5 250 __I uint32_t HSW0; /*!< H-SW Control Circuit Register (Unit0) */
AnnaBridge 172:7d866c31b3c5 251 __I uint32_t HSW1; /*!< H-SW Control Circuit Register (Unit0) */
AnnaBridge 172:7d866c31b3c5 252 } TSB_TD0_TypeDef;
AnnaBridge 172:7d866c31b3c5 253
AnnaBridge 172:7d866c31b3c5 254 /**
AnnaBridge 172:7d866c31b3c5 255 * @brief Timer D common
AnnaBridge 172:7d866c31b3c5 256 */
AnnaBridge 172:7d866c31b3c5 257 typedef struct {
AnnaBridge 172:7d866c31b3c5 258 __IO uint32_t BCR; /*!< Update Flag Setting Register */
AnnaBridge 172:7d866c31b3c5 259 uint32_t RESERVED0[3];
AnnaBridge 172:7d866c31b3c5 260 __IO uint32_t EN; /*!< Timer Enable Register */
AnnaBridge 172:7d866c31b3c5 261 __IO uint32_t CONF; /*!< Timer Configuration Register */
AnnaBridge 172:7d866c31b3c5 262 } TSB_TD_TypeDef;
AnnaBridge 172:7d866c31b3c5 263
AnnaBridge 172:7d866c31b3c5 264 /**
AnnaBridge 172:7d866c31b3c5 265 * @brief Timer D (Unit1)
AnnaBridge 172:7d866c31b3c5 266 */
AnnaBridge 172:7d866c31b3c5 267 typedef struct {
AnnaBridge 172:7d866c31b3c5 268 __IO uint32_t RG0; /*!< Timer Register0 (Unit1) */
AnnaBridge 172:7d866c31b3c5 269 __IO uint32_t RG1; /*!< Timer Register1 (Unit1) */
AnnaBridge 172:7d866c31b3c5 270 __IO uint32_t RG2; /*!< Timer Register2 (Unit1) */
AnnaBridge 172:7d866c31b3c5 271 __IO uint32_t RG3; /*!< Timer Register3 (Unit1) */
AnnaBridge 172:7d866c31b3c5 272 __IO uint32_t RG4; /*!< Timer Register4 (Unit1) */
AnnaBridge 172:7d866c31b3c5 273 uint32_t RESERVED0[10];
AnnaBridge 172:7d866c31b3c5 274 __IO uint32_t HSWB0; /*!< H-SW Control Circuit Register Buffer0 (Unit1) */
AnnaBridge 172:7d866c31b3c5 275 __IO uint32_t HSWB1; /*!< H-SW Control Circuit Register Buffer1 (Unit1) */
AnnaBridge 172:7d866c31b3c5 276 uint32_t RESERVED1[36];
AnnaBridge 172:7d866c31b3c5 277 __O uint32_t RUN; /*!< Timer Run Register (Unit1) */
AnnaBridge 172:7d866c31b3c5 278 __IO uint32_t CR; /*!< Timer Control Register (Unit1) */
AnnaBridge 172:7d866c31b3c5 279 __IO uint32_t MOD; /*!< Timer Mode Register (Unit1) */
AnnaBridge 172:7d866c31b3c5 280 __IO uint32_t DMA; /*!< DMA Request Enable Register (Unit1) */
AnnaBridge 172:7d866c31b3c5 281 uint32_t RESERVED2[7];
AnnaBridge 172:7d866c31b3c5 282 __I uint32_t CP0; /*!< Compare Register0 (Unit1) */
AnnaBridge 172:7d866c31b3c5 283 __I uint32_t CP1; /*!< Compare Register1 (Unit1) */
AnnaBridge 172:7d866c31b3c5 284 __I uint32_t CP2; /*!< Compare Register2 (Unit1) */
AnnaBridge 172:7d866c31b3c5 285 __I uint32_t CP3; /*!< Compare Register3 (Unit1) */
AnnaBridge 172:7d866c31b3c5 286 __I uint32_t CP4; /*!< Compare Register4 (Unit1) */
AnnaBridge 172:7d866c31b3c5 287 uint32_t RESERVED3[10];
AnnaBridge 172:7d866c31b3c5 288 __I uint32_t HSW0; /*!< H-SW Control Circuit Register (Unit1) */
AnnaBridge 172:7d866c31b3c5 289 __I uint32_t HSW1; /*!< H-SW Control Circuit Register (Unit1) */
AnnaBridge 172:7d866c31b3c5 290 } TSB_TD1_TypeDef;
AnnaBridge 172:7d866c31b3c5 291
AnnaBridge 172:7d866c31b3c5 292 /**
AnnaBridge 172:7d866c31b3c5 293 * @brief 16-bit TimerA
AnnaBridge 172:7d866c31b3c5 294 */
AnnaBridge 172:7d866c31b3c5 295 typedef struct {
AnnaBridge 172:7d866c31b3c5 296 __IO uint32_t EN; /*!< Enable Register */
AnnaBridge 172:7d866c31b3c5 297 __IO uint32_t RUN; /*!< RUN Register */
AnnaBridge 172:7d866c31b3c5 298 __IO uint32_t CR; /*!< Control Register */
AnnaBridge 172:7d866c31b3c5 299 __IO uint32_t RG; /*!< Timer Register */
AnnaBridge 172:7d866c31b3c5 300 __I uint32_t CP; /*!< Capture Register */
AnnaBridge 172:7d866c31b3c5 301 } TSB_T16A_TypeDef;
AnnaBridge 172:7d866c31b3c5 302
AnnaBridge 172:7d866c31b3c5 303 /**
AnnaBridge 172:7d866c31b3c5 304 * @brief Serial Interface (TSPI)
AnnaBridge 172:7d866c31b3c5 305 */
AnnaBridge 172:7d866c31b3c5 306 typedef struct {
AnnaBridge 172:7d866c31b3c5 307 __IO uint32_t CR0; /*!< TSPI Control Register 0 */
AnnaBridge 172:7d866c31b3c5 308 __IO uint32_t CR1; /*!< TSPI Control Register 1 */
AnnaBridge 172:7d866c31b3c5 309 __IO uint32_t CR2; /*!< TSPI Control Register 2 */
AnnaBridge 172:7d866c31b3c5 310 __IO uint32_t CR3; /*!< TSPI Control Register 3 */
AnnaBridge 172:7d866c31b3c5 311 __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */
AnnaBridge 172:7d866c31b3c5 312 __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */
AnnaBridge 172:7d866c31b3c5 313 __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */
AnnaBridge 172:7d866c31b3c5 314 uint32_t RESERVED0[57];
AnnaBridge 172:7d866c31b3c5 315 __IO uint32_t DR; /*!< TSPI Data Register */
AnnaBridge 172:7d866c31b3c5 316 uint32_t RESERVED1[63];
AnnaBridge 172:7d866c31b3c5 317 __IO uint32_t SR; /*!< TSPI Status Register */
AnnaBridge 172:7d866c31b3c5 318 __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */
AnnaBridge 172:7d866c31b3c5 319 } TSB_TSPI_TypeDef;
AnnaBridge 172:7d866c31b3c5 320
AnnaBridge 172:7d866c31b3c5 321 #if defined ( __CC_ARM ) /* RealView Compiler */
AnnaBridge 172:7d866c31b3c5 322 #pragma anon_unions
AnnaBridge 172:7d866c31b3c5 323 #elif (defined (__ICCARM__)) /* ICC Compiler */
AnnaBridge 172:7d866c31b3c5 324 #pragma language=extended
AnnaBridge 172:7d866c31b3c5 325 #endif
AnnaBridge 172:7d866c31b3c5 326
AnnaBridge 172:7d866c31b3c5 327 /**
AnnaBridge 172:7d866c31b3c5 328 * @brief I2C
AnnaBridge 172:7d866c31b3c5 329 */
AnnaBridge 172:7d866c31b3c5 330 typedef struct {
AnnaBridge 172:7d866c31b3c5 331 __IO uint32_t CR1; /*!< I2C Control Register 1 */
AnnaBridge 172:7d866c31b3c5 332 __IO uint32_t DBR; /*!< Data Buffer Register */
AnnaBridge 172:7d866c31b3c5 333 __IO uint32_t AR; /*!< Bus address Register */
AnnaBridge 172:7d866c31b3c5 334 union {
AnnaBridge 172:7d866c31b3c5 335 __O uint32_t CR2; /*!< Control Register 2 */
AnnaBridge 172:7d866c31b3c5 336 __I uint32_t SR; /*!< Status Register */
AnnaBridge 172:7d866c31b3c5 337 };
AnnaBridge 172:7d866c31b3c5 338 __IO uint32_t PRS; /*!< Prescaler clcok setting Register */
AnnaBridge 172:7d866c31b3c5 339 __IO uint32_t IE; /*!< Interrupt Enable Register */
AnnaBridge 172:7d866c31b3c5 340 __IO uint32_t ST; /*!< Interrupt Register */
AnnaBridge 172:7d866c31b3c5 341 __IO uint32_t OP; /*!< Optiononal Function register */
AnnaBridge 172:7d866c31b3c5 342 __I uint32_t PM; /*!< Bus Monitor register */
AnnaBridge 172:7d866c31b3c5 343 __IO uint32_t AR2; /*!< Second Slave address register */
AnnaBridge 172:7d866c31b3c5 344 } TSB_I2C_TypeDef;
AnnaBridge 172:7d866c31b3c5 345
AnnaBridge 172:7d866c31b3c5 346 /**
AnnaBridge 172:7d866c31b3c5 347 * @brief Port A
AnnaBridge 172:7d866c31b3c5 348 */
AnnaBridge 172:7d866c31b3c5 349 typedef struct {
AnnaBridge 172:7d866c31b3c5 350 __IO uint32_t DATA; /*!< PA Data Register */
AnnaBridge 172:7d866c31b3c5 351 __IO uint32_t CR; /*!< PA Control Register */
AnnaBridge 172:7d866c31b3c5 352 __IO uint32_t FR1; /*!< PA Function Register 1 */
AnnaBridge 172:7d866c31b3c5 353 uint32_t RESERVED0[7];
AnnaBridge 172:7d866c31b3c5 354 __IO uint32_t OD; /*!< PA Open Drain Control Register */
AnnaBridge 172:7d866c31b3c5 355 __IO uint32_t PUP; /*!< PA Pull-up Control Register */
AnnaBridge 172:7d866c31b3c5 356 __IO uint32_t PDN; /*!< PA Pull-Down Control Register */
AnnaBridge 172:7d866c31b3c5 357 uint32_t RESERVED1;
AnnaBridge 172:7d866c31b3c5 358 __IO uint32_t IE; /*!< PA Input Enable Control Register */
AnnaBridge 172:7d866c31b3c5 359 } TSB_PA_TypeDef;
AnnaBridge 172:7d866c31b3c5 360
AnnaBridge 172:7d866c31b3c5 361 /**
AnnaBridge 172:7d866c31b3c5 362 * @brief Port B
AnnaBridge 172:7d866c31b3c5 363 */
AnnaBridge 172:7d866c31b3c5 364 typedef struct {
AnnaBridge 172:7d866c31b3c5 365 __IO uint32_t DATA; /*!< PB Data Register */
AnnaBridge 172:7d866c31b3c5 366 __IO uint32_t CR; /*!< PB Control Register */
AnnaBridge 172:7d866c31b3c5 367 uint32_t RESERVED0[8];
AnnaBridge 172:7d866c31b3c5 368 __IO uint32_t OD; /*!< PB Open Drain Control Register */
AnnaBridge 172:7d866c31b3c5 369 __IO uint32_t PUP; /*!< PB Pull-up Control Register */
AnnaBridge 172:7d866c31b3c5 370 __IO uint32_t PDN; /*!< PB Pull-Down Control Register */
AnnaBridge 172:7d866c31b3c5 371 uint32_t RESERVED1;
AnnaBridge 172:7d866c31b3c5 372 __IO uint32_t IE; /*!< PB Input Enable Control Register */
AnnaBridge 172:7d866c31b3c5 373 } TSB_PB_TypeDef;
AnnaBridge 172:7d866c31b3c5 374
AnnaBridge 172:7d866c31b3c5 375 /**
AnnaBridge 172:7d866c31b3c5 376 * @brief Port C
AnnaBridge 172:7d866c31b3c5 377 */
AnnaBridge 172:7d866c31b3c5 378 typedef struct {
AnnaBridge 172:7d866c31b3c5 379 __IO uint32_t DATA; /*!< PC Data Register */
AnnaBridge 172:7d866c31b3c5 380 __IO uint32_t CR; /*!< PC Control Register */
AnnaBridge 172:7d866c31b3c5 381 __IO uint32_t FR1; /*!< PC Function Register 1 */
AnnaBridge 172:7d866c31b3c5 382 uint32_t RESERVED0[7];
AnnaBridge 172:7d866c31b3c5 383 __IO uint32_t OD; /*!< PC Open Drain Control Register */
AnnaBridge 172:7d866c31b3c5 384 __IO uint32_t PUP; /*!< PC Pull-up Control Register */
AnnaBridge 172:7d866c31b3c5 385 __IO uint32_t PDN; /*!< PC Pull-Down Control Register */
AnnaBridge 172:7d866c31b3c5 386 __IO uint32_t SEL; /*!< PC input voltage selection Register */
AnnaBridge 172:7d866c31b3c5 387 __IO uint32_t IE; /*!< PC Input Enable Control Register */
AnnaBridge 172:7d866c31b3c5 388 } TSB_PC_TypeDef;
AnnaBridge 172:7d866c31b3c5 389
AnnaBridge 172:7d866c31b3c5 390 /**
AnnaBridge 172:7d866c31b3c5 391 * @brief Port D
AnnaBridge 172:7d866c31b3c5 392 */
AnnaBridge 172:7d866c31b3c5 393 typedef struct {
AnnaBridge 172:7d866c31b3c5 394 __IO uint32_t DATA; /*!< PD Data Register */
AnnaBridge 172:7d866c31b3c5 395 __IO uint32_t CR; /*!< PD Control Register */
AnnaBridge 172:7d866c31b3c5 396 __IO uint32_t FR1; /*!< PD Function Register 1 */
AnnaBridge 172:7d866c31b3c5 397 __IO uint32_t FR2; /*!< PD Function Register 2 */
AnnaBridge 172:7d866c31b3c5 398 uint32_t RESERVED0[6];
AnnaBridge 172:7d866c31b3c5 399 __IO uint32_t OD; /*!< PD Open Drain Control Register */
AnnaBridge 172:7d866c31b3c5 400 __IO uint32_t PUP; /*!< PD Pull-up Control Register */
AnnaBridge 172:7d866c31b3c5 401 __IO uint32_t PDN; /*!< PD Pull-Down Control Register */
AnnaBridge 172:7d866c31b3c5 402 __IO uint32_t SEL; /*!< PD input voltage selection Register */
AnnaBridge 172:7d866c31b3c5 403 __IO uint32_t IE; /*!< PD Input Enable Control Register */
AnnaBridge 172:7d866c31b3c5 404 } TSB_PD_TypeDef;
AnnaBridge 172:7d866c31b3c5 405
AnnaBridge 172:7d866c31b3c5 406 /**
AnnaBridge 172:7d866c31b3c5 407 * @brief Port E
AnnaBridge 172:7d866c31b3c5 408 */
AnnaBridge 172:7d866c31b3c5 409 typedef struct {
AnnaBridge 172:7d866c31b3c5 410 __IO uint32_t DATA; /*!< PE Data Register */
AnnaBridge 172:7d866c31b3c5 411 __IO uint32_t CR; /*!< PE Control Register */
AnnaBridge 172:7d866c31b3c5 412 __IO uint32_t FR1; /*!< PE Function Register 1 */
AnnaBridge 172:7d866c31b3c5 413 __IO uint32_t FR2; /*!< PE Function Register 2 */
AnnaBridge 172:7d866c31b3c5 414 uint32_t RESERVED0[6];
AnnaBridge 172:7d866c31b3c5 415 __IO uint32_t OD; /*!< PE Open Drain Control Register */
AnnaBridge 172:7d866c31b3c5 416 __IO uint32_t PUP; /*!< PE Pull-up Control Register */
AnnaBridge 172:7d866c31b3c5 417 __IO uint32_t PDN; /*!< PE Pull-Down Control Register */
AnnaBridge 172:7d866c31b3c5 418 uint32_t RESERVED1;
AnnaBridge 172:7d866c31b3c5 419 __IO uint32_t IE; /*!< PE Input Enable Control Register */
AnnaBridge 172:7d866c31b3c5 420 } TSB_PE_TypeDef;
AnnaBridge 172:7d866c31b3c5 421
AnnaBridge 172:7d866c31b3c5 422 /**
AnnaBridge 172:7d866c31b3c5 423 * @brief Port F
AnnaBridge 172:7d866c31b3c5 424 */
AnnaBridge 172:7d866c31b3c5 425 typedef struct {
AnnaBridge 172:7d866c31b3c5 426 __IO uint32_t DATA; /*!< PF Data Register */
AnnaBridge 172:7d866c31b3c5 427 __IO uint32_t CR; /*!< PF Control Register */
AnnaBridge 172:7d866c31b3c5 428 __IO uint32_t FR1; /*!< PF Function Register 1 */
AnnaBridge 172:7d866c31b3c5 429 __IO uint32_t FR2; /*!< PF Function Register 2 */
AnnaBridge 172:7d866c31b3c5 430 uint32_t RESERVED0[6];
AnnaBridge 172:7d866c31b3c5 431 __IO uint32_t OD; /*!< PF Open Drain Control Register */
AnnaBridge 172:7d866c31b3c5 432 __IO uint32_t PUP; /*!< PF Pull-up Control Register */
AnnaBridge 172:7d866c31b3c5 433 __IO uint32_t PDN; /*!< PF Pull-Down Control Register */
AnnaBridge 172:7d866c31b3c5 434 uint32_t RESERVED1;
AnnaBridge 172:7d866c31b3c5 435 __IO uint32_t IE; /*!< PF Input Enable Control Register */
AnnaBridge 172:7d866c31b3c5 436 } TSB_PF_TypeDef;
AnnaBridge 172:7d866c31b3c5 437
AnnaBridge 172:7d866c31b3c5 438 /**
AnnaBridge 172:7d866c31b3c5 439 * @brief Port G
AnnaBridge 172:7d866c31b3c5 440 */
AnnaBridge 172:7d866c31b3c5 441 typedef struct {
AnnaBridge 172:7d866c31b3c5 442 __IO uint32_t DATA; /*!< PG Data Register */
AnnaBridge 172:7d866c31b3c5 443 __IO uint32_t CR; /*!< PG Control Register */
AnnaBridge 172:7d866c31b3c5 444 __IO uint32_t FR1; /*!< PG Function Register 1 */
AnnaBridge 172:7d866c31b3c5 445 uint32_t RESERVED0[7];
AnnaBridge 172:7d866c31b3c5 446 __IO uint32_t OD; /*!< PG Open Drain Control Register */
AnnaBridge 172:7d866c31b3c5 447 __IO uint32_t PUP; /*!< PG Pull-up Control Register */
AnnaBridge 172:7d866c31b3c5 448 __IO uint32_t PDN; /*!< PG Pull-Down Control Register */
AnnaBridge 172:7d866c31b3c5 449 __IO uint32_t SEL; /*!< PG input voltage selection Register */
AnnaBridge 172:7d866c31b3c5 450 __IO uint32_t IE; /*!< PG Input Enable Control Register */
AnnaBridge 172:7d866c31b3c5 451 } TSB_PG_TypeDef;
AnnaBridge 172:7d866c31b3c5 452
AnnaBridge 172:7d866c31b3c5 453 /**
AnnaBridge 172:7d866c31b3c5 454 * @brief Port H
AnnaBridge 172:7d866c31b3c5 455 */
AnnaBridge 172:7d866c31b3c5 456 typedef struct {
AnnaBridge 172:7d866c31b3c5 457 __IO uint32_t DATA; /*!< PH Data Register */
AnnaBridge 172:7d866c31b3c5 458 __IO uint32_t CR; /*!< PH Control Register */
AnnaBridge 172:7d866c31b3c5 459 __IO uint32_t FR1; /*!< PF Function Register 1 */
AnnaBridge 172:7d866c31b3c5 460 uint32_t RESERVED0[7];
AnnaBridge 172:7d866c31b3c5 461 __IO uint32_t OD; /*!< PH Open Drain Control Register */
AnnaBridge 172:7d866c31b3c5 462 __IO uint32_t PUP; /*!< PH Pull-up Control Register */
AnnaBridge 172:7d866c31b3c5 463 __IO uint32_t PDN; /*!< PH Pull-Down Control Register */
AnnaBridge 172:7d866c31b3c5 464 uint32_t RESERVED1;
AnnaBridge 172:7d866c31b3c5 465 __IO uint32_t IE; /*!< PH Input Enable Control Register */
AnnaBridge 172:7d866c31b3c5 466 } TSB_PH_TypeDef;
AnnaBridge 172:7d866c31b3c5 467
AnnaBridge 172:7d866c31b3c5 468 /**
AnnaBridge 172:7d866c31b3c5 469 * @brief Port J
AnnaBridge 172:7d866c31b3c5 470 */
AnnaBridge 172:7d866c31b3c5 471 typedef struct {
AnnaBridge 172:7d866c31b3c5 472 __IO uint32_t DATA; /*!< PJ Data Register */
AnnaBridge 172:7d866c31b3c5 473 __IO uint32_t CR; /*!< PJ Control Register */
AnnaBridge 172:7d866c31b3c5 474 __IO uint32_t FR1; /*!< PJ Function Register 1 */
AnnaBridge 172:7d866c31b3c5 475 uint32_t RESERVED0[7];
AnnaBridge 172:7d866c31b3c5 476 __IO uint32_t OD; /*!< PJ Open Drain Control Register */
AnnaBridge 172:7d866c31b3c5 477 __IO uint32_t PUP; /*!< PJ Pull-up Control Register */
AnnaBridge 172:7d866c31b3c5 478 __IO uint32_t PDN; /*!< PJ Pull-Down Control Register */
AnnaBridge 172:7d866c31b3c5 479 uint32_t RESERVED1;
AnnaBridge 172:7d866c31b3c5 480 __IO uint32_t IE; /*!< PJ Input Enable Control Register */
AnnaBridge 172:7d866c31b3c5 481 } TSB_PJ_TypeDef;
AnnaBridge 172:7d866c31b3c5 482
AnnaBridge 172:7d866c31b3c5 483 /**
AnnaBridge 172:7d866c31b3c5 484 * @brief 16-bit Timer/Event Counter (TB)
AnnaBridge 172:7d866c31b3c5 485 */
AnnaBridge 172:7d866c31b3c5 486 typedef struct {
AnnaBridge 172:7d866c31b3c5 487 __IO uint32_t EN; /*!< TB Enable Register */
AnnaBridge 172:7d866c31b3c5 488 __IO uint32_t RUN; /*!< TB RUN Register */
AnnaBridge 172:7d866c31b3c5 489 __IO uint32_t CR; /*!< TB Control Register */
AnnaBridge 172:7d866c31b3c5 490 __IO uint32_t MOD; /*!< TB Mode Register */
AnnaBridge 172:7d866c31b3c5 491 __IO uint32_t FFCR; /*!< TB Flip-Flop Control Register */
AnnaBridge 172:7d866c31b3c5 492 __I uint32_t ST; /*!< TB Status Register */
AnnaBridge 172:7d866c31b3c5 493 __IO uint32_t IM; /*!< TB Interrupt Mask Register */
AnnaBridge 172:7d866c31b3c5 494 __I uint32_t UC; /*!< TB Read Capture Register */
AnnaBridge 172:7d866c31b3c5 495 __IO uint32_t RG0; /*!< TB RG0 Timer Register */
AnnaBridge 172:7d866c31b3c5 496 __IO uint32_t RG1; /*!< TB RG1 Timer Register */
AnnaBridge 172:7d866c31b3c5 497 __I uint32_t CP0; /*!< TB CP0 Capture Register */
AnnaBridge 172:7d866c31b3c5 498 __I uint32_t CP1; /*!< TB CP1 Capture Register */
AnnaBridge 172:7d866c31b3c5 499 __IO uint32_t DMA; /*!< TB DMA Enable Register */
AnnaBridge 172:7d866c31b3c5 500 } TSB_TB_TypeDef;
AnnaBridge 172:7d866c31b3c5 501
AnnaBridge 172:7d866c31b3c5 502 /**
AnnaBridge 172:7d866c31b3c5 503 * @brief SC
AnnaBridge 172:7d866c31b3c5 504 */
AnnaBridge 172:7d866c31b3c5 505 typedef struct {
AnnaBridge 172:7d866c31b3c5 506 __IO uint32_t EN; /*!< SC Enable Register */
AnnaBridge 172:7d866c31b3c5 507 __IO uint32_t BUF; /*!< SC Buffer Register */
AnnaBridge 172:7d866c31b3c5 508 __IO uint32_t CR; /*!< SC Control Register */
AnnaBridge 172:7d866c31b3c5 509 __IO uint32_t MOD0; /*!< SC Mode Control Register 0 */
AnnaBridge 172:7d866c31b3c5 510 __IO uint32_t BRCR; /*!< SC Baud Rate Generator Control Register */
AnnaBridge 172:7d866c31b3c5 511 __IO uint32_t BRADD; /*!< SC Baud Rate Generator Control Register 2 */
AnnaBridge 172:7d866c31b3c5 512 __IO uint32_t MOD1; /*!< SC Mode Control Register 1 */
AnnaBridge 172:7d866c31b3c5 513 __IO uint32_t MOD2; /*!< SC Mode Control Register 2 */
AnnaBridge 172:7d866c31b3c5 514 __IO uint32_t RFC; /*!< SC RX FIFO Configuration Register */
AnnaBridge 172:7d866c31b3c5 515 __IO uint32_t TFC; /*!< SC TX FIFO Configuration Register */
AnnaBridge 172:7d866c31b3c5 516 __I uint32_t RST; /*!< SC RX FIFO Status Register */
AnnaBridge 172:7d866c31b3c5 517 __I uint32_t TST; /*!< SC TX FIFO Status Register */
AnnaBridge 172:7d866c31b3c5 518 __IO uint32_t FCNF; /*!< SC FIFO Configuration Register */
AnnaBridge 172:7d866c31b3c5 519 __IO uint32_t DMA; /*!< SC DMA Request Register */
AnnaBridge 172:7d866c31b3c5 520 } TSB_SC_TypeDef;
AnnaBridge 172:7d866c31b3c5 521
AnnaBridge 172:7d866c31b3c5 522 /**
AnnaBridge 172:7d866c31b3c5 523 * @brief WDT
AnnaBridge 172:7d866c31b3c5 524 */
AnnaBridge 172:7d866c31b3c5 525 typedef struct {
AnnaBridge 172:7d866c31b3c5 526 __IO uint32_t MOD; /*!< WD Mode Register */
AnnaBridge 172:7d866c31b3c5 527 __O uint32_t CR; /*!< WD Control Register */
AnnaBridge 172:7d866c31b3c5 528 __I uint32_t FLG; /*!< WD Flag Register */
AnnaBridge 172:7d866c31b3c5 529 } TSB_WD_TypeDef;
AnnaBridge 172:7d866c31b3c5 530
AnnaBridge 172:7d866c31b3c5 531 /**
AnnaBridge 172:7d866c31b3c5 532 * @brief CG
AnnaBridge 172:7d866c31b3c5 533 */
AnnaBridge 172:7d866c31b3c5 534 typedef struct {
AnnaBridge 172:7d866c31b3c5 535 __IO uint32_t PROTECT; /*!< Protect Register */
AnnaBridge 172:7d866c31b3c5 536 __IO uint32_t OSCCR; /*!< Oscillation Control Register */
AnnaBridge 172:7d866c31b3c5 537 __IO uint32_t SYSCR; /*!< System clock control register */
AnnaBridge 172:7d866c31b3c5 538 __IO uint32_t STBYCR; /*!< Standby Control Register */
AnnaBridge 172:7d866c31b3c5 539 uint32_t RESERVED0[4];
AnnaBridge 172:7d866c31b3c5 540 __IO uint32_t PLL0SEL; /*!< PLL select register for fsys */
AnnaBridge 172:7d866c31b3c5 541 uint32_t RESERVED1[3];
AnnaBridge 172:7d866c31b3c5 542 __IO uint32_t WUPHCR; /*!< Warmup register for HOSC */
AnnaBridge 172:7d866c31b3c5 543 uint32_t RESERVED2[7];
AnnaBridge 172:7d866c31b3c5 544 __IO uint32_t FSYSENA; /*!< output control register A for fsys clock */
AnnaBridge 172:7d866c31b3c5 545 __O uint32_t FSYSENB; /*!< output control register B for fsys clock */
AnnaBridge 172:7d866c31b3c5 546 uint32_t RESERVED3;
AnnaBridge 172:7d866c31b3c5 547 __IO uint32_t SPCLKEN; /*!< Output control register for ADC and TRACE CLOCK */
AnnaBridge 172:7d866c31b3c5 548 __IO uint32_t EXTENDO0; /*!< Optional Function setting Register */
AnnaBridge 172:7d866c31b3c5 549 } TSB_CG_TypeDef;
AnnaBridge 172:7d866c31b3c5 550
AnnaBridge 172:7d866c31b3c5 551 /**
AnnaBridge 172:7d866c31b3c5 552 * @brief LVD
AnnaBridge 172:7d866c31b3c5 553 */
AnnaBridge 172:7d866c31b3c5 554 typedef struct {
AnnaBridge 172:7d866c31b3c5 555 __IO uint32_t CR0; /*!< LVD Control register0 */
AnnaBridge 172:7d866c31b3c5 556 __IO uint32_t CR1; /*!< LVD Control register1 */
AnnaBridge 172:7d866c31b3c5 557 } TSB_LVD_TypeDef;
AnnaBridge 172:7d866c31b3c5 558
AnnaBridge 172:7d866c31b3c5 559 /**
AnnaBridge 172:7d866c31b3c5 560 * @brief SD Area register1
AnnaBridge 172:7d866c31b3c5 561 */
AnnaBridge 172:7d866c31b3c5 562 typedef struct {
AnnaBridge 172:7d866c31b3c5 563 uint8_t RESERVED0[16];
AnnaBridge 172:7d866c31b3c5 564 __IO uint8_t STOP1INT_016; /*!< STOP1INT(NMI_LVD) I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 565 __IO uint8_t STOP1INT_017; /*!< STOP1INT(NMI_LVD) I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 566 __IO uint8_t IDLEINT_018; /*!< ILDEINT(NMI_WDT) I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 567 uint8_t RESERVED1[77];
AnnaBridge 172:7d866c31b3c5 568 __IO uint8_t IDLEINT_096; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 569 __IO uint8_t IDLEINT_097; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 570 __IO uint8_t IDLEINT_098; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 571 __IO uint8_t IDLEINT_099; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 572 __IO uint8_t IDLEINT_100; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 573 __IO uint8_t IDLEINT_101; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 574 __IO uint8_t IDLEINT_102; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 575 __IO uint8_t IDLEINT_103; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 576 __IO uint8_t IDLEINT_104; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 577 __IO uint8_t IDLEINT_105; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 578 __IO uint8_t IDLEINT_106; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 579 __IO uint8_t IDLEINT_107; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 580 __IO uint8_t IDLEINT_108; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 581 __IO uint8_t IDLEINT_109; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 582 __IO uint8_t IDLEINT_110; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 583 __IO uint8_t IDLEINT_111; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 584 __IO uint8_t IDLEINT_112; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 585 __IO uint8_t IDLEINT_113; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 586 __IO uint8_t IDLEINT_114; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 587 __IO uint8_t IDLEINT_115; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 588 __IO uint8_t IDLEINT_116; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 589 __IO uint8_t IDLEINT_117; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 590 __IO uint8_t IDLEINT_118; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 591 __IO uint8_t IDLEINT_119; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 592 __IO uint8_t IDLEINT_120; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 593 __IO uint8_t IDLEINT_121; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 594 __IO uint8_t IDLEINT_122; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 595 __IO uint8_t IDLEINT_123; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 596 __IO uint8_t IDLEINT_124; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 597 __IO uint8_t IDLEINT_125; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 598 __IO uint8_t IDLEINT_126; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 599 __IO uint8_t IDLEINT_127; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 600 __IO uint8_t IDLEINT_128; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 601 __IO uint8_t IDLEINT_129; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 602 __IO uint8_t IDLEINT_130; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 603 __IO uint8_t IDLEINT_131; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 604 __IO uint8_t IDLEINT_132; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 605 __IO uint8_t IDLEINT_133; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 606 __IO uint8_t IDLEINT_134; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 607 __IO uint8_t IDLEINT_135; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 608 __IO uint8_t IDLEINT_136; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 609 __IO uint8_t IDLEINT_137; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 610 __IO uint8_t IDLEINT_138; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 611 __IO uint8_t IDLEINT_139; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 612 __IO uint8_t IDLEINT_140; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 613 __IO uint8_t IDLEINT_141; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 614 __IO uint8_t IDLEINT_142; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 615 __IO uint8_t IDLEINT_143; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 616 __IO uint8_t IDLEINT_144; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 617 __IO uint8_t IDLEINT_145; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 618 __IO uint8_t IDLEINT_146; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 619 __IO uint8_t IDLEINT_147; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 620 __IO uint8_t IDLEINT_148; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 621 __IO uint8_t IDLEINT_149; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 622 __IO uint8_t IDLEINT_150; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 623 __IO uint8_t IDLEINT_151; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 624 __IO uint8_t IDLEINT_152; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 625 __IO uint8_t IDLEINT_153; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 626 __IO uint8_t IDLEINT_154; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 627 __IO uint8_t IDLEINT_155; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 628 __IO uint8_t IDLEINT_156; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 629 __IO uint8_t IDLEINT_157; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 630 __IO uint8_t IDLEINT_158; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 631 __IO uint8_t IDLEINT_159; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 632 __IO uint8_t IDLEINT_160; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 633 __IO uint8_t IDLEINT_161; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 634 __IO uint8_t IDLEINT_162; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 635 __IO uint8_t IDLEINT_163; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 636 __IO uint8_t IDLEINT_164; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 637 __IO uint8_t IDLEINT_165; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 638 __IO uint8_t IDLEINT_166; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 639 __IO uint8_t IDLEINT_167; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 640 __IO uint8_t IDLEINT_168; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 641 __IO uint8_t IDLEINT_169; /*!< IDLEINT I/F Control Register in SD Area */
AnnaBridge 172:7d866c31b3c5 642 uint32_t RESERVED2[21];
AnnaBridge 172:7d866c31b3c5 643 __I uint32_t FLAG0; /*!< NMI interrupt status flag register */
AnnaBridge 172:7d866c31b3c5 644 __I uint32_t FLAG1; /*!< interrupt status flag register1 for AO area */
AnnaBridge 172:7d866c31b3c5 645 uint32_t RESERVED3;
AnnaBridge 172:7d866c31b3c5 646 __I uint32_t FLAG3; /*!< interrupt status flag register3 for SD area */
AnnaBridge 172:7d866c31b3c5 647 __I uint32_t FLAG4; /*!< interrupt status flag register4 for SD area */
AnnaBridge 172:7d866c31b3c5 648 __I uint32_t FLAG5; /*!< interrupt status flag register5 for SD area */
AnnaBridge 172:7d866c31b3c5 649 } TSB_INTIFSD_TypeDef;
AnnaBridge 172:7d866c31b3c5 650
AnnaBridge 172:7d866c31b3c5 651 /**
AnnaBridge 172:7d866c31b3c5 652 * @brief ADC
AnnaBridge 172:7d866c31b3c5 653 */
AnnaBridge 172:7d866c31b3c5 654 typedef struct {
AnnaBridge 172:7d866c31b3c5 655 __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */
AnnaBridge 172:7d866c31b3c5 656 __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */
AnnaBridge 172:7d866c31b3c5 657 __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */
AnnaBridge 172:7d866c31b3c5 658 __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */
AnnaBridge 172:7d866c31b3c5 659 __IO uint32_t MOD3; /*!< AD Mode Control Register 3 */
AnnaBridge 172:7d866c31b3c5 660 __IO uint32_t MOD4; /*!< AD Mode Control Register 4 */
AnnaBridge 172:7d866c31b3c5 661 __IO uint32_t MOD5; /*!< AD Mode Control Register 5 */
AnnaBridge 172:7d866c31b3c5 662 __IO uint32_t MOD6; /*!< AD Mode Control Register 6 */
AnnaBridge 172:7d866c31b3c5 663 uint32_t RESERVED0[4];
AnnaBridge 172:7d866c31b3c5 664 __I uint32_t REG0; /*!< AD Conversion Result Register 0 */
AnnaBridge 172:7d866c31b3c5 665 __I uint32_t REG1; /*!< AD Conversion Result Register 1 */
AnnaBridge 172:7d866c31b3c5 666 __I uint32_t REG2; /*!< AD Conversion Result Register 2 */
AnnaBridge 172:7d866c31b3c5 667 __I uint32_t REG3; /*!< AD Conversion Result Register 3 */
AnnaBridge 172:7d866c31b3c5 668 __I uint32_t REG4; /*!< AD Conversion Result Register 4 */
AnnaBridge 172:7d866c31b3c5 669 __I uint32_t REG5; /*!< AD Conversion Result Register 5 */
AnnaBridge 172:7d866c31b3c5 670 __I uint32_t REG6; /*!< AD Conversion Result Register 6 */
AnnaBridge 172:7d866c31b3c5 671 __I uint32_t REG7; /*!< AD Conversion Result Register 7 */
AnnaBridge 172:7d866c31b3c5 672 uint32_t RESERVED1[4];
AnnaBridge 172:7d866c31b3c5 673 __I uint32_t REGSP; /*!< AD Conversion Result Register SP */
AnnaBridge 172:7d866c31b3c5 674 __IO uint32_t CMP0; /*!< AD Conversion Result comparing register0 */
AnnaBridge 172:7d866c31b3c5 675 __IO uint32_t CMP1; /*!< AD Conversion result comparing register1 */
AnnaBridge 172:7d866c31b3c5 676 } TSB_AD_TypeDef;
AnnaBridge 172:7d866c31b3c5 677
AnnaBridge 172:7d866c31b3c5 678 /**
AnnaBridge 172:7d866c31b3c5 679 * @brief FC
AnnaBridge 172:7d866c31b3c5 680 */
AnnaBridge 172:7d866c31b3c5 681 typedef struct {
AnnaBridge 172:7d866c31b3c5 682 uint32_t RESERVED0[4];
AnnaBridge 172:7d866c31b3c5 683 __IO uint32_t SECBIT; /*!< FC Security Bit Register */
AnnaBridge 172:7d866c31b3c5 684 uint32_t RESERVED1[3];
AnnaBridge 172:7d866c31b3c5 685 __I uint32_t SR; /*!< FC Flash Status Register */
AnnaBridge 172:7d866c31b3c5 686 uint32_t RESERVED2[3];
AnnaBridge 172:7d866c31b3c5 687 __I uint32_t PSRA; /*!< FC Protect status register */
AnnaBridge 172:7d866c31b3c5 688 uint32_t RESERVED3;
AnnaBridge 172:7d866c31b3c5 689 __IO uint32_t PMRA; /*!< FC Protect Mask register */
AnnaBridge 172:7d866c31b3c5 690 } TSB_FC_TypeDef;
AnnaBridge 172:7d866c31b3c5 691
AnnaBridge 172:7d866c31b3c5 692
AnnaBridge 172:7d866c31b3c5 693 /* Memory map */
AnnaBridge 172:7d866c31b3c5 694 #define FLASH_BASE (0x00000000UL)
AnnaBridge 172:7d866c31b3c5 695 #define RAM_BASE (0x20000000UL)
AnnaBridge 172:7d866c31b3c5 696 #define PERI_BASE (0x40000000UL)
AnnaBridge 172:7d866c31b3c5 697
AnnaBridge 172:7d866c31b3c5 698
AnnaBridge 172:7d866c31b3c5 699 #define TSB_UDFS_BASE (PERI_BASE + 0x0008000UL)
AnnaBridge 172:7d866c31b3c5 700 #define TSB_UDFS2_BASE (PERI_BASE + 0x0008200UL)
AnnaBridge 172:7d866c31b3c5 701 #define TSB_INTIFAO_BASE (PERI_BASE + 0x0038000UL)
AnnaBridge 172:7d866c31b3c5 702 #define TSB_AOREG_BASE (PERI_BASE + 0x0038400UL)
AnnaBridge 172:7d866c31b3c5 703 #define TSB_I2CS_BASE (PERI_BASE + 0x0038800UL)
AnnaBridge 172:7d866c31b3c5 704 #define TSB_DMA_BASE (PERI_BASE + 0x004C000UL)
AnnaBridge 172:7d866c31b3c5 705 #define TSB_TD0_BASE (PERI_BASE + 0x0058000UL)
AnnaBridge 172:7d866c31b3c5 706 #define TSB_TD_BASE (PERI_BASE + 0x0058040UL)
AnnaBridge 172:7d866c31b3c5 707 #define TSB_TD1_BASE (PERI_BASE + 0x005802CUL)
AnnaBridge 172:7d866c31b3c5 708 #define TSB_T16A0_BASE (PERI_BASE + 0x008D000UL)
AnnaBridge 172:7d866c31b3c5 709 #define TSB_T16A1_BASE (PERI_BASE + 0x008E000UL)
AnnaBridge 172:7d866c31b3c5 710 #define TSB_TSPI0_BASE (PERI_BASE + 0x0098000UL)
AnnaBridge 172:7d866c31b3c5 711 #define TSB_I2C0_BASE (PERI_BASE + 0x00A0000UL)
AnnaBridge 172:7d866c31b3c5 712 #define TSB_I2C1_BASE (PERI_BASE + 0x00A1000UL)
AnnaBridge 172:7d866c31b3c5 713 #define TSB_PA_BASE (PERI_BASE + 0x00C0000UL)
AnnaBridge 172:7d866c31b3c5 714 #define TSB_PB_BASE (PERI_BASE + 0x00C0100UL)
AnnaBridge 172:7d866c31b3c5 715 #define TSB_PC_BASE (PERI_BASE + 0x00C0200UL)
AnnaBridge 172:7d866c31b3c5 716 #define TSB_PD_BASE (PERI_BASE + 0x00C0300UL)
AnnaBridge 172:7d866c31b3c5 717 #define TSB_PE_BASE (PERI_BASE + 0x00C0400UL)
AnnaBridge 172:7d866c31b3c5 718 #define TSB_PF_BASE (PERI_BASE + 0x00C0500UL)
AnnaBridge 172:7d866c31b3c5 719 #define TSB_PG_BASE (PERI_BASE + 0x00C0600UL)
AnnaBridge 172:7d866c31b3c5 720 #define TSB_PH_BASE (PERI_BASE + 0x00C0700UL)
AnnaBridge 172:7d866c31b3c5 721 #define TSB_PJ_BASE (PERI_BASE + 0x00C0800UL)
AnnaBridge 172:7d866c31b3c5 722 #define TSB_TB0_BASE (PERI_BASE + 0x00C4000UL)
AnnaBridge 172:7d866c31b3c5 723 #define TSB_TB1_BASE (PERI_BASE + 0x00C4100UL)
AnnaBridge 172:7d866c31b3c5 724 #define TSB_TB2_BASE (PERI_BASE + 0x00C4200UL)
AnnaBridge 172:7d866c31b3c5 725 #define TSB_TB3_BASE (PERI_BASE + 0x00C4300UL)
AnnaBridge 172:7d866c31b3c5 726 #define TSB_TB4_BASE (PERI_BASE + 0x00C4400UL)
AnnaBridge 172:7d866c31b3c5 727 #define TSB_TB5_BASE (PERI_BASE + 0x00C4500UL)
AnnaBridge 172:7d866c31b3c5 728 #define TSB_TB6_BASE (PERI_BASE + 0x00C4600UL)
AnnaBridge 172:7d866c31b3c5 729 #define TSB_TB7_BASE (PERI_BASE + 0x00C4700UL)
AnnaBridge 172:7d866c31b3c5 730 #define TSB_SC0_BASE (PERI_BASE + 0x00E1000UL)
AnnaBridge 172:7d866c31b3c5 731 #define TSB_SC1_BASE (PERI_BASE + 0x00E1100UL)
AnnaBridge 172:7d866c31b3c5 732 #define TSB_WD_BASE (PERI_BASE + 0x00F2000UL)
AnnaBridge 172:7d866c31b3c5 733 #define TSB_CG_BASE (PERI_BASE + 0x00F3000UL)
AnnaBridge 172:7d866c31b3c5 734 #define TSB_LVD_BASE (PERI_BASE + 0x00F4000UL)
AnnaBridge 172:7d866c31b3c5 735 #define TSB_INTIFSD_BASE (PERI_BASE + 0x00F4E00UL)
AnnaBridge 172:7d866c31b3c5 736 #define TSB_AD_BASE (PERI_BASE + 0x00FC000UL)
AnnaBridge 172:7d866c31b3c5 737 #define TSB_FC_BASE (PERI_BASE + 0x1FFF000UL)
AnnaBridge 172:7d866c31b3c5 738
AnnaBridge 172:7d866c31b3c5 739
AnnaBridge 172:7d866c31b3c5 740 /* Peripheral declaration */
AnnaBridge 172:7d866c31b3c5 741 #define TSB_UDFS (( TSB_UDFS_TypeDef *) TSB_UDFS_BASE)
AnnaBridge 172:7d866c31b3c5 742 #define TSB_UDFS2 (( TSB_UDFS2_TypeDef *) TSB_UDFS2_BASE)
AnnaBridge 172:7d866c31b3c5 743 #define TSB_INTIFAO ((TSB_INTIFAO_TypeDef *)TSB_INTIFAO_BASE)
AnnaBridge 172:7d866c31b3c5 744 #define TSB_AOREG (( TSB_AOREG_TypeDef *) TSB_AOREG_BASE)
AnnaBridge 172:7d866c31b3c5 745 #define TSB_I2CS (( TSB_I2CS_TypeDef *) TSB_I2CS_BASE)
AnnaBridge 172:7d866c31b3c5 746 #define TSB_DMA (( TSB_DMA_TypeDef *) TSB_DMA_BASE)
AnnaBridge 172:7d866c31b3c5 747 #define TSB_TD0 (( TSB_TD0_TypeDef *) TSB_TD0_BASE)
AnnaBridge 172:7d866c31b3c5 748 #define TSB_TD (( TSB_TD_TypeDef *) TSB_TD_BASE)
AnnaBridge 172:7d866c31b3c5 749 #define TSB_TD1 (( TSB_TD1_TypeDef *) TSB_TD1_BASE)
AnnaBridge 172:7d866c31b3c5 750 #define TSB_T16A0 (( TSB_T16A_TypeDef *) TSB_T16A0_BASE)
AnnaBridge 172:7d866c31b3c5 751 #define TSB_T16A1 (( TSB_T16A_TypeDef *) TSB_T16A1_BASE)
AnnaBridge 172:7d866c31b3c5 752 #define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE)
AnnaBridge 172:7d866c31b3c5 753 #define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE)
AnnaBridge 172:7d866c31b3c5 754 #define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE)
AnnaBridge 172:7d866c31b3c5 755 #define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE)
AnnaBridge 172:7d866c31b3c5 756 #define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE)
AnnaBridge 172:7d866c31b3c5 757 #define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE)
AnnaBridge 172:7d866c31b3c5 758 #define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE)
AnnaBridge 172:7d866c31b3c5 759 #define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE)
AnnaBridge 172:7d866c31b3c5 760 #define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE)
AnnaBridge 172:7d866c31b3c5 761 #define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE)
AnnaBridge 172:7d866c31b3c5 762 #define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE)
AnnaBridge 172:7d866c31b3c5 763 #define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE)
AnnaBridge 172:7d866c31b3c5 764 #define TSB_TB0 (( TSB_TB_TypeDef *) TSB_TB0_BASE)
AnnaBridge 172:7d866c31b3c5 765 #define TSB_TB1 (( TSB_TB_TypeDef *) TSB_TB1_BASE)
AnnaBridge 172:7d866c31b3c5 766 #define TSB_TB2 (( TSB_TB_TypeDef *) TSB_TB2_BASE)
AnnaBridge 172:7d866c31b3c5 767 #define TSB_TB3 (( TSB_TB_TypeDef *) TSB_TB3_BASE)
AnnaBridge 172:7d866c31b3c5 768 #define TSB_TB4 (( TSB_TB_TypeDef *) TSB_TB4_BASE)
AnnaBridge 172:7d866c31b3c5 769 #define TSB_TB5 (( TSB_TB_TypeDef *) TSB_TB5_BASE)
AnnaBridge 172:7d866c31b3c5 770 #define TSB_TB6 (( TSB_TB_TypeDef *) TSB_TB6_BASE)
AnnaBridge 172:7d866c31b3c5 771 #define TSB_TB7 (( TSB_TB_TypeDef *) TSB_TB7_BASE)
AnnaBridge 172:7d866c31b3c5 772 #define TSB_SC0 (( TSB_SC_TypeDef *) TSB_SC0_BASE)
AnnaBridge 172:7d866c31b3c5 773 #define TSB_SC1 (( TSB_SC_TypeDef *) TSB_SC1_BASE)
AnnaBridge 172:7d866c31b3c5 774 #define TSB_WD (( TSB_WD_TypeDef *) TSB_WD_BASE)
AnnaBridge 172:7d866c31b3c5 775 #define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE)
AnnaBridge 172:7d866c31b3c5 776 #define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE)
AnnaBridge 172:7d866c31b3c5 777 #define TSB_INTIFSD ((TSB_INTIFSD_TypeDef *)TSB_INTIFSD_BASE)
AnnaBridge 172:7d866c31b3c5 778 #define TSB_AD (( TSB_AD_TypeDef *) TSB_AD_BASE)
AnnaBridge 172:7d866c31b3c5 779 #define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE)
AnnaBridge 172:7d866c31b3c5 780
AnnaBridge 172:7d866c31b3c5 781
AnnaBridge 172:7d866c31b3c5 782 /* Bit-Band for Device Specific Peripheral Registers */
AnnaBridge 172:7d866c31b3c5 783 #define BITBAND_OFFSET (0x02000000UL)
AnnaBridge 172:7d866c31b3c5 784 #define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET)
AnnaBridge 172:7d866c31b3c5 785 #define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2))
AnnaBridge 172:7d866c31b3c5 786
AnnaBridge 172:7d866c31b3c5 787
AnnaBridge 172:7d866c31b3c5 788
AnnaBridge 172:7d866c31b3c5 789 /* UDC2 AHB Bridge */
AnnaBridge 172:7d866c31b3c5 790 #define TSB_UDFS_INTSTS_INT_SETUP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,0)))
AnnaBridge 172:7d866c31b3c5 791 #define TSB_UDFS_INTSTS_INT_STATUS_NAK (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,1)))
AnnaBridge 172:7d866c31b3c5 792 #define TSB_UDFS_INTSTS_INT_STATUS (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,2)))
AnnaBridge 172:7d866c31b3c5 793 #define TSB_UDFS_INTSTS_INT_RX_ZERO (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,3)))
AnnaBridge 172:7d866c31b3c5 794 #define TSB_UDFS_INTSTS_INT_SOF (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,4)))
AnnaBridge 172:7d866c31b3c5 795 #define TSB_UDFS_INTSTS_INT_EP0 (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,5)))
AnnaBridge 172:7d866c31b3c5 796 #define TSB_UDFS_INTSTS_INT_EP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,6)))
AnnaBridge 172:7d866c31b3c5 797 #define TSB_UDFS_INTSTS_INT_NAK (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,7)))
AnnaBridge 172:7d866c31b3c5 798 #define TSB_UDFS_INTSTS_INT_SUSPEND_RESUME (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,8)))
AnnaBridge 172:7d866c31b3c5 799 #define TSB_UDFS_INTSTS_INT_USB_RESET (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,9)))
AnnaBridge 172:7d866c31b3c5 800 #define TSB_UDFS_INTSTS_INT_USB_RESET_END (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,10)))
AnnaBridge 172:7d866c31b3c5 801 #define TSB_UDFS_INTSTS_INT_MW_SET_ADD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,17)))
AnnaBridge 172:7d866c31b3c5 802 #define TSB_UDFS_INTSTS_INT_MW_END_ADD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,18)))
AnnaBridge 172:7d866c31b3c5 803 #define TSB_UDFS_INTSTS_INT_MW_TIMEOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,19)))
AnnaBridge 172:7d866c31b3c5 804 #define TSB_UDFS_INTSTS_INT_MW_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,20)))
AnnaBridge 172:7d866c31b3c5 805 #define TSB_UDFS_INTSTS_INT_MR_END_ADD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,21)))
AnnaBridge 172:7d866c31b3c5 806 #define TSB_UDFS_INTSTS_INT_MR_EP_DSET (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,22)))
AnnaBridge 172:7d866c31b3c5 807 #define TSB_UDFS_INTSTS_INT_MR_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,23)))
AnnaBridge 172:7d866c31b3c5 808 #define TSB_UDFS_INTSTS_INT_UDC2_REGINT__RD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,24)))
AnnaBridge 172:7d866c31b3c5 809 #define TSB_UDFS_INTSTS_INT_DMAC_REG_RD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,25)))
AnnaBridge 172:7d866c31b3c5 810 #define TSB_UDFS_INTSTS_INT_POWERDETECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,28)))
AnnaBridge 172:7d866c31b3c5 811 #define TSB_UDFS_INTSTS_INT_MW_RERROR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,29)))
AnnaBridge 172:7d866c31b3c5 812 #define TSB_UDFS_INTENB_SUSPEND_RESUME_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,8)))
AnnaBridge 172:7d866c31b3c5 813 #define TSB_UDFS_INTENB_RESET_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,9)))
AnnaBridge 172:7d866c31b3c5 814 #define TSB_UDFS_INTENB_RESET_END_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,10)))
AnnaBridge 172:7d866c31b3c5 815 #define TSB_UDFS_INTENB_MW_SET_ADD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,17)))
AnnaBridge 172:7d866c31b3c5 816 #define TSB_UDFS_INTENB_MW_END_ADD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,18)))
AnnaBridge 172:7d866c31b3c5 817 #define TSB_UDFS_INTENB_MW_TIMEOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,19)))
AnnaBridge 172:7d866c31b3c5 818 #define TSB_UDFS_INTENB_MW_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,20)))
AnnaBridge 172:7d866c31b3c5 819 #define TSB_UDFS_INTENB_MR_END_ADD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,21)))
AnnaBridge 172:7d866c31b3c5 820 #define TSB_UDFS_INTENB_MR_EP_DSET_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,22)))
AnnaBridge 172:7d866c31b3c5 821 #define TSB_UDFS_INTENB_MR_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,23)))
AnnaBridge 172:7d866c31b3c5 822 #define TSB_UDFS_INTENB_UDC2_REG_RD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,24)))
AnnaBridge 172:7d866c31b3c5 823 #define TSB_UDFS_INTENB_DMAC_REG_RD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,25)))
AnnaBridge 172:7d866c31b3c5 824 #define TSB_UDFS_INTENB_POWER_DETECT_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,28)))
AnnaBridge 172:7d866c31b3c5 825 #define TSB_UDFS_INTENB_MW_RERROR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,29)))
AnnaBridge 172:7d866c31b3c5 826 #define TSB_UDFS_MWTOUT_TIMEOUT_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->MWTOUT,0)))
AnnaBridge 172:7d866c31b3c5 827 #define TSB_UDFS_C2STSET_TX0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->C2STSET,0)))
AnnaBridge 172:7d866c31b3c5 828 #define TSB_UDFS_C2STSET_EOPB_ENABLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->C2STSET,4)))
AnnaBridge 172:7d866c31b3c5 829 #define TSB_UDFS_DMACRDREQ_DMARDCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->DMACRDREQ,30)))
AnnaBridge 172:7d866c31b3c5 830 #define TSB_UDFS_DMACRDREQ_DMARDREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->DMACRDREQ,31)))
AnnaBridge 172:7d866c31b3c5 831 #define TSB_UDFS_UDC2RDREQ_UDC2RDCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->UDC2RDREQ,30)))
AnnaBridge 172:7d866c31b3c5 832 #define TSB_UDFS_UDC2RDREQ_UDC2RDREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->UDC2RDREQ,31)))
AnnaBridge 172:7d866c31b3c5 833 #define TSB_UDFS_ARBTSET_ABTMOD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->ARBTSET,28)))
AnnaBridge 172:7d866c31b3c5 834 #define TSB_UDFS_ARBTSET_ABT_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->ARBTSET,31)))
AnnaBridge 172:7d866c31b3c5 835 #define TSB_UDFS_PWCTL_USB_RESET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,0)))
AnnaBridge 172:7d866c31b3c5 836 #define TSB_UDFS_PWCTL_PW_RESETB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,1)))
AnnaBridge 172:7d866c31b3c5 837 #define TSB_UDFS_PWCTL_PW_DETECT (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,2)))
AnnaBridge 172:7d866c31b3c5 838 #define TSB_UDFS_PWCTL_PHY_SUSPEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,3)))
AnnaBridge 172:7d866c31b3c5 839 #define TSB_UDFS_PWCTL_SUSPEND_X (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,4)))
AnnaBridge 172:7d866c31b3c5 840 #define TSB_UDFS_PWCTL_PHY_RESETB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,5)))
AnnaBridge 172:7d866c31b3c5 841 #define TSB_UDFS_PWCTL_PHY_REMOTE_WKUP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,6)))
AnnaBridge 172:7d866c31b3c5 842 #define TSB_UDFS_PWCTL_WAKEUP_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,7)))
AnnaBridge 172:7d866c31b3c5 843 #define TSB_UDFS_MSTSTS_MWEPDSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,0)))
AnnaBridge 172:7d866c31b3c5 844 #define TSB_UDFS_MSTSTS_MREPDSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,1)))
AnnaBridge 172:7d866c31b3c5 845 #define TSB_UDFS_MSTSTS_MWBFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,2)))
AnnaBridge 172:7d866c31b3c5 846 #define TSB_UDFS_MSTSTS_MRBFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,3)))
AnnaBridge 172:7d866c31b3c5 847 #define TSB_UDFS_MSTSTS_MREPEMPTY (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,4)))
AnnaBridge 172:7d866c31b3c5 848
AnnaBridge 172:7d866c31b3c5 849
AnnaBridge 172:7d866c31b3c5 850 /* UDC2(USB -Spec2.0 Device contoller) */
AnnaBridge 172:7d866c31b3c5 851 #define TSB_UDFS2_ADR_SUSPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,11)))
AnnaBridge 172:7d866c31b3c5 852 #define TSB_UDFS2_ADR_EP_BI_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,14)))
AnnaBridge 172:7d866c31b3c5 853 #define TSB_UDFS2_ADR_STAGE_ERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,15)))
AnnaBridge 172:7d866c31b3c5 854 #define TSB_UDFS2_FRM_CREATE_SOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->FRM,15)))
AnnaBridge 172:7d866c31b3c5 855 #define TSB_UDFS2_CMD_INT_TOGGLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->CMD,15)))
AnnaBridge 172:7d866c31b3c5 856 #define TSB_UDFS2_BRQ_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->BRQ,7)))
AnnaBridge 172:7d866c31b3c5 857 #define TSB_UDFS2_INT_I_SETUP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,0)))
AnnaBridge 172:7d866c31b3c5 858 #define TSB_UDFS2_INT_I_STATUS_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,1)))
AnnaBridge 172:7d866c31b3c5 859 #define TSB_UDFS2_INT_I_STATUS (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,2)))
AnnaBridge 172:7d866c31b3c5 860 #define TSB_UDFS2_INT_I_RX_DATA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,3)))
AnnaBridge 172:7d866c31b3c5 861 #define TSB_UDFS2_INT_I_SOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,4)))
AnnaBridge 172:7d866c31b3c5 862 #define TSB_UDFS2_INT_I_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,5)))
AnnaBridge 172:7d866c31b3c5 863 #define TSB_UDFS2_INT_I_EP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,6)))
AnnaBridge 172:7d866c31b3c5 864 #define TSB_UDFS2_INT_I_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,7)))
AnnaBridge 172:7d866c31b3c5 865 #define TSB_UDFS2_INT_M_SETUP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,8)))
AnnaBridge 172:7d866c31b3c5 866 #define TSB_UDFS2_INT_M_STATUS_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,9)))
AnnaBridge 172:7d866c31b3c5 867 #define TSB_UDFS2_INT_M_STATUS (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,10)))
AnnaBridge 172:7d866c31b3c5 868 #define TSB_UDFS2_INT_M_RX_DATA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,11)))
AnnaBridge 172:7d866c31b3c5 869 #define TSB_UDFS2_INT_M_SOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,12)))
AnnaBridge 172:7d866c31b3c5 870 #define TSB_UDFS2_INT_M_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,13)))
AnnaBridge 172:7d866c31b3c5 871 #define TSB_UDFS2_INT_M_EP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,14)))
AnnaBridge 172:7d866c31b3c5 872 #define TSB_UDFS2_INT_M_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,15)))
AnnaBridge 172:7d866c31b3c5 873 #define TSB_UDFS2_INTEP_I_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,1)))
AnnaBridge 172:7d866c31b3c5 874 #define TSB_UDFS2_INTEP_I_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,2)))
AnnaBridge 172:7d866c31b3c5 875 #define TSB_UDFS2_INTEP_I_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,3)))
AnnaBridge 172:7d866c31b3c5 876 #define TSB_UDFS2_INTEP_I_EP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,4)))
AnnaBridge 172:7d866c31b3c5 877 #define TSB_UDFS2_INTEPMSK_M_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,0)))
AnnaBridge 172:7d866c31b3c5 878 #define TSB_UDFS2_INTEPMSK_M_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,1)))
AnnaBridge 172:7d866c31b3c5 879 #define TSB_UDFS2_INTEPMSK_M_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,2)))
AnnaBridge 172:7d866c31b3c5 880 #define TSB_UDFS2_INTEPMSK_M_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,3)))
AnnaBridge 172:7d866c31b3c5 881 #define TSB_UDFS2_INTEPMSK_M_EP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,4)))
AnnaBridge 172:7d866c31b3c5 882 #define TSB_UDFS2_INTRX0_RX_D0_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,0)))
AnnaBridge 172:7d866c31b3c5 883 #define TSB_UDFS2_INTRX0_RX_D0_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,1)))
AnnaBridge 172:7d866c31b3c5 884 #define TSB_UDFS2_INTRX0_RX_D0_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,2)))
AnnaBridge 172:7d866c31b3c5 885 #define TSB_UDFS2_INTRX0_RX_D0_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,3)))
AnnaBridge 172:7d866c31b3c5 886 #define TSB_UDFS2_INTRX0_RX_D0_EP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,4)))
AnnaBridge 172:7d866c31b3c5 887 #define TSB_UDFS2_EP0MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0MSZ,12)))
AnnaBridge 172:7d866c31b3c5 888 #define TSB_UDFS2_EP0MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0MSZ,15)))
AnnaBridge 172:7d866c31b3c5 889 #define TSB_UDFS2_EP0STS_EP0_MASK (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0STS,15)))
AnnaBridge 172:7d866c31b3c5 890 #define TSB_UDFS2_EP1MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1MSZ,12)))
AnnaBridge 172:7d866c31b3c5 891 #define TSB_UDFS2_EP1MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1MSZ,15)))
AnnaBridge 172:7d866c31b3c5 892 #define TSB_UDFS2_EP1STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,7)))
AnnaBridge 172:7d866c31b3c5 893 #define TSB_UDFS2_EP1STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,8)))
AnnaBridge 172:7d866c31b3c5 894 #define TSB_UDFS2_EP1STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,14)))
AnnaBridge 172:7d866c31b3c5 895 #define TSB_UDFS2_EP1STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,15)))
AnnaBridge 172:7d866c31b3c5 896 #define TSB_UDFS2_EP2MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2MSZ,12)))
AnnaBridge 172:7d866c31b3c5 897 #define TSB_UDFS2_EP2MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2MSZ,15)))
AnnaBridge 172:7d866c31b3c5 898 #define TSB_UDFS2_EP2STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,7)))
AnnaBridge 172:7d866c31b3c5 899 #define TSB_UDFS2_EP2STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,8)))
AnnaBridge 172:7d866c31b3c5 900 #define TSB_UDFS2_EP2STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,14)))
AnnaBridge 172:7d866c31b3c5 901 #define TSB_UDFS2_EP2STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,15)))
AnnaBridge 172:7d866c31b3c5 902 #define TSB_UDFS2_EP3MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3MSZ,12)))
AnnaBridge 172:7d866c31b3c5 903 #define TSB_UDFS2_EP3MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3MSZ,15)))
AnnaBridge 172:7d866c31b3c5 904 #define TSB_UDFS2_EP3STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,7)))
AnnaBridge 172:7d866c31b3c5 905 #define TSB_UDFS2_EP3STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,8)))
AnnaBridge 172:7d866c31b3c5 906 #define TSB_UDFS2_EP3STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,14)))
AnnaBridge 172:7d866c31b3c5 907 #define TSB_UDFS2_EP3STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,15)))
AnnaBridge 172:7d866c31b3c5 908 #define TSB_UDFS2_EP4MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4MSZ,12)))
AnnaBridge 172:7d866c31b3c5 909 #define TSB_UDFS2_EP4MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4MSZ,15)))
AnnaBridge 172:7d866c31b3c5 910 #define TSB_UDFS2_EP4STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,7)))
AnnaBridge 172:7d866c31b3c5 911 #define TSB_UDFS2_EP4STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,8)))
AnnaBridge 172:7d866c31b3c5 912 #define TSB_UDFS2_EP4STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,14)))
AnnaBridge 172:7d866c31b3c5 913 #define TSB_UDFS2_EP4STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,15)))
AnnaBridge 172:7d866c31b3c5 914 #define TSB_UDFS2_INTNAK_I_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,1)))
AnnaBridge 172:7d866c31b3c5 915 #define TSB_UDFS2_INTNAK_I_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,2)))
AnnaBridge 172:7d866c31b3c5 916 #define TSB_UDFS2_INTNAK_I_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,3)))
AnnaBridge 172:7d866c31b3c5 917 #define TSB_UDFS2_INTNAKMSK_M_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,1)))
AnnaBridge 172:7d866c31b3c5 918 #define TSB_UDFS2_INTNAKMSK_M_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,2)))
AnnaBridge 172:7d866c31b3c5 919 #define TSB_UDFS2_INTNAKMSK_M_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,3)))
AnnaBridge 172:7d866c31b3c5 920
AnnaBridge 172:7d866c31b3c5 921
AnnaBridge 172:7d866c31b3c5 922 /* AO Area register1 */
AnnaBridge 172:7d866c31b3c5 923 #define TSB_INTIFAO_STOP2INT_032_INT032EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,0)))
AnnaBridge 172:7d866c31b3c5 924 #define TSB_INTIFAO_STOP2INT_032_INT032PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,4)))
AnnaBridge 172:7d866c31b3c5 925 #define TSB_INTIFAO_STOP2INT_032_INT032NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,5)))
AnnaBridge 172:7d866c31b3c5 926 #define TSB_INTIFAO_STOP2INT_032_INT032PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,6)))
AnnaBridge 172:7d866c31b3c5 927 #define TSB_INTIFAO_STOP2INT_032_INT032NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,7)))
AnnaBridge 172:7d866c31b3c5 928 #define TSB_INTIFAO_STOP2INT_033_INT033EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,0)))
AnnaBridge 172:7d866c31b3c5 929 #define TSB_INTIFAO_STOP2INT_033_INT033PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,4)))
AnnaBridge 172:7d866c31b3c5 930 #define TSB_INTIFAO_STOP2INT_033_INT033NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,5)))
AnnaBridge 172:7d866c31b3c5 931 #define TSB_INTIFAO_STOP2INT_033_INT033PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,6)))
AnnaBridge 172:7d866c31b3c5 932 #define TSB_INTIFAO_STOP2INT_033_INT033NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,7)))
AnnaBridge 172:7d866c31b3c5 933 #define TSB_INTIFAO_STOP2INT_034_INT034EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,0)))
AnnaBridge 172:7d866c31b3c5 934 #define TSB_INTIFAO_STOP2INT_034_INT034PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,4)))
AnnaBridge 172:7d866c31b3c5 935 #define TSB_INTIFAO_STOP2INT_034_INT034NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,5)))
AnnaBridge 172:7d866c31b3c5 936 #define TSB_INTIFAO_STOP2INT_034_INT034PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,6)))
AnnaBridge 172:7d866c31b3c5 937 #define TSB_INTIFAO_STOP2INT_034_INT034NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,7)))
AnnaBridge 172:7d866c31b3c5 938 #define TSB_INTIFAO_STOP2INT_035_INT035EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,0)))
AnnaBridge 172:7d866c31b3c5 939 #define TSB_INTIFAO_STOP2INT_035_INT035PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,4)))
AnnaBridge 172:7d866c31b3c5 940 #define TSB_INTIFAO_STOP2INT_035_INT035NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,5)))
AnnaBridge 172:7d866c31b3c5 941 #define TSB_INTIFAO_STOP2INT_035_INT035PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,6)))
AnnaBridge 172:7d866c31b3c5 942 #define TSB_INTIFAO_STOP2INT_035_INT035NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,7)))
AnnaBridge 172:7d866c31b3c5 943 #define TSB_INTIFAO_STOP2INT_036_INT036EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,0)))
AnnaBridge 172:7d866c31b3c5 944 #define TSB_INTIFAO_STOP2INT_036_INT036PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,4)))
AnnaBridge 172:7d866c31b3c5 945 #define TSB_INTIFAO_STOP2INT_036_INT036NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,5)))
AnnaBridge 172:7d866c31b3c5 946 #define TSB_INTIFAO_STOP2INT_036_INT036PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,6)))
AnnaBridge 172:7d866c31b3c5 947 #define TSB_INTIFAO_STOP2INT_036_INT036NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,7)))
AnnaBridge 172:7d866c31b3c5 948 #define TSB_INTIFAO_STOP2INT_037_INT037EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,0)))
AnnaBridge 172:7d866c31b3c5 949 #define TSB_INTIFAO_STOP2INT_037_INT037PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,4)))
AnnaBridge 172:7d866c31b3c5 950 #define TSB_INTIFAO_STOP2INT_037_INT037NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,5)))
AnnaBridge 172:7d866c31b3c5 951 #define TSB_INTIFAO_STOP2INT_037_INT037PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,6)))
AnnaBridge 172:7d866c31b3c5 952 #define TSB_INTIFAO_STOP2INT_037_INT037NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,7)))
AnnaBridge 172:7d866c31b3c5 953 #define TSB_INTIFAO_STOP2INT_038_INT038EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,0)))
AnnaBridge 172:7d866c31b3c5 954 #define TSB_INTIFAO_STOP2INT_038_INT038PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,4)))
AnnaBridge 172:7d866c31b3c5 955 #define TSB_INTIFAO_STOP2INT_038_INT038NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,5)))
AnnaBridge 172:7d866c31b3c5 956 #define TSB_INTIFAO_STOP2INT_038_INT038PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,6)))
AnnaBridge 172:7d866c31b3c5 957 #define TSB_INTIFAO_STOP2INT_038_INT038NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,7)))
AnnaBridge 172:7d866c31b3c5 958 #define TSB_INTIFAO_STOP2INT_039_INT039EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,0)))
AnnaBridge 172:7d866c31b3c5 959 #define TSB_INTIFAO_STOP2INT_039_INT039PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,4)))
AnnaBridge 172:7d866c31b3c5 960 #define TSB_INTIFAO_STOP2INT_039_INT039NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,5)))
AnnaBridge 172:7d866c31b3c5 961 #define TSB_INTIFAO_STOP2INT_039_INT039PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,6)))
AnnaBridge 172:7d866c31b3c5 962 #define TSB_INTIFAO_STOP2INT_039_INT039NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,7)))
AnnaBridge 172:7d866c31b3c5 963
AnnaBridge 172:7d866c31b3c5 964
AnnaBridge 172:7d866c31b3c5 965 /* AO Area register2 */
AnnaBridge 172:7d866c31b3c5 966 #define TSB_AOREG_RSTFLG_PORF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,0)))
AnnaBridge 172:7d866c31b3c5 967 #define TSB_AOREG_RSTFLG_PINRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,3)))
AnnaBridge 172:7d866c31b3c5 968 #define TSB_AOREG_RSTFLG_LVDRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,5)))
AnnaBridge 172:7d866c31b3c5 969 #define TSB_AOREG_RSTFLG1_SYSRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG1,0)))
AnnaBridge 172:7d866c31b3c5 970 #define TSB_AOREG_RSTFLG1_WDTRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG1,2)))
AnnaBridge 172:7d866c31b3c5 971
AnnaBridge 172:7d866c31b3c5 972
AnnaBridge 172:7d866c31b3c5 973 /* I2C Wakeup I/F register */
AnnaBridge 172:7d866c31b3c5 974 #define TSB_I2CS_WUPCR1_INTEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,0)))
AnnaBridge 172:7d866c31b3c5 975 #define TSB_I2CS_WUPCR1_GC (*((uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,1)))
AnnaBridge 172:7d866c31b3c5 976 #define TSB_I2CS_WUPCR1_RW (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,3)))
AnnaBridge 172:7d866c31b3c5 977 #define TSB_I2CS_WUPCR1_I2RES (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,4)))
AnnaBridge 172:7d866c31b3c5 978 #define TSB_I2CS_WUPCR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,5)))
AnnaBridge 172:7d866c31b3c5 979 #define TSB_I2CS_WUPCR1_SGCDI (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,6)))
AnnaBridge 172:7d866c31b3c5 980 #define TSB_I2CS_WUPCR1_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,7)))
AnnaBridge 172:7d866c31b3c5 981 #define TSB_I2CS_WUPCR3_WUPSA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR3,0)))
AnnaBridge 172:7d866c31b3c5 982 #define TSB_I2CS_WUPSL_WUPSA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPSL,1)))
AnnaBridge 172:7d866c31b3c5 983 #define TSB_I2CS_WUPSL_WUPSA2 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPSL,2)))
AnnaBridge 172:7d866c31b3c5 984
AnnaBridge 172:7d866c31b3c5 985
AnnaBridge 172:7d866c31b3c5 986 /* DMA Controller */
AnnaBridge 172:7d866c31b3c5 987 #define TSB_DMA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMA->STATUS,0)))
AnnaBridge 172:7d866c31b3c5 988 #define TSB_DMA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMA->CFG,0)))
AnnaBridge 172:7d866c31b3c5 989 #define TSB_DMA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMA->ERRCLR,0)))
AnnaBridge 172:7d866c31b3c5 990
AnnaBridge 172:7d866c31b3c5 991
AnnaBridge 172:7d866c31b3c5 992 /* Timer D (Unit0) */
AnnaBridge 172:7d866c31b3c5 993 #define TSB_TD0_RUN_TDRUN (*((__O uint32_t *)BITBAND_PERI(&TSB_TD0->RUN,0)))
AnnaBridge 172:7d866c31b3c5 994 #define TSB_TD0_CR_TDRDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,2)))
AnnaBridge 172:7d866c31b3c5 995 #define TSB_TD0_CR_TDMDPT00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,4)))
AnnaBridge 172:7d866c31b3c5 996 #define TSB_TD0_CR_TDMDPT01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,8)))
AnnaBridge 172:7d866c31b3c5 997 #define TSB_TD0_MOD_TDCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,4)))
AnnaBridge 172:7d866c31b3c5 998 #define TSB_TD0_MOD_TDIV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,6)))
AnnaBridge 172:7d866c31b3c5 999 #define TSB_TD0_MOD_TDIV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,7)))
AnnaBridge 172:7d866c31b3c5 1000 #define TSB_TD0_DMA_DMAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1001 #define TSB_TD0_RG2_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->RG2,31)))
AnnaBridge 172:7d866c31b3c5 1002 #define TSB_TD0_RG4_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->RG4,31)))
AnnaBridge 172:7d866c31b3c5 1003 #define TSB_TD0_HSWB0_OUTV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->HSWB0,2)))
AnnaBridge 172:7d866c31b3c5 1004 #define TSB_TD0_HSWB1_OUTV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->HSWB1,2)))
AnnaBridge 172:7d866c31b3c5 1005 #define TSB_TD0_CP2_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->CP2,31)))
AnnaBridge 172:7d866c31b3c5 1006 #define TSB_TD0_CP4_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->CP4,31)))
AnnaBridge 172:7d866c31b3c5 1007 #define TSB_TD0_HSW0_OUTV0 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->HSW0,2)))
AnnaBridge 172:7d866c31b3c5 1008 #define TSB_TD0_HSW1_OUTV1 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->HSW1,2)))
AnnaBridge 172:7d866c31b3c5 1009
AnnaBridge 172:7d866c31b3c5 1010
AnnaBridge 172:7d866c31b3c5 1011 /* Timer D common */
AnnaBridge 172:7d866c31b3c5 1012 #define TSB_TD_BCR_TDSFT00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,0)))
AnnaBridge 172:7d866c31b3c5 1013 #define TSB_TD_BCR_TDSFT01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,1)))
AnnaBridge 172:7d866c31b3c5 1014 #define TSB_TD_BCR_TDSFT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,2)))
AnnaBridge 172:7d866c31b3c5 1015 #define TSB_TD_BCR_TDSFT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,3)))
AnnaBridge 172:7d866c31b3c5 1016 #define TSB_TD_BCR_PHSCHG (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,4)))
AnnaBridge 172:7d866c31b3c5 1017 #define TSB_TD_EN_TDHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,5)))
AnnaBridge 172:7d866c31b3c5 1018 #define TSB_TD_EN_TDEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,6)))
AnnaBridge 172:7d866c31b3c5 1019 #define TSB_TD_EN_TDEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,7)))
AnnaBridge 172:7d866c31b3c5 1020
AnnaBridge 172:7d866c31b3c5 1021
AnnaBridge 172:7d866c31b3c5 1022 /* Timer D (Unit1) */
AnnaBridge 172:7d866c31b3c5 1023 #define TSB_TD1_RG2_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->RG2,31)))
AnnaBridge 172:7d866c31b3c5 1024 #define TSB_TD1_RG4_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->RG4,31)))
AnnaBridge 172:7d866c31b3c5 1025 #define TSB_TD1_HSWB0_OUTV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->HSWB0,2)))
AnnaBridge 172:7d866c31b3c5 1026 #define TSB_TD1_HSWB1_OUTV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->HSWB1,2)))
AnnaBridge 172:7d866c31b3c5 1027 #define TSB_TD1_RUN_TDRUN (*((__O uint32_t *)BITBAND_PERI(&TSB_TD1->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1028 #define TSB_TD1_CR_TDRDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,2)))
AnnaBridge 172:7d866c31b3c5 1029 #define TSB_TD1_CR_TDMDPT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,4)))
AnnaBridge 172:7d866c31b3c5 1030 #define TSB_TD1_CR_TDMDPT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,8)))
AnnaBridge 172:7d866c31b3c5 1031 #define TSB_TD1_MOD_TDCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,4)))
AnnaBridge 172:7d866c31b3c5 1032 #define TSB_TD1_MOD_TDIV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,6)))
AnnaBridge 172:7d866c31b3c5 1033 #define TSB_TD1_MOD_TDIV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,7)))
AnnaBridge 172:7d866c31b3c5 1034 #define TSB_TD1_DMA_DMAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1035 #define TSB_TD1_CP2_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->CP2,31)))
AnnaBridge 172:7d866c31b3c5 1036 #define TSB_TD1_CP4_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->CP4,31)))
AnnaBridge 172:7d866c31b3c5 1037 #define TSB_TD1_HSW0_OUTV0 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->HSW0,2)))
AnnaBridge 172:7d866c31b3c5 1038 #define TSB_TD1_HSW1_OUTV1 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->HSW1,2)))
AnnaBridge 172:7d866c31b3c5 1039
AnnaBridge 172:7d866c31b3c5 1040
AnnaBridge 172:7d866c31b3c5 1041 /* 16-bit TimerA */
AnnaBridge 172:7d866c31b3c5 1042 #define TSB_T16A0_EN_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->EN,1)))
AnnaBridge 172:7d866c31b3c5 1043 #define TSB_T16A0_RUN_RUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1044 #define TSB_T16A0_CR_CLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->CR,0)))
AnnaBridge 172:7d866c31b3c5 1045 #define TSB_T16A0_CR_FFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->CR,7)))
AnnaBridge 172:7d866c31b3c5 1046
AnnaBridge 172:7d866c31b3c5 1047 #define TSB_T16A1_EN_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->EN,1)))
AnnaBridge 172:7d866c31b3c5 1048 #define TSB_T16A1_RUN_RUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1049 #define TSB_T16A1_CR_CLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->CR,0)))
AnnaBridge 172:7d866c31b3c5 1050 #define TSB_T16A1_CR_FFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->CR,7)))
AnnaBridge 172:7d866c31b3c5 1051
AnnaBridge 172:7d866c31b3c5 1052
AnnaBridge 172:7d866c31b3c5 1053 /* Serial Interface (TSPI) */
AnnaBridge 172:7d866c31b3c5 1054 #define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0)))
AnnaBridge 172:7d866c31b3c5 1055 #define TSB_TSPI0_CR1_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,8)))
AnnaBridge 172:7d866c31b3c5 1056 #define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12)))
AnnaBridge 172:7d866c31b3c5 1057 #define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13)))
AnnaBridge 172:7d866c31b3c5 1058 #define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14)))
AnnaBridge 172:7d866c31b3c5 1059 #define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0)))
AnnaBridge 172:7d866c31b3c5 1060 #define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1)))
AnnaBridge 172:7d866c31b3c5 1061 #define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2)))
AnnaBridge 172:7d866c31b3c5 1062 #define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4)))
AnnaBridge 172:7d866c31b3c5 1063 #define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5)))
AnnaBridge 172:7d866c31b3c5 1064 #define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6)))
AnnaBridge 172:7d866c31b3c5 1065 #define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7)))
AnnaBridge 172:7d866c31b3c5 1066 #define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21)))
AnnaBridge 172:7d866c31b3c5 1067 #define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0)))
AnnaBridge 172:7d866c31b3c5 1068 #define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1)))
AnnaBridge 172:7d866c31b3c5 1069 #define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,8)))
AnnaBridge 172:7d866c31b3c5 1070 #define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14)))
AnnaBridge 172:7d866c31b3c5 1071 #define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31)))
AnnaBridge 172:7d866c31b3c5 1072 #define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0)))
AnnaBridge 172:7d866c31b3c5 1073 #define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1)))
AnnaBridge 172:7d866c31b3c5 1074 #define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4)))
AnnaBridge 172:7d866c31b3c5 1075 #define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5)))
AnnaBridge 172:7d866c31b3c5 1076 #define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6)))
AnnaBridge 172:7d866c31b3c5 1077 #define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7)))
AnnaBridge 172:7d866c31b3c5 1078 #define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20)))
AnnaBridge 172:7d866c31b3c5 1079 #define TSB_TSPI0_SR_INTTXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21)))
AnnaBridge 172:7d866c31b3c5 1080 #define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22)))
AnnaBridge 172:7d866c31b3c5 1081 #define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23)))
AnnaBridge 172:7d866c31b3c5 1082 #define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31)))
AnnaBridge 172:7d866c31b3c5 1083 #define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,9)))
AnnaBridge 172:7d866c31b3c5 1084 #define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,10)))
AnnaBridge 172:7d866c31b3c5 1085 #define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,11)))
AnnaBridge 172:7d866c31b3c5 1086
AnnaBridge 172:7d866c31b3c5 1087
AnnaBridge 172:7d866c31b3c5 1088 /* I2C */
AnnaBridge 172:7d866c31b3c5 1089 #define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3)))
AnnaBridge 172:7d866c31b3c5 1090 #define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4)))
AnnaBridge 172:7d866c31b3c5 1091 #define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0)))
AnnaBridge 172:7d866c31b3c5 1092 #define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3)))
AnnaBridge 172:7d866c31b3c5 1093 #define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4)))
AnnaBridge 172:7d866c31b3c5 1094 #define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5)))
AnnaBridge 172:7d866c31b3c5 1095 #define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6)))
AnnaBridge 172:7d866c31b3c5 1096 #define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7)))
AnnaBridge 172:7d866c31b3c5 1097 #define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0)))
AnnaBridge 172:7d866c31b3c5 1098 #define TSB_I2C0_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1)))
AnnaBridge 172:7d866c31b3c5 1099 #define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2)))
AnnaBridge 172:7d866c31b3c5 1100 #define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3)))
AnnaBridge 172:7d866c31b3c5 1101 #define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4)))
AnnaBridge 172:7d866c31b3c5 1102 #define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5)))
AnnaBridge 172:7d866c31b3c5 1103 #define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6)))
AnnaBridge 172:7d866c31b3c5 1104 #define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7)))
AnnaBridge 172:7d866c31b3c5 1105 #define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0)))
AnnaBridge 172:7d866c31b3c5 1106 #define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1)))
AnnaBridge 172:7d866c31b3c5 1107 #define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2)))
AnnaBridge 172:7d866c31b3c5 1108 #define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3)))
AnnaBridge 172:7d866c31b3c5 1109 #define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4)))
AnnaBridge 172:7d866c31b3c5 1110 #define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5)))
AnnaBridge 172:7d866c31b3c5 1111 #define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6)))
AnnaBridge 172:7d866c31b3c5 1112 #define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0)))
AnnaBridge 172:7d866c31b3c5 1113 #define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1)))
AnnaBridge 172:7d866c31b3c5 1114 #define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2)))
AnnaBridge 172:7d866c31b3c5 1115 #define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3)))
AnnaBridge 172:7d866c31b3c5 1116 #define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0)))
AnnaBridge 172:7d866c31b3c5 1117 #define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1)))
AnnaBridge 172:7d866c31b3c5 1118 #define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2)))
AnnaBridge 172:7d866c31b3c5 1119 #define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3)))
AnnaBridge 172:7d866c31b3c5 1120 #define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4)))
AnnaBridge 172:7d866c31b3c5 1121 #define TSB_I2C0_OP_SAST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5)))
AnnaBridge 172:7d866c31b3c5 1122 #define TSB_I2C0_OP_SA2ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6)))
AnnaBridge 172:7d866c31b3c5 1123 #define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0)))
AnnaBridge 172:7d866c31b3c5 1124 #define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1)))
AnnaBridge 172:7d866c31b3c5 1125 #define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0)))
AnnaBridge 172:7d866c31b3c5 1126
AnnaBridge 172:7d866c31b3c5 1127 #define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3)))
AnnaBridge 172:7d866c31b3c5 1128 #define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4)))
AnnaBridge 172:7d866c31b3c5 1129 #define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0)))
AnnaBridge 172:7d866c31b3c5 1130 #define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3)))
AnnaBridge 172:7d866c31b3c5 1131 #define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4)))
AnnaBridge 172:7d866c31b3c5 1132 #define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5)))
AnnaBridge 172:7d866c31b3c5 1133 #define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6)))
AnnaBridge 172:7d866c31b3c5 1134 #define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7)))
AnnaBridge 172:7d866c31b3c5 1135 #define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0)))
AnnaBridge 172:7d866c31b3c5 1136 #define TSB_I2C1_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1)))
AnnaBridge 172:7d866c31b3c5 1137 #define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2)))
AnnaBridge 172:7d866c31b3c5 1138 #define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3)))
AnnaBridge 172:7d866c31b3c5 1139 #define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4)))
AnnaBridge 172:7d866c31b3c5 1140 #define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5)))
AnnaBridge 172:7d866c31b3c5 1141 #define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6)))
AnnaBridge 172:7d866c31b3c5 1142 #define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7)))
AnnaBridge 172:7d866c31b3c5 1143 #define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0)))
AnnaBridge 172:7d866c31b3c5 1144 #define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1)))
AnnaBridge 172:7d866c31b3c5 1145 #define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2)))
AnnaBridge 172:7d866c31b3c5 1146 #define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3)))
AnnaBridge 172:7d866c31b3c5 1147 #define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4)))
AnnaBridge 172:7d866c31b3c5 1148 #define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5)))
AnnaBridge 172:7d866c31b3c5 1149 #define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6)))
AnnaBridge 172:7d866c31b3c5 1150 #define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0)))
AnnaBridge 172:7d866c31b3c5 1151 #define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1)))
AnnaBridge 172:7d866c31b3c5 1152 #define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2)))
AnnaBridge 172:7d866c31b3c5 1153 #define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3)))
AnnaBridge 172:7d866c31b3c5 1154 #define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0)))
AnnaBridge 172:7d866c31b3c5 1155 #define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1)))
AnnaBridge 172:7d866c31b3c5 1156 #define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2)))
AnnaBridge 172:7d866c31b3c5 1157 #define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3)))
AnnaBridge 172:7d866c31b3c5 1158 #define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4)))
AnnaBridge 172:7d866c31b3c5 1159 #define TSB_I2C1_OP_SAST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5)))
AnnaBridge 172:7d866c31b3c5 1160 #define TSB_I2C1_OP_SA2ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6)))
AnnaBridge 172:7d866c31b3c5 1161 #define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0)))
AnnaBridge 172:7d866c31b3c5 1162 #define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1)))
AnnaBridge 172:7d866c31b3c5 1163 #define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0)))
AnnaBridge 172:7d866c31b3c5 1164
AnnaBridge 172:7d866c31b3c5 1165
AnnaBridge 172:7d866c31b3c5 1166 /* Port A */
AnnaBridge 172:7d866c31b3c5 1167 #define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0)))
AnnaBridge 172:7d866c31b3c5 1168 #define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1)))
AnnaBridge 172:7d866c31b3c5 1169 #define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2)))
AnnaBridge 172:7d866c31b3c5 1170 #define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3)))
AnnaBridge 172:7d866c31b3c5 1171 #define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4)))
AnnaBridge 172:7d866c31b3c5 1172 #define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5)))
AnnaBridge 172:7d866c31b3c5 1173 #define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6)))
AnnaBridge 172:7d866c31b3c5 1174 #define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7)))
AnnaBridge 172:7d866c31b3c5 1175 #define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0)))
AnnaBridge 172:7d866c31b3c5 1176 #define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1)))
AnnaBridge 172:7d866c31b3c5 1177 #define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2)))
AnnaBridge 172:7d866c31b3c5 1178 #define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3)))
AnnaBridge 172:7d866c31b3c5 1179 #define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4)))
AnnaBridge 172:7d866c31b3c5 1180 #define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5)))
AnnaBridge 172:7d866c31b3c5 1181 #define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6)))
AnnaBridge 172:7d866c31b3c5 1182 #define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7)))
AnnaBridge 172:7d866c31b3c5 1183 #define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7)))
AnnaBridge 172:7d866c31b3c5 1184 #define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0)))
AnnaBridge 172:7d866c31b3c5 1185 #define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1)))
AnnaBridge 172:7d866c31b3c5 1186 #define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2)))
AnnaBridge 172:7d866c31b3c5 1187 #define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3)))
AnnaBridge 172:7d866c31b3c5 1188 #define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4)))
AnnaBridge 172:7d866c31b3c5 1189 #define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5)))
AnnaBridge 172:7d866c31b3c5 1190 #define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6)))
AnnaBridge 172:7d866c31b3c5 1191 #define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7)))
AnnaBridge 172:7d866c31b3c5 1192 #define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0)))
AnnaBridge 172:7d866c31b3c5 1193 #define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1)))
AnnaBridge 172:7d866c31b3c5 1194 #define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2)))
AnnaBridge 172:7d866c31b3c5 1195 #define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3)))
AnnaBridge 172:7d866c31b3c5 1196 #define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4)))
AnnaBridge 172:7d866c31b3c5 1197 #define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5)))
AnnaBridge 172:7d866c31b3c5 1198 #define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6)))
AnnaBridge 172:7d866c31b3c5 1199 #define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7)))
AnnaBridge 172:7d866c31b3c5 1200 #define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0)))
AnnaBridge 172:7d866c31b3c5 1201 #define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1)))
AnnaBridge 172:7d866c31b3c5 1202 #define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2)))
AnnaBridge 172:7d866c31b3c5 1203 #define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3)))
AnnaBridge 172:7d866c31b3c5 1204 #define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4)))
AnnaBridge 172:7d866c31b3c5 1205 #define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5)))
AnnaBridge 172:7d866c31b3c5 1206 #define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6)))
AnnaBridge 172:7d866c31b3c5 1207 #define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7)))
AnnaBridge 172:7d866c31b3c5 1208 #define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0)))
AnnaBridge 172:7d866c31b3c5 1209 #define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1)))
AnnaBridge 172:7d866c31b3c5 1210 #define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2)))
AnnaBridge 172:7d866c31b3c5 1211 #define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3)))
AnnaBridge 172:7d866c31b3c5 1212 #define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4)))
AnnaBridge 172:7d866c31b3c5 1213 #define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5)))
AnnaBridge 172:7d866c31b3c5 1214 #define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6)))
AnnaBridge 172:7d866c31b3c5 1215 #define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7)))
AnnaBridge 172:7d866c31b3c5 1216
AnnaBridge 172:7d866c31b3c5 1217
AnnaBridge 172:7d866c31b3c5 1218 /* Port B */
AnnaBridge 172:7d866c31b3c5 1219 #define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0)))
AnnaBridge 172:7d866c31b3c5 1220 #define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1)))
AnnaBridge 172:7d866c31b3c5 1221 #define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2)))
AnnaBridge 172:7d866c31b3c5 1222 #define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3)))
AnnaBridge 172:7d866c31b3c5 1223 #define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0)))
AnnaBridge 172:7d866c31b3c5 1224 #define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1)))
AnnaBridge 172:7d866c31b3c5 1225 #define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2)))
AnnaBridge 172:7d866c31b3c5 1226 #define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3)))
AnnaBridge 172:7d866c31b3c5 1227 #define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0)))
AnnaBridge 172:7d866c31b3c5 1228 #define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1)))
AnnaBridge 172:7d866c31b3c5 1229 #define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2)))
AnnaBridge 172:7d866c31b3c5 1230 #define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3)))
AnnaBridge 172:7d866c31b3c5 1231 #define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0)))
AnnaBridge 172:7d866c31b3c5 1232 #define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1)))
AnnaBridge 172:7d866c31b3c5 1233 #define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2)))
AnnaBridge 172:7d866c31b3c5 1234 #define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3)))
AnnaBridge 172:7d866c31b3c5 1235 #define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0)))
AnnaBridge 172:7d866c31b3c5 1236 #define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1)))
AnnaBridge 172:7d866c31b3c5 1237 #define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2)))
AnnaBridge 172:7d866c31b3c5 1238 #define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3)))
AnnaBridge 172:7d866c31b3c5 1239 #define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0)))
AnnaBridge 172:7d866c31b3c5 1240 #define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1)))
AnnaBridge 172:7d866c31b3c5 1241 #define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2)))
AnnaBridge 172:7d866c31b3c5 1242 #define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3)))
AnnaBridge 172:7d866c31b3c5 1243
AnnaBridge 172:7d866c31b3c5 1244
AnnaBridge 172:7d866c31b3c5 1245 /* Port C */
AnnaBridge 172:7d866c31b3c5 1246 #define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0)))
AnnaBridge 172:7d866c31b3c5 1247 #define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1)))
AnnaBridge 172:7d866c31b3c5 1248 #define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2)))
AnnaBridge 172:7d866c31b3c5 1249 #define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3)))
AnnaBridge 172:7d866c31b3c5 1250 #define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4)))
AnnaBridge 172:7d866c31b3c5 1251 #define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5)))
AnnaBridge 172:7d866c31b3c5 1252 #define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0)))
AnnaBridge 172:7d866c31b3c5 1253 #define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1)))
AnnaBridge 172:7d866c31b3c5 1254 #define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2)))
AnnaBridge 172:7d866c31b3c5 1255 #define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3)))
AnnaBridge 172:7d866c31b3c5 1256 #define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4)))
AnnaBridge 172:7d866c31b3c5 1257 #define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5)))
AnnaBridge 172:7d866c31b3c5 1258 #define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0)))
AnnaBridge 172:7d866c31b3c5 1259 #define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1)))
AnnaBridge 172:7d866c31b3c5 1260 #define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2)))
AnnaBridge 172:7d866c31b3c5 1261 #define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3)))
AnnaBridge 172:7d866c31b3c5 1262 #define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4)))
AnnaBridge 172:7d866c31b3c5 1263 #define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5)))
AnnaBridge 172:7d866c31b3c5 1264 #define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0)))
AnnaBridge 172:7d866c31b3c5 1265 #define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1)))
AnnaBridge 172:7d866c31b3c5 1266 #define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2)))
AnnaBridge 172:7d866c31b3c5 1267 #define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3)))
AnnaBridge 172:7d866c31b3c5 1268 #define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4)))
AnnaBridge 172:7d866c31b3c5 1269 #define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5)))
AnnaBridge 172:7d866c31b3c5 1270 #define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0)))
AnnaBridge 172:7d866c31b3c5 1271 #define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1)))
AnnaBridge 172:7d866c31b3c5 1272 #define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2)))
AnnaBridge 172:7d866c31b3c5 1273 #define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3)))
AnnaBridge 172:7d866c31b3c5 1274 #define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4)))
AnnaBridge 172:7d866c31b3c5 1275 #define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5)))
AnnaBridge 172:7d866c31b3c5 1276 #define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0)))
AnnaBridge 172:7d866c31b3c5 1277 #define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1)))
AnnaBridge 172:7d866c31b3c5 1278 #define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2)))
AnnaBridge 172:7d866c31b3c5 1279 #define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3)))
AnnaBridge 172:7d866c31b3c5 1280 #define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4)))
AnnaBridge 172:7d866c31b3c5 1281 #define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5)))
AnnaBridge 172:7d866c31b3c5 1282 #define TSB_PC_SEL_PC0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->SEL,0)))
AnnaBridge 172:7d866c31b3c5 1283 #define TSB_PC_SEL_PC1SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->SEL,1)))
AnnaBridge 172:7d866c31b3c5 1284 #define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0)))
AnnaBridge 172:7d866c31b3c5 1285 #define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1)))
AnnaBridge 172:7d866c31b3c5 1286 #define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2)))
AnnaBridge 172:7d866c31b3c5 1287 #define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3)))
AnnaBridge 172:7d866c31b3c5 1288 #define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4)))
AnnaBridge 172:7d866c31b3c5 1289 #define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5)))
AnnaBridge 172:7d866c31b3c5 1290
AnnaBridge 172:7d866c31b3c5 1291
AnnaBridge 172:7d866c31b3c5 1292 /* Port D */
AnnaBridge 172:7d866c31b3c5 1293 #define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0)))
AnnaBridge 172:7d866c31b3c5 1294 #define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1)))
AnnaBridge 172:7d866c31b3c5 1295 #define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2)))
AnnaBridge 172:7d866c31b3c5 1296 #define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3)))
AnnaBridge 172:7d866c31b3c5 1297 #define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4)))
AnnaBridge 172:7d866c31b3c5 1298 #define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5)))
AnnaBridge 172:7d866c31b3c5 1299 #define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0)))
AnnaBridge 172:7d866c31b3c5 1300 #define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1)))
AnnaBridge 172:7d866c31b3c5 1301 #define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2)))
AnnaBridge 172:7d866c31b3c5 1302 #define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3)))
AnnaBridge 172:7d866c31b3c5 1303 #define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4)))
AnnaBridge 172:7d866c31b3c5 1304 #define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5)))
AnnaBridge 172:7d866c31b3c5 1305 #define TSB_PD_FR1_PD0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,0)))
AnnaBridge 172:7d866c31b3c5 1306 #define TSB_PD_FR1_PD1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1)))
AnnaBridge 172:7d866c31b3c5 1307 #define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2)))
AnnaBridge 172:7d866c31b3c5 1308 #define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3)))
AnnaBridge 172:7d866c31b3c5 1309 #define TSB_PD_FR1_PD4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4)))
AnnaBridge 172:7d866c31b3c5 1310 #define TSB_PD_FR2_PD0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,0)))
AnnaBridge 172:7d866c31b3c5 1311 #define TSB_PD_FR2_PD1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,1)))
AnnaBridge 172:7d866c31b3c5 1312 #define TSB_PD_FR2_PD2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,2)))
AnnaBridge 172:7d866c31b3c5 1313 #define TSB_PD_FR2_PD3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,3)))
AnnaBridge 172:7d866c31b3c5 1314 #define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0)))
AnnaBridge 172:7d866c31b3c5 1315 #define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1)))
AnnaBridge 172:7d866c31b3c5 1316 #define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2)))
AnnaBridge 172:7d866c31b3c5 1317 #define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3)))
AnnaBridge 172:7d866c31b3c5 1318 #define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4)))
AnnaBridge 172:7d866c31b3c5 1319 #define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5)))
AnnaBridge 172:7d866c31b3c5 1320 #define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0)))
AnnaBridge 172:7d866c31b3c5 1321 #define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1)))
AnnaBridge 172:7d866c31b3c5 1322 #define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2)))
AnnaBridge 172:7d866c31b3c5 1323 #define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3)))
AnnaBridge 172:7d866c31b3c5 1324 #define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4)))
AnnaBridge 172:7d866c31b3c5 1325 #define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5)))
AnnaBridge 172:7d866c31b3c5 1326 #define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0)))
AnnaBridge 172:7d866c31b3c5 1327 #define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1)))
AnnaBridge 172:7d866c31b3c5 1328 #define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2)))
AnnaBridge 172:7d866c31b3c5 1329 #define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3)))
AnnaBridge 172:7d866c31b3c5 1330 #define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4)))
AnnaBridge 172:7d866c31b3c5 1331 #define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5)))
AnnaBridge 172:7d866c31b3c5 1332 #define TSB_PD_SEL_PD4SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->SEL,4)))
AnnaBridge 172:7d866c31b3c5 1333 #define TSB_PD_SEL_PD5SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->SEL,5)))
AnnaBridge 172:7d866c31b3c5 1334 #define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0)))
AnnaBridge 172:7d866c31b3c5 1335 #define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1)))
AnnaBridge 172:7d866c31b3c5 1336 #define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2)))
AnnaBridge 172:7d866c31b3c5 1337 #define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3)))
AnnaBridge 172:7d866c31b3c5 1338 #define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4)))
AnnaBridge 172:7d866c31b3c5 1339 #define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5)))
AnnaBridge 172:7d866c31b3c5 1340
AnnaBridge 172:7d866c31b3c5 1341
AnnaBridge 172:7d866c31b3c5 1342 /* Port E */
AnnaBridge 172:7d866c31b3c5 1343 #define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0)))
AnnaBridge 172:7d866c31b3c5 1344 #define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1)))
AnnaBridge 172:7d866c31b3c5 1345 #define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2)))
AnnaBridge 172:7d866c31b3c5 1346 #define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3)))
AnnaBridge 172:7d866c31b3c5 1347 #define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4)))
AnnaBridge 172:7d866c31b3c5 1348 #define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5)))
AnnaBridge 172:7d866c31b3c5 1349 #define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0)))
AnnaBridge 172:7d866c31b3c5 1350 #define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1)))
AnnaBridge 172:7d866c31b3c5 1351 #define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2)))
AnnaBridge 172:7d866c31b3c5 1352 #define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3)))
AnnaBridge 172:7d866c31b3c5 1353 #define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4)))
AnnaBridge 172:7d866c31b3c5 1354 #define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5)))
AnnaBridge 172:7d866c31b3c5 1355 #define TSB_PE_FR1_PE0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,0)))
AnnaBridge 172:7d866c31b3c5 1356 #define TSB_PE_FR1_PE1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1)))
AnnaBridge 172:7d866c31b3c5 1357 #define TSB_PE_FR1_PE2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2)))
AnnaBridge 172:7d866c31b3c5 1358 #define TSB_PE_FR1_PE3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3)))
AnnaBridge 172:7d866c31b3c5 1359 #define TSB_PE_FR1_PE4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4)))
AnnaBridge 172:7d866c31b3c5 1360 #define TSB_PE_FR1_PE5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5)))
AnnaBridge 172:7d866c31b3c5 1361 #define TSB_PE_FR2_PE1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,1)))
AnnaBridge 172:7d866c31b3c5 1362 #define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0)))
AnnaBridge 172:7d866c31b3c5 1363 #define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1)))
AnnaBridge 172:7d866c31b3c5 1364 #define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2)))
AnnaBridge 172:7d866c31b3c5 1365 #define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3)))
AnnaBridge 172:7d866c31b3c5 1366 #define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4)))
AnnaBridge 172:7d866c31b3c5 1367 #define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5)))
AnnaBridge 172:7d866c31b3c5 1368 #define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0)))
AnnaBridge 172:7d866c31b3c5 1369 #define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1)))
AnnaBridge 172:7d866c31b3c5 1370 #define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2)))
AnnaBridge 172:7d866c31b3c5 1371 #define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3)))
AnnaBridge 172:7d866c31b3c5 1372 #define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4)))
AnnaBridge 172:7d866c31b3c5 1373 #define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5)))
AnnaBridge 172:7d866c31b3c5 1374 #define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0)))
AnnaBridge 172:7d866c31b3c5 1375 #define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1)))
AnnaBridge 172:7d866c31b3c5 1376 #define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2)))
AnnaBridge 172:7d866c31b3c5 1377 #define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3)))
AnnaBridge 172:7d866c31b3c5 1378 #define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4)))
AnnaBridge 172:7d866c31b3c5 1379 #define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5)))
AnnaBridge 172:7d866c31b3c5 1380 #define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0)))
AnnaBridge 172:7d866c31b3c5 1381 #define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1)))
AnnaBridge 172:7d866c31b3c5 1382 #define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2)))
AnnaBridge 172:7d866c31b3c5 1383 #define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3)))
AnnaBridge 172:7d866c31b3c5 1384 #define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4)))
AnnaBridge 172:7d866c31b3c5 1385 #define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5)))
AnnaBridge 172:7d866c31b3c5 1386
AnnaBridge 172:7d866c31b3c5 1387
AnnaBridge 172:7d866c31b3c5 1388 /* Port F */
AnnaBridge 172:7d866c31b3c5 1389 #define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0)))
AnnaBridge 172:7d866c31b3c5 1390 #define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1)))
AnnaBridge 172:7d866c31b3c5 1391 #define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2)))
AnnaBridge 172:7d866c31b3c5 1392 #define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3)))
AnnaBridge 172:7d866c31b3c5 1393 #define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4)))
AnnaBridge 172:7d866c31b3c5 1394 #define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5)))
AnnaBridge 172:7d866c31b3c5 1395 #define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6)))
AnnaBridge 172:7d866c31b3c5 1396 #define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7)))
AnnaBridge 172:7d866c31b3c5 1397 #define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0)))
AnnaBridge 172:7d866c31b3c5 1398 #define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1)))
AnnaBridge 172:7d866c31b3c5 1399 #define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2)))
AnnaBridge 172:7d866c31b3c5 1400 #define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3)))
AnnaBridge 172:7d866c31b3c5 1401 #define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4)))
AnnaBridge 172:7d866c31b3c5 1402 #define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5)))
AnnaBridge 172:7d866c31b3c5 1403 #define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6)))
AnnaBridge 172:7d866c31b3c5 1404 #define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7)))
AnnaBridge 172:7d866c31b3c5 1405 #define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0)))
AnnaBridge 172:7d866c31b3c5 1406 #define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1)))
AnnaBridge 172:7d866c31b3c5 1407 #define TSB_PF_FR1_PF2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,2)))
AnnaBridge 172:7d866c31b3c5 1408 #define TSB_PF_FR1_PF3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,3)))
AnnaBridge 172:7d866c31b3c5 1409 #define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4)))
AnnaBridge 172:7d866c31b3c5 1410 #define TSB_PF_FR1_PF5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5)))
AnnaBridge 172:7d866c31b3c5 1411 #define TSB_PF_FR2_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,0)))
AnnaBridge 172:7d866c31b3c5 1412 #define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0)))
AnnaBridge 172:7d866c31b3c5 1413 #define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1)))
AnnaBridge 172:7d866c31b3c5 1414 #define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2)))
AnnaBridge 172:7d866c31b3c5 1415 #define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3)))
AnnaBridge 172:7d866c31b3c5 1416 #define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4)))
AnnaBridge 172:7d866c31b3c5 1417 #define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5)))
AnnaBridge 172:7d866c31b3c5 1418 #define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6)))
AnnaBridge 172:7d866c31b3c5 1419 #define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7)))
AnnaBridge 172:7d866c31b3c5 1420 #define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0)))
AnnaBridge 172:7d866c31b3c5 1421 #define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1)))
AnnaBridge 172:7d866c31b3c5 1422 #define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2)))
AnnaBridge 172:7d866c31b3c5 1423 #define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3)))
AnnaBridge 172:7d866c31b3c5 1424 #define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4)))
AnnaBridge 172:7d866c31b3c5 1425 #define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5)))
AnnaBridge 172:7d866c31b3c5 1426 #define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6)))
AnnaBridge 172:7d866c31b3c5 1427 #define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7)))
AnnaBridge 172:7d866c31b3c5 1428 #define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0)))
AnnaBridge 172:7d866c31b3c5 1429 #define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1)))
AnnaBridge 172:7d866c31b3c5 1430 #define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2)))
AnnaBridge 172:7d866c31b3c5 1431 #define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3)))
AnnaBridge 172:7d866c31b3c5 1432 #define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4)))
AnnaBridge 172:7d866c31b3c5 1433 #define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5)))
AnnaBridge 172:7d866c31b3c5 1434 #define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6)))
AnnaBridge 172:7d866c31b3c5 1435 #define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7)))
AnnaBridge 172:7d866c31b3c5 1436 #define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0)))
AnnaBridge 172:7d866c31b3c5 1437 #define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1)))
AnnaBridge 172:7d866c31b3c5 1438 #define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2)))
AnnaBridge 172:7d866c31b3c5 1439 #define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3)))
AnnaBridge 172:7d866c31b3c5 1440 #define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4)))
AnnaBridge 172:7d866c31b3c5 1441 #define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5)))
AnnaBridge 172:7d866c31b3c5 1442 #define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6)))
AnnaBridge 172:7d866c31b3c5 1443 #define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7)))
AnnaBridge 172:7d866c31b3c5 1444
AnnaBridge 172:7d866c31b3c5 1445
AnnaBridge 172:7d866c31b3c5 1446 /* Port G */
AnnaBridge 172:7d866c31b3c5 1447 #define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0)))
AnnaBridge 172:7d866c31b3c5 1448 #define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1)))
AnnaBridge 172:7d866c31b3c5 1449 #define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0)))
AnnaBridge 172:7d866c31b3c5 1450 #define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1)))
AnnaBridge 172:7d866c31b3c5 1451 #define TSB_PG_FR1_PG0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0)))
AnnaBridge 172:7d866c31b3c5 1452 #define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1)))
AnnaBridge 172:7d866c31b3c5 1453 #define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0)))
AnnaBridge 172:7d866c31b3c5 1454 #define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1)))
AnnaBridge 172:7d866c31b3c5 1455 #define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0)))
AnnaBridge 172:7d866c31b3c5 1456 #define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1)))
AnnaBridge 172:7d866c31b3c5 1457 #define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0)))
AnnaBridge 172:7d866c31b3c5 1458 #define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1)))
AnnaBridge 172:7d866c31b3c5 1459 #define TSB_PG_SEL_PG0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->SEL,0)))
AnnaBridge 172:7d866c31b3c5 1460 #define TSB_PG_SEL_PG1SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->SEL,1)))
AnnaBridge 172:7d866c31b3c5 1461 #define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0)))
AnnaBridge 172:7d866c31b3c5 1462 #define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1)))
AnnaBridge 172:7d866c31b3c5 1463
AnnaBridge 172:7d866c31b3c5 1464
AnnaBridge 172:7d866c31b3c5 1465 /* Port H */
AnnaBridge 172:7d866c31b3c5 1466 #define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0)))
AnnaBridge 172:7d866c31b3c5 1467 #define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1)))
AnnaBridge 172:7d866c31b3c5 1468 #define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2)))
AnnaBridge 172:7d866c31b3c5 1469 #define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3)))
AnnaBridge 172:7d866c31b3c5 1470 #define TSB_PH_CR_PH0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0)))
AnnaBridge 172:7d866c31b3c5 1471 #define TSB_PH_CR_PH1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1)))
AnnaBridge 172:7d866c31b3c5 1472 #define TSB_PH_CR_PH2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2)))
AnnaBridge 172:7d866c31b3c5 1473 #define TSB_PH_CR_PH3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3)))
AnnaBridge 172:7d866c31b3c5 1474 #define TSB_PH_FR1_PH0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0)))
AnnaBridge 172:7d866c31b3c5 1475 #define TSB_PH_FR1_PH1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1)))
AnnaBridge 172:7d866c31b3c5 1476 #define TSB_PH_FR1_PH2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2)))
AnnaBridge 172:7d866c31b3c5 1477 #define TSB_PH_FR1_PH3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3)))
AnnaBridge 172:7d866c31b3c5 1478 #define TSB_PH_OD_PH0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0)))
AnnaBridge 172:7d866c31b3c5 1479 #define TSB_PH_OD_PH1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1)))
AnnaBridge 172:7d866c31b3c5 1480 #define TSB_PH_OD_PH2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2)))
AnnaBridge 172:7d866c31b3c5 1481 #define TSB_PH_OD_PH3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3)))
AnnaBridge 172:7d866c31b3c5 1482 #define TSB_PH_PUP_PH0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0)))
AnnaBridge 172:7d866c31b3c5 1483 #define TSB_PH_PUP_PH1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1)))
AnnaBridge 172:7d866c31b3c5 1484 #define TSB_PH_PUP_PH2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2)))
AnnaBridge 172:7d866c31b3c5 1485 #define TSB_PH_PUP_PH3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3)))
AnnaBridge 172:7d866c31b3c5 1486 #define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0)))
AnnaBridge 172:7d866c31b3c5 1487 #define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1)))
AnnaBridge 172:7d866c31b3c5 1488 #define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2)))
AnnaBridge 172:7d866c31b3c5 1489 #define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3)))
AnnaBridge 172:7d866c31b3c5 1490 #define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0)))
AnnaBridge 172:7d866c31b3c5 1491 #define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1)))
AnnaBridge 172:7d866c31b3c5 1492 #define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2)))
AnnaBridge 172:7d866c31b3c5 1493 #define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3)))
AnnaBridge 172:7d866c31b3c5 1494
AnnaBridge 172:7d866c31b3c5 1495
AnnaBridge 172:7d866c31b3c5 1496 /* Port J */
AnnaBridge 172:7d866c31b3c5 1497 #define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0)))
AnnaBridge 172:7d866c31b3c5 1498 #define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1)))
AnnaBridge 172:7d866c31b3c5 1499 #define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2)))
AnnaBridge 172:7d866c31b3c5 1500 #define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3)))
AnnaBridge 172:7d866c31b3c5 1501 #define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0)))
AnnaBridge 172:7d866c31b3c5 1502 #define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1)))
AnnaBridge 172:7d866c31b3c5 1503 #define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2)))
AnnaBridge 172:7d866c31b3c5 1504 #define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3)))
AnnaBridge 172:7d866c31b3c5 1505 #define TSB_PJ_FR1_PJ0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,0)))
AnnaBridge 172:7d866c31b3c5 1506 #define TSB_PJ_FR1_PJ1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,1)))
AnnaBridge 172:7d866c31b3c5 1507 #define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0)))
AnnaBridge 172:7d866c31b3c5 1508 #define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1)))
AnnaBridge 172:7d866c31b3c5 1509 #define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2)))
AnnaBridge 172:7d866c31b3c5 1510 #define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3)))
AnnaBridge 172:7d866c31b3c5 1511 #define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0)))
AnnaBridge 172:7d866c31b3c5 1512 #define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1)))
AnnaBridge 172:7d866c31b3c5 1513 #define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2)))
AnnaBridge 172:7d866c31b3c5 1514 #define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3)))
AnnaBridge 172:7d866c31b3c5 1515 #define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0)))
AnnaBridge 172:7d866c31b3c5 1516 #define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1)))
AnnaBridge 172:7d866c31b3c5 1517 #define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2)))
AnnaBridge 172:7d866c31b3c5 1518 #define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3)))
AnnaBridge 172:7d866c31b3c5 1519 #define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0)))
AnnaBridge 172:7d866c31b3c5 1520 #define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1)))
AnnaBridge 172:7d866c31b3c5 1521 #define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2)))
AnnaBridge 172:7d866c31b3c5 1522 #define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3)))
AnnaBridge 172:7d866c31b3c5 1523
AnnaBridge 172:7d866c31b3c5 1524
AnnaBridge 172:7d866c31b3c5 1525 /* 16-bit Timer/Event Counter (TB) */
AnnaBridge 172:7d866c31b3c5 1526 #define TSB_TB0_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->EN,6)))
AnnaBridge 172:7d866c31b3c5 1527 #define TSB_TB0_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->EN,7)))
AnnaBridge 172:7d866c31b3c5 1528 #define TSB_TB0_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1529 #define TSB_TB0_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->RUN,2)))
AnnaBridge 172:7d866c31b3c5 1530 #define TSB_TB0_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,0)))
AnnaBridge 172:7d866c31b3c5 1531 #define TSB_TB0_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,1)))
AnnaBridge 172:7d866c31b3c5 1532 #define TSB_TB0_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,5)))
AnnaBridge 172:7d866c31b3c5 1533 #define TSB_TB0_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,7)))
AnnaBridge 172:7d866c31b3c5 1534 #define TSB_TB0_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->MOD,3)))
AnnaBridge 172:7d866c31b3c5 1535 #define TSB_TB0_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB0->MOD,6)))
AnnaBridge 172:7d866c31b3c5 1536 #define TSB_TB0_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,2)))
AnnaBridge 172:7d866c31b3c5 1537 #define TSB_TB0_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,3)))
AnnaBridge 172:7d866c31b3c5 1538 #define TSB_TB0_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,4)))
AnnaBridge 172:7d866c31b3c5 1539 #define TSB_TB0_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,5)))
AnnaBridge 172:7d866c31b3c5 1540 #define TSB_TB0_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,0)))
AnnaBridge 172:7d866c31b3c5 1541 #define TSB_TB0_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,1)))
AnnaBridge 172:7d866c31b3c5 1542 #define TSB_TB0_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,2)))
AnnaBridge 172:7d866c31b3c5 1543 #define TSB_TB0_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1544 #define TSB_TB0_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,1)))
AnnaBridge 172:7d866c31b3c5 1545 #define TSB_TB0_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,2)))
AnnaBridge 172:7d866c31b3c5 1546
AnnaBridge 172:7d866c31b3c5 1547 #define TSB_TB1_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->EN,6)))
AnnaBridge 172:7d866c31b3c5 1548 #define TSB_TB1_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->EN,7)))
AnnaBridge 172:7d866c31b3c5 1549 #define TSB_TB1_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1550 #define TSB_TB1_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->RUN,2)))
AnnaBridge 172:7d866c31b3c5 1551 #define TSB_TB1_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,0)))
AnnaBridge 172:7d866c31b3c5 1552 #define TSB_TB1_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,1)))
AnnaBridge 172:7d866c31b3c5 1553 #define TSB_TB1_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,5)))
AnnaBridge 172:7d866c31b3c5 1554 #define TSB_TB1_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,7)))
AnnaBridge 172:7d866c31b3c5 1555 #define TSB_TB1_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->MOD,3)))
AnnaBridge 172:7d866c31b3c5 1556 #define TSB_TB1_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB1->MOD,6)))
AnnaBridge 172:7d866c31b3c5 1557 #define TSB_TB1_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,2)))
AnnaBridge 172:7d866c31b3c5 1558 #define TSB_TB1_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,3)))
AnnaBridge 172:7d866c31b3c5 1559 #define TSB_TB1_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,4)))
AnnaBridge 172:7d866c31b3c5 1560 #define TSB_TB1_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,5)))
AnnaBridge 172:7d866c31b3c5 1561 #define TSB_TB1_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,0)))
AnnaBridge 172:7d866c31b3c5 1562 #define TSB_TB1_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,1)))
AnnaBridge 172:7d866c31b3c5 1563 #define TSB_TB1_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,2)))
AnnaBridge 172:7d866c31b3c5 1564 #define TSB_TB1_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1565 #define TSB_TB1_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,1)))
AnnaBridge 172:7d866c31b3c5 1566 #define TSB_TB1_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,2)))
AnnaBridge 172:7d866c31b3c5 1567
AnnaBridge 172:7d866c31b3c5 1568 #define TSB_TB2_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->EN,6)))
AnnaBridge 172:7d866c31b3c5 1569 #define TSB_TB2_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->EN,7)))
AnnaBridge 172:7d866c31b3c5 1570 #define TSB_TB2_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1571 #define TSB_TB2_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->RUN,2)))
AnnaBridge 172:7d866c31b3c5 1572 #define TSB_TB2_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,0)))
AnnaBridge 172:7d866c31b3c5 1573 #define TSB_TB2_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,1)))
AnnaBridge 172:7d866c31b3c5 1574 #define TSB_TB2_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,5)))
AnnaBridge 172:7d866c31b3c5 1575 #define TSB_TB2_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,7)))
AnnaBridge 172:7d866c31b3c5 1576 #define TSB_TB2_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->MOD,3)))
AnnaBridge 172:7d866c31b3c5 1577 #define TSB_TB2_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB2->MOD,6)))
AnnaBridge 172:7d866c31b3c5 1578 #define TSB_TB2_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,2)))
AnnaBridge 172:7d866c31b3c5 1579 #define TSB_TB2_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,3)))
AnnaBridge 172:7d866c31b3c5 1580 #define TSB_TB2_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,4)))
AnnaBridge 172:7d866c31b3c5 1581 #define TSB_TB2_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,5)))
AnnaBridge 172:7d866c31b3c5 1582 #define TSB_TB2_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,0)))
AnnaBridge 172:7d866c31b3c5 1583 #define TSB_TB2_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,1)))
AnnaBridge 172:7d866c31b3c5 1584 #define TSB_TB2_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,2)))
AnnaBridge 172:7d866c31b3c5 1585 #define TSB_TB2_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1586 #define TSB_TB2_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,1)))
AnnaBridge 172:7d866c31b3c5 1587 #define TSB_TB2_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,2)))
AnnaBridge 172:7d866c31b3c5 1588
AnnaBridge 172:7d866c31b3c5 1589 #define TSB_TB3_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->EN,6)))
AnnaBridge 172:7d866c31b3c5 1590 #define TSB_TB3_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->EN,7)))
AnnaBridge 172:7d866c31b3c5 1591 #define TSB_TB3_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1592 #define TSB_TB3_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->RUN,2)))
AnnaBridge 172:7d866c31b3c5 1593 #define TSB_TB3_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,0)))
AnnaBridge 172:7d866c31b3c5 1594 #define TSB_TB3_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,1)))
AnnaBridge 172:7d866c31b3c5 1595 #define TSB_TB3_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,5)))
AnnaBridge 172:7d866c31b3c5 1596 #define TSB_TB3_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,7)))
AnnaBridge 172:7d866c31b3c5 1597 #define TSB_TB3_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->MOD,3)))
AnnaBridge 172:7d866c31b3c5 1598 #define TSB_TB3_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB3->MOD,6)))
AnnaBridge 172:7d866c31b3c5 1599 #define TSB_TB3_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,2)))
AnnaBridge 172:7d866c31b3c5 1600 #define TSB_TB3_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,3)))
AnnaBridge 172:7d866c31b3c5 1601 #define TSB_TB3_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,4)))
AnnaBridge 172:7d866c31b3c5 1602 #define TSB_TB3_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,5)))
AnnaBridge 172:7d866c31b3c5 1603 #define TSB_TB3_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,0)))
AnnaBridge 172:7d866c31b3c5 1604 #define TSB_TB3_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,1)))
AnnaBridge 172:7d866c31b3c5 1605 #define TSB_TB3_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,2)))
AnnaBridge 172:7d866c31b3c5 1606 #define TSB_TB3_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1607 #define TSB_TB3_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,1)))
AnnaBridge 172:7d866c31b3c5 1608 #define TSB_TB3_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,2)))
AnnaBridge 172:7d866c31b3c5 1609
AnnaBridge 172:7d866c31b3c5 1610 #define TSB_TB4_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->EN,6)))
AnnaBridge 172:7d866c31b3c5 1611 #define TSB_TB4_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->EN,7)))
AnnaBridge 172:7d866c31b3c5 1612 #define TSB_TB4_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1613 #define TSB_TB4_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->RUN,2)))
AnnaBridge 172:7d866c31b3c5 1614 #define TSB_TB4_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,0)))
AnnaBridge 172:7d866c31b3c5 1615 #define TSB_TB4_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,1)))
AnnaBridge 172:7d866c31b3c5 1616 #define TSB_TB4_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,5)))
AnnaBridge 172:7d866c31b3c5 1617 #define TSB_TB4_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,7)))
AnnaBridge 172:7d866c31b3c5 1618 #define TSB_TB4_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->MOD,3)))
AnnaBridge 172:7d866c31b3c5 1619 #define TSB_TB4_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB4->MOD,6)))
AnnaBridge 172:7d866c31b3c5 1620 #define TSB_TB4_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,2)))
AnnaBridge 172:7d866c31b3c5 1621 #define TSB_TB4_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,3)))
AnnaBridge 172:7d866c31b3c5 1622 #define TSB_TB4_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,4)))
AnnaBridge 172:7d866c31b3c5 1623 #define TSB_TB4_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,5)))
AnnaBridge 172:7d866c31b3c5 1624 #define TSB_TB4_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,0)))
AnnaBridge 172:7d866c31b3c5 1625 #define TSB_TB4_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,1)))
AnnaBridge 172:7d866c31b3c5 1626 #define TSB_TB4_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,2)))
AnnaBridge 172:7d866c31b3c5 1627 #define TSB_TB4_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1628 #define TSB_TB4_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,1)))
AnnaBridge 172:7d866c31b3c5 1629 #define TSB_TB4_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,2)))
AnnaBridge 172:7d866c31b3c5 1630
AnnaBridge 172:7d866c31b3c5 1631 #define TSB_TB5_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->EN,6)))
AnnaBridge 172:7d866c31b3c5 1632 #define TSB_TB5_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->EN,7)))
AnnaBridge 172:7d866c31b3c5 1633 #define TSB_TB5_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1634 #define TSB_TB5_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->RUN,2)))
AnnaBridge 172:7d866c31b3c5 1635 #define TSB_TB5_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,0)))
AnnaBridge 172:7d866c31b3c5 1636 #define TSB_TB5_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,1)))
AnnaBridge 172:7d866c31b3c5 1637 #define TSB_TB5_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,5)))
AnnaBridge 172:7d866c31b3c5 1638 #define TSB_TB5_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,7)))
AnnaBridge 172:7d866c31b3c5 1639 #define TSB_TB5_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->MOD,3)))
AnnaBridge 172:7d866c31b3c5 1640 #define TSB_TB5_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB5->MOD,6)))
AnnaBridge 172:7d866c31b3c5 1641 #define TSB_TB5_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,2)))
AnnaBridge 172:7d866c31b3c5 1642 #define TSB_TB5_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,3)))
AnnaBridge 172:7d866c31b3c5 1643 #define TSB_TB5_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,4)))
AnnaBridge 172:7d866c31b3c5 1644 #define TSB_TB5_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,5)))
AnnaBridge 172:7d866c31b3c5 1645 #define TSB_TB5_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,0)))
AnnaBridge 172:7d866c31b3c5 1646 #define TSB_TB5_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,1)))
AnnaBridge 172:7d866c31b3c5 1647 #define TSB_TB5_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,2)))
AnnaBridge 172:7d866c31b3c5 1648 #define TSB_TB5_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1649 #define TSB_TB5_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,1)))
AnnaBridge 172:7d866c31b3c5 1650 #define TSB_TB5_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,2)))
AnnaBridge 172:7d866c31b3c5 1651
AnnaBridge 172:7d866c31b3c5 1652 #define TSB_TB6_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->EN,6)))
AnnaBridge 172:7d866c31b3c5 1653 #define TSB_TB6_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->EN,7)))
AnnaBridge 172:7d866c31b3c5 1654 #define TSB_TB6_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1655 #define TSB_TB6_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->RUN,2)))
AnnaBridge 172:7d866c31b3c5 1656 #define TSB_TB6_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,0)))
AnnaBridge 172:7d866c31b3c5 1657 #define TSB_TB6_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,1)))
AnnaBridge 172:7d866c31b3c5 1658 #define TSB_TB6_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,5)))
AnnaBridge 172:7d866c31b3c5 1659 #define TSB_TB6_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,7)))
AnnaBridge 172:7d866c31b3c5 1660 #define TSB_TB6_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->MOD,3)))
AnnaBridge 172:7d866c31b3c5 1661 #define TSB_TB6_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB6->MOD,6)))
AnnaBridge 172:7d866c31b3c5 1662 #define TSB_TB6_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,2)))
AnnaBridge 172:7d866c31b3c5 1663 #define TSB_TB6_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,3)))
AnnaBridge 172:7d866c31b3c5 1664 #define TSB_TB6_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,4)))
AnnaBridge 172:7d866c31b3c5 1665 #define TSB_TB6_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,5)))
AnnaBridge 172:7d866c31b3c5 1666 #define TSB_TB6_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,0)))
AnnaBridge 172:7d866c31b3c5 1667 #define TSB_TB6_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,1)))
AnnaBridge 172:7d866c31b3c5 1668 #define TSB_TB6_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,2)))
AnnaBridge 172:7d866c31b3c5 1669 #define TSB_TB6_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1670 #define TSB_TB6_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,1)))
AnnaBridge 172:7d866c31b3c5 1671 #define TSB_TB6_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,2)))
AnnaBridge 172:7d866c31b3c5 1672
AnnaBridge 172:7d866c31b3c5 1673 #define TSB_TB7_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->EN,6)))
AnnaBridge 172:7d866c31b3c5 1674 #define TSB_TB7_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->EN,7)))
AnnaBridge 172:7d866c31b3c5 1675 #define TSB_TB7_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->RUN,0)))
AnnaBridge 172:7d866c31b3c5 1676 #define TSB_TB7_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->RUN,2)))
AnnaBridge 172:7d866c31b3c5 1677 #define TSB_TB7_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,0)))
AnnaBridge 172:7d866c31b3c5 1678 #define TSB_TB7_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,1)))
AnnaBridge 172:7d866c31b3c5 1679 #define TSB_TB7_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,5)))
AnnaBridge 172:7d866c31b3c5 1680 #define TSB_TB7_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,7)))
AnnaBridge 172:7d866c31b3c5 1681 #define TSB_TB7_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->MOD,3)))
AnnaBridge 172:7d866c31b3c5 1682 #define TSB_TB7_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB7->MOD,6)))
AnnaBridge 172:7d866c31b3c5 1683 #define TSB_TB7_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,2)))
AnnaBridge 172:7d866c31b3c5 1684 #define TSB_TB7_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,3)))
AnnaBridge 172:7d866c31b3c5 1685 #define TSB_TB7_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,4)))
AnnaBridge 172:7d866c31b3c5 1686 #define TSB_TB7_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,5)))
AnnaBridge 172:7d866c31b3c5 1687 #define TSB_TB7_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,0)))
AnnaBridge 172:7d866c31b3c5 1688 #define TSB_TB7_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,1)))
AnnaBridge 172:7d866c31b3c5 1689 #define TSB_TB7_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,2)))
AnnaBridge 172:7d866c31b3c5 1690 #define TSB_TB7_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1691 #define TSB_TB7_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,1)))
AnnaBridge 172:7d866c31b3c5 1692 #define TSB_TB7_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,2)))
AnnaBridge 172:7d866c31b3c5 1693
AnnaBridge 172:7d866c31b3c5 1694
AnnaBridge 172:7d866c31b3c5 1695 /* SC */
AnnaBridge 172:7d866c31b3c5 1696 #define TSB_SC0_EN_SIOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->EN,0)))
AnnaBridge 172:7d866c31b3c5 1697 #define TSB_SC0_EN_BRCKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->EN,1)))
AnnaBridge 172:7d866c31b3c5 1698 #define TSB_SC0_MOD0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,4)))
AnnaBridge 172:7d866c31b3c5 1699 #define TSB_SC0_MOD0_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,5)))
AnnaBridge 172:7d866c31b3c5 1700 #define TSB_SC0_MOD0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,6)))
AnnaBridge 172:7d866c31b3c5 1701 #define TSB_SC0_MOD0_TB8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,7)))
AnnaBridge 172:7d866c31b3c5 1702 #define TSB_SC0_BRCR_BRADDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->BRCR,6)))
AnnaBridge 172:7d866c31b3c5 1703 #define TSB_SC0_MOD1_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD1,4)))
AnnaBridge 172:7d866c31b3c5 1704 #define TSB_SC0_MOD2_WBUF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,2)))
AnnaBridge 172:7d866c31b3c5 1705 #define TSB_SC0_MOD2_DRCHG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,3)))
AnnaBridge 172:7d866c31b3c5 1706 #define TSB_SC0_MOD2_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,4)))
AnnaBridge 172:7d866c31b3c5 1707 #define TSB_SC0_MOD2_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,5)))
AnnaBridge 172:7d866c31b3c5 1708 #define TSB_SC0_MOD2_RBFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,6)))
AnnaBridge 172:7d866c31b3c5 1709 #define TSB_SC0_MOD2_TBEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,7)))
AnnaBridge 172:7d866c31b3c5 1710 #define TSB_SC0_RST_ROR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->RST,7)))
AnnaBridge 172:7d866c31b3c5 1711 #define TSB_SC0_TST_TUR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->TST,7)))
AnnaBridge 172:7d866c31b3c5 1712 #define TSB_SC0_FCNF_CNFG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,0)))
AnnaBridge 172:7d866c31b3c5 1713 #define TSB_SC0_FCNF_RXTXCNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,1)))
AnnaBridge 172:7d866c31b3c5 1714 #define TSB_SC0_FCNF_RFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,2)))
AnnaBridge 172:7d866c31b3c5 1715 #define TSB_SC0_FCNF_TFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,3)))
AnnaBridge 172:7d866c31b3c5 1716 #define TSB_SC0_FCNF_RFST (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,4)))
AnnaBridge 172:7d866c31b3c5 1717 #define TSB_SC0_DMA_DMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1718 #define TSB_SC0_DMA_DMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->DMA,1)))
AnnaBridge 172:7d866c31b3c5 1719
AnnaBridge 172:7d866c31b3c5 1720 #define TSB_SC1_EN_SIOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->EN,0)))
AnnaBridge 172:7d866c31b3c5 1721 #define TSB_SC1_EN_BRCKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->EN,1)))
AnnaBridge 172:7d866c31b3c5 1722 #define TSB_SC1_MOD0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,4)))
AnnaBridge 172:7d866c31b3c5 1723 #define TSB_SC1_MOD0_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,5)))
AnnaBridge 172:7d866c31b3c5 1724 #define TSB_SC1_MOD0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,6)))
AnnaBridge 172:7d866c31b3c5 1725 #define TSB_SC1_MOD0_TB8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,7)))
AnnaBridge 172:7d866c31b3c5 1726 #define TSB_SC1_BRCR_BRADDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->BRCR,6)))
AnnaBridge 172:7d866c31b3c5 1727 #define TSB_SC1_MOD1_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD1,4)))
AnnaBridge 172:7d866c31b3c5 1728 #define TSB_SC1_MOD2_WBUF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,2)))
AnnaBridge 172:7d866c31b3c5 1729 #define TSB_SC1_MOD2_DRCHG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,3)))
AnnaBridge 172:7d866c31b3c5 1730 #define TSB_SC1_MOD2_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,4)))
AnnaBridge 172:7d866c31b3c5 1731 #define TSB_SC1_MOD2_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,5)))
AnnaBridge 172:7d866c31b3c5 1732 #define TSB_SC1_MOD2_RBFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,6)))
AnnaBridge 172:7d866c31b3c5 1733 #define TSB_SC1_MOD2_TBEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,7)))
AnnaBridge 172:7d866c31b3c5 1734 #define TSB_SC1_RST_ROR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->RST,7)))
AnnaBridge 172:7d866c31b3c5 1735 #define TSB_SC1_TST_TUR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->TST,7)))
AnnaBridge 172:7d866c31b3c5 1736 #define TSB_SC1_FCNF_CNFG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,0)))
AnnaBridge 172:7d866c31b3c5 1737 #define TSB_SC1_FCNF_RXTXCNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,1)))
AnnaBridge 172:7d866c31b3c5 1738 #define TSB_SC1_FCNF_RFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,2)))
AnnaBridge 172:7d866c31b3c5 1739 #define TSB_SC1_FCNF_TFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,3)))
AnnaBridge 172:7d866c31b3c5 1740 #define TSB_SC1_FCNF_RFST (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,4)))
AnnaBridge 172:7d866c31b3c5 1741 #define TSB_SC1_DMA_DMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->DMA,0)))
AnnaBridge 172:7d866c31b3c5 1742 #define TSB_SC1_DMA_DMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->DMA,1)))
AnnaBridge 172:7d866c31b3c5 1743
AnnaBridge 172:7d866c31b3c5 1744
AnnaBridge 172:7d866c31b3c5 1745 /* WDT */
AnnaBridge 172:7d866c31b3c5 1746 #define TSB_WD_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,1)))
AnnaBridge 172:7d866c31b3c5 1747 #define TSB_WD_MOD_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,7)))
AnnaBridge 172:7d866c31b3c5 1748 #define TSB_WD_FLG_FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_WD->FLG,0)))
AnnaBridge 172:7d866c31b3c5 1749
AnnaBridge 172:7d866c31b3c5 1750
AnnaBridge 172:7d866c31b3c5 1751 /* CG */
AnnaBridge 172:7d866c31b3c5 1752 #define TSB_CG_OSCCR_IOSCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0)))
AnnaBridge 172:7d866c31b3c5 1753 #define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8)))
AnnaBridge 172:7d866c31b3c5 1754 #define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9)))
AnnaBridge 172:7d866c31b3c5 1755 #define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0)))
AnnaBridge 172:7d866c31b3c5 1756 #define TSB_CG_PLL0SEL_PPL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1)))
AnnaBridge 172:7d866c31b3c5 1757 #define TSB_CG_PLL0SEL_PLL0ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2)))
AnnaBridge 172:7d866c31b3c5 1758 #define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0)))
AnnaBridge 172:7d866c31b3c5 1759 #define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1)))
AnnaBridge 172:7d866c31b3c5 1760 #define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8)))
AnnaBridge 172:7d866c31b3c5 1761 #define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7)))
AnnaBridge 172:7d866c31b3c5 1762 #define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8)))
AnnaBridge 172:7d866c31b3c5 1763 #define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9)))
AnnaBridge 172:7d866c31b3c5 1764 #define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10)))
AnnaBridge 172:7d866c31b3c5 1765 #define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11)))
AnnaBridge 172:7d866c31b3c5 1766 #define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12)))
AnnaBridge 172:7d866c31b3c5 1767 #define TSB_CG_FSYSENA_IPENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,13)))
AnnaBridge 172:7d866c31b3c5 1768 #define TSB_CG_FSYSENA_IPENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,14)))
AnnaBridge 172:7d866c31b3c5 1769 #define TSB_CG_FSYSENA_IPENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,15)))
AnnaBridge 172:7d866c31b3c5 1770 #define TSB_CG_FSYSENA_IPENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,16)))
AnnaBridge 172:7d866c31b3c5 1771 #define TSB_CG_FSYSENA_IPENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,17)))
AnnaBridge 172:7d866c31b3c5 1772 #define TSB_CG_FSYSENA_IPENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,18)))
AnnaBridge 172:7d866c31b3c5 1773 #define TSB_CG_FSYSENB_IPENB28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,28)))
AnnaBridge 172:7d866c31b3c5 1774 #define TSB_CG_FSYSENB_IPENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,29)))
AnnaBridge 172:7d866c31b3c5 1775 #define TSB_CG_FSYSENB_IPENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,30)))
AnnaBridge 172:7d866c31b3c5 1776 #define TSB_CG_FSYSENB_IPENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,31)))
AnnaBridge 172:7d866c31b3c5 1777 #define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16)))
AnnaBridge 172:7d866c31b3c5 1778 #define TSB_CG_EXTENDO0_USBENA (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,0)))
AnnaBridge 172:7d866c31b3c5 1779 #define TSB_CG_EXTENDO0_USBSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,1)))
AnnaBridge 172:7d866c31b3c5 1780 #define TSB_CG_EXTENDO0_EHCLKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,4)))
AnnaBridge 172:7d866c31b3c5 1781 #define TSB_CG_EXTENDO0_DCLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,5)))
AnnaBridge 172:7d866c31b3c5 1782
AnnaBridge 172:7d866c31b3c5 1783
AnnaBridge 172:7d866c31b3c5 1784 /* LVD */
AnnaBridge 172:7d866c31b3c5 1785 #define TSB_LVD_CR0_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,0)))
AnnaBridge 172:7d866c31b3c5 1786 #define TSB_LVD_CR0_INTSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,4)))
AnnaBridge 172:7d866c31b3c5 1787 #define TSB_LVD_CR0_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,5)))
AnnaBridge 172:7d866c31b3c5 1788 #define TSB_LVD_CR0_RSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,6)))
AnnaBridge 172:7d866c31b3c5 1789 #define TSB_LVD_CR0_ST (*((__I uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,7)))
AnnaBridge 172:7d866c31b3c5 1790 #define TSB_LVD_CR1_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,0)))
AnnaBridge 172:7d866c31b3c5 1791 #define TSB_LVD_CR1_INTSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,4)))
AnnaBridge 172:7d866c31b3c5 1792 #define TSB_LVD_CR1_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,5)))
AnnaBridge 172:7d866c31b3c5 1793 #define TSB_LVD_CR1_RSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,6)))
AnnaBridge 172:7d866c31b3c5 1794 #define TSB_LVD_CR1_ST (*((__I uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,7)))
AnnaBridge 172:7d866c31b3c5 1795
AnnaBridge 172:7d866c31b3c5 1796
AnnaBridge 172:7d866c31b3c5 1797 /* SD Area register1 */
AnnaBridge 172:7d866c31b3c5 1798 #define TSB_INTIFSD_STOP1INT_016_INT016EN (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,0)))
AnnaBridge 172:7d866c31b3c5 1799 #define TSB_INTIFSD_STOP1INT_016_INT016PFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,4)))
AnnaBridge 172:7d866c31b3c5 1800 #define TSB_INTIFSD_STOP1INT_016_INT016NFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,5)))
AnnaBridge 172:7d866c31b3c5 1801 #define TSB_INTIFSD_STOP1INT_016_INT016PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,6)))
AnnaBridge 172:7d866c31b3c5 1802 #define TSB_INTIFSD_STOP1INT_016_INT016NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,7)))
AnnaBridge 172:7d866c31b3c5 1803 #define TSB_INTIFSD_STOP1INT_017_INT017EN (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,0)))
AnnaBridge 172:7d866c31b3c5 1804 #define TSB_INTIFSD_STOP1INT_017_INT017PFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,4)))
AnnaBridge 172:7d866c31b3c5 1805 #define TSB_INTIFSD_STOP1INT_017_INT017NFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,5)))
AnnaBridge 172:7d866c31b3c5 1806 #define TSB_INTIFSD_STOP1INT_017_INT017PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,6)))
AnnaBridge 172:7d866c31b3c5 1807 #define TSB_INTIFSD_STOP1INT_017_INT017NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,7)))
AnnaBridge 172:7d866c31b3c5 1808 #define TSB_INTIFSD_IDLEINT_018_INT018EN (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,0)))
AnnaBridge 172:7d866c31b3c5 1809 #define TSB_INTIFSD_IDLEINT_018_INT018PFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,4)))
AnnaBridge 172:7d866c31b3c5 1810 #define TSB_INTIFSD_IDLEINT_018_INT018NFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,5)))
AnnaBridge 172:7d866c31b3c5 1811 #define TSB_INTIFSD_IDLEINT_018_INT018PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,6)))
AnnaBridge 172:7d866c31b3c5 1812 #define TSB_INTIFSD_IDLEINT_018_INT018NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,7)))
AnnaBridge 172:7d866c31b3c5 1813 #define TSB_INTIFSD_IDLEINT_096_INT096EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,0)))
AnnaBridge 172:7d866c31b3c5 1814 #define TSB_INTIFSD_IDLEINT_096_INT096PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,4)))
AnnaBridge 172:7d866c31b3c5 1815 #define TSB_INTIFSD_IDLEINT_096_INT096NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,5)))
AnnaBridge 172:7d866c31b3c5 1816 #define TSB_INTIFSD_IDLEINT_096_INT096PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,6)))
AnnaBridge 172:7d866c31b3c5 1817 #define TSB_INTIFSD_IDLEINT_096_INT096NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,7)))
AnnaBridge 172:7d866c31b3c5 1818 #define TSB_INTIFSD_IDLEINT_097_INT097EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,0)))
AnnaBridge 172:7d866c31b3c5 1819 #define TSB_INTIFSD_IDLEINT_097_INT097PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,4)))
AnnaBridge 172:7d866c31b3c5 1820 #define TSB_INTIFSD_IDLEINT_097_INT097NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,5)))
AnnaBridge 172:7d866c31b3c5 1821 #define TSB_INTIFSD_IDLEINT_097_INT097PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,6)))
AnnaBridge 172:7d866c31b3c5 1822 #define TSB_INTIFSD_IDLEINT_097_INT097NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,7)))
AnnaBridge 172:7d866c31b3c5 1823 #define TSB_INTIFSD_IDLEINT_098_INT098EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,0)))
AnnaBridge 172:7d866c31b3c5 1824 #define TSB_INTIFSD_IDLEINT_098_INT098PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,4)))
AnnaBridge 172:7d866c31b3c5 1825 #define TSB_INTIFSD_IDLEINT_098_INT098NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,5)))
AnnaBridge 172:7d866c31b3c5 1826 #define TSB_INTIFSD_IDLEINT_098_INT098PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,6)))
AnnaBridge 172:7d866c31b3c5 1827 #define TSB_INTIFSD_IDLEINT_098_INT098NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,7)))
AnnaBridge 172:7d866c31b3c5 1828 #define TSB_INTIFSD_IDLEINT_099_INT099EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,0)))
AnnaBridge 172:7d866c31b3c5 1829 #define TSB_INTIFSD_IDLEINT_099_INT099PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,4)))
AnnaBridge 172:7d866c31b3c5 1830 #define TSB_INTIFSD_IDLEINT_099_INT099NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,5)))
AnnaBridge 172:7d866c31b3c5 1831 #define TSB_INTIFSD_IDLEINT_099_INT099PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,6)))
AnnaBridge 172:7d866c31b3c5 1832 #define TSB_INTIFSD_IDLEINT_099_INT099NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,7)))
AnnaBridge 172:7d866c31b3c5 1833 #define TSB_INTIFSD_IDLEINT_100_INT100EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,0)))
AnnaBridge 172:7d866c31b3c5 1834 #define TSB_INTIFSD_IDLEINT_100_INT100PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,4)))
AnnaBridge 172:7d866c31b3c5 1835 #define TSB_INTIFSD_IDLEINT_100_INT100NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,5)))
AnnaBridge 172:7d866c31b3c5 1836 #define TSB_INTIFSD_IDLEINT_100_INT100PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,6)))
AnnaBridge 172:7d866c31b3c5 1837 #define TSB_INTIFSD_IDLEINT_100_INT100NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,7)))
AnnaBridge 172:7d866c31b3c5 1838 #define TSB_INTIFSD_IDLEINT_101_INT101EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,0)))
AnnaBridge 172:7d866c31b3c5 1839 #define TSB_INTIFSD_IDLEINT_101_INT101PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,4)))
AnnaBridge 172:7d866c31b3c5 1840 #define TSB_INTIFSD_IDLEINT_101_INT101NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,5)))
AnnaBridge 172:7d866c31b3c5 1841 #define TSB_INTIFSD_IDLEINT_101_INT101PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,6)))
AnnaBridge 172:7d866c31b3c5 1842 #define TSB_INTIFSD_IDLEINT_101_INT101NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,7)))
AnnaBridge 172:7d866c31b3c5 1843 #define TSB_INTIFSD_IDLEINT_102_INT102EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,0)))
AnnaBridge 172:7d866c31b3c5 1844 #define TSB_INTIFSD_IDLEINT_102_INT102PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,4)))
AnnaBridge 172:7d866c31b3c5 1845 #define TSB_INTIFSD_IDLEINT_102_INT102NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,5)))
AnnaBridge 172:7d866c31b3c5 1846 #define TSB_INTIFSD_IDLEINT_102_INT102PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,6)))
AnnaBridge 172:7d866c31b3c5 1847 #define TSB_INTIFSD_IDLEINT_102_INT102NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,7)))
AnnaBridge 172:7d866c31b3c5 1848 #define TSB_INTIFSD_IDLEINT_103_INT103EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,0)))
AnnaBridge 172:7d866c31b3c5 1849 #define TSB_INTIFSD_IDLEINT_103_INT103PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,4)))
AnnaBridge 172:7d866c31b3c5 1850 #define TSB_INTIFSD_IDLEINT_103_INT103NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,5)))
AnnaBridge 172:7d866c31b3c5 1851 #define TSB_INTIFSD_IDLEINT_103_INT103PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,6)))
AnnaBridge 172:7d866c31b3c5 1852 #define TSB_INTIFSD_IDLEINT_103_INT103NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,7)))
AnnaBridge 172:7d866c31b3c5 1853 #define TSB_INTIFSD_IDLEINT_104_INT104EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,0)))
AnnaBridge 172:7d866c31b3c5 1854 #define TSB_INTIFSD_IDLEINT_104_INT104PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,4)))
AnnaBridge 172:7d866c31b3c5 1855 #define TSB_INTIFSD_IDLEINT_104_INT104NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,5)))
AnnaBridge 172:7d866c31b3c5 1856 #define TSB_INTIFSD_IDLEINT_104_INT104PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,6)))
AnnaBridge 172:7d866c31b3c5 1857 #define TSB_INTIFSD_IDLEINT_104_INT104NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,7)))
AnnaBridge 172:7d866c31b3c5 1858 #define TSB_INTIFSD_IDLEINT_105_INT105EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,0)))
AnnaBridge 172:7d866c31b3c5 1859 #define TSB_INTIFSD_IDLEINT_105_INT105PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,4)))
AnnaBridge 172:7d866c31b3c5 1860 #define TSB_INTIFSD_IDLEINT_105_INT105NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,5)))
AnnaBridge 172:7d866c31b3c5 1861 #define TSB_INTIFSD_IDLEINT_105_INT105PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,6)))
AnnaBridge 172:7d866c31b3c5 1862 #define TSB_INTIFSD_IDLEINT_105_INT105NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,7)))
AnnaBridge 172:7d866c31b3c5 1863 #define TSB_INTIFSD_IDLEINT_106_INT106EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,0)))
AnnaBridge 172:7d866c31b3c5 1864 #define TSB_INTIFSD_IDLEINT_106_INT106PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,4)))
AnnaBridge 172:7d866c31b3c5 1865 #define TSB_INTIFSD_IDLEINT_106_INT106NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,5)))
AnnaBridge 172:7d866c31b3c5 1866 #define TSB_INTIFSD_IDLEINT_106_INT106PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,6)))
AnnaBridge 172:7d866c31b3c5 1867 #define TSB_INTIFSD_IDLEINT_106_INT106NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,7)))
AnnaBridge 172:7d866c31b3c5 1868 #define TSB_INTIFSD_IDLEINT_107_INT107EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,0)))
AnnaBridge 172:7d866c31b3c5 1869 #define TSB_INTIFSD_IDLEINT_107_INT107PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,4)))
AnnaBridge 172:7d866c31b3c5 1870 #define TSB_INTIFSD_IDLEINT_107_INT107NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,5)))
AnnaBridge 172:7d866c31b3c5 1871 #define TSB_INTIFSD_IDLEINT_107_INT107PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,6)))
AnnaBridge 172:7d866c31b3c5 1872 #define TSB_INTIFSD_IDLEINT_107_INT107NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,7)))
AnnaBridge 172:7d866c31b3c5 1873 #define TSB_INTIFSD_IDLEINT_108_INT108EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,0)))
AnnaBridge 172:7d866c31b3c5 1874 #define TSB_INTIFSD_IDLEINT_108_INT108PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,4)))
AnnaBridge 172:7d866c31b3c5 1875 #define TSB_INTIFSD_IDLEINT_108_INT108NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,5)))
AnnaBridge 172:7d866c31b3c5 1876 #define TSB_INTIFSD_IDLEINT_108_INT108PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,6)))
AnnaBridge 172:7d866c31b3c5 1877 #define TSB_INTIFSD_IDLEINT_108_INT108NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,7)))
AnnaBridge 172:7d866c31b3c5 1878 #define TSB_INTIFSD_IDLEINT_109_INT109EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,0)))
AnnaBridge 172:7d866c31b3c5 1879 #define TSB_INTIFSD_IDLEINT_109_INT109PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,4)))
AnnaBridge 172:7d866c31b3c5 1880 #define TSB_INTIFSD_IDLEINT_109_INT109NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,5)))
AnnaBridge 172:7d866c31b3c5 1881 #define TSB_INTIFSD_IDLEINT_109_INT109PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,6)))
AnnaBridge 172:7d866c31b3c5 1882 #define TSB_INTIFSD_IDLEINT_109_INT109NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,7)))
AnnaBridge 172:7d866c31b3c5 1883 #define TSB_INTIFSD_IDLEINT_110_INT110EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,0)))
AnnaBridge 172:7d866c31b3c5 1884 #define TSB_INTIFSD_IDLEINT_110_INT110PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,4)))
AnnaBridge 172:7d866c31b3c5 1885 #define TSB_INTIFSD_IDLEINT_110_INT110NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,5)))
AnnaBridge 172:7d866c31b3c5 1886 #define TSB_INTIFSD_IDLEINT_110_INT110PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,6)))
AnnaBridge 172:7d866c31b3c5 1887 #define TSB_INTIFSD_IDLEINT_110_INT110NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,7)))
AnnaBridge 172:7d866c31b3c5 1888 #define TSB_INTIFSD_IDLEINT_111_INT111EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,0)))
AnnaBridge 172:7d866c31b3c5 1889 #define TSB_INTIFSD_IDLEINT_111_INT111PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,4)))
AnnaBridge 172:7d866c31b3c5 1890 #define TSB_INTIFSD_IDLEINT_111_INT111NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,5)))
AnnaBridge 172:7d866c31b3c5 1891 #define TSB_INTIFSD_IDLEINT_111_INT111PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,6)))
AnnaBridge 172:7d866c31b3c5 1892 #define TSB_INTIFSD_IDLEINT_111_INT111NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,7)))
AnnaBridge 172:7d866c31b3c5 1893 #define TSB_INTIFSD_IDLEINT_112_INT112EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,0)))
AnnaBridge 172:7d866c31b3c5 1894 #define TSB_INTIFSD_IDLEINT_112_INT112PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,4)))
AnnaBridge 172:7d866c31b3c5 1895 #define TSB_INTIFSD_IDLEINT_112_INT112NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,5)))
AnnaBridge 172:7d866c31b3c5 1896 #define TSB_INTIFSD_IDLEINT_112_INT112PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,6)))
AnnaBridge 172:7d866c31b3c5 1897 #define TSB_INTIFSD_IDLEINT_112_INT112NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,7)))
AnnaBridge 172:7d866c31b3c5 1898 #define TSB_INTIFSD_IDLEINT_113_INT113EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,0)))
AnnaBridge 172:7d866c31b3c5 1899 #define TSB_INTIFSD_IDLEINT_113_INT113PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,4)))
AnnaBridge 172:7d866c31b3c5 1900 #define TSB_INTIFSD_IDLEINT_113_INT113NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,5)))
AnnaBridge 172:7d866c31b3c5 1901 #define TSB_INTIFSD_IDLEINT_113_INT113PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,6)))
AnnaBridge 172:7d866c31b3c5 1902 #define TSB_INTIFSD_IDLEINT_113_INT113NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,7)))
AnnaBridge 172:7d866c31b3c5 1903 #define TSB_INTIFSD_IDLEINT_114_INT114EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,0)))
AnnaBridge 172:7d866c31b3c5 1904 #define TSB_INTIFSD_IDLEINT_114_INT114PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,4)))
AnnaBridge 172:7d866c31b3c5 1905 #define TSB_INTIFSD_IDLEINT_114_INT114NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,5)))
AnnaBridge 172:7d866c31b3c5 1906 #define TSB_INTIFSD_IDLEINT_114_INT114PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,6)))
AnnaBridge 172:7d866c31b3c5 1907 #define TSB_INTIFSD_IDLEINT_114_INT114NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,7)))
AnnaBridge 172:7d866c31b3c5 1908 #define TSB_INTIFSD_IDLEINT_115_INT115EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,0)))
AnnaBridge 172:7d866c31b3c5 1909 #define TSB_INTIFSD_IDLEINT_115_INT115PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,4)))
AnnaBridge 172:7d866c31b3c5 1910 #define TSB_INTIFSD_IDLEINT_115_INT115NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,5)))
AnnaBridge 172:7d866c31b3c5 1911 #define TSB_INTIFSD_IDLEINT_115_INT115PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,6)))
AnnaBridge 172:7d866c31b3c5 1912 #define TSB_INTIFSD_IDLEINT_115_INT115NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,7)))
AnnaBridge 172:7d866c31b3c5 1913 #define TSB_INTIFSD_IDLEINT_116_INT116EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,0)))
AnnaBridge 172:7d866c31b3c5 1914 #define TSB_INTIFSD_IDLEINT_116_INT116PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,4)))
AnnaBridge 172:7d866c31b3c5 1915 #define TSB_INTIFSD_IDLEINT_116_INT116NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,5)))
AnnaBridge 172:7d866c31b3c5 1916 #define TSB_INTIFSD_IDLEINT_116_INT116PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,6)))
AnnaBridge 172:7d866c31b3c5 1917 #define TSB_INTIFSD_IDLEINT_116_INT116NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,7)))
AnnaBridge 172:7d866c31b3c5 1918 #define TSB_INTIFSD_IDLEINT_117_INT117EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,0)))
AnnaBridge 172:7d866c31b3c5 1919 #define TSB_INTIFSD_IDLEINT_117_INT117PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,4)))
AnnaBridge 172:7d866c31b3c5 1920 #define TSB_INTIFSD_IDLEINT_117_INT117NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,5)))
AnnaBridge 172:7d866c31b3c5 1921 #define TSB_INTIFSD_IDLEINT_117_INT117PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,6)))
AnnaBridge 172:7d866c31b3c5 1922 #define TSB_INTIFSD_IDLEINT_117_INT117NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,7)))
AnnaBridge 172:7d866c31b3c5 1923 #define TSB_INTIFSD_IDLEINT_118_INT118EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,0)))
AnnaBridge 172:7d866c31b3c5 1924 #define TSB_INTIFSD_IDLEINT_118_INT118PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,4)))
AnnaBridge 172:7d866c31b3c5 1925 #define TSB_INTIFSD_IDLEINT_118_INT118NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,5)))
AnnaBridge 172:7d866c31b3c5 1926 #define TSB_INTIFSD_IDLEINT_118_INT118PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,6)))
AnnaBridge 172:7d866c31b3c5 1927 #define TSB_INTIFSD_IDLEINT_118_INT118NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,7)))
AnnaBridge 172:7d866c31b3c5 1928 #define TSB_INTIFSD_IDLEINT_119_INT119EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,0)))
AnnaBridge 172:7d866c31b3c5 1929 #define TSB_INTIFSD_IDLEINT_119_INT119PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,4)))
AnnaBridge 172:7d866c31b3c5 1930 #define TSB_INTIFSD_IDLEINT_119_INT119NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,5)))
AnnaBridge 172:7d866c31b3c5 1931 #define TSB_INTIFSD_IDLEINT_119_INT119PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,6)))
AnnaBridge 172:7d866c31b3c5 1932 #define TSB_INTIFSD_IDLEINT_119_INT119NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,7)))
AnnaBridge 172:7d866c31b3c5 1933 #define TSB_INTIFSD_IDLEINT_120_INT120EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,0)))
AnnaBridge 172:7d866c31b3c5 1934 #define TSB_INTIFSD_IDLEINT_120_INT120PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,4)))
AnnaBridge 172:7d866c31b3c5 1935 #define TSB_INTIFSD_IDLEINT_120_INT120NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,5)))
AnnaBridge 172:7d866c31b3c5 1936 #define TSB_INTIFSD_IDLEINT_120_INT120PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,6)))
AnnaBridge 172:7d866c31b3c5 1937 #define TSB_INTIFSD_IDLEINT_120_INT120NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,7)))
AnnaBridge 172:7d866c31b3c5 1938 #define TSB_INTIFSD_IDLEINT_121_INT121EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,0)))
AnnaBridge 172:7d866c31b3c5 1939 #define TSB_INTIFSD_IDLEINT_121_INT121PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,4)))
AnnaBridge 172:7d866c31b3c5 1940 #define TSB_INTIFSD_IDLEINT_121_INT121NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,5)))
AnnaBridge 172:7d866c31b3c5 1941 #define TSB_INTIFSD_IDLEINT_121_INT121PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,6)))
AnnaBridge 172:7d866c31b3c5 1942 #define TSB_INTIFSD_IDLEINT_121_INT121NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,7)))
AnnaBridge 172:7d866c31b3c5 1943 #define TSB_INTIFSD_IDLEINT_122_INT122EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,0)))
AnnaBridge 172:7d866c31b3c5 1944 #define TSB_INTIFSD_IDLEINT_122_INT122PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,4)))
AnnaBridge 172:7d866c31b3c5 1945 #define TSB_INTIFSD_IDLEINT_122_INT122NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,5)))
AnnaBridge 172:7d866c31b3c5 1946 #define TSB_INTIFSD_IDLEINT_122_INT122PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,6)))
AnnaBridge 172:7d866c31b3c5 1947 #define TSB_INTIFSD_IDLEINT_122_INT122NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,7)))
AnnaBridge 172:7d866c31b3c5 1948 #define TSB_INTIFSD_IDLEINT_123_INT123EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,0)))
AnnaBridge 172:7d866c31b3c5 1949 #define TSB_INTIFSD_IDLEINT_123_INT123PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,4)))
AnnaBridge 172:7d866c31b3c5 1950 #define TSB_INTIFSD_IDLEINT_123_INT123NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,5)))
AnnaBridge 172:7d866c31b3c5 1951 #define TSB_INTIFSD_IDLEINT_123_INT123PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,6)))
AnnaBridge 172:7d866c31b3c5 1952 #define TSB_INTIFSD_IDLEINT_123_INT123NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,7)))
AnnaBridge 172:7d866c31b3c5 1953 #define TSB_INTIFSD_IDLEINT_124_INT124EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,0)))
AnnaBridge 172:7d866c31b3c5 1954 #define TSB_INTIFSD_IDLEINT_124_INT124PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,4)))
AnnaBridge 172:7d866c31b3c5 1955 #define TSB_INTIFSD_IDLEINT_124_INT124NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,5)))
AnnaBridge 172:7d866c31b3c5 1956 #define TSB_INTIFSD_IDLEINT_124_INT124PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,6)))
AnnaBridge 172:7d866c31b3c5 1957 #define TSB_INTIFSD_IDLEINT_124_INT124NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,7)))
AnnaBridge 172:7d866c31b3c5 1958 #define TSB_INTIFSD_IDLEINT_125_INT125EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,0)))
AnnaBridge 172:7d866c31b3c5 1959 #define TSB_INTIFSD_IDLEINT_125_INT125PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,4)))
AnnaBridge 172:7d866c31b3c5 1960 #define TSB_INTIFSD_IDLEINT_125_INT125NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,5)))
AnnaBridge 172:7d866c31b3c5 1961 #define TSB_INTIFSD_IDLEINT_125_INT125PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,6)))
AnnaBridge 172:7d866c31b3c5 1962 #define TSB_INTIFSD_IDLEINT_125_INT125NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,7)))
AnnaBridge 172:7d866c31b3c5 1963 #define TSB_INTIFSD_IDLEINT_126_INT126EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,0)))
AnnaBridge 172:7d866c31b3c5 1964 #define TSB_INTIFSD_IDLEINT_126_INT126PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,4)))
AnnaBridge 172:7d866c31b3c5 1965 #define TSB_INTIFSD_IDLEINT_126_INT126NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,5)))
AnnaBridge 172:7d866c31b3c5 1966 #define TSB_INTIFSD_IDLEINT_126_INT126PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,6)))
AnnaBridge 172:7d866c31b3c5 1967 #define TSB_INTIFSD_IDLEINT_126_INT126NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,7)))
AnnaBridge 172:7d866c31b3c5 1968 #define TSB_INTIFSD_IDLEINT_127_INT127EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,0)))
AnnaBridge 172:7d866c31b3c5 1969 #define TSB_INTIFSD_IDLEINT_127_INT127PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,4)))
AnnaBridge 172:7d866c31b3c5 1970 #define TSB_INTIFSD_IDLEINT_127_INT127NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,5)))
AnnaBridge 172:7d866c31b3c5 1971 #define TSB_INTIFSD_IDLEINT_127_INT127PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,6)))
AnnaBridge 172:7d866c31b3c5 1972 #define TSB_INTIFSD_IDLEINT_127_INT127NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,7)))
AnnaBridge 172:7d866c31b3c5 1973 #define TSB_INTIFSD_IDLEINT_128_INT128EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,0)))
AnnaBridge 172:7d866c31b3c5 1974 #define TSB_INTIFSD_IDLEINT_128_INT128PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,4)))
AnnaBridge 172:7d866c31b3c5 1975 #define TSB_INTIFSD_IDLEINT_128_INT128NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,5)))
AnnaBridge 172:7d866c31b3c5 1976 #define TSB_INTIFSD_IDLEINT_128_INT128PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,6)))
AnnaBridge 172:7d866c31b3c5 1977 #define TSB_INTIFSD_IDLEINT_128_INT128NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,7)))
AnnaBridge 172:7d866c31b3c5 1978 #define TSB_INTIFSD_IDLEINT_129_INT129EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,0)))
AnnaBridge 172:7d866c31b3c5 1979 #define TSB_INTIFSD_IDLEINT_129_INT129PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,4)))
AnnaBridge 172:7d866c31b3c5 1980 #define TSB_INTIFSD_IDLEINT_129_INT129NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,5)))
AnnaBridge 172:7d866c31b3c5 1981 #define TSB_INTIFSD_IDLEINT_129_INT129PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,6)))
AnnaBridge 172:7d866c31b3c5 1982 #define TSB_INTIFSD_IDLEINT_129_INT129NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,7)))
AnnaBridge 172:7d866c31b3c5 1983 #define TSB_INTIFSD_IDLEINT_130_INT130EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,0)))
AnnaBridge 172:7d866c31b3c5 1984 #define TSB_INTIFSD_IDLEINT_130_INT130PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,4)))
AnnaBridge 172:7d866c31b3c5 1985 #define TSB_INTIFSD_IDLEINT_130_INT130NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,5)))
AnnaBridge 172:7d866c31b3c5 1986 #define TSB_INTIFSD_IDLEINT_130_INT130PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,6)))
AnnaBridge 172:7d866c31b3c5 1987 #define TSB_INTIFSD_IDLEINT_130_INT130NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,7)))
AnnaBridge 172:7d866c31b3c5 1988 #define TSB_INTIFSD_IDLEINT_131_INT131EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,0)))
AnnaBridge 172:7d866c31b3c5 1989 #define TSB_INTIFSD_IDLEINT_131_INT131PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,4)))
AnnaBridge 172:7d866c31b3c5 1990 #define TSB_INTIFSD_IDLEINT_131_INT131NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,5)))
AnnaBridge 172:7d866c31b3c5 1991 #define TSB_INTIFSD_IDLEINT_131_INT131PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,6)))
AnnaBridge 172:7d866c31b3c5 1992 #define TSB_INTIFSD_IDLEINT_131_INT131NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,7)))
AnnaBridge 172:7d866c31b3c5 1993 #define TSB_INTIFSD_IDLEINT_132_INT132EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,0)))
AnnaBridge 172:7d866c31b3c5 1994 #define TSB_INTIFSD_IDLEINT_132_INT132PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,4)))
AnnaBridge 172:7d866c31b3c5 1995 #define TSB_INTIFSD_IDLEINT_132_INT132NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,5)))
AnnaBridge 172:7d866c31b3c5 1996 #define TSB_INTIFSD_IDLEINT_132_INT132PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,6)))
AnnaBridge 172:7d866c31b3c5 1997 #define TSB_INTIFSD_IDLEINT_132_INT132NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,7)))
AnnaBridge 172:7d866c31b3c5 1998 #define TSB_INTIFSD_IDLEINT_133_INT133EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,0)))
AnnaBridge 172:7d866c31b3c5 1999 #define TSB_INTIFSD_IDLEINT_133_INT133PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,4)))
AnnaBridge 172:7d866c31b3c5 2000 #define TSB_INTIFSD_IDLEINT_133_INT133NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,5)))
AnnaBridge 172:7d866c31b3c5 2001 #define TSB_INTIFSD_IDLEINT_133_INT133PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,6)))
AnnaBridge 172:7d866c31b3c5 2002 #define TSB_INTIFSD_IDLEINT_133_INT133NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,7)))
AnnaBridge 172:7d866c31b3c5 2003 #define TSB_INTIFSD_IDLEINT_134_INT134EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,0)))
AnnaBridge 172:7d866c31b3c5 2004 #define TSB_INTIFSD_IDLEINT_134_INT134PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,4)))
AnnaBridge 172:7d866c31b3c5 2005 #define TSB_INTIFSD_IDLEINT_134_INT134NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,5)))
AnnaBridge 172:7d866c31b3c5 2006 #define TSB_INTIFSD_IDLEINT_134_INT134PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,6)))
AnnaBridge 172:7d866c31b3c5 2007 #define TSB_INTIFSD_IDLEINT_134_INT134NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,7)))
AnnaBridge 172:7d866c31b3c5 2008 #define TSB_INTIFSD_IDLEINT_135_INT135EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,0)))
AnnaBridge 172:7d866c31b3c5 2009 #define TSB_INTIFSD_IDLEINT_135_INT135PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,4)))
AnnaBridge 172:7d866c31b3c5 2010 #define TSB_INTIFSD_IDLEINT_135_INT135NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,5)))
AnnaBridge 172:7d866c31b3c5 2011 #define TSB_INTIFSD_IDLEINT_135_INT135PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,6)))
AnnaBridge 172:7d866c31b3c5 2012 #define TSB_INTIFSD_IDLEINT_135_INT135NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,7)))
AnnaBridge 172:7d866c31b3c5 2013 #define TSB_INTIFSD_IDLEINT_136_INT136EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,0)))
AnnaBridge 172:7d866c31b3c5 2014 #define TSB_INTIFSD_IDLEINT_136_INT136PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,4)))
AnnaBridge 172:7d866c31b3c5 2015 #define TSB_INTIFSD_IDLEINT_136_INT136NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,5)))
AnnaBridge 172:7d866c31b3c5 2016 #define TSB_INTIFSD_IDLEINT_136_INT136PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,6)))
AnnaBridge 172:7d866c31b3c5 2017 #define TSB_INTIFSD_IDLEINT_136_INT136NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,7)))
AnnaBridge 172:7d866c31b3c5 2018 #define TSB_INTIFSD_IDLEINT_137_INT137EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,0)))
AnnaBridge 172:7d866c31b3c5 2019 #define TSB_INTIFSD_IDLEINT_137_INT137PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,4)))
AnnaBridge 172:7d866c31b3c5 2020 #define TSB_INTIFSD_IDLEINT_137_INT137NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,5)))
AnnaBridge 172:7d866c31b3c5 2021 #define TSB_INTIFSD_IDLEINT_137_INT137PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,6)))
AnnaBridge 172:7d866c31b3c5 2022 #define TSB_INTIFSD_IDLEINT_137_INT137NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,7)))
AnnaBridge 172:7d866c31b3c5 2023 #define TSB_INTIFSD_IDLEINT_138_INT138EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,0)))
AnnaBridge 172:7d866c31b3c5 2024 #define TSB_INTIFSD_IDLEINT_138_INT138PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,4)))
AnnaBridge 172:7d866c31b3c5 2025 #define TSB_INTIFSD_IDLEINT_138_INT138NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,5)))
AnnaBridge 172:7d866c31b3c5 2026 #define TSB_INTIFSD_IDLEINT_138_INT138PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,6)))
AnnaBridge 172:7d866c31b3c5 2027 #define TSB_INTIFSD_IDLEINT_138_INT138NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,7)))
AnnaBridge 172:7d866c31b3c5 2028 #define TSB_INTIFSD_IDLEINT_139_INT139EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,0)))
AnnaBridge 172:7d866c31b3c5 2029 #define TSB_INTIFSD_IDLEINT_139_INT139PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,4)))
AnnaBridge 172:7d866c31b3c5 2030 #define TSB_INTIFSD_IDLEINT_139_INT139NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,5)))
AnnaBridge 172:7d866c31b3c5 2031 #define TSB_INTIFSD_IDLEINT_139_INT139PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,6)))
AnnaBridge 172:7d866c31b3c5 2032 #define TSB_INTIFSD_IDLEINT_139_INT139NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,7)))
AnnaBridge 172:7d866c31b3c5 2033 #define TSB_INTIFSD_IDLEINT_140_INT140EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,0)))
AnnaBridge 172:7d866c31b3c5 2034 #define TSB_INTIFSD_IDLEINT_140_INT140PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,4)))
AnnaBridge 172:7d866c31b3c5 2035 #define TSB_INTIFSD_IDLEINT_140_INT140NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,5)))
AnnaBridge 172:7d866c31b3c5 2036 #define TSB_INTIFSD_IDLEINT_140_INT140PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,6)))
AnnaBridge 172:7d866c31b3c5 2037 #define TSB_INTIFSD_IDLEINT_140_INT140NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,7)))
AnnaBridge 172:7d866c31b3c5 2038 #define TSB_INTIFSD_IDLEINT_141_INT141EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,0)))
AnnaBridge 172:7d866c31b3c5 2039 #define TSB_INTIFSD_IDLEINT_141_INT141PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,4)))
AnnaBridge 172:7d866c31b3c5 2040 #define TSB_INTIFSD_IDLEINT_141_INT141NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,5)))
AnnaBridge 172:7d866c31b3c5 2041 #define TSB_INTIFSD_IDLEINT_141_INT141PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,6)))
AnnaBridge 172:7d866c31b3c5 2042 #define TSB_INTIFSD_IDLEINT_141_INT141NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,7)))
AnnaBridge 172:7d866c31b3c5 2043 #define TSB_INTIFSD_IDLEINT_142_INT142EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,0)))
AnnaBridge 172:7d866c31b3c5 2044 #define TSB_INTIFSD_IDLEINT_142_INT142PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,4)))
AnnaBridge 172:7d866c31b3c5 2045 #define TSB_INTIFSD_IDLEINT_142_INT142NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,5)))
AnnaBridge 172:7d866c31b3c5 2046 #define TSB_INTIFSD_IDLEINT_142_INT142PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,6)))
AnnaBridge 172:7d866c31b3c5 2047 #define TSB_INTIFSD_IDLEINT_142_INT142NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,7)))
AnnaBridge 172:7d866c31b3c5 2048 #define TSB_INTIFSD_IDLEINT_143_INT143EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,0)))
AnnaBridge 172:7d866c31b3c5 2049 #define TSB_INTIFSD_IDLEINT_143_INT143PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,4)))
AnnaBridge 172:7d866c31b3c5 2050 #define TSB_INTIFSD_IDLEINT_143_INT143NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,5)))
AnnaBridge 172:7d866c31b3c5 2051 #define TSB_INTIFSD_IDLEINT_143_INT143PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,6)))
AnnaBridge 172:7d866c31b3c5 2052 #define TSB_INTIFSD_IDLEINT_143_INT143NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,7)))
AnnaBridge 172:7d866c31b3c5 2053 #define TSB_INTIFSD_IDLEINT_144_INT144EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,0)))
AnnaBridge 172:7d866c31b3c5 2054 #define TSB_INTIFSD_IDLEINT_144_INT144PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,4)))
AnnaBridge 172:7d866c31b3c5 2055 #define TSB_INTIFSD_IDLEINT_144_INT144NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,5)))
AnnaBridge 172:7d866c31b3c5 2056 #define TSB_INTIFSD_IDLEINT_144_INT144PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,6)))
AnnaBridge 172:7d866c31b3c5 2057 #define TSB_INTIFSD_IDLEINT_144_INT144NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,7)))
AnnaBridge 172:7d866c31b3c5 2058 #define TSB_INTIFSD_IDLEINT_145_INT145EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,0)))
AnnaBridge 172:7d866c31b3c5 2059 #define TSB_INTIFSD_IDLEINT_145_INT145PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,4)))
AnnaBridge 172:7d866c31b3c5 2060 #define TSB_INTIFSD_IDLEINT_145_INT145NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,5)))
AnnaBridge 172:7d866c31b3c5 2061 #define TSB_INTIFSD_IDLEINT_145_INT145PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,6)))
AnnaBridge 172:7d866c31b3c5 2062 #define TSB_INTIFSD_IDLEINT_145_INT145NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,7)))
AnnaBridge 172:7d866c31b3c5 2063 #define TSB_INTIFSD_IDLEINT_146_INT146EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,0)))
AnnaBridge 172:7d866c31b3c5 2064 #define TSB_INTIFSD_IDLEINT_146_INT146PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,4)))
AnnaBridge 172:7d866c31b3c5 2065 #define TSB_INTIFSD_IDLEINT_146_INT146NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,5)))
AnnaBridge 172:7d866c31b3c5 2066 #define TSB_INTIFSD_IDLEINT_146_INT146PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,6)))
AnnaBridge 172:7d866c31b3c5 2067 #define TSB_INTIFSD_IDLEINT_146_INT146NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,7)))
AnnaBridge 172:7d866c31b3c5 2068 #define TSB_INTIFSD_IDLEINT_147_INT147EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,0)))
AnnaBridge 172:7d866c31b3c5 2069 #define TSB_INTIFSD_IDLEINT_147_INT147PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,4)))
AnnaBridge 172:7d866c31b3c5 2070 #define TSB_INTIFSD_IDLEINT_147_INT147NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,5)))
AnnaBridge 172:7d866c31b3c5 2071 #define TSB_INTIFSD_IDLEINT_147_INT147PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,6)))
AnnaBridge 172:7d866c31b3c5 2072 #define TSB_INTIFSD_IDLEINT_147_INT147NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,7)))
AnnaBridge 172:7d866c31b3c5 2073 #define TSB_INTIFSD_IDLEINT_148_INT148EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,0)))
AnnaBridge 172:7d866c31b3c5 2074 #define TSB_INTIFSD_IDLEINT_148_INT148PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,4)))
AnnaBridge 172:7d866c31b3c5 2075 #define TSB_INTIFSD_IDLEINT_148_INT148NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,5)))
AnnaBridge 172:7d866c31b3c5 2076 #define TSB_INTIFSD_IDLEINT_148_INT148PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,6)))
AnnaBridge 172:7d866c31b3c5 2077 #define TSB_INTIFSD_IDLEINT_148_INT148NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,7)))
AnnaBridge 172:7d866c31b3c5 2078 #define TSB_INTIFSD_IDLEINT_149_INT149EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,0)))
AnnaBridge 172:7d866c31b3c5 2079 #define TSB_INTIFSD_IDLEINT_149_INT149PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,4)))
AnnaBridge 172:7d866c31b3c5 2080 #define TSB_INTIFSD_IDLEINT_149_INT149NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,5)))
AnnaBridge 172:7d866c31b3c5 2081 #define TSB_INTIFSD_IDLEINT_149_INT149PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,6)))
AnnaBridge 172:7d866c31b3c5 2082 #define TSB_INTIFSD_IDLEINT_149_INT149NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,7)))
AnnaBridge 172:7d866c31b3c5 2083 #define TSB_INTIFSD_IDLEINT_150_INT150EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,0)))
AnnaBridge 172:7d866c31b3c5 2084 #define TSB_INTIFSD_IDLEINT_150_INT150PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,4)))
AnnaBridge 172:7d866c31b3c5 2085 #define TSB_INTIFSD_IDLEINT_150_INT150NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,5)))
AnnaBridge 172:7d866c31b3c5 2086 #define TSB_INTIFSD_IDLEINT_150_INT150PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,6)))
AnnaBridge 172:7d866c31b3c5 2087 #define TSB_INTIFSD_IDLEINT_150_INT150NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,7)))
AnnaBridge 172:7d866c31b3c5 2088 #define TSB_INTIFSD_IDLEINT_151_INT151EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,0)))
AnnaBridge 172:7d866c31b3c5 2089 #define TSB_INTIFSD_IDLEINT_151_INT151PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,4)))
AnnaBridge 172:7d866c31b3c5 2090 #define TSB_INTIFSD_IDLEINT_151_INT151NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,5)))
AnnaBridge 172:7d866c31b3c5 2091 #define TSB_INTIFSD_IDLEINT_151_INT151PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,6)))
AnnaBridge 172:7d866c31b3c5 2092 #define TSB_INTIFSD_IDLEINT_151_INT151NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,7)))
AnnaBridge 172:7d866c31b3c5 2093 #define TSB_INTIFSD_IDLEINT_152_INT152EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,0)))
AnnaBridge 172:7d866c31b3c5 2094 #define TSB_INTIFSD_IDLEINT_152_INT152PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,4)))
AnnaBridge 172:7d866c31b3c5 2095 #define TSB_INTIFSD_IDLEINT_152_INT152NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,5)))
AnnaBridge 172:7d866c31b3c5 2096 #define TSB_INTIFSD_IDLEINT_152_INT152PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,6)))
AnnaBridge 172:7d866c31b3c5 2097 #define TSB_INTIFSD_IDLEINT_152_INT152NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,7)))
AnnaBridge 172:7d866c31b3c5 2098 #define TSB_INTIFSD_IDLEINT_153_INT153EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,0)))
AnnaBridge 172:7d866c31b3c5 2099 #define TSB_INTIFSD_IDLEINT_153_INT153PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,4)))
AnnaBridge 172:7d866c31b3c5 2100 #define TSB_INTIFSD_IDLEINT_153_INT153NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,5)))
AnnaBridge 172:7d866c31b3c5 2101 #define TSB_INTIFSD_IDLEINT_153_INT153PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,6)))
AnnaBridge 172:7d866c31b3c5 2102 #define TSB_INTIFSD_IDLEINT_153_INT153NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,7)))
AnnaBridge 172:7d866c31b3c5 2103 #define TSB_INTIFSD_IDLEINT_154_INT154EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,0)))
AnnaBridge 172:7d866c31b3c5 2104 #define TSB_INTIFSD_IDLEINT_154_INT154PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,4)))
AnnaBridge 172:7d866c31b3c5 2105 #define TSB_INTIFSD_IDLEINT_154_INT154NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,5)))
AnnaBridge 172:7d866c31b3c5 2106 #define TSB_INTIFSD_IDLEINT_154_INT154PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,6)))
AnnaBridge 172:7d866c31b3c5 2107 #define TSB_INTIFSD_IDLEINT_154_INT154NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,7)))
AnnaBridge 172:7d866c31b3c5 2108 #define TSB_INTIFSD_IDLEINT_155_INT155EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,0)))
AnnaBridge 172:7d866c31b3c5 2109 #define TSB_INTIFSD_IDLEINT_155_INT155PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,4)))
AnnaBridge 172:7d866c31b3c5 2110 #define TSB_INTIFSD_IDLEINT_155_INT155NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,5)))
AnnaBridge 172:7d866c31b3c5 2111 #define TSB_INTIFSD_IDLEINT_155_INT155PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,6)))
AnnaBridge 172:7d866c31b3c5 2112 #define TSB_INTIFSD_IDLEINT_155_INT155NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,7)))
AnnaBridge 172:7d866c31b3c5 2113 #define TSB_INTIFSD_IDLEINT_156_INT156EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,0)))
AnnaBridge 172:7d866c31b3c5 2114 #define TSB_INTIFSD_IDLEINT_156_INT156PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,4)))
AnnaBridge 172:7d866c31b3c5 2115 #define TSB_INTIFSD_IDLEINT_156_INT156NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,5)))
AnnaBridge 172:7d866c31b3c5 2116 #define TSB_INTIFSD_IDLEINT_156_INT156PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,6)))
AnnaBridge 172:7d866c31b3c5 2117 #define TSB_INTIFSD_IDLEINT_156_INT156NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,7)))
AnnaBridge 172:7d866c31b3c5 2118 #define TSB_INTIFSD_IDLEINT_157_INT157EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,0)))
AnnaBridge 172:7d866c31b3c5 2119 #define TSB_INTIFSD_IDLEINT_157_INT157PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,4)))
AnnaBridge 172:7d866c31b3c5 2120 #define TSB_INTIFSD_IDLEINT_157_INT157NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,5)))
AnnaBridge 172:7d866c31b3c5 2121 #define TSB_INTIFSD_IDLEINT_157_INT157PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,6)))
AnnaBridge 172:7d866c31b3c5 2122 #define TSB_INTIFSD_IDLEINT_157_INT157NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,7)))
AnnaBridge 172:7d866c31b3c5 2123 #define TSB_INTIFSD_IDLEINT_158_INT158EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,0)))
AnnaBridge 172:7d866c31b3c5 2124 #define TSB_INTIFSD_IDLEINT_158_INT158PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,4)))
AnnaBridge 172:7d866c31b3c5 2125 #define TSB_INTIFSD_IDLEINT_158_INT158NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,5)))
AnnaBridge 172:7d866c31b3c5 2126 #define TSB_INTIFSD_IDLEINT_158_INT158PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,6)))
AnnaBridge 172:7d866c31b3c5 2127 #define TSB_INTIFSD_IDLEINT_158_INT158NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,7)))
AnnaBridge 172:7d866c31b3c5 2128 #define TSB_INTIFSD_IDLEINT_159_INT159EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,0)))
AnnaBridge 172:7d866c31b3c5 2129 #define TSB_INTIFSD_IDLEINT_159_INT159PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,4)))
AnnaBridge 172:7d866c31b3c5 2130 #define TSB_INTIFSD_IDLEINT_159_INT159NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,5)))
AnnaBridge 172:7d866c31b3c5 2131 #define TSB_INTIFSD_IDLEINT_159_INT159PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,6)))
AnnaBridge 172:7d866c31b3c5 2132 #define TSB_INTIFSD_IDLEINT_159_INT159NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,7)))
AnnaBridge 172:7d866c31b3c5 2133 #define TSB_INTIFSD_IDLEINT_160_INT160EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,0)))
AnnaBridge 172:7d866c31b3c5 2134 #define TSB_INTIFSD_IDLEINT_160_INT160PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,4)))
AnnaBridge 172:7d866c31b3c5 2135 #define TSB_INTIFSD_IDLEINT_160_INT160NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,5)))
AnnaBridge 172:7d866c31b3c5 2136 #define TSB_INTIFSD_IDLEINT_160_INT160PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,6)))
AnnaBridge 172:7d866c31b3c5 2137 #define TSB_INTIFSD_IDLEINT_160_INT160NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,7)))
AnnaBridge 172:7d866c31b3c5 2138 #define TSB_INTIFSD_IDLEINT_161_INT161EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,0)))
AnnaBridge 172:7d866c31b3c5 2139 #define TSB_INTIFSD_IDLEINT_161_INT161PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,4)))
AnnaBridge 172:7d866c31b3c5 2140 #define TSB_INTIFSD_IDLEINT_161_INT161NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,5)))
AnnaBridge 172:7d866c31b3c5 2141 #define TSB_INTIFSD_IDLEINT_161_INT161PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,6)))
AnnaBridge 172:7d866c31b3c5 2142 #define TSB_INTIFSD_IDLEINT_161_INT161NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,7)))
AnnaBridge 172:7d866c31b3c5 2143 #define TSB_INTIFSD_IDLEINT_162_INT162EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,0)))
AnnaBridge 172:7d866c31b3c5 2144 #define TSB_INTIFSD_IDLEINT_162_INT162PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,4)))
AnnaBridge 172:7d866c31b3c5 2145 #define TSB_INTIFSD_IDLEINT_162_INT162NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,5)))
AnnaBridge 172:7d866c31b3c5 2146 #define TSB_INTIFSD_IDLEINT_162_INT162PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,6)))
AnnaBridge 172:7d866c31b3c5 2147 #define TSB_INTIFSD_IDLEINT_162_INT162NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,7)))
AnnaBridge 172:7d866c31b3c5 2148 #define TSB_INTIFSD_IDLEINT_163_INT163EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,0)))
AnnaBridge 172:7d866c31b3c5 2149 #define TSB_INTIFSD_IDLEINT_163_INT163PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,4)))
AnnaBridge 172:7d866c31b3c5 2150 #define TSB_INTIFSD_IDLEINT_163_INT163NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,5)))
AnnaBridge 172:7d866c31b3c5 2151 #define TSB_INTIFSD_IDLEINT_163_INT163PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,6)))
AnnaBridge 172:7d866c31b3c5 2152 #define TSB_INTIFSD_IDLEINT_163_INT163NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,7)))
AnnaBridge 172:7d866c31b3c5 2153 #define TSB_INTIFSD_IDLEINT_164_INT164EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,0)))
AnnaBridge 172:7d866c31b3c5 2154 #define TSB_INTIFSD_IDLEINT_164_INT164PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,4)))
AnnaBridge 172:7d866c31b3c5 2155 #define TSB_INTIFSD_IDLEINT_164_INT164NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,5)))
AnnaBridge 172:7d866c31b3c5 2156 #define TSB_INTIFSD_IDLEINT_164_INT164PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,6)))
AnnaBridge 172:7d866c31b3c5 2157 #define TSB_INTIFSD_IDLEINT_164_INT164NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,7)))
AnnaBridge 172:7d866c31b3c5 2158 #define TSB_INTIFSD_IDLEINT_165_INT165EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,0)))
AnnaBridge 172:7d866c31b3c5 2159 #define TSB_INTIFSD_IDLEINT_165_INT165PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,4)))
AnnaBridge 172:7d866c31b3c5 2160 #define TSB_INTIFSD_IDLEINT_165_INT165NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,5)))
AnnaBridge 172:7d866c31b3c5 2161 #define TSB_INTIFSD_IDLEINT_165_INT165PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,6)))
AnnaBridge 172:7d866c31b3c5 2162 #define TSB_INTIFSD_IDLEINT_165_INT165NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,7)))
AnnaBridge 172:7d866c31b3c5 2163 #define TSB_INTIFSD_IDLEINT_166_INT166EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,0)))
AnnaBridge 172:7d866c31b3c5 2164 #define TSB_INTIFSD_IDLEINT_166_INT166PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,4)))
AnnaBridge 172:7d866c31b3c5 2165 #define TSB_INTIFSD_IDLEINT_166_INT166NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,5)))
AnnaBridge 172:7d866c31b3c5 2166 #define TSB_INTIFSD_IDLEINT_166_INT166PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,6)))
AnnaBridge 172:7d866c31b3c5 2167 #define TSB_INTIFSD_IDLEINT_166_INT166NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,7)))
AnnaBridge 172:7d866c31b3c5 2168 #define TSB_INTIFSD_IDLEINT_167_INT167EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,0)))
AnnaBridge 172:7d866c31b3c5 2169 #define TSB_INTIFSD_IDLEINT_167_INT167PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,4)))
AnnaBridge 172:7d866c31b3c5 2170 #define TSB_INTIFSD_IDLEINT_167_INT167NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,5)))
AnnaBridge 172:7d866c31b3c5 2171 #define TSB_INTIFSD_IDLEINT_167_INT167PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,6)))
AnnaBridge 172:7d866c31b3c5 2172 #define TSB_INTIFSD_IDLEINT_167_INT167NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,7)))
AnnaBridge 172:7d866c31b3c5 2173 #define TSB_INTIFSD_IDLEINT_168_INT168EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,0)))
AnnaBridge 172:7d866c31b3c5 2174 #define TSB_INTIFSD_IDLEINT_168_INT168PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,4)))
AnnaBridge 172:7d866c31b3c5 2175 #define TSB_INTIFSD_IDLEINT_168_INT168NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,5)))
AnnaBridge 172:7d866c31b3c5 2176 #define TSB_INTIFSD_IDLEINT_168_INT168PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,6)))
AnnaBridge 172:7d866c31b3c5 2177 #define TSB_INTIFSD_IDLEINT_168_INT168NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,7)))
AnnaBridge 172:7d866c31b3c5 2178 #define TSB_INTIFSD_IDLEINT_169_INT169EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,0)))
AnnaBridge 172:7d866c31b3c5 2179 #define TSB_INTIFSD_IDLEINT_169_INT169PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,4)))
AnnaBridge 172:7d866c31b3c5 2180 #define TSB_INTIFSD_IDLEINT_169_INT169NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,5)))
AnnaBridge 172:7d866c31b3c5 2181 #define TSB_INTIFSD_IDLEINT_169_INT169PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,6)))
AnnaBridge 172:7d866c31b3c5 2182 #define TSB_INTIFSD_IDLEINT_169_INT169NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,7)))
AnnaBridge 172:7d866c31b3c5 2183 #define TSB_INTIFSD_FLAG0_INT16FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,16)))
AnnaBridge 172:7d866c31b3c5 2184 #define TSB_INTIFSD_FLAG0_INT17FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,17)))
AnnaBridge 172:7d866c31b3c5 2185 #define TSB_INTIFSD_FLAG0_INT18FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,18)))
AnnaBridge 172:7d866c31b3c5 2186 #define TSB_INTIFSD_FLAG1_INT32FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,0)))
AnnaBridge 172:7d866c31b3c5 2187 #define TSB_INTIFSD_FLAG1_INT33FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,1)))
AnnaBridge 172:7d866c31b3c5 2188 #define TSB_INTIFSD_FLAG1_INT34FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,2)))
AnnaBridge 172:7d866c31b3c5 2189 #define TSB_INTIFSD_FLAG1_INT35FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,3)))
AnnaBridge 172:7d866c31b3c5 2190 #define TSB_INTIFSD_FLAG1_INT36FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,4)))
AnnaBridge 172:7d866c31b3c5 2191 #define TSB_INTIFSD_FLAG1_INT37FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,5)))
AnnaBridge 172:7d866c31b3c5 2192 #define TSB_INTIFSD_FLAG1_INT38FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,6)))
AnnaBridge 172:7d866c31b3c5 2193 #define TSB_INTIFSD_FLAG1_INT39FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,7)))
AnnaBridge 172:7d866c31b3c5 2194 #define TSB_INTIFSD_FLAG3_INT96FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,0)))
AnnaBridge 172:7d866c31b3c5 2195 #define TSB_INTIFSD_FLAG3_INT97FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,1)))
AnnaBridge 172:7d866c31b3c5 2196 #define TSB_INTIFSD_FLAG3_INT98FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,2)))
AnnaBridge 172:7d866c31b3c5 2197 #define TSB_INTIFSD_FLAG3_INT99FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,3)))
AnnaBridge 172:7d866c31b3c5 2198 #define TSB_INTIFSD_FLAG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,4)))
AnnaBridge 172:7d866c31b3c5 2199 #define TSB_INTIFSD_FLAG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,5)))
AnnaBridge 172:7d866c31b3c5 2200 #define TSB_INTIFSD_FLAG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,6)))
AnnaBridge 172:7d866c31b3c5 2201 #define TSB_INTIFSD_FLAG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,7)))
AnnaBridge 172:7d866c31b3c5 2202 #define TSB_INTIFSD_FLAG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,8)))
AnnaBridge 172:7d866c31b3c5 2203 #define TSB_INTIFSD_FLAG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,9)))
AnnaBridge 172:7d866c31b3c5 2204 #define TSB_INTIFSD_FLAG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,10)))
AnnaBridge 172:7d866c31b3c5 2205 #define TSB_INTIFSD_FLAG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,11)))
AnnaBridge 172:7d866c31b3c5 2206 #define TSB_INTIFSD_FLAG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,12)))
AnnaBridge 172:7d866c31b3c5 2207 #define TSB_INTIFSD_FLAG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,13)))
AnnaBridge 172:7d866c31b3c5 2208 #define TSB_INTIFSD_FLAG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,14)))
AnnaBridge 172:7d866c31b3c5 2209 #define TSB_INTIFSD_FLAG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,15)))
AnnaBridge 172:7d866c31b3c5 2210 #define TSB_INTIFSD_FLAG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,16)))
AnnaBridge 172:7d866c31b3c5 2211 #define TSB_INTIFSD_FLAG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,17)))
AnnaBridge 172:7d866c31b3c5 2212 #define TSB_INTIFSD_FLAG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,18)))
AnnaBridge 172:7d866c31b3c5 2213 #define TSB_INTIFSD_FLAG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,19)))
AnnaBridge 172:7d866c31b3c5 2214 #define TSB_INTIFSD_FLAG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,20)))
AnnaBridge 172:7d866c31b3c5 2215 #define TSB_INTIFSD_FLAG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,21)))
AnnaBridge 172:7d866c31b3c5 2216 #define TSB_INTIFSD_FLAG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,22)))
AnnaBridge 172:7d866c31b3c5 2217 #define TSB_INTIFSD_FLAG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,23)))
AnnaBridge 172:7d866c31b3c5 2218 #define TSB_INTIFSD_FLAG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,24)))
AnnaBridge 172:7d866c31b3c5 2219 #define TSB_INTIFSD_FLAG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,25)))
AnnaBridge 172:7d866c31b3c5 2220 #define TSB_INTIFSD_FLAG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,26)))
AnnaBridge 172:7d866c31b3c5 2221 #define TSB_INTIFSD_FLAG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,27)))
AnnaBridge 172:7d866c31b3c5 2222 #define TSB_INTIFSD_FLAG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,28)))
AnnaBridge 172:7d866c31b3c5 2223 #define TSB_INTIFSD_FLAG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,29)))
AnnaBridge 172:7d866c31b3c5 2224 #define TSB_INTIFSD_FLAG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,30)))
AnnaBridge 172:7d866c31b3c5 2225 #define TSB_INTIFSD_FLAG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,31)))
AnnaBridge 172:7d866c31b3c5 2226 #define TSB_INTIFSD_FLAG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,0)))
AnnaBridge 172:7d866c31b3c5 2227 #define TSB_INTIFSD_FLAG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,1)))
AnnaBridge 172:7d866c31b3c5 2228 #define TSB_INTIFSD_FLAG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,2)))
AnnaBridge 172:7d866c31b3c5 2229 #define TSB_INTIFSD_FLAG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,3)))
AnnaBridge 172:7d866c31b3c5 2230 #define TSB_INTIFSD_FLAG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,4)))
AnnaBridge 172:7d866c31b3c5 2231 #define TSB_INTIFSD_FLAG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,5)))
AnnaBridge 172:7d866c31b3c5 2232 #define TSB_INTIFSD_FLAG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,6)))
AnnaBridge 172:7d866c31b3c5 2233 #define TSB_INTIFSD_FLAG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,7)))
AnnaBridge 172:7d866c31b3c5 2234 #define TSB_INTIFSD_FLAG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,8)))
AnnaBridge 172:7d866c31b3c5 2235 #define TSB_INTIFSD_FLAG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,9)))
AnnaBridge 172:7d866c31b3c5 2236 #define TSB_INTIFSD_FLAG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,10)))
AnnaBridge 172:7d866c31b3c5 2237 #define TSB_INTIFSD_FLAG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,11)))
AnnaBridge 172:7d866c31b3c5 2238 #define TSB_INTIFSD_FLAG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,12)))
AnnaBridge 172:7d866c31b3c5 2239 #define TSB_INTIFSD_FLAG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,13)))
AnnaBridge 172:7d866c31b3c5 2240 #define TSB_INTIFSD_FLAG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,14)))
AnnaBridge 172:7d866c31b3c5 2241 #define TSB_INTIFSD_FLAG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,15)))
AnnaBridge 172:7d866c31b3c5 2242 #define TSB_INTIFSD_FLAG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,16)))
AnnaBridge 172:7d866c31b3c5 2243 #define TSB_INTIFSD_FLAG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,17)))
AnnaBridge 172:7d866c31b3c5 2244 #define TSB_INTIFSD_FLAG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,18)))
AnnaBridge 172:7d866c31b3c5 2245 #define TSB_INTIFSD_FLAG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,19)))
AnnaBridge 172:7d866c31b3c5 2246 #define TSB_INTIFSD_FLAG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,20)))
AnnaBridge 172:7d866c31b3c5 2247 #define TSB_INTIFSD_FLAG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,21)))
AnnaBridge 172:7d866c31b3c5 2248 #define TSB_INTIFSD_FLAG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,22)))
AnnaBridge 172:7d866c31b3c5 2249 #define TSB_INTIFSD_FLAG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,23)))
AnnaBridge 172:7d866c31b3c5 2250 #define TSB_INTIFSD_FLAG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,24)))
AnnaBridge 172:7d866c31b3c5 2251 #define TSB_INTIFSD_FLAG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,0)))
AnnaBridge 172:7d866c31b3c5 2252 #define TSB_INTIFSD_FLAG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,1)))
AnnaBridge 172:7d866c31b3c5 2253 #define TSB_INTIFSD_FLAG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,2)))
AnnaBridge 172:7d866c31b3c5 2254 #define TSB_INTIFSD_FLAG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,3)))
AnnaBridge 172:7d866c31b3c5 2255 #define TSB_INTIFSD_FLAG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,4)))
AnnaBridge 172:7d866c31b3c5 2256 #define TSB_INTIFSD_FLAG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,5)))
AnnaBridge 172:7d866c31b3c5 2257 #define TSB_INTIFSD_FLAG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,6)))
AnnaBridge 172:7d866c31b3c5 2258 #define TSB_INTIFSD_FLAG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,7)))
AnnaBridge 172:7d866c31b3c5 2259 #define TSB_INTIFSD_FLAG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,8)))
AnnaBridge 172:7d866c31b3c5 2260 #define TSB_INTIFSD_FLAG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,9)))
AnnaBridge 172:7d866c31b3c5 2261
AnnaBridge 172:7d866c31b3c5 2262
AnnaBridge 172:7d866c31b3c5 2263 /* ADC */
AnnaBridge 172:7d866c31b3c5 2264 #define TSB_AD_MOD1_I2AD (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,6)))
AnnaBridge 172:7d866c31b3c5 2265 #define TSB_AD_MOD1_VREFON (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,7)))
AnnaBridge 172:7d866c31b3c5 2266 #define TSB_AD_MOD3_ADOBSV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD3,0)))
AnnaBridge 172:7d866c31b3c5 2267 #define TSB_AD_MOD3_ADOBIC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD3,5)))
AnnaBridge 172:7d866c31b3c5 2268 #define TSB_AD_MOD4_ADHTG (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,4)))
AnnaBridge 172:7d866c31b3c5 2269 #define TSB_AD_MOD4_ADHS (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,5)))
AnnaBridge 172:7d866c31b3c5 2270 #define TSB_AD_MOD4_HADHTG (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,6)))
AnnaBridge 172:7d866c31b3c5 2271 #define TSB_AD_MOD4_HADHS (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,7)))
AnnaBridge 172:7d866c31b3c5 2272 #define TSB_AD_MOD5_ADOBSV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD5,0)))
AnnaBridge 172:7d866c31b3c5 2273 #define TSB_AD_MOD5_ADOBIC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD5,5)))
AnnaBridge 172:7d866c31b3c5 2274 #define TSB_AD_MOD6_ADDMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,0)))
AnnaBridge 172:7d866c31b3c5 2275 #define TSB_AD_MOD6_ADHPDMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,1)))
AnnaBridge 172:7d866c31b3c5 2276 #define TSB_AD_MOD6_ADM0DMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,2)))
AnnaBridge 172:7d866c31b3c5 2277 #define TSB_AD_MOD6_ADM1DMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,3)))
AnnaBridge 172:7d866c31b3c5 2278
AnnaBridge 172:7d866c31b3c5 2279 /** @} *//* End of group Device_Peripheral_registers */
AnnaBridge 172:7d866c31b3c5 2280
AnnaBridge 172:7d866c31b3c5 2281 #ifdef __cplusplus
AnnaBridge 172:7d866c31b3c5 2282 }
AnnaBridge 172:7d866c31b3c5 2283 #endif
AnnaBridge 172:7d866c31b3c5 2284 #endif /* __TMPM066_H__ */
AnnaBridge 172:7d866c31b3c5 2285
AnnaBridge 172:7d866c31b3c5 2286 /** @} *//* End of group TMPM066 */
AnnaBridge 172:7d866c31b3c5 2287 /** @} *//* End of group TOSHIBA_TX00_MICROCONTROLLER */