FT_Gpu_Hal.cpp

00001 /* mbed Library for FTDI FT800  Enbedded Video Engine "EVE"
00002  * based on Original Code Sample from FTDI
00003  * ported to mbed by Peter Drescher, DC2PD 2014
00004  * Released under the MIT License: http://mbed.org/license/mit 
00005  * 19.09.14 changed to shorter function names  
00006  * FTDI was using very long names. 
00007  * Ft_App_Flush_Co_Buffer -> Flush_Co_Buffer ...  */
00008 
00009 #include "FT_Platform.h"
00010 #include "mbed.h"
00011 #include "FT_LCD_Type.h"
00012 
00013 FT800::FT800(PinName mosi,
00014             PinName miso,
00015             PinName sck,
00016             PinName ss,
00017             PinName intr,
00018             PinName pd)
00019     :_spi(mosi, miso, sck),
00020      _ss(ss),
00021      _f800_isr(InterruptIn(intr)),
00022      _pd(pd)
00023      {
00024          _spi.format(8,0);                  // 8 bit spi mode 0
00025          _spi.frequency(10000000);          // start with 10 Mhz SPI clock
00026          _ss = 1;                           // cs high
00027          _pd = 1;                           // PD high
00028          Bootup();
00029      }
00030 
00031 
00032 ft_bool_t FT800::Bootup(void){
00033     Open();
00034     BootupConfig();
00035 
00036     return(1);
00037     }
00038 
00039 
00040 ft_void_t FT800::BootupConfig(void){
00041     ft_uint8_t chipid;
00042     /* Do a power cycle for safer side */
00043     Powercycle( FT_TRUE);
00044 
00045     /* Access address 0 to wake up the FT800 */
00046     HostCommand( FT_GPU_ACTIVE_M);
00047     Sleep(20);
00048 
00049     /* Set the clk to external clock */
00050     HostCommand( FT_GPU_EXTERNAL_OSC);
00051     Sleep(10);
00052 
00053 
00054     /* Switch PLL output to 48MHz */
00055     HostCommand( FT_GPU_PLL_48M);
00056     Sleep(10);
00057 
00058     /* Do a core reset for safer side */
00059     HostCommand( FT_GPU_CORE_RESET);
00060 
00061     //Read Register ID to check if FT800 is ready.
00062     chipid = Rd8(  REG_ID);
00063     while(chipid != 0x7C)
00064         chipid = Rd8(  REG_ID);
00065 
00066 
00067     // Speed up
00068     _spi.frequency(16000000);           // 20 Mhz SPI clock
00069 
00070     /* Configuration of LCD display */
00071     DispHCycle = my_DispHCycle;
00072     Wr16(  REG_HCYCLE, DispHCycle);
00073     DispHOffset = my_DispHOffset;
00074     Wr16(  REG_HOFFSET, DispHOffset);
00075     DispWidth = my_DispWidth;
00076     Wr16(  REG_HSIZE, DispWidth);
00077     DispHSync0 = my_DispHSync0;
00078     Wr16(  REG_HSYNC0, DispHSync0);
00079     DispHSync1 = my_DispHSync1;
00080     Wr16(  REG_HSYNC1, DispHSync1);
00081     DispVCycle = my_DispVCycle;
00082     Wr16(  REG_VCYCLE, DispVCycle);
00083     DispVOffset = my_DispVOffset;
00084     Wr16(  REG_VOFFSET, DispVOffset);
00085     DispHeight = my_DispHeight;
00086     Wr16(  REG_VSIZE, DispHeight);
00087     DispVSync0 = my_DispVSync0;
00088     Wr16(  REG_VSYNC0, DispVSync0);
00089     DispVSync1 = my_DispVSync1;
00090     Wr16(  REG_VSYNC1, DispVSync1);
00091     DispSwizzle = my_DispSwizzle;
00092     Wr8(  REG_SWIZZLE, DispSwizzle);
00093     DispPCLKPol = my_DispPCLKPol;
00094     Wr8(  REG_PCLK_POL, DispPCLKPol);
00095     Wr8(  REG_CSPREAD, 1);
00096     DispPCLK = my_DispPCLK;
00097     Wr8(  REG_PCLK, DispPCLK);//after this display is visible on the LCD
00098 
00099     Wr16(  REG_PWM_HZ, 1000);
00100 
00101 #ifdef Inv_Backlite               // turn on backlite
00102     Wr16(  REG_PWM_DUTY, 0);
00103 #else
00104     Wr16(  REG_PWM_DUTY, 100);
00105 #endif
00106 
00107     Wr8(  REG_GPIO_DIR,0x82);  //| Rd8( REG_GPIO_DIR));
00108     Wr8(  REG_GPIO,0x080);     //| Rd8( REG_GPIO));
00109 
00110     Wr32(  RAM_DL, CLEAR(1,1,1));
00111     Wr32(  RAM_DL+4, DISPLAY());
00112     Wr32(  REG_DLSWAP,1);
00113 
00114     Wr16(  REG_PCLK, DispPCLK);
00115 
00116     /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
00117     Wr16(  REG_TOUCH_RZTHRESH,1200);
00118 
00119 }
00120 
00121 
00122 
00123 /* API to initialize the SPI interface */
00124 ft_bool_t  FT800::Init()
00125 {
00126     // is done in constructor
00127     return 1;
00128 }
00129 
00130 
00131 ft_bool_t  FT800::Open()
00132 {
00133     cmd_fifo_wp = dl_buff_wp = 0;
00134     status = OPENED;
00135     return 1;
00136 }
00137 
00138 ft_void_t  FT800::Close( )
00139 {
00140     status = CLOSED;
00141 }
00142 
00143 ft_void_t FT800::DeInit()
00144 {
00145 
00146 }
00147 
00148 /*The APIs for reading/writing transfer continuously only with small buffer system*/
00149 ft_void_t  FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
00150 {
00151     if (FT_GPU_READ == rw){
00152         _ss = 0;       // cs low
00153         _spi.write(addr >> 16);
00154         _spi.write(addr >> 8);
00155         _spi.write(addr & 0xff);
00156         _spi.write(0); //Dummy Read Byte
00157         status = READING;
00158     }else{
00159         _ss = 0;       // cs low
00160         _spi.write(0x80 | (addr >> 16));
00161         _spi.write(addr >> 8);
00162         _spi.write(addr & 0xff);
00163         status = WRITING;
00164     }
00165 }
00166 
00167 
00168 /*The APIs for writing transfer continuously only*/
00169 ft_void_t  FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
00170 {
00171     StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
00172 }
00173 
00174 ft_uint8_t  FT800::TransferString( const ft_char8_t *string)
00175 {
00176     ft_uint16_t length = strlen(string);
00177     while(length --){
00178        Transfer8( *string);
00179        string ++;
00180     }
00181     //Append one null as ending flag
00182     Transfer8( 0);
00183     return(1);
00184 }
00185 
00186 
00187 ft_uint8_t  FT800::Transfer8( ft_uint8_t value)
00188 {
00189         return _spi.write(value);
00190 }
00191 
00192 
00193 ft_uint16_t  FT800::Transfer16( ft_uint16_t value)
00194 {
00195     ft_uint16_t retVal = 0;
00196 
00197         if (status == WRITING){
00198         Transfer8( value & 0xFF);//LSB first
00199         Transfer8( (value >> 8) & 0xFF);
00200     }else{
00201         retVal = Transfer8( 0);
00202         retVal |= (ft_uint16_t)Transfer8( 0) << 8;
00203     }
00204 
00205     return retVal;
00206 }
00207 
00208 ft_uint32_t  FT800::Transfer32( ft_uint32_t value)
00209 {
00210     ft_uint32_t retVal = 0;
00211     if (status == WRITING){
00212         Transfer16( value & 0xFFFF);//LSB first
00213         Transfer16( (value >> 16) & 0xFFFF);
00214     }else{
00215         retVal = Transfer16( 0);
00216         retVal |= (ft_uint32_t)Transfer16( 0) << 16;
00217     }
00218     return retVal;
00219 }
00220 
00221 ft_void_t   FT800::EndTransfer( )
00222 {
00223     _ss = 1;
00224     status = OPENED;
00225 }
00226 
00227 
00228 ft_uint8_t  FT800::Rd8( ft_uint32_t addr)
00229 {
00230     ft_uint8_t value;
00231     StartTransfer( FT_GPU_READ,addr);
00232     value = Transfer8( 0);
00233     EndTransfer( );
00234     return value;
00235 }
00236 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
00237 {
00238     ft_uint16_t value;
00239     StartTransfer( FT_GPU_READ,addr);
00240     value = Transfer16( 0);
00241     EndTransfer( );
00242     return value;
00243 }
00244 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
00245 {
00246     ft_uint32_t value;
00247     StartTransfer( FT_GPU_READ,addr);
00248     value = Transfer32( 0);
00249     EndTransfer( );
00250     return value;
00251 }
00252 
00253 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
00254 {
00255     StartTransfer( FT_GPU_WRITE,addr);
00256     Transfer8( v);
00257     EndTransfer( );
00258 }
00259 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
00260 {
00261     StartTransfer( FT_GPU_WRITE,addr);
00262     Transfer16( v);
00263     EndTransfer( );
00264 }
00265 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
00266 {
00267     StartTransfer( FT_GPU_WRITE,addr);
00268     Transfer32( v);
00269     EndTransfer( );
00270 }
00271 
00272 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
00273 {
00274   _ss = 0;
00275   _spi.write(cmd);
00276   _spi.write(0);
00277   _spi.write(0);
00278   _ss = 1;
00279 }
00280 
00281 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
00282 {
00283    HostCommand( pllsource);
00284 }
00285 
00286 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
00287 {
00288    HostCommand( freq);
00289 }
00290 
00291 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
00292 {
00293    HostCommand( pwrmode);
00294 }
00295 
00296 ft_void_t FT800::CoreReset( )
00297 {
00298    HostCommand( 0x68);
00299 }
00300 
00301 
00302 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
00303 {
00304      cmd_fifo_wp  = ( cmd_fifo_wp + count) & 4095;
00305     //4 byte alignment
00306      cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
00307     Wr16( REG_CMD_WRITE, cmd_fifo_wp);
00308 }
00309 
00310 
00311 ft_uint16_t FT800::fifo_Freespace( )
00312 {
00313     ft_uint16_t fullness,retval;
00314 
00315     fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
00316     retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
00317     return (retval);
00318 }
00319 
00320 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
00321 {
00322     ft_uint32_t length =0, SizeTransfered = 0;
00323 
00324 #define MAX_CMD_FIFO_TRANSFER   fifo_Freespace( )
00325     do {
00326         length = count;
00327         if (length > MAX_CMD_FIFO_TRANSFER){
00328             length = MAX_CMD_FIFO_TRANSFER;
00329         }
00330                 CheckCmdBuffer( length);
00331 
00332                 StartCmdTransfer( FT_GPU_WRITE,length);
00333 
00334                 SizeTransfered = 0;
00335         while (length--) {
00336                     Transfer8( *buffer);
00337                     buffer++;
00338                     SizeTransfered ++;
00339         }
00340                 length = SizeTransfered;
00341 
00342         EndTransfer( );
00343         Updatecmdfifo( length);
00344 
00345         WaitCmdfifo_empty( );
00346 
00347         count -= length;
00348     }while (count > 0);
00349 }
00350 
00351 
00352 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
00353 {
00354     ft_uint32_t length =0, SizeTransfered = 0;
00355 
00356 #define MAX_CMD_FIFO_TRANSFER   fifo_Freespace( )
00357     do {
00358         length = count;
00359         if (length > MAX_CMD_FIFO_TRANSFER){
00360             length = MAX_CMD_FIFO_TRANSFER;
00361         }
00362                 CheckCmdBuffer( length);
00363 
00364                 StartCmdTransfer( FT_GPU_WRITE,length);
00365 
00366 
00367                 SizeTransfered = 0;
00368         while (length--) {
00369                     Transfer8( ft_pgm_read_byte_near(buffer));
00370             buffer++;
00371                     SizeTransfered ++;
00372         }
00373                 length = SizeTransfered;
00374 
00375                 EndTransfer( );
00376         Updatecmdfifo( length);
00377 
00378         WaitCmdfifo_empty( );
00379 
00380         count -= length;
00381     }while (count > 0);
00382 }
00383 
00384 
00385 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
00386 {
00387    ft_uint16_t getfreespace;
00388    do{
00389         getfreespace = fifo_Freespace( );
00390    }while(getfreespace < count);
00391 }
00392 
00393 ft_void_t FT800::WaitCmdfifo_empty( )
00394 {
00395    while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
00396 
00397     cmd_fifo_wp = Rd16( REG_CMD_WRITE);
00398 }
00399 
00400 ft_void_t FT800::WaitLogo_Finish( )
00401 {
00402     ft_int16_t cmdrdptr,cmdwrptr;
00403 
00404     do{
00405          cmdrdptr = Rd16( REG_CMD_READ);
00406          cmdwrptr = Rd16( REG_CMD_WRITE);
00407     }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
00408      cmd_fifo_wp = 0;
00409 }
00410 
00411 
00412 ft_void_t FT800::ResetCmdFifo( )
00413 {
00414     cmd_fifo_wp = 0;
00415 }
00416 
00417 
00418 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
00419 {
00420          CheckCmdBuffer( sizeof(cmd));
00421 
00422          Wr32( RAM_CMD +  cmd_fifo_wp,cmd);
00423 
00424          Updatecmdfifo( sizeof(cmd));
00425 }
00426 
00427 
00428 ft_void_t FT800::ResetDLBuffer( )
00429 {
00430             dl_buff_wp = 0;
00431 }
00432 
00433 /* Toggle PD_N pin of FT800 board for a power cycle*/
00434 ft_void_t FT800::Powercycle(  ft_bool_t up)
00435 {
00436     if (up)
00437     {
00438              //Toggle PD_N from low to high for power up switch
00439             _pd = 0;
00440             Sleep(20);
00441 
00442             _pd = 1;
00443             Sleep(20);
00444     }else
00445     {
00446              //Toggle PD_N from high to low for power down switch
00447             _pd = 1;
00448             Sleep(20);
00449 
00450             _pd = 0;
00451             Sleep(20);
00452     }
00453 }
00454 
00455 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
00456 {
00457     //ft_uint32_t SizeTransfered = 0;
00458 
00459     StartTransfer( FT_GPU_WRITE,addr);
00460 
00461     while (length--) {
00462             Transfer8( ft_pgm_read_byte_near(buffer));
00463         buffer++;
00464     }
00465 
00466     EndTransfer( );
00467 }
00468 
00469 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
00470 {
00471     //ft_uint32_t SizeTransfered = 0;
00472 
00473     StartTransfer( FT_GPU_WRITE,addr);
00474 
00475     while (length--) {
00476             Transfer8( *buffer);
00477         buffer++;
00478     }
00479 
00480     EndTransfer( );
00481 }
00482 
00483 
00484 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
00485 {
00486     //ft_uint32_t SizeTransfered = 0;
00487 
00488     StartTransfer( FT_GPU_READ,addr);
00489 
00490     while (length--) {
00491        *buffer = Transfer8( 0);
00492        buffer++;
00493     }
00494 
00495     EndTransfer( );
00496 }
00497 
00498 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
00499 {
00500     ft_int16_t Length;
00501     ft_char8_t *pdst,charval;
00502     ft_int32_t CurrVal = value,tmpval,i;
00503     ft_char8_t tmparray[16],idx = 0;
00504 
00505     Length = strlen(pSrc);
00506     pdst = pSrc + Length;
00507 
00508     if(0 == value)
00509     {
00510         *pdst++ = '0';
00511         *pdst++ = '\0';
00512         return 0;
00513     }
00514 
00515     if(CurrVal < 0)
00516     {
00517         *pdst++ = '-';
00518         CurrVal = - CurrVal;
00519     }
00520     /* insert the value */
00521     while(CurrVal > 0){
00522         tmpval = CurrVal;
00523         CurrVal /= 10;
00524         tmpval = tmpval - CurrVal*10;
00525         charval = '0' + tmpval;
00526         tmparray[idx++] = charval;
00527     }
00528 
00529     for(i=0;i<idx;i++)
00530     {
00531         *pdst++ = tmparray[idx - i - 1];
00532     }
00533     *pdst++ = '\0';
00534 
00535     return 0;
00536 }
00537 
00538 
00539 ft_void_t FT800::Sleep(ft_uint16_t ms)
00540 {
00541     wait_ms(ms);
00542 }
00543 
00544 ft_void_t FT800::Sound_ON(){
00545      Wr8(  REG_GPIO, 0x02 | Rd8( REG_GPIO));
00546 }
00547 
00548 ft_void_t FT800::Sound_OFF(){
00549      Wr8(  REG_GPIO, 0xFD & Rd8( REG_GPIO));
00550 }
00551