Andrew SaLoutos / ICM_20948

Modified Arduino library for ICM_20948 IMU for Nucleo boards

util/ICM_20948_ENUMERATIONS.h@0:894b603d32ee, 2022-01-31 (annotated)

Committer:
saloutos
Date:
Mon Jan 31 03:25:31 2022 +0000
Revision:
0:894b603d32ee
modified ICM_20948 Arduino library for Nucleo boards

Who changed what in which revision?

UserRevisionLine numberNew contents of line
saloutos 0:894b603d32ee 1 /*
saloutos 0:894b603d32ee 2
saloutos 0:894b603d32ee 3 This file contains a useful c translation of the datasheet register map values
saloutos 0:894b603d32ee 4
saloutos 0:894b603d32ee 5 */
saloutos 0:894b603d32ee 6
saloutos 0:894b603d32ee 7 #ifndef _ICM_20948_ENUMERATIONS_H_
saloutos 0:894b603d32ee 8 #define _ICM_20948_ENUMERATIONS_H_
saloutos 0:894b603d32ee 9
saloutos 0:894b603d32ee 10 #ifdef __cplusplus
saloutos 0:894b603d32ee 11 extern "C"
saloutos 0:894b603d32ee 12 {
saloutos 0:894b603d32ee 13 #endif /* __cplusplus */
saloutos 0:894b603d32ee 14
saloutos 0:894b603d32ee 15 // // Generalized
saloutos 0:894b603d32ee 16 // REG_BANK_SEL = 0x7F,
saloutos 0:894b603d32ee 17
saloutos 0:894b603d32ee 18 // // Gyroscope and Accelerometer
saloutos 0:894b603d32ee 19 // // User Bank 0
saloutos 0:894b603d32ee 20 // AGB0_REG_WHO_AM_I = 0x00,
saloutos 0:894b603d32ee 21 // // Break
saloutos 0:894b603d32ee 22 // AGB0_REG_USER_CTRL = 0x03,
saloutos 0:894b603d32ee 23 // // Break
saloutos 0:894b603d32ee 24 // AGB0_REG_LP_CONFIG = 0x05,
saloutos 0:894b603d32ee 25
saloutos 0:894b603d32ee 26 typedef enum
saloutos 0:894b603d32ee 27 {
saloutos 0:894b603d32ee 28 ICM_20948_Sample_Mode_Continuous = 0x00,
saloutos 0:894b603d32ee 29 ICM_20948_Sample_Mode_Cycled,
saloutos 0:894b603d32ee 30 } ICM_20948_LP_CONFIG_CYCLE_e;
saloutos 0:894b603d32ee 31
saloutos 0:894b603d32ee 32 // AGB0_REG_PWR_MGMT_1,
saloutos 0:894b603d32ee 33
saloutos 0:894b603d32ee 34 typedef enum
saloutos 0:894b603d32ee 35 {
saloutos 0:894b603d32ee 36 ICM_20948_Clock_Internal_20MHz = 0x00,
saloutos 0:894b603d32ee 37 ICM_20948_Clock_Auto,
saloutos 0:894b603d32ee 38 ICM_20948_Clock_TimingReset = 0x07
saloutos 0:894b603d32ee 39 } ICM_20948_PWR_MGMT_1_CLKSEL_e;
saloutos 0:894b603d32ee 40
saloutos 0:894b603d32ee 41 // AGB0_REG_PWR_MGMT_2,
saloutos 0:894b603d32ee 42 // // Break
saloutos 0:894b603d32ee 43 // AGB0_REG_INT_PIN_CONFIG = 0x0F,
saloutos 0:894b603d32ee 44 // AGB0_REG_INT_ENABLE,
saloutos 0:894b603d32ee 45 // AGB0_REG_INT_ENABLE_1,
saloutos 0:894b603d32ee 46 // AGB0_REG_INT_ENABLE_2,
saloutos 0:894b603d32ee 47 // AGB0_REG_INT_ENABLE_3,
saloutos 0:894b603d32ee 48 // // Break
saloutos 0:894b603d32ee 49 // AGB0_REG_I2C_MST_STATUS = 0x17,
saloutos 0:894b603d32ee 50 // // Break
saloutos 0:894b603d32ee 51 // AGB0_REG_INT_STATUS = 0x19,
saloutos 0:894b603d32ee 52 // AGB0_REG_INT_STATUS_1,
saloutos 0:894b603d32ee 53 // AGB0_REG_INT_STATUS_2,
saloutos 0:894b603d32ee 54 // AGB0_REG_INT_STATUS_3,
saloutos 0:894b603d32ee 55 // // Break
saloutos 0:894b603d32ee 56 // AGB0_REG_DELAY_TIMEH = 0x28,
saloutos 0:894b603d32ee 57 // AGB0_REG_DELAY_TIMEL,
saloutos 0:894b603d32ee 58 // // Break
saloutos 0:894b603d32ee 59 // AGB0_REG_ACCEL_XOUT_H = 0x2D,
saloutos 0:894b603d32ee 60 // AGB0_REG_ACCEL_XOUT_L,
saloutos 0:894b603d32ee 61 // AGB0_REG_ACCEL_YOUT_H,
saloutos 0:894b603d32ee 62 // AGB0_REG_ACCEL_YOUT_L,
saloutos 0:894b603d32ee 63 // AGB0_REG_ACCEL_ZOUT_H,
saloutos 0:894b603d32ee 64 // AGB0_REG_ACCEL_ZOUT_L,
saloutos 0:894b603d32ee 65 // AGB0_REG_GYRO_XOUT_H,
saloutos 0:894b603d32ee 66 // AGB0_REG_GYRO_XOUT_L,
saloutos 0:894b603d32ee 67 // AGB0_REG_GYRO_YOUT_H,
saloutos 0:894b603d32ee 68 // AGB0_REG_GYRO_YOUT_L,
saloutos 0:894b603d32ee 69 // AGB0_REG_GYRO_ZOUT_H,
saloutos 0:894b603d32ee 70 // AGB0_REG_GYRO_ZOUT_L,
saloutos 0:894b603d32ee 71 // AGB0_REG_TEMP_OUT_H,
saloutos 0:894b603d32ee 72 // AGB0_REG_TEMP_OUT_L,
saloutos 0:894b603d32ee 73 // AGB0_REG_EXT_PERIPH_SENS_DATA_00,
saloutos 0:894b603d32ee 74 // AGB0_REG_EXT_PERIPH_SENS_DATA_01,
saloutos 0:894b603d32ee 75 // AGB0_REG_EXT_PERIPH_SENS_DATA_02,
saloutos 0:894b603d32ee 76 // AGB0_REG_EXT_PERIPH_SENS_DATA_03,
saloutos 0:894b603d32ee 77 // AGB0_REG_EXT_PERIPH_SENS_DATA_04,
saloutos 0:894b603d32ee 78 // AGB0_REG_EXT_PERIPH_SENS_DATA_05,
saloutos 0:894b603d32ee 79 // AGB0_REG_EXT_PERIPH_SENS_DATA_06,
saloutos 0:894b603d32ee 80 // AGB0_REG_EXT_PERIPH_SENS_DATA_07,
saloutos 0:894b603d32ee 81 // AGB0_REG_EXT_PERIPH_SENS_DATA_08,
saloutos 0:894b603d32ee 82 // AGB0_REG_EXT_PERIPH_SENS_DATA_09,
saloutos 0:894b603d32ee 83 // AGB0_REG_EXT_PERIPH_SENS_DATA_10,
saloutos 0:894b603d32ee 84 // AGB0_REG_EXT_PERIPH_SENS_DATA_11,
saloutos 0:894b603d32ee 85 // AGB0_REG_EXT_PERIPH_SENS_DATA_12,
saloutos 0:894b603d32ee 86 // AGB0_REG_EXT_PERIPH_SENS_DATA_13,
saloutos 0:894b603d32ee 87 // AGB0_REG_EXT_PERIPH_SENS_DATA_14,
saloutos 0:894b603d32ee 88 // AGB0_REG_EXT_PERIPH_SENS_DATA_15,
saloutos 0:894b603d32ee 89 // AGB0_REG_EXT_PERIPH_SENS_DATA_16,
saloutos 0:894b603d32ee 90 // AGB0_REG_EXT_PERIPH_SENS_DATA_17,
saloutos 0:894b603d32ee 91 // AGB0_REG_EXT_PERIPH_SENS_DATA_18,
saloutos 0:894b603d32ee 92 // AGB0_REG_EXT_PERIPH_SENS_DATA_19,
saloutos 0:894b603d32ee 93 // AGB0_REG_EXT_PERIPH_SENS_DATA_20,
saloutos 0:894b603d32ee 94 // AGB0_REG_EXT_PERIPH_SENS_DATA_21,
saloutos 0:894b603d32ee 95 // AGB0_REG_EXT_PERIPH_SENS_DATA_22,
saloutos 0:894b603d32ee 96 // AGB0_REG_EXT_PERIPH_SENS_DATA_23,
saloutos 0:894b603d32ee 97 // // Break
saloutos 0:894b603d32ee 98 // AGB0_REG_FIFO_EN_1 = 0x66,
saloutos 0:894b603d32ee 99 // AGB0_REG_FIFO_EN_2,
saloutos 0:894b603d32ee 100 // AGB0_REG_FIFO_MODE,
saloutos 0:894b603d32ee 101 // // Break
saloutos 0:894b603d32ee 102 // AGB0_REG_FIFO_COUNT_H = 0x70,
saloutos 0:894b603d32ee 103 // AGB0_REG_FIFO_COUNT_L,
saloutos 0:894b603d32ee 104 // AGB0_REG_FIFO_R_W,
saloutos 0:894b603d32ee 105 // // Break
saloutos 0:894b603d32ee 106 // AGB0_REG_DATA_RDY_STATUS = 0x74,
saloutos 0:894b603d32ee 107 // // Break
saloutos 0:894b603d32ee 108 // AGB0_REG_FIFO_CFG = 0x76,
saloutos 0:894b603d32ee 109 // // Break
saloutos 0:894b603d32ee 110 // AGB0_REG_MEM_START_ADDR = 0x7C, // Hmm, Invensense thought they were sneaky not listing these locations on the datasheet...
saloutos 0:894b603d32ee 111 // AGB0_REG_MEM_R_W = 0x7D, // These three locations seem to be able to access some memory within the device
saloutos 0:894b603d32ee 112 // AGB0_REG_MEM_BANK_SEL = 0x7E, // And that location is also where the DMP image gets loaded
saloutos 0:894b603d32ee 113 // AGB0_REG_REG_BANK_SEL = 0x7F,
saloutos 0:894b603d32ee 114
saloutos 0:894b603d32ee 115 // // Bank 1
saloutos 0:894b603d32ee 116 // AGB1_REG_SELF_TEST_X_GYRO = 0x02,
saloutos 0:894b603d32ee 117 // AGB1_REG_SELF_TEST_Y_GYRO,
saloutos 0:894b603d32ee 118 // AGB1_REG_SELF_TEST_Z_GYRO,
saloutos 0:894b603d32ee 119 // // Break
saloutos 0:894b603d32ee 120 // AGB1_REG_SELF_TEST_X_ACCEL = 0x0E,
saloutos 0:894b603d32ee 121 // AGB1_REG_SELF_TEST_Y_ACCEL,
saloutos 0:894b603d32ee 122 // AGB1_REG_SELF_TEST_Z_ACCEL,
saloutos 0:894b603d32ee 123 // // Break
saloutos 0:894b603d32ee 124 // AGB1_REG_XA_OFFS_H = 0x14,
saloutos 0:894b603d32ee 125 // AGB1_REG_XA_OFFS_L,
saloutos 0:894b603d32ee 126 // // Break
saloutos 0:894b603d32ee 127 // AGB1_REG_YA_OFFS_H = 0x17,
saloutos 0:894b603d32ee 128 // AGB1_REG_YA_OFFS_L,
saloutos 0:894b603d32ee 129 // // Break
saloutos 0:894b603d32ee 130 // AGB1_REG_ZA_OFFS_H = 0x1A,
saloutos 0:894b603d32ee 131 // AGB1_REG_ZA_OFFS_L,
saloutos 0:894b603d32ee 132 // // Break
saloutos 0:894b603d32ee 133 // AGB1_REG_TIMEBASE_CORRECTION_PLL = 0x28,
saloutos 0:894b603d32ee 134 // // Break
saloutos 0:894b603d32ee 135 // AGB1_REG_REG_BANK_SEL = 0x7F,
saloutos 0:894b603d32ee 136
saloutos 0:894b603d32ee 137 // // Bank 2
saloutos 0:894b603d32ee 138 // AGB2_REG_GYRO_SMPLRT_DIV = 0x00,
saloutos 0:894b603d32ee 139
saloutos 0:894b603d32ee 140 /*
saloutos 0:894b603d32ee 141 Gyro sample rate divider. Divides the internal sample rate to generate the sample
saloutos 0:894b603d32ee 142 rate that controls sensor data output rate, FIFO sample rate, and DMP sequence rate.
saloutos 0:894b603d32ee 143 NOTE: This register is only effective when FCHOICE = 1’b1 (FCHOICE_B register bit is 1’b0), and
saloutos 0:894b603d32ee 144 (0 < DLPF_CFG < 7).
saloutos 0:894b603d32ee 145 ODR is computed as follows:
saloutos 0:894b603d32ee 146 1.1 kHz/(1+GYRO_SMPLRT_DIV[7:0])
saloutos 0:894b603d32ee 147 */
saloutos 0:894b603d32ee 148
saloutos 0:894b603d32ee 149 // AGB2_REG_GYRO_CONFIG_1,
saloutos 0:894b603d32ee 150
saloutos 0:894b603d32ee 151 typedef enum
saloutos 0:894b603d32ee 152 { // Full scale range options in degrees per second
saloutos 0:894b603d32ee 153 dps250 = 0x00,
saloutos 0:894b603d32ee 154 dps500,
saloutos 0:894b603d32ee 155 dps1000,
saloutos 0:894b603d32ee 156 dps2000,
saloutos 0:894b603d32ee 157 } ICM_20948_GYRO_CONFIG_1_FS_SEL_e;
saloutos 0:894b603d32ee 158
saloutos 0:894b603d32ee 159 typedef enum
saloutos 0:894b603d32ee 160 { // Format is dAbwB_nXbwY - A is integer part of 3db BW, B is fraction. X is integer part of nyquist bandwidth, Y is fraction
saloutos 0:894b603d32ee 161 gyr_d196bw6_n229bw8 = 0x00,
saloutos 0:894b603d32ee 162 gyr_d151bw8_n187bw6,
saloutos 0:894b603d32ee 163 gyr_d119bw5_n154bw3,
saloutos 0:894b603d32ee 164 gyr_d51bw2_n73bw3,
saloutos 0:894b603d32ee 165 gyr_d23bw9_n35bw9,
saloutos 0:894b603d32ee 166 gyr_d11bw6_n17bw8,
saloutos 0:894b603d32ee 167 gyr_d5bw7_n8bw9,
saloutos 0:894b603d32ee 168 gyr_d361bw4_n376bw5,
saloutos 0:894b603d32ee 169 } ICM_20948_GYRO_CONFIG_1_DLPCFG_e;
saloutos 0:894b603d32ee 170
saloutos 0:894b603d32ee 171 // AGB2_REG_GYRO_CONFIG_2,
saloutos 0:894b603d32ee 172 // AGB2_REG_XG_OFFS_USRH,
saloutos 0:894b603d32ee 173 // AGB2_REG_XG_OFFS_USRL,
saloutos 0:894b603d32ee 174 // AGB2_REG_YG_OFFS_USRH,
saloutos 0:894b603d32ee 175 // AGB2_REG_YG_OFFS_USRL,
saloutos 0:894b603d32ee 176 // AGB2_REG_ZG_OFFS_USRH,
saloutos 0:894b603d32ee 177 // AGB2_REG_ZG_OFFS_USRL,
saloutos 0:894b603d32ee 178 // AGB2_REG_ODR_ALIGN_EN,
saloutos 0:894b603d32ee 179 // // Break
saloutos 0:894b603d32ee 180 // AGB2_REG_ACCEL_SMPLRT_DIV_1 = 0x10,
saloutos 0:894b603d32ee 181 // AGB2_REG_ACCEL_SMPLRT_DIV_2,
saloutos 0:894b603d32ee 182 // AGB2_REG_ACCEL_INTEL_CTRL,
saloutos 0:894b603d32ee 183 // AGB2_REG_ACCEL_WOM_THR,
saloutos 0:894b603d32ee 184 // AGB2_REG_ACCEL_CONFIG,
saloutos 0:894b603d32ee 185
saloutos 0:894b603d32ee 186 typedef enum
saloutos 0:894b603d32ee 187 {
saloutos 0:894b603d32ee 188 gpm2 = 0x00,
saloutos 0:894b603d32ee 189 gpm4,
saloutos 0:894b603d32ee 190 gpm8,
saloutos 0:894b603d32ee 191 gpm16,
saloutos 0:894b603d32ee 192 } ICM_20948_ACCEL_CONFIG_FS_SEL_e;
saloutos 0:894b603d32ee 193
saloutos 0:894b603d32ee 194 typedef enum
saloutos 0:894b603d32ee 195 { // Format is dAbwB_nXbwZ - A is integer part of 3db BW, B is fraction. X is integer part of nyquist bandwidth, Y is fraction
saloutos 0:894b603d32ee 196 acc_d246bw_n265bw = 0x00,
saloutos 0:894b603d32ee 197 acc_d246bw_n265bw_1,
saloutos 0:894b603d32ee 198 acc_d111bw4_n136bw,
saloutos 0:894b603d32ee 199 acc_d50bw4_n68bw8,
saloutos 0:894b603d32ee 200 acc_d23bw9_n34bw4,
saloutos 0:894b603d32ee 201 acc_d11bw5_n17bw,
saloutos 0:894b603d32ee 202 acc_d5bw7_n8bw3,
saloutos 0:894b603d32ee 203 acc_d473bw_n499bw,
saloutos 0:894b603d32ee 204 } ICM_20948_ACCEL_CONFIG_DLPCFG_e;
saloutos 0:894b603d32ee 205
saloutos 0:894b603d32ee 206 // AGB2_REG_ACCEL_CONFIG_2,
saloutos 0:894b603d32ee 207 // // Break
saloutos 0:894b603d32ee 208 // AGB2_REG_FSYNC_CONFIG = 0x52,
saloutos 0:894b603d32ee 209 // AGB2_REG_TEMP_CONFIG,
saloutos 0:894b603d32ee 210 // AGB2_REG_MOD_CTRL_USR,
saloutos 0:894b603d32ee 211 // // Break
saloutos 0:894b603d32ee 212 // AGB2_REG_REG_BANK_SEL = 0x7F,
saloutos 0:894b603d32ee 213
saloutos 0:894b603d32ee 214 // // Bank 3
saloutos 0:894b603d32ee 215 // AGB3_REG_I2C_MST_ODR_CONFIG = 0x00,
saloutos 0:894b603d32ee 216 // AGB3_REG_I2C_MST_CTRL,
saloutos 0:894b603d32ee 217 // AGB3_REG_I2C_MST_DELAY_CTRL,
saloutos 0:894b603d32ee 218 // AGB3_REG_I2C_PERIPH0_ADDR,
saloutos 0:894b603d32ee 219 // AGB3_REG_I2C_PERIPH0_REG,
saloutos 0:894b603d32ee 220 // AGB3_REG_I2C_PERIPH0_CTRL,
saloutos 0:894b603d32ee 221 // AGB3_REG_I2C_PERIPH0_DO,
saloutos 0:894b603d32ee 222 // AGB3_REG_I2C_PERIPH1_ADDR,
saloutos 0:894b603d32ee 223 // AGB3_REG_I2C_PERIPH1_REG,
saloutos 0:894b603d32ee 224 // AGB3_REG_I2C_PERIPH1_CTRL,
saloutos 0:894b603d32ee 225 // AGB3_REG_I2C_PERIPH1_DO,
saloutos 0:894b603d32ee 226 // AGB3_REG_I2C_PERIPH2_ADDR,
saloutos 0:894b603d32ee 227 // AGB3_REG_I2C_PERIPH2_REG,
saloutos 0:894b603d32ee 228 // AGB3_REG_I2C_PERIPH2_CTRL,
saloutos 0:894b603d32ee 229 // AGB3_REG_I2C_PERIPH2_DO,
saloutos 0:894b603d32ee 230 // AGB3_REG_I2C_PERIPH3_ADDR,
saloutos 0:894b603d32ee 231 // AGB3_REG_I2C_PERIPH3_REG,
saloutos 0:894b603d32ee 232 // AGB3_REG_I2C_PERIPH3_CTRL,
saloutos 0:894b603d32ee 233 // AGB3_REG_I2C_PERIPH3_DO,
saloutos 0:894b603d32ee 234 // AGB3_REG_I2C_PERIPH4_ADDR,
saloutos 0:894b603d32ee 235 // AGB3_REG_I2C_PERIPH4_REG,
saloutos 0:894b603d32ee 236 // AGB3_REG_I2C_PERIPH4_CTRL,
saloutos 0:894b603d32ee 237 // AGB3_REG_I2C_PERIPH4_DO,
saloutos 0:894b603d32ee 238 // AGB3_REG_I2C_PERIPH4_DI,
saloutos 0:894b603d32ee 239 // // Break
saloutos 0:894b603d32ee 240 // AGB3_REG_REG_BANK_SEL = 0x7F,
saloutos 0:894b603d32ee 241
saloutos 0:894b603d32ee 242 // // Magnetometer
saloutos 0:894b603d32ee 243 // M_REG_WIA2 = 0x01,
saloutos 0:894b603d32ee 244 // // Break
saloutos 0:894b603d32ee 245 // M_REG_ST1 = 0x10,
saloutos 0:894b603d32ee 246 // M_REG_HXL,
saloutos 0:894b603d32ee 247 // M_REG_HXH,
saloutos 0:894b603d32ee 248 // M_REG_HYL,
saloutos 0:894b603d32ee 249 // M_REG_HYH,
saloutos 0:894b603d32ee 250 // M_REG_HZL,
saloutos 0:894b603d32ee 251 // M_REG_HZH,
saloutos 0:894b603d32ee 252 // M_REG_ST2,
saloutos 0:894b603d32ee 253 // // Break
saloutos 0:894b603d32ee 254 // M_REG_CNTL2 = 0x31,
saloutos 0:894b603d32ee 255 // M_REG_CNTL3,
saloutos 0:894b603d32ee 256 // M_REG_TS1,
saloutos 0:894b603d32ee 257 // M_REG_TS2,
saloutos 0:894b603d32ee 258
saloutos 0:894b603d32ee 259 #ifdef __cplusplus
saloutos 0:894b603d32ee 260 }
saloutos 0:894b603d32ee 261 #endif /* __cplusplus */
saloutos 0:894b603d32ee 262
saloutos 0:894b603d32ee 263 #endif /* _ICM_20948_ENUMERATIONS_H_ */