v 0.4

Dependents:   MCP23S17Test MCP23S17_Basic_IO_Demo HelloWorld Lab3-SnakeGame ... more

Committer:
romilly
Date:
Sun Aug 22 12:41:26 2010 +0000
Revision:
6:7b5e59c0e71c
Parent:
5:cb3c24f94370
Child:
7:53498e24592c

        

Who changed what in which revision?

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romilly 2:6144709f1700 1 /* MCP23S17 - drive the Microchip MCP23S17 16-bit Port Extender using SPI
romilly 2:6144709f1700 2 * Copyright (c) 2010 Romilly Cocking
romilly 2:6144709f1700 3 * Released under the MIT License: http://mbed.org/license/mit
romilly 2:6144709f1700 4 *
romilly 2:6144709f1700 5 * version 0.1
romilly 2:6144709f1700 6 */
romilly 2:6144709f1700 7 #include "mbed.h"
romilly 2:6144709f1700 8
romilly 2:6144709f1700 9 #ifndef SER23K256_H
romilly 2:6144709f1700 10 #define SER23K256_H
romilly 2:6144709f1700 11
romilly 4:d501c74550a0 12 // all register addresses assume IOCON.BANK = 0 (POR default)
romilly 2:6144709f1700 13
romilly 4:d501c74550a0 14 #define IODIRA 0x00
romilly 4:d501c74550a0 15 #define IODIRB 0x01
romilly 5:cb3c24f94370 16 #define GPINTENA 0x04
romilly 4:d501c74550a0 17 #define IOCON 0x0A
romilly 4:d501c74550a0 18 #define GPIOA 0x12
romilly 4:d501c74550a0 19 #define GPIOB 0x13
romilly 4:d501c74550a0 20 #define OLATA 0x14
romilly 4:d501c74550a0 21 #define OLATB 0x15
romilly 2:6144709f1700 22
romilly 2:6144709f1700 23 // Control settings
romilly 2:6144709f1700 24
romilly 2:6144709f1700 25 #define IOCON_BANK 0x80 // Banked registers
romilly 2:6144709f1700 26 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation. If bank = 0, operations toggle between A and B registers
romilly 2:6144709f1700 27 #define IOCON_HAEN 0x08 // Hardware address enable
romilly 2:6144709f1700 28
romilly 2:6144709f1700 29 class MCP23S17 {
romilly 2:6144709f1700 30 public:
romilly 2:6144709f1700 31 MCP23S17(SPI& spi, PinName ncs, char writeOpcode);
romilly 2:6144709f1700 32 void directionA(char direction);
romilly 2:6144709f1700 33 void directionB(char direction);
romilly 4:d501c74550a0 34 void gpIntEnA(char interruptsEnabledMask);
romilly 2:6144709f1700 35 char inputA();
romilly 2:6144709f1700 36 char inputB();
romilly 2:6144709f1700 37 void outputA(char byte);
romilly 2:6144709f1700 38 void outputB(char byte);
romilly 2:6144709f1700 39 protected:
romilly 2:6144709f1700 40 SPI& _spi;
romilly 2:6144709f1700 41 DigitalOut _ncs;
romilly 2:6144709f1700 42 void _init();
romilly 2:6144709f1700 43 void _write(char address, char data);
romilly 2:6144709f1700 44 char _read(char address);
romilly 2:6144709f1700 45 char _readOpcode;
romilly 2:6144709f1700 46 char _writeOpcode;
romilly 2:6144709f1700 47 };
romilly 2:6144709f1700 48
romilly 6:7b5e59c0e71c 49 #endif/* MCP23S17 - drive the Microchip MCP23S17 16-bit Port Extender using SPI
romilly 6:7b5e59c0e71c 50 * Copyright (c) 2010 Romilly Cocking
romilly 6:7b5e59c0e71c 51 * Released under the MIT License: http://mbed.org/license/mit
romilly 6:7b5e59c0e71c 52 *
romilly 6:7b5e59c0e71c 53 * version 0.1
romilly 6:7b5e59c0e71c 54 */
romilly 6:7b5e59c0e71c 55 #include "mbed.h"
romilly 6:7b5e59c0e71c 56
romilly 6:7b5e59c0e71c 57 #ifndef SER23K256_H
romilly 6:7b5e59c0e71c 58 #define SER23K256_H
romilly 6:7b5e59c0e71c 59
romilly 6:7b5e59c0e71c 60 // all register addresses assume IOCON.BANK = 0 (POR default)
romilly 6:7b5e59c0e71c 61
romilly 6:7b5e59c0e71c 62 #define IODIRA 0x00
romilly 6:7b5e59c0e71c 63 #define IODIRB 0x01
romilly 6:7b5e59c0e71c 64 #define GPINTENA 0x04
romilly 6:7b5e59c0e71c 65 #define IOCON 0x0A
romilly 6:7b5e59c0e71c 66 #define GPIOA 0x12
romilly 6:7b5e59c0e71c 67 #define GPIOB 0x13
romilly 6:7b5e59c0e71c 68 #define OLATA 0x14
romilly 6:7b5e59c0e71c 69 #define OLATB 0x15
romilly 6:7b5e59c0e71c 70
romilly 6:7b5e59c0e71c 71 // Control settings
romilly 6:7b5e59c0e71c 72
romilly 6:7b5e59c0e71c 73 #define IOCON_BANK 0x80 // Banked registers
romilly 6:7b5e59c0e71c 74 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation. If bank = 0, operations toggle between A and B registers
romilly 6:7b5e59c0e71c 75 #define IOCON_HAEN 0x08 // Hardware address enable
romilly 6:7b5e59c0e71c 76
romilly 6:7b5e59c0e71c 77 class MCP23S17 {
romilly 6:7b5e59c0e71c 78 public:
romilly 6:7b5e59c0e71c 79 MCP23S17(SPI& spi, PinName ncs, char writeOpcode);
romilly 6:7b5e59c0e71c 80 void directionA(char direction);
romilly 6:7b5e59c0e71c 81 void directionB(char direction);
romilly 6:7b5e59c0e71c 82 void gpIntEnA(char interruptsEnabledMask);
romilly 6:7b5e59c0e71c 83 char inputA();
romilly 6:7b5e59c0e71c 84 char inputB();
romilly 6:7b5e59c0e71c 85 void outputA(char byte);
romilly 6:7b5e59c0e71c 86 void outputB(char byte);
romilly 6:7b5e59c0e71c 87 protected:
romilly 6:7b5e59c0e71c 88 SPI& _spi;
romilly 6:7b5e59c0e71c 89 DigitalOut _ncs;
romilly 6:7b5e59c0e71c 90 void _init();
romilly 6:7b5e59c0e71c 91 void _write(char address, char data);
romilly 6:7b5e59c0e71c 92 char _read(char address);
romilly 6:7b5e59c0e71c 93 char _readOpcode;
romilly 6:7b5e59c0e71c 94 char _writeOpcode;
romilly 6:7b5e59c0e71c 95 };
romilly 6:7b5e59c0e71c 96
romilly 6:7b5e59c0e71c 97 #endif/* MCP23S17 - drive the Microchip MCP23S17 16-bit Port Extender using SPI
romilly 6:7b5e59c0e71c 98 * Copyright (c) 2010 Romilly Cocking
romilly 6:7b5e59c0e71c 99 * Released under the MIT License: http://mbed.org/license/mit
romilly 6:7b5e59c0e71c 100 *
romilly 6:7b5e59c0e71c 101 * version 0.1
romilly 6:7b5e59c0e71c 102 */
romilly 6:7b5e59c0e71c 103 #include "mbed.h"
romilly 6:7b5e59c0e71c 104
romilly 6:7b5e59c0e71c 105 #ifndef SER23K256_H
romilly 6:7b5e59c0e71c 106 #define SER23K256_H
romilly 6:7b5e59c0e71c 107
romilly 6:7b5e59c0e71c 108 // all register addresses assume IOCON.BANK = 0 (POR default)
romilly 6:7b5e59c0e71c 109
romilly 6:7b5e59c0e71c 110 #define IODIRA 0x00
romilly 6:7b5e59c0e71c 111 #define IODIRB 0x01
romilly 6:7b5e59c0e71c 112 #define GPINTENA 0x04
romilly 6:7b5e59c0e71c 113 #define IOCON 0x0A
romilly 6:7b5e59c0e71c 114 #define GPIOA 0x12
romilly 6:7b5e59c0e71c 115 #define GPIOB 0x13
romilly 6:7b5e59c0e71c 116 #define OLATA 0x14
romilly 6:7b5e59c0e71c 117 #define OLATB 0x15
romilly 6:7b5e59c0e71c 118
romilly 6:7b5e59c0e71c 119 // Control settings
romilly 6:7b5e59c0e71c 120
romilly 6:7b5e59c0e71c 121 #define IOCON_BANK 0x80 // Banked registers
romilly 6:7b5e59c0e71c 122 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation. If bank = 0, operations toggle between A and B registers
romilly 6:7b5e59c0e71c 123 #define IOCON_HAEN 0x08 // Hardware address enable
romilly 6:7b5e59c0e71c 124
romilly 6:7b5e59c0e71c 125 class MCP23S17 {
romilly 6:7b5e59c0e71c 126 public:
romilly 6:7b5e59c0e71c 127 MCP23S17(SPI& spi, PinName ncs, char writeOpcode);
romilly 6:7b5e59c0e71c 128 void directionA(char direction);
romilly 6:7b5e59c0e71c 129 void directionB(char direction);
romilly 6:7b5e59c0e71c 130 void gpIntEnA(char interruptsEnabledMask);
romilly 6:7b5e59c0e71c 131 char inputA();
romilly 6:7b5e59c0e71c 132 char inputB();
romilly 6:7b5e59c0e71c 133 void outputA(char byte);
romilly 6:7b5e59c0e71c 134 void outputB(char byte);
romilly 6:7b5e59c0e71c 135 protected:
romilly 6:7b5e59c0e71c 136 SPI& _spi;
romilly 6:7b5e59c0e71c 137 DigitalOut _ncs;
romilly 6:7b5e59c0e71c 138 void _init();
romilly 6:7b5e59c0e71c 139 void _write(char address, char data);
romilly 6:7b5e59c0e71c 140 char _read(char address);
romilly 6:7b5e59c0e71c 141 char _readOpcode;
romilly 6:7b5e59c0e71c 142 char _writeOpcode;
romilly 6:7b5e59c0e71c 143 };
romilly 6:7b5e59c0e71c 144
romilly 2:6144709f1700 145 #endif