Aded CMSIS5 DSP and NN folder. Needs some work

Committer:
robert_lp
Date:
Thu Apr 12 01:31:58 2018 +0000
Revision:
0:eedb7d567a5d
CMSIS5 Library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
robert_lp 0:eedb7d567a5d 1 /*
robert_lp 0:eedb7d567a5d 2 * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
robert_lp 0:eedb7d567a5d 3 *
robert_lp 0:eedb7d567a5d 4 * SPDX-License-Identifier: Apache-2.0
robert_lp 0:eedb7d567a5d 5 *
robert_lp 0:eedb7d567a5d 6 * Licensed under the Apache License, Version 2.0 (the License); you may
robert_lp 0:eedb7d567a5d 7 * not use this file except in compliance with the License.
robert_lp 0:eedb7d567a5d 8 * You may obtain a copy of the License at
robert_lp 0:eedb7d567a5d 9 *
robert_lp 0:eedb7d567a5d 10 * www.apache.org/licenses/LICENSE-2.0
robert_lp 0:eedb7d567a5d 11 *
robert_lp 0:eedb7d567a5d 12 * Unless required by applicable law or agreed to in writing, software
robert_lp 0:eedb7d567a5d 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
robert_lp 0:eedb7d567a5d 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
robert_lp 0:eedb7d567a5d 15 * See the License for the specific language governing permissions and
robert_lp 0:eedb7d567a5d 16 * limitations under the License.
robert_lp 0:eedb7d567a5d 17 */
robert_lp 0:eedb7d567a5d 18
robert_lp 0:eedb7d567a5d 19 /* ----------------------------------------------------------------------
robert_lp 0:eedb7d567a5d 20 * Project: CMSIS NN Library
robert_lp 0:eedb7d567a5d 21 * Title: arm_nnsupportfunctions.h
robert_lp 0:eedb7d567a5d 22 * Description: Public header file of support functions for CMSIS NN Library
robert_lp 0:eedb7d567a5d 23 *
robert_lp 0:eedb7d567a5d 24 * $Date: 17. January 2018
robert_lp 0:eedb7d567a5d 25 * $Revision: V.1.0.0
robert_lp 0:eedb7d567a5d 26 *
robert_lp 0:eedb7d567a5d 27 * Target Processor: Cortex-M cores
robert_lp 0:eedb7d567a5d 28 * -------------------------------------------------------------------- */
robert_lp 0:eedb7d567a5d 29
robert_lp 0:eedb7d567a5d 30 #ifndef _ARM_NNSUPPORTFUNCTIONS_H_
robert_lp 0:eedb7d567a5d 31 #define _ARM_NNSUPPORTFUNCTIONS_H_
robert_lp 0:eedb7d567a5d 32
robert_lp 0:eedb7d567a5d 33 #include "../../DSP/include/arm_math.h"
robert_lp 0:eedb7d567a5d 34 #include "../../DSP/include/arm_common_tables.h"
robert_lp 0:eedb7d567a5d 35 #include "../../Core/include/cmsis_armclang.h"
robert_lp 0:eedb7d567a5d 36 //#include <cstring>
robert_lp 0:eedb7d567a5d 37
robert_lp 0:eedb7d567a5d 38 #ifdef __cplusplus
robert_lp 0:eedb7d567a5d 39 extern "C"
robert_lp 0:eedb7d567a5d 40 {
robert_lp 0:eedb7d567a5d 41 #endif
robert_lp 0:eedb7d567a5d 42
robert_lp 0:eedb7d567a5d 43 /**
robert_lp 0:eedb7d567a5d 44 * @brief Union for SIMD access of Q31/Q15/Q7 types
robert_lp 0:eedb7d567a5d 45 */
robert_lp 0:eedb7d567a5d 46 union arm_nnword
robert_lp 0:eedb7d567a5d 47 {
robert_lp 0:eedb7d567a5d 48 q31_t word;
robert_lp 0:eedb7d567a5d 49 /**< Q31 type */
robert_lp 0:eedb7d567a5d 50 q15_t half_words[2];
robert_lp 0:eedb7d567a5d 51 /**< Q15 type */
robert_lp 0:eedb7d567a5d 52 q7_t bytes[4];
robert_lp 0:eedb7d567a5d 53 /**< Q7 type */
robert_lp 0:eedb7d567a5d 54 };
robert_lp 0:eedb7d567a5d 55
robert_lp 0:eedb7d567a5d 56 /**
robert_lp 0:eedb7d567a5d 57 * @brief Struct for specifying activation function types
robert_lp 0:eedb7d567a5d 58 *
robert_lp 0:eedb7d567a5d 59 */
robert_lp 0:eedb7d567a5d 60 typedef enum
robert_lp 0:eedb7d567a5d 61 {
robert_lp 0:eedb7d567a5d 62 ARM_SIGMOID = 0,
robert_lp 0:eedb7d567a5d 63 /**< Sigmoid activation function */
robert_lp 0:eedb7d567a5d 64 ARM_TANH = 1,
robert_lp 0:eedb7d567a5d 65 /**< Tanh activation function */
robert_lp 0:eedb7d567a5d 66 } arm_nn_activation_type;
robert_lp 0:eedb7d567a5d 67
robert_lp 0:eedb7d567a5d 68 /**
robert_lp 0:eedb7d567a5d 69 * @defgroup nndata_convert Neural Network Data Conversion Functions
robert_lp 0:eedb7d567a5d 70 *
robert_lp 0:eedb7d567a5d 71 * Perform data type conversion in-between neural network operations
robert_lp 0:eedb7d567a5d 72 *
robert_lp 0:eedb7d567a5d 73 */
robert_lp 0:eedb7d567a5d 74
robert_lp 0:eedb7d567a5d 75 /**
robert_lp 0:eedb7d567a5d 76 * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift
robert_lp 0:eedb7d567a5d 77 * @param[in] *pSrc points to the Q7 input vector
robert_lp 0:eedb7d567a5d 78 * @param[out] *pDst points to the Q15 output vector
robert_lp 0:eedb7d567a5d 79 * @param[in] blockSize length of the input vector
robert_lp 0:eedb7d567a5d 80 * @return none.
robert_lp 0:eedb7d567a5d 81 *
robert_lp 0:eedb7d567a5d 82 */
robert_lp 0:eedb7d567a5d 83
robert_lp 0:eedb7d567a5d 84 void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize);
robert_lp 0:eedb7d567a5d 85
robert_lp 0:eedb7d567a5d 86 /**
robert_lp 0:eedb7d567a5d 87 * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
robert_lp 0:eedb7d567a5d 88 * @param[in] *pSrc points to the Q7 input vector
robert_lp 0:eedb7d567a5d 89 * @param[out] *pDst points to the Q15 output vector
robert_lp 0:eedb7d567a5d 90 * @param[in] blockSize length of the input vector
robert_lp 0:eedb7d567a5d 91 * @return none.
robert_lp 0:eedb7d567a5d 92 *
robert_lp 0:eedb7d567a5d 93 */
robert_lp 0:eedb7d567a5d 94
robert_lp 0:eedb7d567a5d 95 void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize);
robert_lp 0:eedb7d567a5d 96
robert_lp 0:eedb7d567a5d 97 #if defined (ARM_MATH_DSP)
robert_lp 0:eedb7d567a5d 98
robert_lp 0:eedb7d567a5d 99 /**
robert_lp 0:eedb7d567a5d 100 * @brief read and expand one Q7 word into two Q15 words
robert_lp 0:eedb7d567a5d 101 */
robert_lp 0:eedb7d567a5d 102
robert_lp 0:eedb7d567a5d 103 __STATIC_FORCEINLINE void *read_and_pad(void *source, q31_t * out1, q31_t * out2)
robert_lp 0:eedb7d567a5d 104 {
robert_lp 0:eedb7d567a5d 105 q31_t inA = *__SIMD32(source)++;
robert_lp 0:eedb7d567a5d 106 q31_t inAbuf1 = __SXTB16(__ROR(inA, 8));
robert_lp 0:eedb7d567a5d 107 q31_t inAbuf2 = __SXTB16(inA);
robert_lp 0:eedb7d567a5d 108
robert_lp 0:eedb7d567a5d 109 #ifndef ARM_MATH_BIG_ENDIAN
robert_lp 0:eedb7d567a5d 110 *out2 = __PKHTB(inAbuf1, inAbuf2, 16);
robert_lp 0:eedb7d567a5d 111 *out1 = __PKHBT(inAbuf2, inAbuf1, 16);
robert_lp 0:eedb7d567a5d 112 #else
robert_lp 0:eedb7d567a5d 113 *out1 = __PKHTB(inAbuf1, inAbuf2, 16);
robert_lp 0:eedb7d567a5d 114 *out2 = __PKHBT(inAbuf2, inAbuf1, 16);
robert_lp 0:eedb7d567a5d 115 #endif
robert_lp 0:eedb7d567a5d 116
robert_lp 0:eedb7d567a5d 117 return source;
robert_lp 0:eedb7d567a5d 118 }
robert_lp 0:eedb7d567a5d 119
robert_lp 0:eedb7d567a5d 120 /**
robert_lp 0:eedb7d567a5d 121 * @brief read and expand one Q7 word into two Q15 words with reordering
robert_lp 0:eedb7d567a5d 122 */
robert_lp 0:eedb7d567a5d 123
robert_lp 0:eedb7d567a5d 124 __STATIC_FORCEINLINE void *read_and_pad_reordered(void *source, q31_t * out1, q31_t * out2)
robert_lp 0:eedb7d567a5d 125 {
robert_lp 0:eedb7d567a5d 126 q31_t inA = *__SIMD32(source)++;
robert_lp 0:eedb7d567a5d 127 #ifndef ARM_MATH_BIG_ENDIAN
robert_lp 0:eedb7d567a5d 128 *out2 = __SXTB16(__ROR(inA, 8));
robert_lp 0:eedb7d567a5d 129 *out1 = __SXTB16(inA);
robert_lp 0:eedb7d567a5d 130 #else
robert_lp 0:eedb7d567a5d 131 *out1 = __SXTB16(__ROR(inA, 8));
robert_lp 0:eedb7d567a5d 132 *out2 = __SXTB16(inA);
robert_lp 0:eedb7d567a5d 133 #endif
robert_lp 0:eedb7d567a5d 134
robert_lp 0:eedb7d567a5d 135 return source;
robert_lp 0:eedb7d567a5d 136 }
robert_lp 0:eedb7d567a5d 137 #endif
robert_lp 0:eedb7d567a5d 138
robert_lp 0:eedb7d567a5d 139 /**
robert_lp 0:eedb7d567a5d 140 * @brief defition to adding rouding offset
robert_lp 0:eedb7d567a5d 141 */
robert_lp 0:eedb7d567a5d 142 #ifndef ARM_NN_TRUNCATE
robert_lp 0:eedb7d567a5d 143 #define NN_ROUND(out_shift) ( 0x1 << (out_shift - 1) )
robert_lp 0:eedb7d567a5d 144 #else
robert_lp 0:eedb7d567a5d 145 #define NN_ROUND(out_shift) 0
robert_lp 0:eedb7d567a5d 146 #endif
robert_lp 0:eedb7d567a5d 147
robert_lp 0:eedb7d567a5d 148 #ifdef __cplusplus
robert_lp 0:eedb7d567a5d 149 }
robert_lp 0:eedb7d567a5d 150 #endif
robert_lp 0:eedb7d567a5d 151
robert_lp 0:eedb7d567a5d 152 #endif
robert_lp 0:eedb7d567a5d 153