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lwip-eth/arch/TARGET_NXP/lpc17_emac.c@0:b2805b6888dc, 2016-06-20 (annotated)

Committer:
robert_jw
Date:
Mon Jun 20 01:40:20 2016 +0000
Revision:
0:b2805b6888dc
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robert_jw 0:b2805b6888dc 1 /**********************************************************************
robert_jw 0:b2805b6888dc 2 * $Id$ lpc17_emac.c 2011-11-20
robert_jw 0:b2805b6888dc 3 *//**
robert_jw 0:b2805b6888dc 4 * @file lpc17_emac.c
robert_jw 0:b2805b6888dc 5 * @brief LPC17 ethernet driver for LWIP
robert_jw 0:b2805b6888dc 6 * @version 1.0
robert_jw 0:b2805b6888dc 7 * @date 20. Nov. 2011
robert_jw 0:b2805b6888dc 8 * @author NXP MCU SW Application Team
robert_jw 0:b2805b6888dc 9 *
robert_jw 0:b2805b6888dc 10 * Copyright(C) 2011, NXP Semiconductor
robert_jw 0:b2805b6888dc 11 * All rights reserved.
robert_jw 0:b2805b6888dc 12 *
robert_jw 0:b2805b6888dc 13 ***********************************************************************
robert_jw 0:b2805b6888dc 14 * Software that is described herein is for illustrative purposes only
robert_jw 0:b2805b6888dc 15 * which provides customers with programming information regarding the
robert_jw 0:b2805b6888dc 16 * products. This software is supplied "AS IS" without any warranties.
robert_jw 0:b2805b6888dc 17 * NXP Semiconductors assumes no responsibility or liability for the
robert_jw 0:b2805b6888dc 18 * use of the software, conveys no license or title under any patent,
robert_jw 0:b2805b6888dc 19 * copyright, or mask work right to the product. NXP Semiconductors
robert_jw 0:b2805b6888dc 20 * reserves the right to make changes in the software without
robert_jw 0:b2805b6888dc 21 * notification. NXP Semiconductors also make no representation or
robert_jw 0:b2805b6888dc 22 * warranty that such application will be suitable for the specified
robert_jw 0:b2805b6888dc 23 * use without further testing or modification.
robert_jw 0:b2805b6888dc 24 **********************************************************************/
robert_jw 0:b2805b6888dc 25
robert_jw 0:b2805b6888dc 26 #include "lwip/opt.h"
robert_jw 0:b2805b6888dc 27 #include "lwip/sys.h"
robert_jw 0:b2805b6888dc 28 #include "lwip/def.h"
robert_jw 0:b2805b6888dc 29 #include "lwip/mem.h"
robert_jw 0:b2805b6888dc 30 #include "lwip/pbuf.h"
robert_jw 0:b2805b6888dc 31 #include "lwip/stats.h"
robert_jw 0:b2805b6888dc 32 #include "lwip/snmp.h"
robert_jw 0:b2805b6888dc 33 #include "netif/etharp.h"
robert_jw 0:b2805b6888dc 34 #include "netif/ppp_oe.h"
robert_jw 0:b2805b6888dc 35
robert_jw 0:b2805b6888dc 36 #include "lpc17xx_emac.h"
robert_jw 0:b2805b6888dc 37 #include "eth_arch.h"
robert_jw 0:b2805b6888dc 38 #include "lpc_emac_config.h"
robert_jw 0:b2805b6888dc 39 #include "lpc_phy.h"
robert_jw 0:b2805b6888dc 40 #include "sys_arch.h"
robert_jw 0:b2805b6888dc 41
robert_jw 0:b2805b6888dc 42 #include "mbed_interface.h"
robert_jw 0:b2805b6888dc 43 #include <string.h>
robert_jw 0:b2805b6888dc 44
robert_jw 0:b2805b6888dc 45 #ifndef LPC_EMAC_RMII
robert_jw 0:b2805b6888dc 46 #error LPC_EMAC_RMII is not defined!
robert_jw 0:b2805b6888dc 47 #endif
robert_jw 0:b2805b6888dc 48
robert_jw 0:b2805b6888dc 49 #if LPC_NUM_BUFF_TXDESCS < 2
robert_jw 0:b2805b6888dc 50 #error LPC_NUM_BUFF_TXDESCS must be at least 2
robert_jw 0:b2805b6888dc 51 #endif
robert_jw 0:b2805b6888dc 52
robert_jw 0:b2805b6888dc 53 #if LPC_NUM_BUFF_RXDESCS < 3
robert_jw 0:b2805b6888dc 54 #error LPC_NUM_BUFF_RXDESCS must be at least 3
robert_jw 0:b2805b6888dc 55 #endif
robert_jw 0:b2805b6888dc 56
robert_jw 0:b2805b6888dc 57 /** @defgroup lwip17xx_emac_DRIVER lpc17 EMAC driver for LWIP
robert_jw 0:b2805b6888dc 58 * @ingroup lwip_emac
robert_jw 0:b2805b6888dc 59 *
robert_jw 0:b2805b6888dc 60 * @{
robert_jw 0:b2805b6888dc 61 */
robert_jw 0:b2805b6888dc 62
robert_jw 0:b2805b6888dc 63 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 64 /** \brief Driver transmit and receive thread priorities
robert_jw 0:b2805b6888dc 65 *
robert_jw 0:b2805b6888dc 66 * Thread priorities for receive thread and TX cleanup thread. Alter
robert_jw 0:b2805b6888dc 67 * to prioritize receive or transmit bandwidth. In a heavily loaded
robert_jw 0:b2805b6888dc 68 * system or with LEIP_DEBUG enabled, the priorities might be better
robert_jw 0:b2805b6888dc 69 * the same. */
robert_jw 0:b2805b6888dc 70 #define RX_PRIORITY (osPriorityNormal)
robert_jw 0:b2805b6888dc 71 #define TX_PRIORITY (osPriorityNormal)
robert_jw 0:b2805b6888dc 72
robert_jw 0:b2805b6888dc 73 /** \brief Debug output formatter lock define
robert_jw 0:b2805b6888dc 74 *
robert_jw 0:b2805b6888dc 75 * When using FreeRTOS and with LWIP_DEBUG enabled, enabling this
robert_jw 0:b2805b6888dc 76 * define will allow RX debug messages to not interleave with the
robert_jw 0:b2805b6888dc 77 * TX messages (so they are actually readable). Not enabling this
robert_jw 0:b2805b6888dc 78 * define when the system is under load will cause the output to
robert_jw 0:b2805b6888dc 79 * be unreadable. There is a small tradeoff in performance for this
robert_jw 0:b2805b6888dc 80 * so use it only for debug. */
robert_jw 0:b2805b6888dc 81 //#define LOCK_RX_THREAD
robert_jw 0:b2805b6888dc 82
robert_jw 0:b2805b6888dc 83 /** \brief Receive group interrupts
robert_jw 0:b2805b6888dc 84 */
robert_jw 0:b2805b6888dc 85 #define RXINTGROUP (EMAC_INT_RX_OVERRUN | EMAC_INT_RX_ERR | EMAC_INT_RX_DONE)
robert_jw 0:b2805b6888dc 86
robert_jw 0:b2805b6888dc 87 /** \brief Transmit group interrupts
robert_jw 0:b2805b6888dc 88 */
robert_jw 0:b2805b6888dc 89 #define TXINTGROUP (EMAC_INT_TX_UNDERRUN | EMAC_INT_TX_ERR | EMAC_INT_TX_DONE)
robert_jw 0:b2805b6888dc 90
robert_jw 0:b2805b6888dc 91 /** \brief Signal used for ethernet ISR to signal packet_rx() thread.
robert_jw 0:b2805b6888dc 92 */
robert_jw 0:b2805b6888dc 93 #define RX_SIGNAL 1
robert_jw 0:b2805b6888dc 94
robert_jw 0:b2805b6888dc 95 #else
robert_jw 0:b2805b6888dc 96 #define RXINTGROUP 0
robert_jw 0:b2805b6888dc 97 #define TXINTGROUP 0
robert_jw 0:b2805b6888dc 98 #endif
robert_jw 0:b2805b6888dc 99
robert_jw 0:b2805b6888dc 100 /** \brief Structure of a TX/RX descriptor
robert_jw 0:b2805b6888dc 101 */
robert_jw 0:b2805b6888dc 102 typedef struct
robert_jw 0:b2805b6888dc 103 {
robert_jw 0:b2805b6888dc 104 volatile u32_t packet; /**< Pointer to buffer */
robert_jw 0:b2805b6888dc 105 volatile u32_t control; /**< Control word */
robert_jw 0:b2805b6888dc 106 } LPC_TXRX_DESC_T;
robert_jw 0:b2805b6888dc 107
robert_jw 0:b2805b6888dc 108 /** \brief Structure of a RX status entry
robert_jw 0:b2805b6888dc 109 */
robert_jw 0:b2805b6888dc 110 typedef struct
robert_jw 0:b2805b6888dc 111 {
robert_jw 0:b2805b6888dc 112 volatile u32_t statusinfo; /**< RX status word */
robert_jw 0:b2805b6888dc 113 volatile u32_t statushashcrc; /**< RX hash CRC */
robert_jw 0:b2805b6888dc 114 } LPC_TXRX_STATUS_T;
robert_jw 0:b2805b6888dc 115
robert_jw 0:b2805b6888dc 116 /* LPC EMAC driver data structure */
robert_jw 0:b2805b6888dc 117 struct lpc_enetdata {
robert_jw 0:b2805b6888dc 118 /* prxs must be 8 byte aligned! */
robert_jw 0:b2805b6888dc 119 LPC_TXRX_STATUS_T prxs[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX statuses */
robert_jw 0:b2805b6888dc 120 struct netif *netif; /**< Reference back to LWIP parent netif */
robert_jw 0:b2805b6888dc 121 LPC_TXRX_DESC_T ptxd[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX descriptor list */
robert_jw 0:b2805b6888dc 122 LPC_TXRX_STATUS_T ptxs[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX statuses */
robert_jw 0:b2805b6888dc 123 LPC_TXRX_DESC_T prxd[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX descriptor list */
robert_jw 0:b2805b6888dc 124 struct pbuf *rxb[LPC_NUM_BUFF_RXDESCS]; /**< RX pbuf pointer list, zero-copy mode */
robert_jw 0:b2805b6888dc 125 u32_t rx_fill_desc_index; /**< RX descriptor next available index */
robert_jw 0:b2805b6888dc 126 volatile u32_t rx_free_descs; /**< Count of free RX descriptors */
robert_jw 0:b2805b6888dc 127 struct pbuf *txb[LPC_NUM_BUFF_TXDESCS]; /**< TX pbuf pointer list, zero-copy mode */
robert_jw 0:b2805b6888dc 128 u32_t lpc_last_tx_idx; /**< TX last descriptor index, zero-copy mode */
robert_jw 0:b2805b6888dc 129 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 130 sys_thread_t RxThread; /**< RX receive thread data object pointer */
robert_jw 0:b2805b6888dc 131 sys_sem_t TxCleanSem; /**< TX cleanup thread wakeup semaphore */
robert_jw 0:b2805b6888dc 132 sys_mutex_t TXLockMutex; /**< TX critical section mutex */
robert_jw 0:b2805b6888dc 133 sys_sem_t xTXDCountSem; /**< TX free buffer counting semaphore */
robert_jw 0:b2805b6888dc 134 #endif
robert_jw 0:b2805b6888dc 135 };
robert_jw 0:b2805b6888dc 136
robert_jw 0:b2805b6888dc 137 #if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
robert_jw 0:b2805b6888dc 138 # if defined (__ICCARM__)
robert_jw 0:b2805b6888dc 139 # define ETHMEM_SECTION
robert_jw 0:b2805b6888dc 140 # elif defined(TOOLCHAIN_GCC_CR)
robert_jw 0:b2805b6888dc 141 # define ETHMEM_SECTION __attribute__((section(".data.$RamPeriph32"), aligned))
robert_jw 0:b2805b6888dc 142 # else
robert_jw 0:b2805b6888dc 143 # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
robert_jw 0:b2805b6888dc 144 # endif
robert_jw 0:b2805b6888dc 145 #elif defined(TARGET_LPC1768)
robert_jw 0:b2805b6888dc 146 # if defined(TOOLCHAIN_GCC_ARM)
robert_jw 0:b2805b6888dc 147 # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
robert_jw 0:b2805b6888dc 148 # endif
robert_jw 0:b2805b6888dc 149 #endif
robert_jw 0:b2805b6888dc 150
robert_jw 0:b2805b6888dc 151 #ifndef ETHMEM_SECTION
robert_jw 0:b2805b6888dc 152 #define ETHMEM_SECTION ALIGNED(8)
robert_jw 0:b2805b6888dc 153 #endif
robert_jw 0:b2805b6888dc 154
robert_jw 0:b2805b6888dc 155 /** \brief LPC EMAC driver work data
robert_jw 0:b2805b6888dc 156 */
robert_jw 0:b2805b6888dc 157 ETHMEM_SECTION struct lpc_enetdata lpc_enetdata;
robert_jw 0:b2805b6888dc 158
robert_jw 0:b2805b6888dc 159 /** \brief Queues a pbuf into the RX descriptor list
robert_jw 0:b2805b6888dc 160 *
robert_jw 0:b2805b6888dc 161 * \param[in] lpc_enetif Pointer to the drvier data structure
robert_jw 0:b2805b6888dc 162 * \param[in] p Pointer to pbuf to queue
robert_jw 0:b2805b6888dc 163 */
robert_jw 0:b2805b6888dc 164 static void lpc_rxqueue_pbuf(struct lpc_enetdata *lpc_enetif, struct pbuf *p)
robert_jw 0:b2805b6888dc 165 {
robert_jw 0:b2805b6888dc 166 u32_t idx;
robert_jw 0:b2805b6888dc 167
robert_jw 0:b2805b6888dc 168 /* Get next free descriptor index */
robert_jw 0:b2805b6888dc 169 idx = lpc_enetif->rx_fill_desc_index;
robert_jw 0:b2805b6888dc 170
robert_jw 0:b2805b6888dc 171 /* Setup descriptor and clear statuses */
robert_jw 0:b2805b6888dc 172 lpc_enetif->prxd[idx].control = EMAC_RCTRL_INT | ((u32_t) (p->len - 1));
robert_jw 0:b2805b6888dc 173 lpc_enetif->prxd[idx].packet = (u32_t) p->payload;
robert_jw 0:b2805b6888dc 174 lpc_enetif->prxs[idx].statusinfo = 0xFFFFFFFF;
robert_jw 0:b2805b6888dc 175 lpc_enetif->prxs[idx].statushashcrc = 0xFFFFFFFF;
robert_jw 0:b2805b6888dc 176
robert_jw 0:b2805b6888dc 177 /* Save pbuf pointer for push to network layer later */
robert_jw 0:b2805b6888dc 178 lpc_enetif->rxb[idx] = p;
robert_jw 0:b2805b6888dc 179
robert_jw 0:b2805b6888dc 180 /* Wrap at end of descriptor list */
robert_jw 0:b2805b6888dc 181 idx++;
robert_jw 0:b2805b6888dc 182 if (idx >= LPC_NUM_BUFF_RXDESCS)
robert_jw 0:b2805b6888dc 183 idx = 0;
robert_jw 0:b2805b6888dc 184
robert_jw 0:b2805b6888dc 185 /* Queue descriptor(s) */
robert_jw 0:b2805b6888dc 186 lpc_enetif->rx_free_descs -= 1;
robert_jw 0:b2805b6888dc 187 lpc_enetif->rx_fill_desc_index = idx;
robert_jw 0:b2805b6888dc 188 LPC_EMAC->RxConsumeIndex = idx;
robert_jw 0:b2805b6888dc 189
robert_jw 0:b2805b6888dc 190 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
robert_jw 0:b2805b6888dc 191 ("lpc_rxqueue_pbuf: pbuf packet queued: %p (free desc=%d)\n", p,
robert_jw 0:b2805b6888dc 192 lpc_enetif->rx_free_descs));
robert_jw 0:b2805b6888dc 193 }
robert_jw 0:b2805b6888dc 194
robert_jw 0:b2805b6888dc 195 /** \brief Attempt to allocate and requeue a new pbuf for RX
robert_jw 0:b2805b6888dc 196 *
robert_jw 0:b2805b6888dc 197 * \param[in] netif Pointer to the netif structure
robert_jw 0:b2805b6888dc 198 * \returns 1 if a packet was allocated and requeued, otherwise 0
robert_jw 0:b2805b6888dc 199 */
robert_jw 0:b2805b6888dc 200 s32_t lpc_rx_queue(struct netif *netif)
robert_jw 0:b2805b6888dc 201 {
robert_jw 0:b2805b6888dc 202 struct lpc_enetdata *lpc_enetif = netif->state;
robert_jw 0:b2805b6888dc 203 struct pbuf *p;
robert_jw 0:b2805b6888dc 204 s32_t queued = 0;
robert_jw 0:b2805b6888dc 205
robert_jw 0:b2805b6888dc 206 /* Attempt to requeue as many packets as possible */
robert_jw 0:b2805b6888dc 207 while (lpc_enetif->rx_free_descs > 0) {
robert_jw 0:b2805b6888dc 208 /* Allocate a pbuf from the pool. We need to allocate at the
robert_jw 0:b2805b6888dc 209 maximum size as we don't know the size of the yet to be
robert_jw 0:b2805b6888dc 210 received packet. */
robert_jw 0:b2805b6888dc 211 p = pbuf_alloc(PBUF_RAW, (u16_t) EMAC_ETH_MAX_FLEN, PBUF_RAM);
robert_jw 0:b2805b6888dc 212 if (p == NULL) {
robert_jw 0:b2805b6888dc 213 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
robert_jw 0:b2805b6888dc 214 ("lpc_rx_queue: could not allocate RX pbuf (free desc=%d)\n",
robert_jw 0:b2805b6888dc 215 lpc_enetif->rx_free_descs));
robert_jw 0:b2805b6888dc 216 return queued;
robert_jw 0:b2805b6888dc 217 }
robert_jw 0:b2805b6888dc 218
robert_jw 0:b2805b6888dc 219 /* pbufs allocated from the RAM pool should be non-chained. */
robert_jw 0:b2805b6888dc 220 LWIP_ASSERT("lpc_rx_queue: pbuf is not contiguous (chained)",
robert_jw 0:b2805b6888dc 221 pbuf_clen(p) <= 1);
robert_jw 0:b2805b6888dc 222
robert_jw 0:b2805b6888dc 223 /* Queue packet */
robert_jw 0:b2805b6888dc 224 lpc_rxqueue_pbuf(lpc_enetif, p);
robert_jw 0:b2805b6888dc 225
robert_jw 0:b2805b6888dc 226 /* Update queued count */
robert_jw 0:b2805b6888dc 227 queued++;
robert_jw 0:b2805b6888dc 228 }
robert_jw 0:b2805b6888dc 229
robert_jw 0:b2805b6888dc 230 return queued;
robert_jw 0:b2805b6888dc 231 }
robert_jw 0:b2805b6888dc 232
robert_jw 0:b2805b6888dc 233 /** \brief Sets up the RX descriptor ring buffers.
robert_jw 0:b2805b6888dc 234 *
robert_jw 0:b2805b6888dc 235 * This function sets up the descriptor list used for receive packets.
robert_jw 0:b2805b6888dc 236 *
robert_jw 0:b2805b6888dc 237 * \param[in] lpc_enetif Pointer to driver data structure
robert_jw 0:b2805b6888dc 238 * \returns Always returns ERR_OK
robert_jw 0:b2805b6888dc 239 */
robert_jw 0:b2805b6888dc 240 static err_t lpc_rx_setup(struct lpc_enetdata *lpc_enetif)
robert_jw 0:b2805b6888dc 241 {
robert_jw 0:b2805b6888dc 242 /* Setup pointers to RX structures */
robert_jw 0:b2805b6888dc 243 LPC_EMAC->RxDescriptor = (u32_t) &lpc_enetif->prxd[0];
robert_jw 0:b2805b6888dc 244 LPC_EMAC->RxStatus = (u32_t) &lpc_enetif->prxs[0];
robert_jw 0:b2805b6888dc 245 LPC_EMAC->RxDescriptorNumber = LPC_NUM_BUFF_RXDESCS - 1;
robert_jw 0:b2805b6888dc 246
robert_jw 0:b2805b6888dc 247 lpc_enetif->rx_free_descs = LPC_NUM_BUFF_RXDESCS;
robert_jw 0:b2805b6888dc 248 lpc_enetif->rx_fill_desc_index = 0;
robert_jw 0:b2805b6888dc 249
robert_jw 0:b2805b6888dc 250 /* Build RX buffer and descriptors */
robert_jw 0:b2805b6888dc 251 lpc_rx_queue(lpc_enetif->netif);
robert_jw 0:b2805b6888dc 252
robert_jw 0:b2805b6888dc 253 return ERR_OK;
robert_jw 0:b2805b6888dc 254 }
robert_jw 0:b2805b6888dc 255
robert_jw 0:b2805b6888dc 256 /** \brief Allocates a pbuf and returns the data from the incoming packet.
robert_jw 0:b2805b6888dc 257 *
robert_jw 0:b2805b6888dc 258 * \param[in] netif the lwip network interface structure for this lpc_enetif
robert_jw 0:b2805b6888dc 259 * \return a pbuf filled with the received packet (including MAC header)
robert_jw 0:b2805b6888dc 260 * NULL on memory error
robert_jw 0:b2805b6888dc 261 */
robert_jw 0:b2805b6888dc 262 static struct pbuf *lpc_low_level_input(struct netif *netif)
robert_jw 0:b2805b6888dc 263 {
robert_jw 0:b2805b6888dc 264 struct lpc_enetdata *lpc_enetif = netif->state;
robert_jw 0:b2805b6888dc 265 struct pbuf *p = NULL;
robert_jw 0:b2805b6888dc 266 u32_t idx, length;
robert_jw 0:b2805b6888dc 267 u16_t origLength;
robert_jw 0:b2805b6888dc 268
robert_jw 0:b2805b6888dc 269 #ifdef LOCK_RX_THREAD
robert_jw 0:b2805b6888dc 270 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 271 /* Get exclusive access */
robert_jw 0:b2805b6888dc 272 sys_mutex_lock(&lpc_enetif->TXLockMutex);
robert_jw 0:b2805b6888dc 273 #endif
robert_jw 0:b2805b6888dc 274 #endif
robert_jw 0:b2805b6888dc 275
robert_jw 0:b2805b6888dc 276 /* Monitor RX overrun status. This should never happen unless
robert_jw 0:b2805b6888dc 277 (possibly) the internal bus is behing held up by something.
robert_jw 0:b2805b6888dc 278 Unless your system is running at a very low clock speed or
robert_jw 0:b2805b6888dc 279 there are possibilities that the internal buses may be held
robert_jw 0:b2805b6888dc 280 up for a long time, this can probably safely be removed. */
robert_jw 0:b2805b6888dc 281 if (LPC_EMAC->IntStatus & EMAC_INT_RX_OVERRUN) {
robert_jw 0:b2805b6888dc 282 LINK_STATS_INC(link.err);
robert_jw 0:b2805b6888dc 283 LINK_STATS_INC(link.drop);
robert_jw 0:b2805b6888dc 284
robert_jw 0:b2805b6888dc 285 /* Temporarily disable RX */
robert_jw 0:b2805b6888dc 286 LPC_EMAC->MAC1 &= ~EMAC_MAC1_REC_EN;
robert_jw 0:b2805b6888dc 287
robert_jw 0:b2805b6888dc 288 /* Reset the RX side */
robert_jw 0:b2805b6888dc 289 LPC_EMAC->MAC1 |= EMAC_MAC1_RES_RX;
robert_jw 0:b2805b6888dc 290 LPC_EMAC->IntClear = EMAC_INT_RX_OVERRUN;
robert_jw 0:b2805b6888dc 291
robert_jw 0:b2805b6888dc 292 /* De-allocate all queued RX pbufs */
robert_jw 0:b2805b6888dc 293 for (idx = 0; idx < LPC_NUM_BUFF_RXDESCS; idx++) {
robert_jw 0:b2805b6888dc 294 if (lpc_enetif->rxb[idx] != NULL) {
robert_jw 0:b2805b6888dc 295 pbuf_free(lpc_enetif->rxb[idx]);
robert_jw 0:b2805b6888dc 296 lpc_enetif->rxb[idx] = NULL;
robert_jw 0:b2805b6888dc 297 }
robert_jw 0:b2805b6888dc 298 }
robert_jw 0:b2805b6888dc 299
robert_jw 0:b2805b6888dc 300 /* Start RX side again */
robert_jw 0:b2805b6888dc 301 lpc_rx_setup(lpc_enetif);
robert_jw 0:b2805b6888dc 302
robert_jw 0:b2805b6888dc 303 /* Re-enable RX */
robert_jw 0:b2805b6888dc 304 LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
robert_jw 0:b2805b6888dc 305
robert_jw 0:b2805b6888dc 306 #ifdef LOCK_RX_THREAD
robert_jw 0:b2805b6888dc 307 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 308 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
robert_jw 0:b2805b6888dc 309 #endif
robert_jw 0:b2805b6888dc 310 #endif
robert_jw 0:b2805b6888dc 311
robert_jw 0:b2805b6888dc 312 return NULL;
robert_jw 0:b2805b6888dc 313 }
robert_jw 0:b2805b6888dc 314
robert_jw 0:b2805b6888dc 315 /* Determine if a frame has been received */
robert_jw 0:b2805b6888dc 316 length = 0;
robert_jw 0:b2805b6888dc 317 idx = LPC_EMAC->RxConsumeIndex;
robert_jw 0:b2805b6888dc 318 if (LPC_EMAC->RxProduceIndex != idx) {
robert_jw 0:b2805b6888dc 319 /* Handle errors */
robert_jw 0:b2805b6888dc 320 if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
robert_jw 0:b2805b6888dc 321 EMAC_RINFO_SYM_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_LEN_ERR)) {
robert_jw 0:b2805b6888dc 322 #if LINK_STATS
robert_jw 0:b2805b6888dc 323 if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
robert_jw 0:b2805b6888dc 324 EMAC_RINFO_SYM_ERR | EMAC_RINFO_ALIGN_ERR))
robert_jw 0:b2805b6888dc 325 LINK_STATS_INC(link.chkerr);
robert_jw 0:b2805b6888dc 326 if (lpc_enetif->prxs[idx].statusinfo & EMAC_RINFO_LEN_ERR)
robert_jw 0:b2805b6888dc 327 LINK_STATS_INC(link.lenerr);
robert_jw 0:b2805b6888dc 328 #endif
robert_jw 0:b2805b6888dc 329
robert_jw 0:b2805b6888dc 330 /* Drop the frame */
robert_jw 0:b2805b6888dc 331 LINK_STATS_INC(link.drop);
robert_jw 0:b2805b6888dc 332
robert_jw 0:b2805b6888dc 333 /* Re-queue the pbuf for receive */
robert_jw 0:b2805b6888dc 334 lpc_enetif->rx_free_descs++;
robert_jw 0:b2805b6888dc 335 p = lpc_enetif->rxb[idx];
robert_jw 0:b2805b6888dc 336 lpc_enetif->rxb[idx] = NULL;
robert_jw 0:b2805b6888dc 337 lpc_rxqueue_pbuf(lpc_enetif, p);
robert_jw 0:b2805b6888dc 338
robert_jw 0:b2805b6888dc 339 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
robert_jw 0:b2805b6888dc 340 ("lpc_low_level_input: Packet dropped with errors (0x%x)\n",
robert_jw 0:b2805b6888dc 341 lpc_enetif->prxs[idx].statusinfo));
robert_jw 0:b2805b6888dc 342
robert_jw 0:b2805b6888dc 343 p = NULL;
robert_jw 0:b2805b6888dc 344 } else {
robert_jw 0:b2805b6888dc 345 /* A packet is waiting, get length */
robert_jw 0:b2805b6888dc 346 length = (lpc_enetif->prxs[idx].statusinfo & 0x7FF) + 1;
robert_jw 0:b2805b6888dc 347
robert_jw 0:b2805b6888dc 348 /* Zero-copy */
robert_jw 0:b2805b6888dc 349 p = lpc_enetif->rxb[idx];
robert_jw 0:b2805b6888dc 350 origLength = p->len;
robert_jw 0:b2805b6888dc 351 p->len = (u16_t) length;
robert_jw 0:b2805b6888dc 352
robert_jw 0:b2805b6888dc 353 /* Free pbuf from descriptor */
robert_jw 0:b2805b6888dc 354 lpc_enetif->rxb[idx] = NULL;
robert_jw 0:b2805b6888dc 355 lpc_enetif->rx_free_descs++;
robert_jw 0:b2805b6888dc 356
robert_jw 0:b2805b6888dc 357 /* Attempt to queue new buffer(s) */
robert_jw 0:b2805b6888dc 358 if (lpc_rx_queue(lpc_enetif->netif) == 0) {
robert_jw 0:b2805b6888dc 359 /* Drop the frame due to OOM. */
robert_jw 0:b2805b6888dc 360 LINK_STATS_INC(link.drop);
robert_jw 0:b2805b6888dc 361
robert_jw 0:b2805b6888dc 362 /* Re-queue the pbuf for receive */
robert_jw 0:b2805b6888dc 363 p->len = origLength;
robert_jw 0:b2805b6888dc 364 lpc_rxqueue_pbuf(lpc_enetif, p);
robert_jw 0:b2805b6888dc 365
robert_jw 0:b2805b6888dc 366 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
robert_jw 0:b2805b6888dc 367 ("lpc_low_level_input: Packet index %d dropped for OOM\n",
robert_jw 0:b2805b6888dc 368 idx));
robert_jw 0:b2805b6888dc 369
robert_jw 0:b2805b6888dc 370 #ifdef LOCK_RX_THREAD
robert_jw 0:b2805b6888dc 371 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 372 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
robert_jw 0:b2805b6888dc 373 #endif
robert_jw 0:b2805b6888dc 374 #endif
robert_jw 0:b2805b6888dc 375
robert_jw 0:b2805b6888dc 376 return NULL;
robert_jw 0:b2805b6888dc 377 }
robert_jw 0:b2805b6888dc 378
robert_jw 0:b2805b6888dc 379 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
robert_jw 0:b2805b6888dc 380 ("lpc_low_level_input: Packet received: %p, size %d (index=%d)\n",
robert_jw 0:b2805b6888dc 381 p, length, idx));
robert_jw 0:b2805b6888dc 382
robert_jw 0:b2805b6888dc 383 /* Save size */
robert_jw 0:b2805b6888dc 384 p->tot_len = (u16_t) length;
robert_jw 0:b2805b6888dc 385 LINK_STATS_INC(link.recv);
robert_jw 0:b2805b6888dc 386 }
robert_jw 0:b2805b6888dc 387 }
robert_jw 0:b2805b6888dc 388
robert_jw 0:b2805b6888dc 389 #ifdef LOCK_RX_THREAD
robert_jw 0:b2805b6888dc 390 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 391 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
robert_jw 0:b2805b6888dc 392 #endif
robert_jw 0:b2805b6888dc 393 #endif
robert_jw 0:b2805b6888dc 394
robert_jw 0:b2805b6888dc 395 return p;
robert_jw 0:b2805b6888dc 396 }
robert_jw 0:b2805b6888dc 397
robert_jw 0:b2805b6888dc 398 /** \brief Attempt to read a packet from the EMAC interface.
robert_jw 0:b2805b6888dc 399 *
robert_jw 0:b2805b6888dc 400 * \param[in] netif the lwip network interface structure for this lpc_enetif
robert_jw 0:b2805b6888dc 401 */
robert_jw 0:b2805b6888dc 402 void lpc_enetif_input(struct netif *netif)
robert_jw 0:b2805b6888dc 403 {
robert_jw 0:b2805b6888dc 404 struct eth_hdr *ethhdr;
robert_jw 0:b2805b6888dc 405 struct pbuf *p;
robert_jw 0:b2805b6888dc 406
robert_jw 0:b2805b6888dc 407 /* move received packet into a new pbuf */
robert_jw 0:b2805b6888dc 408 p = lpc_low_level_input(netif);
robert_jw 0:b2805b6888dc 409 if (p == NULL)
robert_jw 0:b2805b6888dc 410 return;
robert_jw 0:b2805b6888dc 411
robert_jw 0:b2805b6888dc 412 /* points to packet payload, which starts with an Ethernet header */
robert_jw 0:b2805b6888dc 413 ethhdr = p->payload;
robert_jw 0:b2805b6888dc 414
robert_jw 0:b2805b6888dc 415 switch (htons(ethhdr->type)) {
robert_jw 0:b2805b6888dc 416 case ETHTYPE_IP:
robert_jw 0:b2805b6888dc 417 case ETHTYPE_ARP:
robert_jw 0:b2805b6888dc 418 #if PPPOE_SUPPORT
robert_jw 0:b2805b6888dc 419 case ETHTYPE_PPPOEDISC:
robert_jw 0:b2805b6888dc 420 case ETHTYPE_PPPOE:
robert_jw 0:b2805b6888dc 421 #endif /* PPPOE_SUPPORT */
robert_jw 0:b2805b6888dc 422 /* full packet send to tcpip_thread to process */
robert_jw 0:b2805b6888dc 423 if (netif->input(p, netif) != ERR_OK) {
robert_jw 0:b2805b6888dc 424 LWIP_DEBUGF(NETIF_DEBUG, ("lpc_enetif_input: IP input error\n"));
robert_jw 0:b2805b6888dc 425 /* Free buffer */
robert_jw 0:b2805b6888dc 426 pbuf_free(p);
robert_jw 0:b2805b6888dc 427 }
robert_jw 0:b2805b6888dc 428 break;
robert_jw 0:b2805b6888dc 429
robert_jw 0:b2805b6888dc 430 default:
robert_jw 0:b2805b6888dc 431 /* Return buffer */
robert_jw 0:b2805b6888dc 432 pbuf_free(p);
robert_jw 0:b2805b6888dc 433 break;
robert_jw 0:b2805b6888dc 434 }
robert_jw 0:b2805b6888dc 435 }
robert_jw 0:b2805b6888dc 436
robert_jw 0:b2805b6888dc 437 /** \brief Determine if the passed address is usable for the ethernet
robert_jw 0:b2805b6888dc 438 * DMA controller.
robert_jw 0:b2805b6888dc 439 *
robert_jw 0:b2805b6888dc 440 * \param[in] addr Address of packet to check for DMA safe operation
robert_jw 0:b2805b6888dc 441 * \return 1 if the packet address is not safe, otherwise 0
robert_jw 0:b2805b6888dc 442 */
robert_jw 0:b2805b6888dc 443 static s32_t lpc_packet_addr_notsafe(void *addr) {
robert_jw 0:b2805b6888dc 444 /* Check for legal address ranges */
robert_jw 0:b2805b6888dc 445 #if defined(TARGET_LPC1768)
robert_jw 0:b2805b6888dc 446 if ((((u32_t) addr >= 0x2007C000) && ((u32_t) addr < 0x20083FFF))) {
robert_jw 0:b2805b6888dc 447 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
robert_jw 0:b2805b6888dc 448 if ((((u32_t) addr >= 0x20000000) && ((u32_t) addr < 0x20007FFF))) {
robert_jw 0:b2805b6888dc 449 #endif
robert_jw 0:b2805b6888dc 450 return 0;
robert_jw 0:b2805b6888dc 451 }
robert_jw 0:b2805b6888dc 452 return 1;
robert_jw 0:b2805b6888dc 453 }
robert_jw 0:b2805b6888dc 454
robert_jw 0:b2805b6888dc 455 /** \brief Sets up the TX descriptor ring buffers.
robert_jw 0:b2805b6888dc 456 *
robert_jw 0:b2805b6888dc 457 * This function sets up the descriptor list used for transmit packets.
robert_jw 0:b2805b6888dc 458 *
robert_jw 0:b2805b6888dc 459 * \param[in] lpc_enetif Pointer to driver data structure
robert_jw 0:b2805b6888dc 460 */
robert_jw 0:b2805b6888dc 461 static err_t lpc_tx_setup(struct lpc_enetdata *lpc_enetif)
robert_jw 0:b2805b6888dc 462 {
robert_jw 0:b2805b6888dc 463 s32_t idx;
robert_jw 0:b2805b6888dc 464
robert_jw 0:b2805b6888dc 465 /* Build TX descriptors for local buffers */
robert_jw 0:b2805b6888dc 466 for (idx = 0; idx < LPC_NUM_BUFF_TXDESCS; idx++) {
robert_jw 0:b2805b6888dc 467 lpc_enetif->ptxd[idx].control = 0;
robert_jw 0:b2805b6888dc 468 lpc_enetif->ptxs[idx].statusinfo = 0xFFFFFFFF;
robert_jw 0:b2805b6888dc 469 }
robert_jw 0:b2805b6888dc 470
robert_jw 0:b2805b6888dc 471 /* Setup pointers to TX structures */
robert_jw 0:b2805b6888dc 472 LPC_EMAC->TxDescriptor = (u32_t) &lpc_enetif->ptxd[0];
robert_jw 0:b2805b6888dc 473 LPC_EMAC->TxStatus = (u32_t) &lpc_enetif->ptxs[0];
robert_jw 0:b2805b6888dc 474 LPC_EMAC->TxDescriptorNumber = LPC_NUM_BUFF_TXDESCS - 1;
robert_jw 0:b2805b6888dc 475
robert_jw 0:b2805b6888dc 476 lpc_enetif->lpc_last_tx_idx = 0;
robert_jw 0:b2805b6888dc 477
robert_jw 0:b2805b6888dc 478 return ERR_OK;
robert_jw 0:b2805b6888dc 479 }
robert_jw 0:b2805b6888dc 480
robert_jw 0:b2805b6888dc 481 /** \brief Free TX buffers that are complete
robert_jw 0:b2805b6888dc 482 *
robert_jw 0:b2805b6888dc 483 * \param[in] lpc_enetif Pointer to driver data structure
robert_jw 0:b2805b6888dc 484 * \param[in] cidx EMAC current descriptor comsumer index
robert_jw 0:b2805b6888dc 485 */
robert_jw 0:b2805b6888dc 486 static void lpc_tx_reclaim_st(struct lpc_enetdata *lpc_enetif, u32_t cidx)
robert_jw 0:b2805b6888dc 487 {
robert_jw 0:b2805b6888dc 488 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 489 /* Get exclusive access */
robert_jw 0:b2805b6888dc 490 sys_mutex_lock(&lpc_enetif->TXLockMutex);
robert_jw 0:b2805b6888dc 491 #endif
robert_jw 0:b2805b6888dc 492
robert_jw 0:b2805b6888dc 493 while (cidx != lpc_enetif->lpc_last_tx_idx) {
robert_jw 0:b2805b6888dc 494 if (lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx] != NULL) {
robert_jw 0:b2805b6888dc 495 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
robert_jw 0:b2805b6888dc 496 ("lpc_tx_reclaim_st: Freeing packet %p (index %d)\n",
robert_jw 0:b2805b6888dc 497 lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx],
robert_jw 0:b2805b6888dc 498 lpc_enetif->lpc_last_tx_idx));
robert_jw 0:b2805b6888dc 499 pbuf_free(lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx]);
robert_jw 0:b2805b6888dc 500 lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx] = NULL;
robert_jw 0:b2805b6888dc 501 }
robert_jw 0:b2805b6888dc 502
robert_jw 0:b2805b6888dc 503 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 504 osSemaphoreRelease(lpc_enetif->xTXDCountSem.id);
robert_jw 0:b2805b6888dc 505 #endif
robert_jw 0:b2805b6888dc 506 lpc_enetif->lpc_last_tx_idx++;
robert_jw 0:b2805b6888dc 507 if (lpc_enetif->lpc_last_tx_idx >= LPC_NUM_BUFF_TXDESCS)
robert_jw 0:b2805b6888dc 508 lpc_enetif->lpc_last_tx_idx = 0;
robert_jw 0:b2805b6888dc 509 }
robert_jw 0:b2805b6888dc 510
robert_jw 0:b2805b6888dc 511 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 512 /* Restore access */
robert_jw 0:b2805b6888dc 513 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
robert_jw 0:b2805b6888dc 514 #endif
robert_jw 0:b2805b6888dc 515 }
robert_jw 0:b2805b6888dc 516
robert_jw 0:b2805b6888dc 517 /** \brief User call for freeingTX buffers that are complete
robert_jw 0:b2805b6888dc 518 *
robert_jw 0:b2805b6888dc 519 * \param[in] netif the lwip network interface structure for this lpc_enetif
robert_jw 0:b2805b6888dc 520 */
robert_jw 0:b2805b6888dc 521 void lpc_tx_reclaim(struct netif *netif)
robert_jw 0:b2805b6888dc 522 {
robert_jw 0:b2805b6888dc 523 lpc_tx_reclaim_st((struct lpc_enetdata *) netif->state,
robert_jw 0:b2805b6888dc 524 LPC_EMAC->TxConsumeIndex);
robert_jw 0:b2805b6888dc 525 }
robert_jw 0:b2805b6888dc 526
robert_jw 0:b2805b6888dc 527 /** \brief Polls if an available TX descriptor is ready. Can be used to
robert_jw 0:b2805b6888dc 528 * determine if the low level transmit function will block.
robert_jw 0:b2805b6888dc 529 *
robert_jw 0:b2805b6888dc 530 * \param[in] netif the lwip network interface structure for this lpc_enetif
robert_jw 0:b2805b6888dc 531 * \return 0 if no descriptors are read, or >0
robert_jw 0:b2805b6888dc 532 */
robert_jw 0:b2805b6888dc 533 s32_t lpc_tx_ready(struct netif *netif)
robert_jw 0:b2805b6888dc 534 {
robert_jw 0:b2805b6888dc 535 s32_t fb;
robert_jw 0:b2805b6888dc 536 u32_t idx, cidx;
robert_jw 0:b2805b6888dc 537
robert_jw 0:b2805b6888dc 538 cidx = LPC_EMAC->TxConsumeIndex;
robert_jw 0:b2805b6888dc 539 idx = LPC_EMAC->TxProduceIndex;
robert_jw 0:b2805b6888dc 540
robert_jw 0:b2805b6888dc 541 /* Determine number of free buffers */
robert_jw 0:b2805b6888dc 542 if (idx == cidx)
robert_jw 0:b2805b6888dc 543 fb = LPC_NUM_BUFF_TXDESCS;
robert_jw 0:b2805b6888dc 544 else if (cidx > idx)
robert_jw 0:b2805b6888dc 545 fb = (LPC_NUM_BUFF_TXDESCS - 1) -
robert_jw 0:b2805b6888dc 546 ((idx + LPC_NUM_BUFF_TXDESCS) - cidx);
robert_jw 0:b2805b6888dc 547 else
robert_jw 0:b2805b6888dc 548 fb = (LPC_NUM_BUFF_TXDESCS - 1) - (cidx - idx);
robert_jw 0:b2805b6888dc 549
robert_jw 0:b2805b6888dc 550 return fb;
robert_jw 0:b2805b6888dc 551 }
robert_jw 0:b2805b6888dc 552
robert_jw 0:b2805b6888dc 553 /** \brief Low level output of a packet. Never call this from an
robert_jw 0:b2805b6888dc 554 * interrupt context, as it may block until TX descriptors
robert_jw 0:b2805b6888dc 555 * become available.
robert_jw 0:b2805b6888dc 556 *
robert_jw 0:b2805b6888dc 557 * \param[in] netif the lwip network interface structure for this lpc_enetif
robert_jw 0:b2805b6888dc 558 * \param[in] p the MAC packet to send (e.g. IP packet including MAC addresses and type)
robert_jw 0:b2805b6888dc 559 * \return ERR_OK if the packet could be sent or an err_t value if the packet couldn't be sent
robert_jw 0:b2805b6888dc 560 */
robert_jw 0:b2805b6888dc 561 static err_t lpc_low_level_output(struct netif *netif, struct pbuf *p)
robert_jw 0:b2805b6888dc 562 {
robert_jw 0:b2805b6888dc 563 struct lpc_enetdata *lpc_enetif = netif->state;
robert_jw 0:b2805b6888dc 564 struct pbuf *q;
robert_jw 0:b2805b6888dc 565 u8_t *dst;
robert_jw 0:b2805b6888dc 566 u32_t idx, notdmasafe = 0;
robert_jw 0:b2805b6888dc 567 struct pbuf *np;
robert_jw 0:b2805b6888dc 568 s32_t dn;
robert_jw 0:b2805b6888dc 569
robert_jw 0:b2805b6888dc 570 /* Zero-copy TX buffers may be fragmented across mutliple payload
robert_jw 0:b2805b6888dc 571 chains. Determine the number of descriptors needed for the
robert_jw 0:b2805b6888dc 572 transfer. The pbuf chaining can be a mess! */
robert_jw 0:b2805b6888dc 573 dn = (s32_t) pbuf_clen(p);
robert_jw 0:b2805b6888dc 574
robert_jw 0:b2805b6888dc 575 /* Test to make sure packet addresses are DMA safe. A DMA safe
robert_jw 0:b2805b6888dc 576 address is once that uses external memory or periphheral RAM.
robert_jw 0:b2805b6888dc 577 IRAM and FLASH are not safe! */
robert_jw 0:b2805b6888dc 578 for (q = p; q != NULL; q = q->next)
robert_jw 0:b2805b6888dc 579 notdmasafe += lpc_packet_addr_notsafe(q->payload);
robert_jw 0:b2805b6888dc 580
robert_jw 0:b2805b6888dc 581 #if LPC_TX_PBUF_BOUNCE_EN==1
robert_jw 0:b2805b6888dc 582 /* If the pbuf is not DMA safe, a new bounce buffer (pbuf) will be
robert_jw 0:b2805b6888dc 583 created that will be used instead. This requires an copy from the
robert_jw 0:b2805b6888dc 584 non-safe DMA region to the new pbuf */
robert_jw 0:b2805b6888dc 585 if (notdmasafe) {
robert_jw 0:b2805b6888dc 586 /* Allocate a pbuf in DMA memory */
robert_jw 0:b2805b6888dc 587 np = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
robert_jw 0:b2805b6888dc 588 if (np == NULL)
robert_jw 0:b2805b6888dc 589 return ERR_MEM;
robert_jw 0:b2805b6888dc 590
robert_jw 0:b2805b6888dc 591 /* This buffer better be contiguous! */
robert_jw 0:b2805b6888dc 592 LWIP_ASSERT("lpc_low_level_output: New transmit pbuf is chained",
robert_jw 0:b2805b6888dc 593 (pbuf_clen(np) == 1));
robert_jw 0:b2805b6888dc 594
robert_jw 0:b2805b6888dc 595 /* Copy to DMA safe pbuf */
robert_jw 0:b2805b6888dc 596 dst = (u8_t *) np->payload;
robert_jw 0:b2805b6888dc 597 for(q = p; q != NULL; q = q->next) {
robert_jw 0:b2805b6888dc 598 /* Copy the buffer to the descriptor's buffer */
robert_jw 0:b2805b6888dc 599 MEMCPY(dst, (u8_t *) q->payload, q->len);
robert_jw 0:b2805b6888dc 600 dst += q->len;
robert_jw 0:b2805b6888dc 601 }
robert_jw 0:b2805b6888dc 602 np->len = p->tot_len;
robert_jw 0:b2805b6888dc 603
robert_jw 0:b2805b6888dc 604 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
robert_jw 0:b2805b6888dc 605 ("lpc_low_level_output: Switched to DMA safe buffer, old=%p, new=%p\n",
robert_jw 0:b2805b6888dc 606 q, np));
robert_jw 0:b2805b6888dc 607
robert_jw 0:b2805b6888dc 608 /* use the new buffer for descrptor queueing. The original pbuf will
robert_jw 0:b2805b6888dc 609 be de-allocated outsuide this driver. */
robert_jw 0:b2805b6888dc 610 p = np;
robert_jw 0:b2805b6888dc 611 dn = 1;
robert_jw 0:b2805b6888dc 612 }
robert_jw 0:b2805b6888dc 613 #else
robert_jw 0:b2805b6888dc 614 if (notdmasafe)
robert_jw 0:b2805b6888dc 615 LWIP_ASSERT("lpc_low_level_output: Not a DMA safe pbuf",
robert_jw 0:b2805b6888dc 616 (notdmasafe == 0));
robert_jw 0:b2805b6888dc 617 #endif
robert_jw 0:b2805b6888dc 618
robert_jw 0:b2805b6888dc 619 /* Wait until enough descriptors are available for the transfer. */
robert_jw 0:b2805b6888dc 620 /* THIS WILL BLOCK UNTIL THERE ARE ENOUGH DESCRIPTORS AVAILABLE */
robert_jw 0:b2805b6888dc 621 while (dn > lpc_tx_ready(netif))
robert_jw 0:b2805b6888dc 622 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 623 osSemaphoreWait(lpc_enetif->xTXDCountSem.id, osWaitForever);
robert_jw 0:b2805b6888dc 624 #else
robert_jw 0:b2805b6888dc 625 osDelay(1);
robert_jw 0:b2805b6888dc 626 #endif
robert_jw 0:b2805b6888dc 627
robert_jw 0:b2805b6888dc 628 /* Get free TX buffer index */
robert_jw 0:b2805b6888dc 629 idx = LPC_EMAC->TxProduceIndex;
robert_jw 0:b2805b6888dc 630
robert_jw 0:b2805b6888dc 631 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 632 /* Get exclusive access */
robert_jw 0:b2805b6888dc 633 sys_mutex_lock(&lpc_enetif->TXLockMutex);
robert_jw 0:b2805b6888dc 634 #endif
robert_jw 0:b2805b6888dc 635
robert_jw 0:b2805b6888dc 636 /* Prevent LWIP from de-allocating this pbuf. The driver will
robert_jw 0:b2805b6888dc 637 free it once it's been transmitted. */
robert_jw 0:b2805b6888dc 638 if (!notdmasafe)
robert_jw 0:b2805b6888dc 639 pbuf_ref(p);
robert_jw 0:b2805b6888dc 640
robert_jw 0:b2805b6888dc 641 /* Setup transfers */
robert_jw 0:b2805b6888dc 642 q = p;
robert_jw 0:b2805b6888dc 643 while (dn > 0) {
robert_jw 0:b2805b6888dc 644 dn--;
robert_jw 0:b2805b6888dc 645
robert_jw 0:b2805b6888dc 646 /* Only save pointer to free on last descriptor */
robert_jw 0:b2805b6888dc 647 if (dn == 0) {
robert_jw 0:b2805b6888dc 648 /* Save size of packet and signal it's ready */
robert_jw 0:b2805b6888dc 649 lpc_enetif->ptxd[idx].control = (q->len - 1) | EMAC_TCTRL_INT |
robert_jw 0:b2805b6888dc 650 EMAC_TCTRL_LAST;
robert_jw 0:b2805b6888dc 651 lpc_enetif->txb[idx] = p;
robert_jw 0:b2805b6888dc 652 }
robert_jw 0:b2805b6888dc 653 else {
robert_jw 0:b2805b6888dc 654 /* Save size of packet, descriptor is not last */
robert_jw 0:b2805b6888dc 655 lpc_enetif->ptxd[idx].control = (q->len - 1) | EMAC_TCTRL_INT;
robert_jw 0:b2805b6888dc 656 lpc_enetif->txb[idx] = NULL;
robert_jw 0:b2805b6888dc 657 }
robert_jw 0:b2805b6888dc 658
robert_jw 0:b2805b6888dc 659 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
robert_jw 0:b2805b6888dc 660 ("lpc_low_level_output: pbuf packet(%p) sent, chain#=%d,"
robert_jw 0:b2805b6888dc 661 " size = %d (index=%d)\n", q->payload, dn, q->len, idx));
robert_jw 0:b2805b6888dc 662
robert_jw 0:b2805b6888dc 663 lpc_enetif->ptxd[idx].packet = (u32_t) q->payload;
robert_jw 0:b2805b6888dc 664
robert_jw 0:b2805b6888dc 665 q = q->next;
robert_jw 0:b2805b6888dc 666
robert_jw 0:b2805b6888dc 667 idx++;
robert_jw 0:b2805b6888dc 668 if (idx >= LPC_NUM_BUFF_TXDESCS)
robert_jw 0:b2805b6888dc 669 idx = 0;
robert_jw 0:b2805b6888dc 670 }
robert_jw 0:b2805b6888dc 671
robert_jw 0:b2805b6888dc 672 LPC_EMAC->TxProduceIndex = idx;
robert_jw 0:b2805b6888dc 673
robert_jw 0:b2805b6888dc 674 LINK_STATS_INC(link.xmit);
robert_jw 0:b2805b6888dc 675
robert_jw 0:b2805b6888dc 676 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 677 /* Restore access */
robert_jw 0:b2805b6888dc 678 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
robert_jw 0:b2805b6888dc 679 #endif
robert_jw 0:b2805b6888dc 680
robert_jw 0:b2805b6888dc 681 return ERR_OK;
robert_jw 0:b2805b6888dc 682 }
robert_jw 0:b2805b6888dc 683
robert_jw 0:b2805b6888dc 684 /** \brief LPC EMAC interrupt handler.
robert_jw 0:b2805b6888dc 685 *
robert_jw 0:b2805b6888dc 686 * This function handles the transmit, receive, and error interrupt of
robert_jw 0:b2805b6888dc 687 * the LPC177x_8x. This is meant to be used when NO_SYS=0.
robert_jw 0:b2805b6888dc 688 */
robert_jw 0:b2805b6888dc 689 void ENET_IRQHandler(void)
robert_jw 0:b2805b6888dc 690 {
robert_jw 0:b2805b6888dc 691 #if NO_SYS == 1
robert_jw 0:b2805b6888dc 692 /* Interrupts are not used without an RTOS */
robert_jw 0:b2805b6888dc 693 NVIC_DisableIRQ(ENET_IRQn);
robert_jw 0:b2805b6888dc 694 #else
robert_jw 0:b2805b6888dc 695 uint32_t ints;
robert_jw 0:b2805b6888dc 696
robert_jw 0:b2805b6888dc 697 /* Interrupts are of 2 groups - transmit or receive. Based on the
robert_jw 0:b2805b6888dc 698 interrupt, kick off the receive or transmit (cleanup) task */
robert_jw 0:b2805b6888dc 699
robert_jw 0:b2805b6888dc 700 /* Get pending interrupts */
robert_jw 0:b2805b6888dc 701 ints = LPC_EMAC->IntStatus;
robert_jw 0:b2805b6888dc 702
robert_jw 0:b2805b6888dc 703 if (ints & RXINTGROUP) {
robert_jw 0:b2805b6888dc 704 /* RX group interrupt(s): Give signal to wakeup RX receive task.*/
robert_jw 0:b2805b6888dc 705 osSignalSet(lpc_enetdata.RxThread->id, RX_SIGNAL);
robert_jw 0:b2805b6888dc 706 }
robert_jw 0:b2805b6888dc 707
robert_jw 0:b2805b6888dc 708 if (ints & TXINTGROUP) {
robert_jw 0:b2805b6888dc 709 /* TX group interrupt(s): Give semaphore to wakeup TX cleanup task. */
robert_jw 0:b2805b6888dc 710 sys_sem_signal(&lpc_enetdata.TxCleanSem);
robert_jw 0:b2805b6888dc 711 }
robert_jw 0:b2805b6888dc 712
robert_jw 0:b2805b6888dc 713 /* Clear pending interrupts */
robert_jw 0:b2805b6888dc 714 LPC_EMAC->IntClear = ints;
robert_jw 0:b2805b6888dc 715 #endif
robert_jw 0:b2805b6888dc 716 }
robert_jw 0:b2805b6888dc 717
robert_jw 0:b2805b6888dc 718 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 719 /** \brief Packet reception task
robert_jw 0:b2805b6888dc 720 *
robert_jw 0:b2805b6888dc 721 * This task is called when a packet is received. It will
robert_jw 0:b2805b6888dc 722 * pass the packet to the LWIP core.
robert_jw 0:b2805b6888dc 723 *
robert_jw 0:b2805b6888dc 724 * \param[in] pvParameters Not used yet
robert_jw 0:b2805b6888dc 725 */
robert_jw 0:b2805b6888dc 726 static void packet_rx(void* pvParameters) {
robert_jw 0:b2805b6888dc 727 struct lpc_enetdata *lpc_enetif = pvParameters;
robert_jw 0:b2805b6888dc 728
robert_jw 0:b2805b6888dc 729 while (1) {
robert_jw 0:b2805b6888dc 730 /* Wait for receive task to wakeup */
robert_jw 0:b2805b6888dc 731 osSignalWait(RX_SIGNAL, osWaitForever);
robert_jw 0:b2805b6888dc 732
robert_jw 0:b2805b6888dc 733 /* Process packets until all empty */
robert_jw 0:b2805b6888dc 734 while (LPC_EMAC->RxConsumeIndex != LPC_EMAC->RxProduceIndex)
robert_jw 0:b2805b6888dc 735 lpc_enetif_input(lpc_enetif->netif);
robert_jw 0:b2805b6888dc 736 }
robert_jw 0:b2805b6888dc 737 }
robert_jw 0:b2805b6888dc 738
robert_jw 0:b2805b6888dc 739 /** \brief Transmit cleanup task
robert_jw 0:b2805b6888dc 740 *
robert_jw 0:b2805b6888dc 741 * This task is called when a transmit interrupt occurs and
robert_jw 0:b2805b6888dc 742 * reclaims the pbuf and descriptor used for the packet once
robert_jw 0:b2805b6888dc 743 * the packet has been transferred.
robert_jw 0:b2805b6888dc 744 *
robert_jw 0:b2805b6888dc 745 * \param[in] pvParameters Not used yet
robert_jw 0:b2805b6888dc 746 */
robert_jw 0:b2805b6888dc 747 static void packet_tx(void* pvParameters) {
robert_jw 0:b2805b6888dc 748 struct lpc_enetdata *lpc_enetif = pvParameters;
robert_jw 0:b2805b6888dc 749 s32_t idx;
robert_jw 0:b2805b6888dc 750
robert_jw 0:b2805b6888dc 751 while (1) {
robert_jw 0:b2805b6888dc 752 /* Wait for transmit cleanup task to wakeup */
robert_jw 0:b2805b6888dc 753 sys_arch_sem_wait(&lpc_enetif->TxCleanSem, 0);
robert_jw 0:b2805b6888dc 754
robert_jw 0:b2805b6888dc 755 /* Error handling for TX underruns. This should never happen unless
robert_jw 0:b2805b6888dc 756 something is holding the bus or the clocks are going too slow. It
robert_jw 0:b2805b6888dc 757 can probably be safely removed. */
robert_jw 0:b2805b6888dc 758 if (LPC_EMAC->IntStatus & EMAC_INT_TX_UNDERRUN) {
robert_jw 0:b2805b6888dc 759 LINK_STATS_INC(link.err);
robert_jw 0:b2805b6888dc 760 LINK_STATS_INC(link.drop);
robert_jw 0:b2805b6888dc 761
robert_jw 0:b2805b6888dc 762 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 763 /* Get exclusive access */
robert_jw 0:b2805b6888dc 764 sys_mutex_lock(&lpc_enetif->TXLockMutex);
robert_jw 0:b2805b6888dc 765 #endif
robert_jw 0:b2805b6888dc 766 /* Reset the TX side */
robert_jw 0:b2805b6888dc 767 LPC_EMAC->MAC1 |= EMAC_MAC1_RES_TX;
robert_jw 0:b2805b6888dc 768 LPC_EMAC->IntClear = EMAC_INT_TX_UNDERRUN;
robert_jw 0:b2805b6888dc 769
robert_jw 0:b2805b6888dc 770 /* De-allocate all queued TX pbufs */
robert_jw 0:b2805b6888dc 771 for (idx = 0; idx < LPC_NUM_BUFF_TXDESCS; idx++) {
robert_jw 0:b2805b6888dc 772 if (lpc_enetif->txb[idx] != NULL) {
robert_jw 0:b2805b6888dc 773 pbuf_free(lpc_enetif->txb[idx]);
robert_jw 0:b2805b6888dc 774 lpc_enetif->txb[idx] = NULL;
robert_jw 0:b2805b6888dc 775 }
robert_jw 0:b2805b6888dc 776 }
robert_jw 0:b2805b6888dc 777
robert_jw 0:b2805b6888dc 778 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 779 /* Restore access */
robert_jw 0:b2805b6888dc 780 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
robert_jw 0:b2805b6888dc 781 #endif
robert_jw 0:b2805b6888dc 782 /* Start TX side again */
robert_jw 0:b2805b6888dc 783 lpc_tx_setup(lpc_enetif);
robert_jw 0:b2805b6888dc 784 } else {
robert_jw 0:b2805b6888dc 785 /* Free TX buffers that are done sending */
robert_jw 0:b2805b6888dc 786 lpc_tx_reclaim(lpc_enetdata.netif);
robert_jw 0:b2805b6888dc 787 }
robert_jw 0:b2805b6888dc 788 }
robert_jw 0:b2805b6888dc 789 }
robert_jw 0:b2805b6888dc 790 #endif
robert_jw 0:b2805b6888dc 791
robert_jw 0:b2805b6888dc 792 /** \brief Low level init of the MAC and PHY.
robert_jw 0:b2805b6888dc 793 *
robert_jw 0:b2805b6888dc 794 * \param[in] netif Pointer to LWIP netif structure
robert_jw 0:b2805b6888dc 795 */
robert_jw 0:b2805b6888dc 796 static err_t low_level_init(struct netif *netif)
robert_jw 0:b2805b6888dc 797 {
robert_jw 0:b2805b6888dc 798 struct lpc_enetdata *lpc_enetif = netif->state;
robert_jw 0:b2805b6888dc 799 err_t err = ERR_OK;
robert_jw 0:b2805b6888dc 800
robert_jw 0:b2805b6888dc 801 /* Enable MII clocking */
robert_jw 0:b2805b6888dc 802 LPC_SC->PCONP |= CLKPWR_PCONP_PCENET;
robert_jw 0:b2805b6888dc 803
robert_jw 0:b2805b6888dc 804 #if defined(TARGET_LPC1768)
robert_jw 0:b2805b6888dc 805 LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */
robert_jw 0:b2805b6888dc 806 LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
robert_jw 0:b2805b6888dc 807 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
robert_jw 0:b2805b6888dc 808 LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
robert_jw 0:b2805b6888dc 809 LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */
robert_jw 0:b2805b6888dc 810 LPC_IOCON->P1_1 &= ~0x07;
robert_jw 0:b2805b6888dc 811 LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */
robert_jw 0:b2805b6888dc 812 LPC_IOCON->P1_4 &= ~0x07;
robert_jw 0:b2805b6888dc 813 LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */
robert_jw 0:b2805b6888dc 814 LPC_IOCON->P1_8 &= ~0x07;
robert_jw 0:b2805b6888dc 815 LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */
robert_jw 0:b2805b6888dc 816 LPC_IOCON->P1_9 &= ~0x07;
robert_jw 0:b2805b6888dc 817 LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */
robert_jw 0:b2805b6888dc 818 LPC_IOCON->P1_10 &= ~0x07;
robert_jw 0:b2805b6888dc 819 LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */
robert_jw 0:b2805b6888dc 820 LPC_IOCON->P1_14 &= ~0x07;
robert_jw 0:b2805b6888dc 821 LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */
robert_jw 0:b2805b6888dc 822 LPC_IOCON->P1_15 &= ~0x07;
robert_jw 0:b2805b6888dc 823 LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */
robert_jw 0:b2805b6888dc 824 LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
robert_jw 0:b2805b6888dc 825 LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */
robert_jw 0:b2805b6888dc 826 LPC_IOCON->P1_17 &= ~0x07;
robert_jw 0:b2805b6888dc 827 LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */
robert_jw 0:b2805b6888dc 828 #endif
robert_jw 0:b2805b6888dc 829
robert_jw 0:b2805b6888dc 830 /* Reset all MAC logic */
robert_jw 0:b2805b6888dc 831 LPC_EMAC->MAC1 = EMAC_MAC1_RES_TX | EMAC_MAC1_RES_MCS_TX |
robert_jw 0:b2805b6888dc 832 EMAC_MAC1_RES_RX | EMAC_MAC1_RES_MCS_RX | EMAC_MAC1_SIM_RES |
robert_jw 0:b2805b6888dc 833 EMAC_MAC1_SOFT_RES;
robert_jw 0:b2805b6888dc 834 LPC_EMAC->Command = EMAC_CR_REG_RES | EMAC_CR_TX_RES | EMAC_CR_RX_RES |
robert_jw 0:b2805b6888dc 835 EMAC_CR_PASS_RUNT_FRM;
robert_jw 0:b2805b6888dc 836 osDelay(10);
robert_jw 0:b2805b6888dc 837
robert_jw 0:b2805b6888dc 838 /* Initial MAC initialization */
robert_jw 0:b2805b6888dc 839 LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL;
robert_jw 0:b2805b6888dc 840 LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_EN |
robert_jw 0:b2805b6888dc 841 EMAC_MAC2_VLAN_PAD_EN;
robert_jw 0:b2805b6888dc 842 LPC_EMAC->MAXF = EMAC_ETH_MAX_FLEN;
robert_jw 0:b2805b6888dc 843
robert_jw 0:b2805b6888dc 844 /* Set RMII management clock rate to lowest speed */
robert_jw 0:b2805b6888dc 845 LPC_EMAC->MCFG = EMAC_MCFG_CLK_SEL(11) | EMAC_MCFG_RES_MII;
robert_jw 0:b2805b6888dc 846 LPC_EMAC->MCFG &= ~EMAC_MCFG_RES_MII;
robert_jw 0:b2805b6888dc 847
robert_jw 0:b2805b6888dc 848 /* Maximum number of retries, 0x37 collision window, gap */
robert_jw 0:b2805b6888dc 849 LPC_EMAC->CLRT = EMAC_CLRT_DEF;
robert_jw 0:b2805b6888dc 850 LPC_EMAC->IPGR = EMAC_IPGR_P1_DEF | EMAC_IPGR_P2_DEF;
robert_jw 0:b2805b6888dc 851
robert_jw 0:b2805b6888dc 852 #if LPC_EMAC_RMII
robert_jw 0:b2805b6888dc 853 /* RMII setup */
robert_jw 0:b2805b6888dc 854 LPC_EMAC->Command = EMAC_CR_PASS_RUNT_FRM | EMAC_CR_RMII;
robert_jw 0:b2805b6888dc 855 #else
robert_jw 0:b2805b6888dc 856 /* MII setup */
robert_jw 0:b2805b6888dc 857 LPC_EMAC->CR = EMAC_CR_PASS_RUNT_FRM;
robert_jw 0:b2805b6888dc 858 #endif
robert_jw 0:b2805b6888dc 859
robert_jw 0:b2805b6888dc 860 /* Initialize the PHY and reset */
robert_jw 0:b2805b6888dc 861 err = lpc_phy_init(netif, LPC_EMAC_RMII);
robert_jw 0:b2805b6888dc 862 if (err != ERR_OK)
robert_jw 0:b2805b6888dc 863 return err;
robert_jw 0:b2805b6888dc 864
robert_jw 0:b2805b6888dc 865 /* Save station address */
robert_jw 0:b2805b6888dc 866 LPC_EMAC->SA2 = (u32_t) netif->hwaddr[0] |
robert_jw 0:b2805b6888dc 867 (((u32_t) netif->hwaddr[1]) << 8);
robert_jw 0:b2805b6888dc 868 LPC_EMAC->SA1 = (u32_t) netif->hwaddr[2] |
robert_jw 0:b2805b6888dc 869 (((u32_t) netif->hwaddr[3]) << 8);
robert_jw 0:b2805b6888dc 870 LPC_EMAC->SA0 = (u32_t) netif->hwaddr[4] |
robert_jw 0:b2805b6888dc 871 (((u32_t) netif->hwaddr[5]) << 8);
robert_jw 0:b2805b6888dc 872
robert_jw 0:b2805b6888dc 873 /* Setup transmit and receive descriptors */
robert_jw 0:b2805b6888dc 874 if (lpc_tx_setup(lpc_enetif) != ERR_OK)
robert_jw 0:b2805b6888dc 875 return ERR_BUF;
robert_jw 0:b2805b6888dc 876 if (lpc_rx_setup(lpc_enetif) != ERR_OK)
robert_jw 0:b2805b6888dc 877 return ERR_BUF;
robert_jw 0:b2805b6888dc 878
robert_jw 0:b2805b6888dc 879 /* Enable packet reception */
robert_jw 0:b2805b6888dc 880 #if IP_SOF_BROADCAST_RECV
robert_jw 0:b2805b6888dc 881 LPC_EMAC->RxFilterCtrl = EMAC_RFC_PERFECT_EN | EMAC_RFC_BCAST_EN | EMAC_RFC_MCAST_EN;
robert_jw 0:b2805b6888dc 882 #else
robert_jw 0:b2805b6888dc 883 LPC_EMAC->RxFilterCtrl = EMAC_RFC_PERFECT_EN;
robert_jw 0:b2805b6888dc 884 #endif
robert_jw 0:b2805b6888dc 885
robert_jw 0:b2805b6888dc 886 /* Clear and enable rx/tx interrupts */
robert_jw 0:b2805b6888dc 887 LPC_EMAC->IntClear = 0xFFFF;
robert_jw 0:b2805b6888dc 888 LPC_EMAC->IntEnable = RXINTGROUP | TXINTGROUP;
robert_jw 0:b2805b6888dc 889
robert_jw 0:b2805b6888dc 890 /* Enable RX and TX */
robert_jw 0:b2805b6888dc 891 LPC_EMAC->Command |= EMAC_CR_RX_EN | EMAC_CR_TX_EN;
robert_jw 0:b2805b6888dc 892 LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
robert_jw 0:b2805b6888dc 893
robert_jw 0:b2805b6888dc 894 return err;
robert_jw 0:b2805b6888dc 895 }
robert_jw 0:b2805b6888dc 896
robert_jw 0:b2805b6888dc 897 /* This function provides a method for the PHY to setup the EMAC
robert_jw 0:b2805b6888dc 898 for the PHY negotiated duplex mode */
robert_jw 0:b2805b6888dc 899 void lpc_emac_set_duplex(int full_duplex)
robert_jw 0:b2805b6888dc 900 {
robert_jw 0:b2805b6888dc 901 if (full_duplex) {
robert_jw 0:b2805b6888dc 902 LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
robert_jw 0:b2805b6888dc 903 LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
robert_jw 0:b2805b6888dc 904 LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
robert_jw 0:b2805b6888dc 905 } else {
robert_jw 0:b2805b6888dc 906 LPC_EMAC->MAC2 &= ~EMAC_MAC2_FULL_DUP;
robert_jw 0:b2805b6888dc 907 LPC_EMAC->Command &= ~EMAC_CR_FULL_DUP;
robert_jw 0:b2805b6888dc 908 LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
robert_jw 0:b2805b6888dc 909 }
robert_jw 0:b2805b6888dc 910 }
robert_jw 0:b2805b6888dc 911
robert_jw 0:b2805b6888dc 912 /* This function provides a method for the PHY to setup the EMAC
robert_jw 0:b2805b6888dc 913 for the PHY negotiated bit rate */
robert_jw 0:b2805b6888dc 914 void lpc_emac_set_speed(int mbs_100)
robert_jw 0:b2805b6888dc 915 {
robert_jw 0:b2805b6888dc 916 if (mbs_100)
robert_jw 0:b2805b6888dc 917 LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
robert_jw 0:b2805b6888dc 918 else
robert_jw 0:b2805b6888dc 919 LPC_EMAC->SUPP = 0;
robert_jw 0:b2805b6888dc 920 }
robert_jw 0:b2805b6888dc 921
robert_jw 0:b2805b6888dc 922 /**
robert_jw 0:b2805b6888dc 923 * This function is the ethernet packet send function. It calls
robert_jw 0:b2805b6888dc 924 * etharp_output after checking link status.
robert_jw 0:b2805b6888dc 925 *
robert_jw 0:b2805b6888dc 926 * \param[in] netif the lwip network interface structure for this lpc_enetif
robert_jw 0:b2805b6888dc 927 * \param[in] q Pointer to pbug to send
robert_jw 0:b2805b6888dc 928 * \param[in] ipaddr IP address
robert_jw 0:b2805b6888dc 929 * \return ERR_OK or error code
robert_jw 0:b2805b6888dc 930 */
robert_jw 0:b2805b6888dc 931 err_t lpc_etharp_output(struct netif *netif, struct pbuf *q,
robert_jw 0:b2805b6888dc 932 ip_addr_t *ipaddr)
robert_jw 0:b2805b6888dc 933 {
robert_jw 0:b2805b6888dc 934 /* Only send packet is link is up */
robert_jw 0:b2805b6888dc 935 if (netif->flags & NETIF_FLAG_LINK_UP)
robert_jw 0:b2805b6888dc 936 return etharp_output(netif, q, ipaddr);
robert_jw 0:b2805b6888dc 937
robert_jw 0:b2805b6888dc 938 return ERR_CONN;
robert_jw 0:b2805b6888dc 939 }
robert_jw 0:b2805b6888dc 940
robert_jw 0:b2805b6888dc 941 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 942 /* periodic PHY status update */
robert_jw 0:b2805b6888dc 943 void phy_update(void const *nif) {
robert_jw 0:b2805b6888dc 944 lpc_phy_sts_sm((struct netif*)nif);
robert_jw 0:b2805b6888dc 945 }
robert_jw 0:b2805b6888dc 946 osTimerDef(phy_update, phy_update);
robert_jw 0:b2805b6888dc 947 #endif
robert_jw 0:b2805b6888dc 948
robert_jw 0:b2805b6888dc 949 /**
robert_jw 0:b2805b6888dc 950 * Should be called at the beginning of the program to set up the
robert_jw 0:b2805b6888dc 951 * network interface.
robert_jw 0:b2805b6888dc 952 *
robert_jw 0:b2805b6888dc 953 * This function should be passed as a parameter to netif_add().
robert_jw 0:b2805b6888dc 954 *
robert_jw 0:b2805b6888dc 955 * @param[in] netif the lwip network interface structure for this lpc_enetif
robert_jw 0:b2805b6888dc 956 * @return ERR_OK if the loopif is initialized
robert_jw 0:b2805b6888dc 957 * ERR_MEM if private data couldn't be allocated
robert_jw 0:b2805b6888dc 958 * any other err_t on error
robert_jw 0:b2805b6888dc 959 */
robert_jw 0:b2805b6888dc 960 err_t eth_arch_enetif_init(struct netif *netif)
robert_jw 0:b2805b6888dc 961 {
robert_jw 0:b2805b6888dc 962 err_t err;
robert_jw 0:b2805b6888dc 963
robert_jw 0:b2805b6888dc 964 LWIP_ASSERT("netif != NULL", (netif != NULL));
robert_jw 0:b2805b6888dc 965
robert_jw 0:b2805b6888dc 966 lpc_enetdata.netif = netif;
robert_jw 0:b2805b6888dc 967
robert_jw 0:b2805b6888dc 968 /* set MAC hardware address */
robert_jw 0:b2805b6888dc 969 #if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
robert_jw 0:b2805b6888dc 970 netif->hwaddr[0] = MBED_MAC_ADDR_0;
robert_jw 0:b2805b6888dc 971 netif->hwaddr[1] = MBED_MAC_ADDR_1;
robert_jw 0:b2805b6888dc 972 netif->hwaddr[2] = MBED_MAC_ADDR_2;
robert_jw 0:b2805b6888dc 973 netif->hwaddr[3] = MBED_MAC_ADDR_3;
robert_jw 0:b2805b6888dc 974 netif->hwaddr[4] = MBED_MAC_ADDR_4;
robert_jw 0:b2805b6888dc 975 netif->hwaddr[5] = MBED_MAC_ADDR_5;
robert_jw 0:b2805b6888dc 976 #else
robert_jw 0:b2805b6888dc 977 mbed_mac_address((char *)netif->hwaddr);
robert_jw 0:b2805b6888dc 978 #endif
robert_jw 0:b2805b6888dc 979 netif->hwaddr_len = ETHARP_HWADDR_LEN;
robert_jw 0:b2805b6888dc 980
robert_jw 0:b2805b6888dc 981 /* maximum transfer unit */
robert_jw 0:b2805b6888dc 982 netif->mtu = 1500;
robert_jw 0:b2805b6888dc 983
robert_jw 0:b2805b6888dc 984 /* device capabilities */
robert_jw 0:b2805b6888dc 985 netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP;
robert_jw 0:b2805b6888dc 986
robert_jw 0:b2805b6888dc 987 /* Initialize the hardware */
robert_jw 0:b2805b6888dc 988 netif->state = &lpc_enetdata;
robert_jw 0:b2805b6888dc 989 err = low_level_init(netif);
robert_jw 0:b2805b6888dc 990 if (err != ERR_OK)
robert_jw 0:b2805b6888dc 991 return err;
robert_jw 0:b2805b6888dc 992
robert_jw 0:b2805b6888dc 993 #if LWIP_NETIF_HOSTNAME
robert_jw 0:b2805b6888dc 994 /* Initialize interface hostname */
robert_jw 0:b2805b6888dc 995 netif->hostname = "lwiplpc";
robert_jw 0:b2805b6888dc 996 #endif /* LWIP_NETIF_HOSTNAME */
robert_jw 0:b2805b6888dc 997
robert_jw 0:b2805b6888dc 998 netif->name[0] = 'e';
robert_jw 0:b2805b6888dc 999 netif->name[1] = 'n';
robert_jw 0:b2805b6888dc 1000
robert_jw 0:b2805b6888dc 1001 netif->output = lpc_etharp_output;
robert_jw 0:b2805b6888dc 1002 netif->linkoutput = lpc_low_level_output;
robert_jw 0:b2805b6888dc 1003
robert_jw 0:b2805b6888dc 1004 /* CMSIS-RTOS, start tasks */
robert_jw 0:b2805b6888dc 1005 #if NO_SYS == 0
robert_jw 0:b2805b6888dc 1006 #ifdef CMSIS_OS_RTX
robert_jw 0:b2805b6888dc 1007 memset(lpc_enetdata.xTXDCountSem.data, 0, sizeof(lpc_enetdata.xTXDCountSem.data));
robert_jw 0:b2805b6888dc 1008 lpc_enetdata.xTXDCountSem.def.semaphore = lpc_enetdata.xTXDCountSem.data;
robert_jw 0:b2805b6888dc 1009 #endif
robert_jw 0:b2805b6888dc 1010 lpc_enetdata.xTXDCountSem.id = osSemaphoreCreate(&lpc_enetdata.xTXDCountSem.def, LPC_NUM_BUFF_TXDESCS);
robert_jw 0:b2805b6888dc 1011 LWIP_ASSERT("xTXDCountSem creation error", (lpc_enetdata.xTXDCountSem.id != NULL));
robert_jw 0:b2805b6888dc 1012
robert_jw 0:b2805b6888dc 1013 err = sys_mutex_new(&lpc_enetdata.TXLockMutex);
robert_jw 0:b2805b6888dc 1014 LWIP_ASSERT("TXLockMutex creation error", (err == ERR_OK));
robert_jw 0:b2805b6888dc 1015
robert_jw 0:b2805b6888dc 1016 /* Packet receive task */
robert_jw 0:b2805b6888dc 1017 lpc_enetdata.RxThread = sys_thread_new("receive_thread", packet_rx, netif->state, DEFAULT_THREAD_STACKSIZE, RX_PRIORITY);
robert_jw 0:b2805b6888dc 1018 LWIP_ASSERT("RxThread creation error", (lpc_enetdata.RxThread));
robert_jw 0:b2805b6888dc 1019
robert_jw 0:b2805b6888dc 1020 /* Transmit cleanup task */
robert_jw 0:b2805b6888dc 1021 err = sys_sem_new(&lpc_enetdata.TxCleanSem, 0);
robert_jw 0:b2805b6888dc 1022 LWIP_ASSERT("TxCleanSem creation error", (err == ERR_OK));
robert_jw 0:b2805b6888dc 1023 sys_thread_new("txclean_thread", packet_tx, netif->state, DEFAULT_THREAD_STACKSIZE, TX_PRIORITY);
robert_jw 0:b2805b6888dc 1024
robert_jw 0:b2805b6888dc 1025 /* periodic PHY status update */
robert_jw 0:b2805b6888dc 1026 osTimerId phy_timer = osTimerCreate(osTimer(phy_update), osTimerPeriodic, (void *)netif);
robert_jw 0:b2805b6888dc 1027 osTimerStart(phy_timer, 250);
robert_jw 0:b2805b6888dc 1028 #endif
robert_jw 0:b2805b6888dc 1029
robert_jw 0:b2805b6888dc 1030 return ERR_OK;
robert_jw 0:b2805b6888dc 1031 }
robert_jw 0:b2805b6888dc 1032
robert_jw 0:b2805b6888dc 1033 void eth_arch_enable_interrupts(void) {
robert_jw 0:b2805b6888dc 1034 NVIC_SetPriority(ENET_IRQn, ((0x01 << 3) | 0x01));
robert_jw 0:b2805b6888dc 1035 NVIC_EnableIRQ(ENET_IRQn);
robert_jw 0:b2805b6888dc 1036 }
robert_jw 0:b2805b6888dc 1037
robert_jw 0:b2805b6888dc 1038 void eth_arch_disable_interrupts(void) {
robert_jw 0:b2805b6888dc 1039 NVIC_DisableIRQ(ENET_IRQn);
robert_jw 0:b2805b6888dc 1040 }
robert_jw 0:b2805b6888dc 1041
robert_jw 0:b2805b6888dc 1042 /**
robert_jw 0:b2805b6888dc 1043 * @}
robert_jw 0:b2805b6888dc 1044 */
robert_jw 0:b2805b6888dc 1045
robert_jw 0:b2805b6888dc 1046 /* --------------------------------- End Of File ------------------------------ */