FreeRTOS Real Time Operating System, Modified from Kenji Arai's initial port. See freertos.org for full documentation.
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core_cm3.h
00001 /****************************************************************************** 00002 * @file: core_cm3.h 00003 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File 00004 * @version: V1.20 00005 * @date: 22. May 2009 00006 *---------------------------------------------------------------------------- 00007 * 00008 * Copyright (C) 2009 ARM Limited. All rights reserved. 00009 * 00010 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 00011 * processor based microcontrollers. This file can be freely distributed 00012 * within development tools that are supporting such ARM based processors. 00013 * 00014 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00015 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00016 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00017 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00018 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00019 * 00020 ******************************************************************************/ 00021 00022 #ifndef __CM3_CORE_H__ 00023 #define __CM3_CORE_H__ 00024 00025 #ifdef __cplusplus 00026 extern "C" { 00027 #endif 00028 00029 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ 00030 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ 00031 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ 00032 00033 #define __CORTEX_M (0x03) /*!< Cortex core */ 00034 00035 /** 00036 * Lint configuration \n 00037 * ----------------------- \n 00038 * 00039 * The following Lint messages will be suppressed and not shown: \n 00040 * \n 00041 * --- Error 10: --- \n 00042 * register uint32_t __regBasePri __asm("basepri"); \n 00043 * Error 10: Expecting ';' \n 00044 * \n 00045 * --- Error 530: --- \n 00046 * return(__regBasePri); \n 00047 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n 00048 * \n 00049 * --- Error 550: --- \n 00050 * __regBasePri = (basePri & 0x1ff); \n 00051 * } \n 00052 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n 00053 * \n 00054 * --- Error 754: --- \n 00055 * uint32_t RESERVED0[24]; \n 00056 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n 00057 * \n 00058 * --- Error 750: --- \n 00059 * #define __CM3_CORE_H__ \n 00060 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n 00061 * \n 00062 * --- Error 528: --- \n 00063 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n 00064 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n 00065 * \n 00066 * --- Error 751: --- \n 00067 * } InterruptType_Type; \n 00068 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n 00069 * \n 00070 * \n 00071 * Note: To re-enable a Message, insert a space before 'lint' * \n 00072 * 00073 */ 00074 00075 /*lint -save */ 00076 /*lint -e10 */ 00077 /*lint -e530 */ 00078 /*lint -e550 */ 00079 /*lint -e754 */ 00080 /*lint -e750 */ 00081 /*lint -e528 */ 00082 /*lint -e751 */ 00083 00084 00085 #include <stdint.h> /* Include standard types */ 00086 00087 #if defined (__ICCARM__) 00088 #include <intrinsics.h> /* IAR Intrinsics */ 00089 #endif 00090 00091 00092 #ifndef __NVIC_PRIO_BITS 00093 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ 00094 #endif 00095 00096 00097 00098 00099 /** 00100 * IO definitions 00101 * 00102 * define access restrictions to peripheral registers 00103 */ 00104 00105 #ifdef __cplusplus 00106 #define __I volatile /*!< defines 'read only' permissions */ 00107 #else 00108 #define __I volatile const /*!< defines 'read only' permissions */ 00109 #endif 00110 #define __O volatile /*!< defines 'write only' permissions */ 00111 #define __IO volatile /*!< defines 'read / write' permissions */ 00112 00113 00114 00115 /******************************************************************************* 00116 * Register Abstraction 00117 ******************************************************************************/ 00118 00119 00120 /* System Reset */ 00121 #define NVIC_VECTRESET 0 /*!< Vector Reset Bit */ 00122 #define NVIC_SYSRESETREQ 2 /*!< System Reset Request */ 00123 #define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */ 00124 #define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */ 00125 00126 /* Core Debug */ 00127 #define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */ 00128 #define ITM_TCR_ITMENA 1 /*!< ITM enable */ 00129 00130 00131 00132 00133 /* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */ 00134 typedef struct 00135 { 00136 __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */ 00137 uint32_t RESERVED0[24]; 00138 __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */ 00139 uint32_t RSERVED1[24]; 00140 __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */ 00141 uint32_t RESERVED2[24]; 00142 __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */ 00143 uint32_t RESERVED3[24]; 00144 __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */ 00145 uint32_t RESERVED4[56]; 00146 __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */ 00147 uint32_t RESERVED5[644]; 00148 __O uint32_t STIR; /*!< Software Trigger Interrupt Register */ 00149 } NVIC_Type; 00150 00151 00152 /* memory mapping struct for System Control Block */ 00153 typedef struct 00154 { 00155 __I uint32_t CPUID; /*!< CPU ID Base Register */ 00156 __IO uint32_t ICSR; /*!< Interrupt Control State Register */ 00157 __IO uint32_t VTOR; /*!< Vector Table Offset Register */ 00158 __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */ 00159 __IO uint32_t SCR; /*!< System Control Register */ 00160 __IO uint32_t CCR; /*!< Configuration Control Register */ 00161 __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00162 __IO uint32_t SHCSR; /*!< System Handler Control and State Register */ 00163 __IO uint32_t CFSR; /*!< Configurable Fault Status Register */ 00164 __IO uint32_t HFSR; /*!< Hard Fault Status Register */ 00165 __IO uint32_t DFSR; /*!< Debug Fault Status Register */ 00166 __IO uint32_t MMFAR; /*!< Mem Manage Address Register */ 00167 __IO uint32_t BFAR; /*!< Bus Fault Address Register */ 00168 __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */ 00169 __I uint32_t PFR[2]; /*!< Processor Feature Register */ 00170 __I uint32_t DFR; /*!< Debug Feature Register */ 00171 __I uint32_t ADR; /*!< Auxiliary Feature Register */ 00172 __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */ 00173 __I uint32_t ISAR[5]; /*!< ISA Feature Register */ 00174 } SCB_Type; 00175 00176 00177 /* memory mapping struct for SysTick */ 00178 typedef struct 00179 { 00180 __IO uint32_t CTRL; /*!< SysTick Control and Status Register */ 00181 __IO uint32_t LOAD; /*!< SysTick Reload Value Register */ 00182 __IO uint32_t VAL; /*!< SysTick Current Value Register */ 00183 __I uint32_t CALIB; /*!< SysTick Calibration Register */ 00184 } SysTick_Type; 00185 00186 00187 /* memory mapping structur for ITM */ 00188 typedef struct 00189 { 00190 __O union 00191 { 00192 __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */ 00193 __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */ 00194 __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */ 00195 } PORT [32]; /*!< ITM Stimulus Port Registers */ 00196 uint32_t RESERVED0[864]; 00197 __IO uint32_t TER; /*!< ITM Trace Enable Register */ 00198 uint32_t RESERVED1[15]; 00199 __IO uint32_t TPR; /*!< ITM Trace Privilege Register */ 00200 uint32_t RESERVED2[15]; 00201 __IO uint32_t TCR; /*!< ITM Trace Control Register */ 00202 uint32_t RESERVED3[29]; 00203 __IO uint32_t IWR; /*!< ITM Integration Write Register */ 00204 __IO uint32_t IRR; /*!< ITM Integration Read Register */ 00205 __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */ 00206 uint32_t RESERVED4[43]; 00207 __IO uint32_t LAR; /*!< ITM Lock Access Register */ 00208 __IO uint32_t LSR; /*!< ITM Lock Status Register */ 00209 uint32_t RESERVED5[6]; 00210 __I uint32_t PID4; /*!< ITM Product ID Registers */ 00211 __I uint32_t PID5; 00212 __I uint32_t PID6; 00213 __I uint32_t PID7; 00214 __I uint32_t PID0; 00215 __I uint32_t PID1; 00216 __I uint32_t PID2; 00217 __I uint32_t PID3; 00218 __I uint32_t CID0; 00219 __I uint32_t CID1; 00220 __I uint32_t CID2; 00221 __I uint32_t CID3; 00222 } ITM_Type; 00223 00224 00225 /* memory mapped struct for Interrupt Type */ 00226 typedef struct 00227 { 00228 uint32_t RESERVED0; 00229 __I uint32_t ICTR; /*!< Interrupt Control Type Register */ 00230 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) 00231 __IO uint32_t ACTLR; /*!< Auxiliary Control Register */ 00232 #else 00233 uint32_t RESERVED1; 00234 #endif 00235 } InterruptType_Type; 00236 00237 00238 /* Memory Protection Unit */ 00239 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) 00240 typedef struct 00241 { 00242 __I uint32_t TYPE; /*!< MPU Type Register */ 00243 __IO uint32_t CTRL; /*!< MPU Control Register */ 00244 __IO uint32_t RNR; /*!< MPU Region RNRber Register */ 00245 __IO uint32_t RBAR; /*!< MPU Region Base Address Register */ 00246 __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */ 00247 __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */ 00248 __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */ 00249 __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */ 00250 __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */ 00251 __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */ 00252 __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */ 00253 } MPU_Type; 00254 #endif 00255 00256 00257 /* Core Debug Register */ 00258 typedef struct 00259 { 00260 __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */ 00261 __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */ 00262 __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */ 00263 __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */ 00264 } CoreDebug_Type; 00265 00266 00267 /* Memory mapping of Cortex-M3 Hardware */ 00268 #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ 00269 #define ITM_BASE (0xE0000000) /*!< ITM Base Address */ 00270 #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ 00271 #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ 00272 #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ 00273 #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ 00274 00275 #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ 00276 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ 00277 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ 00278 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ 00279 #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ 00280 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 00281 00282 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) 00283 #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ 00284 #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ 00285 #endif 00286 00287 00288 00289 /******************************************************************************* 00290 * Hardware Abstraction Layer 00291 ******************************************************************************/ 00292 00293 00294 #if defined ( __CC_ARM ) 00295 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00296 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00297 00298 #elif defined ( __ICCARM__ ) 00299 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00300 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ 00301 00302 #elif defined ( __GNUC__ ) 00303 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00304 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00305 00306 #elif defined ( __TASKING__ ) 00307 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00308 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00309 00310 #endif 00311 00312 00313 /* ################### Compiler specific Intrinsics ########################### */ 00314 00315 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 00316 /* ARM armcc specific functions */ 00317 00318 #define __enable_fault_irq __enable_fiq 00319 #define __disable_fault_irq __disable_fiq 00320 00321 #define __NOP __nop 00322 #define __WFI __wfi 00323 #define __WFE __wfe 00324 #define __SEV __sev 00325 #define __ISB() __isb(0) 00326 #define __DSB() __dsb(0) 00327 #define __DMB() __dmb(0) 00328 #define __REV __rev 00329 #define __RBIT __rbit 00330 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) 00331 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) 00332 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) 00333 #define __STREXB(value, ptr) __strex(value, ptr) 00334 #define __STREXH(value, ptr) __strex(value, ptr) 00335 #define __STREXW(value, ptr) __strex(value, ptr) 00336 00337 00338 /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ 00339 /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ 00340 /* intrinsic void __enable_irq(); */ 00341 /* intrinsic void __disable_irq(); */ 00342 00343 00344 /** 00345 * @brief Return the Process Stack Pointer 00346 * 00347 * @param none 00348 * @return uint32_t ProcessStackPointer 00349 * 00350 * Return the actual process stack pointer 00351 */ 00352 extern uint32_t __get_PSP(void); 00353 00354 /** 00355 * @brief Set the Process Stack Pointer 00356 * 00357 * @param uint32_t Process Stack Pointer 00358 * @return none 00359 * 00360 * Assign the value ProcessStackPointer to the MSP 00361 * (process stack pointer) Cortex processor register 00362 */ 00363 extern void __set_PSP(uint32_t topOfProcStack); 00364 00365 /** 00366 * @brief Return the Main Stack Pointer 00367 * 00368 * @param none 00369 * @return uint32_t Main Stack Pointer 00370 * 00371 * Return the current value of the MSP (main stack pointer) 00372 * Cortex processor register 00373 */ 00374 extern uint32_t __get_MSP(void); 00375 00376 /** 00377 * @brief Set the Main Stack Pointer 00378 * 00379 * @param uint32_t Main Stack Pointer 00380 * @return none 00381 * 00382 * Assign the value mainStackPointer to the MSP 00383 * (main stack pointer) Cortex processor register 00384 */ 00385 extern void __set_MSP(uint32_t topOfMainStack); 00386 00387 /** 00388 * @brief Reverse byte order in unsigned short value 00389 * 00390 * @param uint16_t value to reverse 00391 * @return uint32_t reversed value 00392 * 00393 * Reverse byte order in unsigned short value 00394 */ 00395 extern uint32_t __REV16(uint16_t value); 00396 00397 /* 00398 * @brief Reverse byte order in signed short value with sign extension to integer 00399 * 00400 * @param int16_t value to reverse 00401 * @return int32_t reversed value 00402 * 00403 * Reverse byte order in signed short value with sign extension to integer 00404 */ 00405 extern int32_t __REVSH(int16_t value); 00406 00407 00408 #if (__ARMCC_VERSION < 400000) 00409 00410 /** 00411 * @brief Remove the exclusive lock created by ldrex 00412 * 00413 * @param none 00414 * @return none 00415 * 00416 * Removes the exclusive lock which is created by ldrex. 00417 */ 00418 extern void __CLREX(void); 00419 00420 /** 00421 * @brief Return the Base Priority value 00422 * 00423 * @param none 00424 * @return uint32_t BasePriority 00425 * 00426 * Return the content of the base priority register 00427 */ 00428 extern uint32_t __get_BASEPRI(void); 00429 00430 /** 00431 * @brief Set the Base Priority value 00432 * 00433 * @param uint32_t BasePriority 00434 * @return none 00435 * 00436 * Set the base priority register 00437 */ 00438 extern void __set_BASEPRI(uint32_t basePri); 00439 00440 /** 00441 * @brief Return the Priority Mask value 00442 * 00443 * @param none 00444 * @return uint32_t PriMask 00445 * 00446 * Return the state of the priority mask bit from the priority mask 00447 * register 00448 */ 00449 extern uint32_t __get_PRIMASK(void); 00450 00451 /** 00452 * @brief Set the Priority Mask value 00453 * 00454 * @param uint32_t PriMask 00455 * @return none 00456 * 00457 * Set the priority mask bit in the priority mask register 00458 */ 00459 extern void __set_PRIMASK(uint32_t priMask); 00460 00461 /** 00462 * @brief Return the Fault Mask value 00463 * 00464 * @param none 00465 * @return uint32_t FaultMask 00466 * 00467 * Return the content of the fault mask register 00468 */ 00469 extern uint32_t __get_FAULTMASK(void); 00470 00471 /** 00472 * @brief Set the Fault Mask value 00473 * 00474 * @param uint32_t faultMask value 00475 * @return none 00476 * 00477 * Set the fault mask register 00478 */ 00479 extern void __set_FAULTMASK(uint32_t faultMask); 00480 00481 /** 00482 * @brief Return the Control Register value 00483 * 00484 * @param none 00485 * @return uint32_t Control value 00486 * 00487 * Return the content of the control register 00488 */ 00489 extern uint32_t __get_CONTROL(void); 00490 00491 /** 00492 * @brief Set the Control Register value 00493 * 00494 * @param uint32_t Control value 00495 * @return none 00496 * 00497 * Set the control register 00498 */ 00499 extern void __set_CONTROL(uint32_t control); 00500 00501 #else /* (__ARMCC_VERSION >= 400000) */ 00502 00503 00504 /** 00505 * @brief Remove the exclusive lock created by ldrex 00506 * 00507 * @param none 00508 * @return none 00509 * 00510 * Removes the exclusive lock which is created by ldrex. 00511 */ 00512 #define __CLREX __clrex 00513 00514 /** 00515 * @brief Return the Base Priority value 00516 * 00517 * @param none 00518 * @return uint32_t BasePriority 00519 * 00520 * Return the content of the base priority register 00521 */ 00522 static __INLINE uint32_t __get_BASEPRI(void) 00523 { 00524 register uint32_t __regBasePri __ASM("basepri"); 00525 return(__regBasePri); 00526 } 00527 00528 /** 00529 * @brief Set the Base Priority value 00530 * 00531 * @param uint32_t BasePriority 00532 * @return none 00533 * 00534 * Set the base priority register 00535 */ 00536 static __INLINE void __set_BASEPRI(uint32_t basePri) 00537 { 00538 register uint32_t __regBasePri __ASM("basepri"); 00539 __regBasePri = (basePri & 0x1ff); 00540 } 00541 00542 /** 00543 * @brief Return the Priority Mask value 00544 * 00545 * @param none 00546 * @return uint32_t PriMask 00547 * 00548 * Return the state of the priority mask bit from the priority mask 00549 * register 00550 */ 00551 static __INLINE uint32_t __get_PRIMASK(void) 00552 { 00553 register uint32_t __regPriMask __ASM("primask"); 00554 return(__regPriMask); 00555 } 00556 00557 /** 00558 * @brief Set the Priority Mask value 00559 * 00560 * @param uint32_t PriMask 00561 * @return none 00562 * 00563 * Set the priority mask bit in the priority mask register 00564 */ 00565 static __INLINE void __set_PRIMASK(uint32_t priMask) 00566 { 00567 register uint32_t __regPriMask __ASM("primask"); 00568 __regPriMask = (priMask); 00569 } 00570 00571 /** 00572 * @brief Return the Fault Mask value 00573 * 00574 * @param none 00575 * @return uint32_t FaultMask 00576 * 00577 * Return the content of the fault mask register 00578 */ 00579 static __INLINE uint32_t __get_FAULTMASK(void) 00580 { 00581 register uint32_t __regFaultMask __ASM("faultmask"); 00582 return(__regFaultMask); 00583 } 00584 00585 /** 00586 * @brief Set the Fault Mask value 00587 * 00588 * @param uint32_t faultMask value 00589 * @return none 00590 * 00591 * Set the fault mask register 00592 */ 00593 static __INLINE void __set_FAULTMASK(uint32_t faultMask) 00594 { 00595 register uint32_t __regFaultMask __ASM("faultmask"); 00596 __regFaultMask = (faultMask & 1); 00597 } 00598 00599 /** 00600 * @brief Return the Control Register value 00601 * 00602 * @param none 00603 * @return uint32_t Control value 00604 * 00605 * Return the content of the control register 00606 */ 00607 static __INLINE uint32_t __get_CONTROL(void) 00608 { 00609 register uint32_t __regControl __ASM("control"); 00610 return(__regControl); 00611 } 00612 00613 /** 00614 * @brief Set the Control Register value 00615 * 00616 * @param uint32_t Control value 00617 * @return none 00618 * 00619 * Set the control register 00620 */ 00621 static __INLINE void __set_CONTROL(uint32_t control) 00622 { 00623 register uint32_t __regControl __ASM("control"); 00624 __regControl = control; 00625 } 00626 00627 #endif /* __ARMCC_VERSION */ 00628 00629 00630 00631 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ 00632 /* IAR iccarm specific functions */ 00633 00634 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */ 00635 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */ 00636 00637 static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } 00638 static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } 00639 00640 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ 00641 static __INLINE void __WFI() { __ASM ("wfi"); } 00642 static __INLINE void __WFE() { __ASM ("wfe"); } 00643 static __INLINE void __SEV() { __ASM ("sev"); } 00644 static __INLINE void __CLREX() { __ASM ("clrex"); } 00645 00646 /* intrinsic void __ISB(void) */ 00647 /* intrinsic void __DSB(void) */ 00648 /* intrinsic void __DMB(void) */ 00649 /* intrinsic void __set_PRIMASK(); */ 00650 /* intrinsic void __get_PRIMASK(); */ 00651 /* intrinsic void __set_FAULTMASK(); */ 00652 /* intrinsic void __get_FAULTMASK(); */ 00653 /* intrinsic uint32_t __REV(uint32_t value); */ 00654 /* intrinsic uint32_t __REVSH(uint32_t value); */ 00655 /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ 00656 /* intrinsic unsigned long __LDREX(unsigned long *); */ 00657 00658 00659 /** 00660 * @brief Return the Process Stack Pointer 00661 * 00662 * @param none 00663 * @return uint32_t ProcessStackPointer 00664 * 00665 * Return the actual process stack pointer 00666 */ 00667 extern uint32_t __get_PSP(void); 00668 00669 /** 00670 * @brief Set the Process Stack Pointer 00671 * 00672 * @param uint32_t Process Stack Pointer 00673 * @return none 00674 * 00675 * Assign the value ProcessStackPointer to the MSP 00676 * (process stack pointer) Cortex processor register 00677 */ 00678 extern void __set_PSP(uint32_t topOfProcStack); 00679 00680 /** 00681 * @brief Return the Main Stack Pointer 00682 * 00683 * @param none 00684 * @return uint32_t Main Stack Pointer 00685 * 00686 * Return the current value of the MSP (main stack pointer) 00687 * Cortex processor register 00688 */ 00689 extern uint32_t __get_MSP(void); 00690 00691 /** 00692 * @brief Set the Main Stack Pointer 00693 * 00694 * @param uint32_t Main Stack Pointer 00695 * @return none 00696 * 00697 * Assign the value mainStackPointer to the MSP 00698 * (main stack pointer) Cortex processor register 00699 */ 00700 extern void __set_MSP(uint32_t topOfMainStack); 00701 00702 /** 00703 * @brief Reverse byte order in unsigned short value 00704 * 00705 * @param uint16_t value to reverse 00706 * @return uint32_t reversed value 00707 * 00708 * Reverse byte order in unsigned short value 00709 */ 00710 extern uint32_t __REV16(uint16_t value); 00711 00712 /** 00713 * @brief Reverse bit order of value 00714 * 00715 * @param uint32_t value to reverse 00716 * @return uint32_t reversed value 00717 * 00718 * Reverse bit order of value 00719 */ 00720 extern uint32_t __RBIT(uint32_t value); 00721 00722 /** 00723 * @brief LDR Exclusive 00724 * 00725 * @param uint8_t* address 00726 * @return uint8_t value of (*address) 00727 * 00728 * Exclusive LDR command 00729 */ 00730 extern uint8_t __LDREXB(uint8_t *addr); 00731 00732 /** 00733 * @brief LDR Exclusive 00734 * 00735 * @param uint16_t* address 00736 * @return uint16_t value of (*address) 00737 * 00738 * Exclusive LDR command 00739 */ 00740 extern uint16_t __LDREXH(uint16_t *addr); 00741 00742 /** 00743 * @brief LDR Exclusive 00744 * 00745 * @param uint32_t* address 00746 * @return uint32_t value of (*address) 00747 * 00748 * Exclusive LDR command 00749 */ 00750 extern uint32_t __LDREXW(uint32_t *addr); 00751 00752 /** 00753 * @brief STR Exclusive 00754 * 00755 * @param uint8_t *address 00756 * @param uint8_t value to store 00757 * @return uint32_t successful / failed 00758 * 00759 * Exclusive STR command 00760 */ 00761 extern uint32_t __STREXB(uint8_t value, uint8_t *addr); 00762 00763 /** 00764 * @brief STR Exclusive 00765 * 00766 * @param uint16_t *address 00767 * @param uint16_t value to store 00768 * @return uint32_t successful / failed 00769 * 00770 * Exclusive STR command 00771 */ 00772 extern uint32_t __STREXH(uint16_t value, uint16_t *addr); 00773 00774 /** 00775 * @brief STR Exclusive 00776 * 00777 * @param uint32_t *address 00778 * @param uint32_t value to store 00779 * @return uint32_t successful / failed 00780 * 00781 * Exclusive STR command 00782 */ 00783 extern uint32_t __STREXW(uint32_t value, uint32_t *addr); 00784 00785 00786 00787 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ 00788 /* GNU gcc specific functions */ 00789 00790 static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } 00791 static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } 00792 00793 static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } 00794 static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } 00795 00796 static __INLINE void __NOP() { __ASM volatile ("nop"); } 00797 static __INLINE void __WFI() { __ASM volatile ("wfi"); } 00798 static __INLINE void __WFE() { __ASM volatile ("wfe"); } 00799 static __INLINE void __SEV() { __ASM volatile ("sev"); } 00800 static __INLINE void __ISB() { __ASM volatile ("isb"); } 00801 static __INLINE void __DSB() { __ASM volatile ("dsb"); } 00802 static __INLINE void __DMB() { __ASM volatile ("dmb"); } 00803 static __INLINE void __CLREX() { __ASM volatile ("clrex"); } 00804 00805 00806 /** 00807 * @brief Return the Process Stack Pointer 00808 * 00809 * @param none 00810 * @return uint32_t ProcessStackPointer 00811 * 00812 * Return the actual process stack pointer 00813 */ 00814 extern uint32_t __get_PSP(void); 00815 00816 /** 00817 * @brief Set the Process Stack Pointer 00818 * 00819 * @param uint32_t Process Stack Pointer 00820 * @return none 00821 * 00822 * Assign the value ProcessStackPointer to the MSP 00823 * (process stack pointer) Cortex processor register 00824 */ 00825 extern void __set_PSP(uint32_t topOfProcStack); 00826 00827 /** 00828 * @brief Return the Main Stack Pointer 00829 * 00830 * @param none 00831 * @return uint32_t Main Stack Pointer 00832 * 00833 * Return the current value of the MSP (main stack pointer) 00834 * Cortex processor register 00835 */ 00836 extern uint32_t __get_MSP(void); 00837 00838 /** 00839 * @brief Set the Main Stack Pointer 00840 * 00841 * @param uint32_t Main Stack Pointer 00842 * @return none 00843 * 00844 * Assign the value mainStackPointer to the MSP 00845 * (main stack pointer) Cortex processor register 00846 */ 00847 extern void __set_MSP(uint32_t topOfMainStack); 00848 00849 /** 00850 * @brief Return the Base Priority value 00851 * 00852 * @param none 00853 * @return uint32_t BasePriority 00854 * 00855 * Return the content of the base priority register 00856 */ 00857 extern uint32_t __get_BASEPRI(void); 00858 00859 /** 00860 * @brief Set the Base Priority value 00861 * 00862 * @param uint32_t BasePriority 00863 * @return none 00864 * 00865 * Set the base priority register 00866 */ 00867 extern void __set_BASEPRI(uint32_t basePri); 00868 00869 /** 00870 * @brief Return the Priority Mask value 00871 * 00872 * @param none 00873 * @return uint32_t PriMask 00874 * 00875 * Return the state of the priority mask bit from the priority mask 00876 * register 00877 */ 00878 extern uint32_t __get_PRIMASK(void); 00879 00880 /** 00881 * @brief Set the Priority Mask value 00882 * 00883 * @param uint32_t PriMask 00884 * @return none 00885 * 00886 * Set the priority mask bit in the priority mask register 00887 */ 00888 extern void __set_PRIMASK(uint32_t priMask); 00889 00890 /** 00891 * @brief Return the Fault Mask value 00892 * 00893 * @param none 00894 * @return uint32_t FaultMask 00895 * 00896 * Return the content of the fault mask register 00897 */ 00898 extern uint32_t __get_FAULTMASK(void); 00899 00900 /** 00901 * @brief Set the Fault Mask value 00902 * 00903 * @param uint32_t faultMask value 00904 * @return none 00905 * 00906 * Set the fault mask register 00907 */ 00908 extern void __set_FAULTMASK(uint32_t faultMask); 00909 00910 /** 00911 * @brief Return the Control Register value 00912 * 00913 * @param none 00914 * @return uint32_t Control value 00915 * 00916 * Return the content of the control register 00917 */ 00918 extern uint32_t __get_CONTROL(void); 00919 00920 /** 00921 * @brief Set the Control Register value 00922 * 00923 * @param uint32_t Control value 00924 * @return none 00925 * 00926 * Set the control register 00927 */ 00928 extern void __set_CONTROL(uint32_t control); 00929 00930 /** 00931 * @brief Reverse byte order in integer value 00932 * 00933 * @param uint32_t value to reverse 00934 * @return uint32_t reversed value 00935 * 00936 * Reverse byte order in integer value 00937 */ 00938 extern uint32_t __REV(uint32_t value); 00939 00940 /** 00941 * @brief Reverse byte order in unsigned short value 00942 * 00943 * @param uint16_t value to reverse 00944 * @return uint32_t reversed value 00945 * 00946 * Reverse byte order in unsigned short value 00947 */ 00948 extern uint32_t __REV16(uint16_t value); 00949 00950 /* 00951 * Reverse byte order in signed short value with sign extension to integer 00952 * 00953 * @param int16_t value to reverse 00954 * @return int32_t reversed value 00955 * 00956 * @brief Reverse byte order in signed short value with sign extension to integer 00957 */ 00958 extern int32_t __REVSH(int16_t value); 00959 00960 /** 00961 * @brief Reverse bit order of value 00962 * 00963 * @param uint32_t value to reverse 00964 * @return uint32_t reversed value 00965 * 00966 * Reverse bit order of value 00967 */ 00968 extern uint32_t __RBIT(uint32_t value); 00969 00970 /** 00971 * @brief LDR Exclusive 00972 * 00973 * @param uint8_t* address 00974 * @return uint8_t value of (*address) 00975 * 00976 * Exclusive LDR command 00977 */ 00978 extern uint8_t __LDREXB(uint8_t *addr); 00979 00980 /** 00981 * @brief LDR Exclusive 00982 * 00983 * @param uint16_t* address 00984 * @return uint16_t value of (*address) 00985 * 00986 * Exclusive LDR command 00987 */ 00988 extern uint16_t __LDREXH(uint16_t *addr); 00989 00990 /** 00991 * @brief LDR Exclusive 00992 * 00993 * @param uint32_t* address 00994 * @return uint32_t value of (*address) 00995 * 00996 * Exclusive LDR command 00997 */ 00998 extern uint32_t __LDREXW(uint32_t *addr); 00999 01000 /** 01001 * @brief STR Exclusive 01002 * 01003 * @param uint8_t *address 01004 * @param uint8_t value to store 01005 * @return uint32_t successful / failed 01006 * 01007 * Exclusive STR command 01008 */ 01009 extern uint32_t __STREXB(uint8_t value, uint8_t *addr); 01010 01011 /** 01012 * @brief STR Exclusive 01013 * 01014 * @param uint16_t *address 01015 * @param uint16_t value to store 01016 * @return uint32_t successful / failed 01017 * 01018 * Exclusive STR command 01019 */ 01020 extern uint32_t __STREXH(uint16_t value, uint16_t *addr); 01021 01022 /** 01023 * @brief STR Exclusive 01024 * 01025 * @param uint32_t *address 01026 * @param uint32_t value to store 01027 * @return uint32_t successful / failed 01028 * 01029 * Exclusive STR command 01030 */ 01031 extern uint32_t __STREXW(uint32_t value, uint32_t *addr); 01032 01033 01034 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ 01035 /* TASKING carm specific functions */ 01036 01037 /* 01038 * The CMSIS functions have been implemented as intrinsics in the compiler. 01039 * Please use "carm -?i" to get an up to date list of all instrinsics, 01040 * Including the CMSIS ones. 01041 */ 01042 01043 #endif 01044 01045 01046 01047 /* ########################## NVIC functions #################################### */ 01048 01049 01050 /** 01051 * @brief Set the Priority Grouping in NVIC Interrupt Controller 01052 * 01053 * @param uint32_t priority_grouping is priority grouping field 01054 * @return none 01055 * 01056 * Set the priority grouping field using the required unlock sequence. 01057 * The parameter priority_grouping is assigned to the field 01058 * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. 01059 * In case of a conflict between priority grouping and available 01060 * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 01061 */ 01062 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01063 { 01064 uint32_t reg_value; 01065 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01066 01067 reg_value = SCB->AIRCR; /* read old register configuration */ 01068 reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */ 01069 reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */ 01070 SCB->AIRCR = reg_value; 01071 } 01072 01073 /** 01074 * @brief Get the Priority Grouping from NVIC Interrupt Controller 01075 * 01076 * @param none 01077 * @return uint32_t priority grouping field 01078 * 01079 * Get the priority grouping from NVIC Interrupt Controller. 01080 * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. 01081 */ 01082 static __INLINE uint32_t NVIC_GetPriorityGrouping(void) 01083 { 01084 return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */ 01085 } 01086 01087 /** 01088 * @brief Enable Interrupt in NVIC Interrupt Controller 01089 * 01090 * @param IRQn_Type IRQn specifies the interrupt number 01091 * @return none 01092 * 01093 * Enable a device specific interupt in the NVIC interrupt controller. 01094 * The interrupt number cannot be a negative value. 01095 */ 01096 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 01097 { 01098 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ 01099 } 01100 01101 /** 01102 * @brief Disable the interrupt line for external interrupt specified 01103 * 01104 * @param IRQn_Type IRQn is the positive number of the external interrupt 01105 * @return none 01106 * 01107 * Disable a device specific interupt in the NVIC interrupt controller. 01108 * The interrupt number cannot be a negative value. 01109 */ 01110 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 01111 { 01112 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ 01113 } 01114 01115 /** 01116 * @brief Read the interrupt pending bit for a device specific interrupt source 01117 * 01118 * @param IRQn_Type IRQn is the number of the device specifc interrupt 01119 * @return uint32_t 1 if pending interrupt else 0 01120 * 01121 * Read the pending register in NVIC and return 1 if its status is pending, 01122 * otherwise it returns 0 01123 */ 01124 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 01125 { 01126 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ 01127 } 01128 01129 /** 01130 * @brief Set the pending bit for an external interrupt 01131 * 01132 * @param IRQn_Type IRQn is the Number of the interrupt 01133 * @return none 01134 * 01135 * Set the pending bit for the specified interrupt. 01136 * The interrupt number cannot be a negative value. 01137 */ 01138 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 01139 { 01140 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ 01141 } 01142 01143 /** 01144 * @brief Clear the pending bit for an external interrupt 01145 * 01146 * @param IRQn_Type IRQn is the Number of the interrupt 01147 * @return none 01148 * 01149 * Clear the pending bit for the specified interrupt. 01150 * The interrupt number cannot be a negative value. 01151 */ 01152 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01153 { 01154 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 01155 } 01156 01157 /** 01158 * @brief Read the active bit for an external interrupt 01159 * 01160 * @param IRQn_Type IRQn is the Number of the interrupt 01161 * @return uint32_t 1 if active else 0 01162 * 01163 * Read the active register in NVIC and returns 1 if its status is active, 01164 * otherwise it returns 0. 01165 */ 01166 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 01167 { 01168 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ 01169 } 01170 01171 /** 01172 * @brief Set the priority for an interrupt 01173 * 01174 * @param IRQn_Type IRQn is the Number of the interrupt 01175 * @param priority is the priority for the interrupt 01176 * @return none 01177 * 01178 * Set the priority for the specified interrupt. The interrupt 01179 * number can be positive to specify an external (device specific) 01180 * interrupt, or negative to specify an internal (core) interrupt. \n 01181 * 01182 * Note: The priority cannot be set for every core interrupt. 01183 */ 01184 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01185 { 01186 if(IRQn < 0) { 01187 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ 01188 else { 01189 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 01190 } 01191 01192 /** 01193 * @brief Read the priority for an interrupt 01194 * 01195 * @param IRQn_Type IRQn is the Number of the interrupt 01196 * @return uint32_t priority is the priority for the interrupt 01197 * 01198 * Read the priority for the specified interrupt. The interrupt 01199 * number can be positive to specify an external (device specific) 01200 * interrupt, or negative to specify an internal (core) interrupt. 01201 * 01202 * The returned priority value is automatically aligned to the implemented 01203 * priority bits of the microcontroller. 01204 * 01205 * Note: The priority cannot be set for every core interrupt. 01206 */ 01207 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 01208 { 01209 01210 if(IRQn < 0) { 01211 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ 01212 else { 01213 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 01214 } 01215 01216 01217 /** 01218 * @brief Encode the priority for an interrupt 01219 * 01220 * @param uint32_t PriorityGroup is the used priority group 01221 * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0) 01222 * @param uint32_t SubPriority is the sub priority value (starting from 0) 01223 * @return uint32_t the priority for the interrupt 01224 * 01225 * Encode the priority for an interrupt with the given priority group, 01226 * preemptive priority value and sub priority value. 01227 * In case of a conflict between priority grouping and available 01228 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. 01229 * 01230 * The returned priority value can be used for NVIC_SetPriority(...) function 01231 */ 01232 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01233 { 01234 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01235 uint32_t PreemptPriorityBits; 01236 uint32_t SubPriorityBits; 01237 01238 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01239 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01240 01241 return ( 01242 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 01243 ((SubPriority & ((1 << (SubPriorityBits )) - 1))) 01244 ); 01245 } 01246 01247 01248 /** 01249 * @brief Decode the priority of an interrupt 01250 * 01251 * @param uint32_t Priority the priority for the interrupt 01252 * @param uint32_t PrioGroup is the used priority group 01253 * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0) 01254 * @param uint32_t* pSubPrio is the sub priority value (starting from 0) 01255 * @return none 01256 * 01257 * Decode an interrupt priority value with the given priority group to 01258 * preemptive priority value and sub priority value. 01259 * In case of a conflict between priority grouping and available 01260 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. 01261 * 01262 * The priority value can be retrieved with NVIC_GetPriority(...) function 01263 */ 01264 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 01265 { 01266 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01267 uint32_t PreemptPriorityBits; 01268 uint32_t SubPriorityBits; 01269 01270 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01271 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01272 01273 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 01274 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); 01275 } 01276 01277 01278 01279 /* ################################## SysTick function ############################################ */ 01280 01281 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) 01282 01283 /* SysTick constants */ 01284 #define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */ 01285 #define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */ 01286 #define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */ 01287 #define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */ 01288 01289 /** 01290 * @brief Initialize and start the SysTick counter and its interrupt. 01291 * 01292 * @param uint32_t ticks is the number of ticks between two interrupts 01293 * @return none 01294 * 01295 * Initialise the system tick timer and its interrupt and start the 01296 * system tick timer / counter in free running mode to generate 01297 * periodical interrupts. 01298 */ 01299 static __INLINE uint32_t SysTick_Config(uint32_t ticks) 01300 { 01301 if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */ 01302 01303 SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */ 01304 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ 01305 SysTick->VAL = (0x00); /* Load the SysTick Counter Value */ 01306 SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */ 01307 return (0); /* Function successful */ 01308 } 01309 #endif 01310 01311 01312 01313 01314 01315 /* ################################## Reset function ############################################ */ 01316 01317 /** 01318 * @brief Initiate a system reset request. 01319 * 01320 * @param none 01321 * @return none 01322 * 01323 * Initialize a system reset request to reset the MCU 01324 */ 01325 static __INLINE void NVIC_SystemReset(void) 01326 { 01327 SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */ 01328 __DSB(); /* Ensure completion of memory access */ 01329 while(1); /* wait until reset */ 01330 } 01331 01332 01333 /* ################################## Debug Output function ############################################ */ 01334 01335 01336 /** 01337 * @brief Outputs a character via the ITM channel 0 01338 * 01339 * @param uint32_t character to output 01340 * @return uint32_t input character 01341 * 01342 * The function outputs a character via the ITM channel 0. 01343 * The function returns when no debugger is connected that has booked the output. 01344 * It is blocking when a debugger is connected, but the previous character send is not transmitted. 01345 */ 01346 static __INLINE uint32_t ITM_SendChar (uint32_t ch) 01347 { 01348 if (ch == '\n') ITM_SendChar('\r'); 01349 01350 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) && 01351 (ITM->TCR & ITM_TCR_ITMENA) && 01352 (ITM->TER & (1UL << 0)) ) 01353 { 01354 while (ITM->PORT[0].u32 == 0); 01355 ITM->PORT[0].u8 = (uint8_t) ch; 01356 } 01357 return (ch); 01358 } 01359 01360 #ifdef __cplusplus 01361 } 01362 #endif 01363 01364 #endif /* __CM3_CORE_H__ */ 01365 01366 /*lint -restore */
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