FreeRTOS Real Time Operating System, Modified from Kenji Arai's initial port. See freertos.org for full documentation.
Fork of FreeRTOS_on_mbed_v1 by
LPC17xx.h
00001 /****************************************************************************** 00002 * @file: LPC17xx.h 00003 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 00004 * NXP LPC17xx Device Series 00005 * @version: V1.04 00006 * @date: 2. July 2009 00007 *---------------------------------------------------------------------------- 00008 * 00009 * Copyright (C) 2008 ARM Limited. All rights reserved. 00010 * 00011 * ARM Limited (ARM) is supplying this software for use with Cortex-M3 00012 * processor based microcontrollers. This file can be freely distributed 00013 * within development tools that are supporting such ARM based processors. 00014 * 00015 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00016 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00017 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00018 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00019 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00020 * 00021 ******************************************************************************/ 00022 00023 #ifndef __LPC17xx_H__ 00024 #define __LPC17xx_H__ 00025 ///////////////////////////////////////////////////////////////////////////// 00026 /* System Control Block (SCB) includes: 00027 Flash Accelerator Module, Clocking and Power Control, External Interrupts, 00028 Reset, System Control and Status 00029 */ 00030 /* 00031 * Modified by following information 00032 * http://www.onarm.com/download/download395.asp 00033 * 00034 * By Kenji Arai / JH1PJL on April 11th,2010 00035 * April 11th,2010 00036 */ 00037 00038 #define SCB_BASE_ADDR 0x400FC000 00039 #define PCONP_PCTIM0 0x00000002 00040 #define PCONP_PCTIM1 0x00000004 00041 #define PCONP_PCUART0 0x00000008 00042 #define PCONP_PCUART1 0x00000010 00043 #define PCONP_PCPWM1 0x00000040 00044 #define PCONP_PCI2C0 0x00000080 00045 #define PCONP_PCSPI 0x00000100 00046 #define PCONP_PCRTC 0x00000200 00047 #define PCONP_PCSSP1 0x00000400 00048 #define PCONP_PCAD 0x00001000 00049 #define PCONP_PCCAN1 0x00002000 00050 #define PCONP_PCCAN2 0x00004000 00051 #define PCONP_PCGPIO 0x00008000 00052 #define PCONP_PCRIT 0x00010000 00053 #define PCONP_PCMCPWM 0x00020000 00054 #define PCONP_PCQEI 0x00040000 00055 #define PCONP_PCI2C1 0x00080000 00056 #define PCONP_PCSSP0 0x00200000 00057 #define PCONP_PCTIM2 0x00400000 00058 #define PCONP_PCTIM3 0x00800000 00059 #define PCONP_PCUART2 0x01000000 00060 #define PCONP_PCUART3 0x02000000 00061 #define PCONP_PCI2C2 0x04000000 00062 #define PCONP_PCI2S 0x08000000 00063 #define PCONP_PCGPDMA 0x20000000 00064 #define PCONP_PCENET 0x40000000 00065 #define PCONP_PCUSB 0x80000000 00066 00067 #define PLLCON_PLLE 0x00000001 00068 #define PLLCON_PLLC 0x00000002 00069 #define PLLCON_MASK 0x00000003 00070 00071 #define PLLCFG_MUL1 0x00000000 00072 #define PLLCFG_MUL2 0x00000001 00073 #define PLLCFG_MUL3 0x00000002 00074 #define PLLCFG_MUL4 0x00000003 00075 #define PLLCFG_MUL5 0x00000004 00076 #define PLLCFG_MUL6 0x00000005 00077 #define PLLCFG_MUL7 0x00000006 00078 #define PLLCFG_MUL8 0x00000007 00079 #define PLLCFG_MUL9 0x00000008 00080 #define PLLCFG_MUL10 0x00000009 00081 #define PLLCFG_MUL11 0x0000000A 00082 #define PLLCFG_MUL12 0x0000000B 00083 #define PLLCFG_MUL13 0x0000000C 00084 #define PLLCFG_MUL14 0x0000000D 00085 #define PLLCFG_MUL15 0x0000000E 00086 #define PLLCFG_MUL16 0x0000000F 00087 #define PLLCFG_MUL17 0x00000010 00088 #define PLLCFG_MUL18 0x00000011 00089 #define PLLCFG_MUL19 0x00000012 00090 #define PLLCFG_MUL20 0x00000013 00091 #define PLLCFG_MUL21 0x00000014 00092 #define PLLCFG_MUL22 0x00000015 00093 #define PLLCFG_MUL23 0x00000016 00094 #define PLLCFG_MUL24 0x00000017 00095 #define PLLCFG_MUL25 0x00000018 00096 #define PLLCFG_MUL26 0x00000019 00097 #define PLLCFG_MUL27 0x0000001A 00098 #define PLLCFG_MUL28 0x0000001B 00099 #define PLLCFG_MUL29 0x0000001C 00100 #define PLLCFG_MUL30 0x0000001D 00101 #define PLLCFG_MUL31 0x0000001E 00102 #define PLLCFG_MUL32 0x0000001F 00103 #define PLLCFG_MUL33 0x00000020 00104 #define PLLCFG_MUL34 0x00000021 00105 #define PLLCFG_MUL35 0x00000022 00106 #define PLLCFG_MUL36 0x00000023 00107 00108 #define PLLCFG_DIV1 0x00000000 00109 #define PLLCFG_DIV2 0x00010000 00110 #define PLLCFG_DIV3 0x00020000 00111 #define PLLCFG_DIV4 0x00030000 00112 #define PLLCFG_DIV5 0x00040000 00113 #define PLLCFG_DIV6 0x00050000 00114 #define PLLCFG_DIV7 0x00060000 00115 #define PLLCFG_DIV8 0x00070000 00116 #define PLLCFG_DIV9 0x00080000 00117 #define PLLCFG_DIV10 0x00090000 00118 #define PLLCFG_MASK 0x00FF7FFF 00119 00120 #define PLLSTAT_MSEL_MASK 0x00007FFF 00121 #define PLLSTAT_NSEL_MASK 0x00FF0000 00122 00123 #define PLLSTAT_PLLE (1 << 24) 00124 #define PLLSTAT_PLLC (1 << 25) 00125 #define PLLSTAT_PLOCK (1 << 26) 00126 00127 #define PLLFEED_FEED1 0x000000AA 00128 #define PLLFEED_FEED2 0x00000055 00129 00130 #define NVIC_IRQ_WDT 0u // IRQ0, exception number 16 00131 #define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17 00132 #define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18 00133 #define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19 00134 #define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20 00135 #define NVIC_IRQ_UART0 5u // IRQ5, exception number 21 00136 #define NVIC_IRQ_UART1 6u // IRQ6, exception number 22 00137 #define NVIC_IRQ_UART2 7u // IRQ7, exception number 23 00138 #define NVIC_IRQ_UART3 8u // IRQ8, exception number 24 00139 #define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25 00140 #define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26 00141 #define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27 00142 #define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28 00143 #define NVIC_IRQ_SPI 13u // IRQ13, exception number 29 00144 #define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30 00145 #define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31 00146 #define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32 00147 #define NVIC_IRQ_RTC 17u // IRQ17, exception number 33 00148 #define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34 00149 #define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35 00150 #define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36 00151 #define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37 00152 #define NVIC_IRQ_ADC 22u // IRQ22, exception number 38 00153 #define NVIC_IRQ_BOD 23u // IRQ23, exception number 39 00154 #define NVIC_IRQ_USB 24u // IRQ24, exception number 40 00155 #define NVIC_IRQ_CAN 25u // IRQ25, exception number 41 00156 #define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42 00157 #define NVIC_IRQ_I2S 27u // IRQ27, exception number 43 00158 #define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44 00159 #define NVIC_IRQ_RIT 29u // IRQ29, exception number 45 00160 #define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46 00161 #define NVIC_IRQ_QE 31u // IRQ31, exception number 47 00162 #define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48 00163 #define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49 00164 #define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50 00165 ///////////////////////////////////////////////////////////////////////////// 00166 00167 /* 00168 * ========================================================================== 00169 * ---------- Interrupt Number Definition ----------------------------------- 00170 * ========================================================================== 00171 */ 00172 00173 typedef enum IRQn 00174 { 00175 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 00176 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 00177 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 00178 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 00179 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 00180 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 00181 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 00182 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 00183 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 00184 00185 /****** LPC17xx Specific Interrupt Numbers *******************************************************/ 00186 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ 00187 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ 00188 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ 00189 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ 00190 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ 00191 UART0_IRQn = 5, /*!< UART0 Interrupt */ 00192 UART1_IRQn = 6, /*!< UART1 Interrupt */ 00193 UART2_IRQn = 7, /*!< UART2 Interrupt */ 00194 UART3_IRQn = 8, /*!< UART3 Interrupt */ 00195 PWM1_IRQn = 9, /*!< PWM1 Interrupt */ 00196 I2C0_IRQn = 10, /*!< I2C0 Interrupt */ 00197 I2C1_IRQn = 11, /*!< I2C1 Interrupt */ 00198 I2C2_IRQn = 12, /*!< I2C2 Interrupt */ 00199 SPI_IRQn = 13, /*!< SPI Interrupt */ 00200 SSP0_IRQn = 14, /*!< SSP0 Interrupt */ 00201 SSP1_IRQn = 15, /*!< SSP1 Interrupt */ 00202 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ 00203 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ 00204 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ 00205 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ 00206 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ 00207 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ 00208 ADC_IRQn = 22, /*!< A/D Converter Interrupt */ 00209 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ 00210 USB_IRQn = 24, /*!< USB Interrupt */ 00211 CAN_IRQn = 25, /*!< CAN Interrupt */ 00212 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ 00213 I2S_IRQn = 27, /*!< I2S Interrupt */ 00214 ENET_IRQn = 28, /*!< Ethernet Interrupt */ 00215 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ 00216 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ 00217 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ 00218 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ 00219 } IRQn_Type; 00220 00221 00222 /* 00223 * ========================================================================== 00224 * ----------- Processor and Core Peripheral Section ------------------------ 00225 * ========================================================================== 00226 */ 00227 00228 /* Configuration of the Cortex-M3 Processor and Core Peripherals */ 00229 #define __MPU_PRESENT 1 /*!< MPU present or not */ 00230 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ 00231 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00232 00233 00234 //#include <core_cm3.h> /* Cortex-M3 processor and core peripherals */ 00235 #include "core_cm3.h" // by roger 00236 00237 /******************************************************************************/ 00238 /* Device Specific Peripheral registers structures */ 00239 /******************************************************************************/ 00240 00241 #pragma anon_unions 00242 00243 /*------------- System Control (SC) ------------------------------------------*/ 00244 typedef struct 00245 { 00246 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ 00247 uint32_t RESERVED0[31]; 00248 __IO uint32_t PLL0CON; /* Clocking and Power Control */ 00249 __IO uint32_t PLL0CFG; 00250 __I uint32_t PLL0STAT; 00251 __O uint32_t PLL0FEED; 00252 uint32_t RESERVED1[4]; 00253 __IO uint32_t PLL1CON; 00254 __IO uint32_t PLL1CFG; 00255 __I uint32_t PLL1STAT; 00256 __O uint32_t PLL1FEED; 00257 uint32_t RESERVED2[4]; 00258 __IO uint32_t PCON; 00259 __IO uint32_t PCONP; 00260 uint32_t RESERVED3[15]; 00261 __IO uint32_t CCLKCFG; 00262 __IO uint32_t USBCLKCFG; 00263 __IO uint32_t CLKSRCSEL; 00264 uint32_t RESERVED4[12]; 00265 __IO uint32_t EXTINT; /* External Interrupts */ 00266 uint32_t RESERVED5; 00267 __IO uint32_t EXTMODE; 00268 __IO uint32_t EXTPOLAR; 00269 uint32_t RESERVED6[12]; 00270 __IO uint32_t RSID; /* Reset */ 00271 uint32_t RESERVED7[7]; 00272 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ 00273 __IO uint32_t IRCTRIM; /* Clock Dividers */ 00274 __IO uint32_t PCLKSEL0; 00275 __IO uint32_t PCLKSEL1; 00276 uint32_t RESERVED8[4]; 00277 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ 00278 uint32_t RESERVED9; 00279 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ 00280 } LPC_SC_TypeDef; 00281 00282 /*------------- Pin Connect Block (PINCON) -----------------------------------*/ 00283 typedef struct 00284 { 00285 __IO uint32_t PINSEL0; 00286 __IO uint32_t PINSEL1; 00287 __IO uint32_t PINSEL2; 00288 __IO uint32_t PINSEL3; 00289 __IO uint32_t PINSEL4; 00290 __IO uint32_t PINSEL5; 00291 __IO uint32_t PINSEL6; 00292 __IO uint32_t PINSEL7; 00293 __IO uint32_t PINSEL8; 00294 __IO uint32_t PINSEL9; 00295 __IO uint32_t PINSEL10; 00296 uint32_t RESERVED0[5]; 00297 __IO uint32_t PINMODE0; 00298 __IO uint32_t PINMODE1; 00299 __IO uint32_t PINMODE2; 00300 __IO uint32_t PINMODE3; 00301 __IO uint32_t PINMODE4; 00302 __IO uint32_t PINMODE5; 00303 __IO uint32_t PINMODE6; 00304 __IO uint32_t PINMODE7; 00305 __IO uint32_t PINMODE8; 00306 __IO uint32_t PINMODE9; 00307 __IO uint32_t PINMODE_OD0; 00308 __IO uint32_t PINMODE_OD1; 00309 __IO uint32_t PINMODE_OD2; 00310 __IO uint32_t PINMODE_OD3; 00311 __IO uint32_t PINMODE_OD4; 00312 __IO uint32_t I2CPADCFG; 00313 } LPC_PINCON_TypeDef; 00314 00315 /*------------- General Purpose Input/Output (GPIO) --------------------------*/ 00316 typedef struct 00317 { 00318 __IO uint32_t FIODIR; 00319 uint32_t RESERVED0[3]; 00320 __IO uint32_t FIOMASK; 00321 __IO uint32_t FIOPIN; 00322 __IO uint32_t FIOSET; 00323 __O uint32_t FIOCLR; 00324 } LPC_GPIO_TypeDef; 00325 00326 typedef struct 00327 { 00328 __I uint32_t IntStatus; 00329 __I uint32_t IO0IntStatR; 00330 __I uint32_t IO0IntStatF; 00331 __O uint32_t IO0IntClr; 00332 __IO uint32_t IO0IntEnR; 00333 __IO uint32_t IO0IntEnF; 00334 uint32_t RESERVED0[3]; 00335 __I uint32_t IO2IntStatR; 00336 __I uint32_t IO2IntStatF; 00337 __O uint32_t IO2IntClr; 00338 __IO uint32_t IO2IntEnR; 00339 __IO uint32_t IO2IntEnF; 00340 } LPC_GPIOINT_TypeDef; 00341 00342 /*------------- Timer (TIM) --------------------------------------------------*/ 00343 typedef struct 00344 { 00345 __IO uint32_t IR; 00346 __IO uint32_t TCR; 00347 __IO uint32_t TC; 00348 __IO uint32_t PR; 00349 __IO uint32_t PC; 00350 __IO uint32_t MCR; 00351 __IO uint32_t MR0; 00352 __IO uint32_t MR1; 00353 __IO uint32_t MR2; 00354 __IO uint32_t MR3; 00355 __IO uint32_t CCR; 00356 __I uint32_t CR0; 00357 __I uint32_t CR1; 00358 uint32_t RESERVED0[2]; 00359 __IO uint32_t EMR; 00360 uint32_t RESERVED1[12]; 00361 __IO uint32_t CTCR; 00362 } LPC_TIM_TypeDef; 00363 00364 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ 00365 typedef struct 00366 { 00367 __IO uint32_t IR; 00368 __IO uint32_t TCR; 00369 __IO uint32_t TC; 00370 __IO uint32_t PR; 00371 __IO uint32_t PC; 00372 __IO uint32_t MCR; 00373 __IO uint32_t MR0; 00374 __IO uint32_t MR1; 00375 __IO uint32_t MR2; 00376 __IO uint32_t MR3; 00377 __IO uint32_t CCR; 00378 __I uint32_t CR0; 00379 __I uint32_t CR1; 00380 __I uint32_t CR2; 00381 __I uint32_t CR3; 00382 uint32_t RESERVED0; 00383 __IO uint32_t MR4; 00384 __IO uint32_t MR5; 00385 __IO uint32_t MR6; 00386 __IO uint32_t PCR; 00387 __IO uint32_t LER; 00388 uint32_t RESERVED1[7]; 00389 __IO uint32_t CTCR; 00390 } LPC_PWM_TypeDef; 00391 00392 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ 00393 typedef struct 00394 { 00395 union { 00396 __I uint8_t RBR; 00397 __O uint8_t THR; 00398 __IO uint8_t DLL; 00399 uint32_t RESERVED0; 00400 }; 00401 union { 00402 __IO uint8_t DLM; 00403 __IO uint32_t IER; 00404 }; 00405 union { 00406 __I uint32_t IIR; 00407 __O uint8_t FCR; 00408 }; 00409 __IO uint8_t LCR; 00410 uint8_t RESERVED1[7]; 00411 __I uint8_t LSR; 00412 uint8_t RESERVED2[7]; 00413 __IO uint8_t SCR; 00414 uint8_t RESERVED3[3]; 00415 __IO uint32_t ACR; 00416 __IO uint8_t ICR; 00417 uint8_t RESERVED4[3]; 00418 __IO uint8_t FDR; 00419 uint8_t RESERVED5[7]; 00420 __IO uint8_t TER; 00421 uint8_t RESERVED6[39]; 00422 __I uint8_t FIFOLVL; 00423 } LPC_UART_TypeDef; 00424 00425 typedef struct 00426 { 00427 union { 00428 __I uint8_t RBR; 00429 __O uint8_t THR; 00430 __IO uint8_t DLL; 00431 uint32_t RESERVED0; 00432 }; 00433 union { 00434 __IO uint8_t DLM; 00435 __IO uint32_t IER; 00436 }; 00437 union { 00438 __I uint32_t IIR; 00439 __O uint8_t FCR; 00440 }; 00441 __IO uint8_t LCR; 00442 uint8_t RESERVED1[7]; 00443 __I uint8_t LSR; 00444 uint8_t RESERVED2[7]; 00445 __IO uint8_t SCR; 00446 uint8_t RESERVED3[3]; 00447 __IO uint32_t ACR; 00448 __IO uint8_t ICR; 00449 uint8_t RESERVED4[3]; 00450 __IO uint8_t FDR; 00451 uint8_t RESERVED5[7]; 00452 __IO uint8_t TER; 00453 uint8_t RESERVED6[39]; 00454 __I uint8_t FIFOLVL; 00455 uint8_t RESERVED7[363]; 00456 __IO uint32_t DMAREQSEL; 00457 } LPC_UART0_TypeDef; 00458 00459 typedef struct 00460 { 00461 union { 00462 __I uint8_t RBR; 00463 __O uint8_t THR; 00464 __IO uint8_t DLL; 00465 uint32_t RESERVED0; 00466 }; 00467 union { 00468 __IO uint8_t DLM; 00469 __IO uint32_t IER; 00470 }; 00471 union { 00472 __I uint32_t IIR; 00473 __O uint8_t FCR; 00474 }; 00475 __IO uint8_t LCR; 00476 uint8_t RESERVED1[3]; 00477 __IO uint8_t MCR; 00478 uint8_t RESERVED2[3]; 00479 __I uint8_t LSR; 00480 uint8_t RESERVED3[3]; 00481 __I uint8_t MSR; 00482 uint8_t RESERVED4[3]; 00483 __IO uint8_t SCR; 00484 uint8_t RESERVED5[3]; 00485 __IO uint32_t ACR; 00486 uint32_t RESERVED6; 00487 __IO uint32_t FDR; 00488 uint32_t RESERVED7; 00489 __IO uint8_t TER; 00490 uint8_t RESERVED8[27]; 00491 __IO uint8_t RS485CTRL; 00492 uint8_t RESERVED9[3]; 00493 __IO uint8_t ADRMATCH; 00494 uint8_t RESERVED10[3]; 00495 __IO uint8_t RS485DLY; 00496 uint8_t RESERVED11[3]; 00497 __I uint8_t FIFOLVL; 00498 } LPC_UART1_TypeDef; 00499 00500 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/ 00501 typedef struct 00502 { 00503 __IO uint32_t SPCR; 00504 __I uint32_t SPSR; 00505 __IO uint32_t SPDR; 00506 __IO uint32_t SPCCR; 00507 uint32_t RESERVED0[3]; 00508 __IO uint32_t SPINT; 00509 } LPC_SPI_TypeDef; 00510 00511 /*------------- Synchronous Serial Communication (SSP) -----------------------*/ 00512 typedef struct 00513 { 00514 __IO uint32_t CR0; 00515 __IO uint32_t CR1; 00516 __IO uint32_t DR; 00517 __I uint32_t SR; 00518 __IO uint32_t CPSR; 00519 __IO uint32_t IMSC; 00520 __IO uint32_t RIS; 00521 __IO uint32_t MIS; 00522 __IO uint32_t ICR; 00523 __IO uint32_t DMACR; 00524 } LPC_SSP_TypeDef; 00525 00526 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ 00527 typedef struct 00528 { 00529 __IO uint32_t I2CONSET; 00530 __I uint32_t I2STAT; 00531 __IO uint32_t I2DAT; 00532 __IO uint32_t I2ADR0; 00533 __IO uint32_t I2SCLH; 00534 __IO uint32_t I2SCLL; 00535 __O uint32_t I2CONCLR; 00536 __IO uint32_t MMCTRL; 00537 __IO uint32_t I2ADR1; 00538 __IO uint32_t I2ADR2; 00539 __IO uint32_t I2ADR3; 00540 __I uint32_t I2DATA_BUFFER; 00541 __IO uint32_t I2MASK0; 00542 __IO uint32_t I2MASK1; 00543 __IO uint32_t I2MASK2; 00544 __IO uint32_t I2MASK3; 00545 } LPC_I2C_TypeDef; 00546 00547 /*------------- Inter IC Sound (I2S) -----------------------------------------*/ 00548 typedef struct 00549 { 00550 __IO uint32_t I2SDAO; 00551 __IO uint32_t I2SDAI; 00552 __O uint32_t I2STXFIFO; 00553 __I uint32_t I2SRXFIFO; 00554 __I uint32_t I2SSTATE; 00555 __IO uint32_t I2SDMA1; 00556 __IO uint32_t I2SDMA2; 00557 __IO uint32_t I2SIRQ; 00558 __IO uint32_t I2STXRATE; 00559 __IO uint32_t I2SRXRATE; 00560 __IO uint32_t I2STXBITRATE; 00561 __IO uint32_t I2SRXBITRATE; 00562 __IO uint32_t I2STXMODE; 00563 __IO uint32_t I2SRXMODE; 00564 } LPC_I2S_TypeDef; 00565 00566 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ 00567 typedef struct 00568 { 00569 __IO uint32_t RICOMPVAL; 00570 __IO uint32_t RIMASK; 00571 __IO uint8_t RICTRL; 00572 uint8_t RESERVED0[3]; 00573 __IO uint32_t RICOUNTER; 00574 } LPC_RIT_TypeDef; 00575 00576 /*------------- Real-Time Clock (RTC) ----------------------------------------*/ 00577 typedef struct 00578 { 00579 __IO uint8_t ILR; 00580 uint8_t RESERVED0[7]; 00581 __IO uint8_t CCR; 00582 uint8_t RESERVED1[3]; 00583 __IO uint8_t CIIR; 00584 uint8_t RESERVED2[3]; 00585 __IO uint8_t AMR; 00586 uint8_t RESERVED3[3]; 00587 __I uint32_t CTIME0; 00588 __I uint32_t CTIME1; 00589 __I uint32_t CTIME2; 00590 __IO uint8_t SEC; 00591 uint8_t RESERVED4[3]; 00592 __IO uint8_t MIN; 00593 uint8_t RESERVED5[3]; 00594 __IO uint8_t HOUR; 00595 uint8_t RESERVED6[3]; 00596 __IO uint8_t DOM; 00597 uint8_t RESERVED7[3]; 00598 __IO uint8_t DOW; 00599 uint8_t RESERVED8[3]; 00600 __IO uint16_t DOY; 00601 uint16_t RESERVED9; 00602 __IO uint8_t MONTH; 00603 uint8_t RESERVED10[3]; 00604 __IO uint16_t YEAR; 00605 uint16_t RESERVED11; 00606 __IO uint32_t CALIBRATION; 00607 __IO uint32_t GPREG0; 00608 __IO uint32_t GPREG1; 00609 __IO uint32_t GPREG2; 00610 __IO uint32_t GPREG3; 00611 __IO uint32_t GPREG4; 00612 __IO uint8_t RTC_AUXEN; 00613 uint8_t RESERVED12[3]; 00614 __IO uint8_t RTC_AUX; 00615 uint8_t RESERVED13[3]; 00616 __IO uint8_t ALSEC; 00617 uint8_t RESERVED14[3]; 00618 __IO uint8_t ALMIN; 00619 uint8_t RESERVED15[3]; 00620 __IO uint8_t ALHOUR; 00621 uint8_t RESERVED16[3]; 00622 __IO uint8_t ALDOM; 00623 uint8_t RESERVED17[3]; 00624 __IO uint8_t ALDOW; 00625 uint8_t RESERVED18[3]; 00626 __IO uint16_t ALDOY; 00627 uint16_t RESERVED19; 00628 __IO uint8_t ALMON; 00629 uint8_t RESERVED20[3]; 00630 __IO uint16_t ALYEAR; 00631 uint16_t RESERVED21; 00632 } LPC_RTC_TypeDef; 00633 00634 /*------------- Watchdog Timer (WDT) -----------------------------------------*/ 00635 typedef struct 00636 { 00637 __IO uint8_t WDMOD; 00638 uint8_t RESERVED0[3]; 00639 __IO uint32_t WDTC; 00640 __O uint8_t WDFEED; 00641 uint8_t RESERVED1[3]; 00642 __I uint32_t WDTV; 00643 __IO uint32_t WDCLKSEL; 00644 } LPC_WDT_TypeDef; 00645 00646 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ 00647 typedef struct 00648 { 00649 __IO uint32_t ADCR; 00650 __IO uint32_t ADGDR; 00651 uint32_t RESERVED0; 00652 __IO uint32_t ADINTEN; 00653 __I uint32_t ADDR0; 00654 __I uint32_t ADDR1; 00655 __I uint32_t ADDR2; 00656 __I uint32_t ADDR3; 00657 __I uint32_t ADDR4; 00658 __I uint32_t ADDR5; 00659 __I uint32_t ADDR6; 00660 __I uint32_t ADDR7; 00661 __I uint32_t ADSTAT; 00662 __IO uint32_t ADTRM; 00663 } LPC_ADC_TypeDef; 00664 00665 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ 00666 typedef struct 00667 { 00668 __IO uint32_t DACR; 00669 __IO uint32_t DACCTRL; 00670 __IO uint16_t DACCNTVAL; 00671 } LPC_DAC_TypeDef; 00672 00673 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ 00674 typedef struct 00675 { 00676 __I uint32_t MCCON; 00677 __O uint32_t MCCON_SET; 00678 __O uint32_t MCCON_CLR; 00679 __I uint32_t MCCAPCON; 00680 __O uint32_t MCCAPCON_SET; 00681 __O uint32_t MCCAPCON_CLR; 00682 __IO uint32_t MCTIM0; 00683 __IO uint32_t MCTIM1; 00684 __IO uint32_t MCTIM2; 00685 __IO uint32_t MCPER0; 00686 __IO uint32_t MCPER1; 00687 __IO uint32_t MCPER2; 00688 __IO uint32_t MCPW0; 00689 __IO uint32_t MCPW1; 00690 __IO uint32_t MCPW2; 00691 __IO uint32_t MCDEADTIME; 00692 __IO uint32_t MCCCP; 00693 __IO uint32_t MCCR0; 00694 __IO uint32_t MCCR1; 00695 __IO uint32_t MCCR2; 00696 __I uint32_t MCINTEN; 00697 __O uint32_t MCINTEN_SET; 00698 __O uint32_t MCINTEN_CLR; 00699 __I uint32_t MCCNTCON; 00700 __O uint32_t MCCNTCON_SET; 00701 __O uint32_t MCCNTCON_CLR; 00702 __I uint32_t MCINTFLAG; 00703 __O uint32_t MCINTFLAG_SET; 00704 __O uint32_t MCINTFLAG_CLR; 00705 __O uint32_t MCCAP_CLR; 00706 } LPC_MCPWM_TypeDef; 00707 00708 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ 00709 typedef struct 00710 { 00711 __O uint32_t QEICON; 00712 __I uint32_t QEISTAT; 00713 __IO uint32_t QEICONF; 00714 __I uint32_t QEIPOS; 00715 __IO uint32_t QEIMAXPOS; 00716 __IO uint32_t CMPOS0; 00717 __IO uint32_t CMPOS1; 00718 __IO uint32_t CMPOS2; 00719 __I uint32_t INXCNT; 00720 __IO uint32_t INXCMP; 00721 __IO uint32_t QEILOAD; 00722 __I uint32_t QEITIME; 00723 __I uint32_t QEIVEL; 00724 __I uint32_t QEICAP; 00725 __IO uint32_t VELCOMP; 00726 __IO uint32_t FILTER; 00727 uint32_t RESERVED0[998]; 00728 __O uint32_t QEIIEC; 00729 __O uint32_t QEIIES; 00730 __I uint32_t QEIINTSTAT; 00731 __I uint32_t QEIIE; 00732 __O uint32_t QEICLR; 00733 __O uint32_t QEISET; 00734 } LPC_QEI_TypeDef; 00735 00736 /*------------- Controller Area Network (CAN) --------------------------------*/ 00737 typedef struct 00738 { 00739 __IO uint32_t mask[512]; /* ID Masks */ 00740 } LPC_CANAF_RAM_TypeDef; 00741 00742 typedef struct /* Acceptance Filter Registers */ 00743 { 00744 __IO uint32_t AFMR; 00745 __IO uint32_t SFF_sa; 00746 __IO uint32_t SFF_GRP_sa; 00747 __IO uint32_t EFF_sa; 00748 __IO uint32_t EFF_GRP_sa; 00749 __IO uint32_t ENDofTable; 00750 __I uint32_t LUTerrAd; 00751 __I uint32_t LUTerr; 00752 __IO uint32_t FCANIE; 00753 __IO uint32_t FCANIC0; 00754 __IO uint32_t FCANIC1; 00755 } LPC_CANAF_TypeDef; 00756 00757 typedef struct /* Central Registers */ 00758 { 00759 __I uint32_t CANTxSR; 00760 __I uint32_t CANRxSR; 00761 __I uint32_t CANMSR; 00762 } LPC_CANCR_TypeDef; 00763 00764 typedef struct /* Controller Registers */ 00765 { 00766 __IO uint32_t MOD; 00767 __O uint32_t CMR; 00768 __IO uint32_t GSR; 00769 __I uint32_t ICR; 00770 __IO uint32_t IER; 00771 __IO uint32_t BTR; 00772 __IO uint32_t EWL; 00773 __I uint32_t SR; 00774 __IO uint32_t RFS; 00775 __IO uint32_t RID; 00776 __IO uint32_t RDA; 00777 __IO uint32_t RDB; 00778 __IO uint32_t TFI1; 00779 __IO uint32_t TID1; 00780 __IO uint32_t TDA1; 00781 __IO uint32_t TDB1; 00782 __IO uint32_t TFI2; 00783 __IO uint32_t TID2; 00784 __IO uint32_t TDA2; 00785 __IO uint32_t TDB2; 00786 __IO uint32_t TFI3; 00787 __IO uint32_t TID3; 00788 __IO uint32_t TDA3; 00789 __IO uint32_t TDB3; 00790 } LPC_CAN_TypeDef; 00791 00792 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ 00793 typedef struct /* Common Registers */ 00794 { 00795 __I uint32_t DMACIntStat; 00796 __I uint32_t DMACIntTCStat; 00797 __O uint32_t DMACIntTCClear; 00798 __I uint32_t DMACIntErrStat; 00799 __O uint32_t DMACIntErrClr; 00800 __I uint32_t DMACRawIntTCStat; 00801 __I uint32_t DMACRawIntErrStat; 00802 __I uint32_t DMACEnbldChns; 00803 __IO uint32_t DMACSoftBReq; 00804 __IO uint32_t DMACSoftSReq; 00805 __IO uint32_t DMACSoftLBReq; 00806 __IO uint32_t DMACSoftLSReq; 00807 __IO uint32_t DMACConfig; 00808 __IO uint32_t DMACSync; 00809 } LPC_GPDMA_TypeDef; 00810 00811 typedef struct /* Channel Registers */ 00812 { 00813 __IO uint32_t DMACCSrcAddr; 00814 __IO uint32_t DMACCDestAddr; 00815 __IO uint32_t DMACCLLI; 00816 __IO uint32_t DMACCControl; 00817 __IO uint32_t DMACCConfig; 00818 } LPC_GPDMACH_TypeDef; 00819 00820 /*------------- Universal Serial Bus (USB) -----------------------------------*/ 00821 typedef struct 00822 { 00823 __I uint32_t HcRevision; /* USB Host Registers */ 00824 __IO uint32_t HcControl; 00825 __IO uint32_t HcCommandStatus; 00826 __IO uint32_t HcInterruptStatus; 00827 __IO uint32_t HcInterruptEnable; 00828 __IO uint32_t HcInterruptDisable; 00829 __IO uint32_t HcHCCA; 00830 __I uint32_t HcPeriodCurrentED; 00831 __IO uint32_t HcControlHeadED; 00832 __IO uint32_t HcControlCurrentED; 00833 __IO uint32_t HcBulkHeadED; 00834 __IO uint32_t HcBulkCurrentED; 00835 __I uint32_t HcDoneHead; 00836 __IO uint32_t HcFmInterval; 00837 __I uint32_t HcFmRemaining; 00838 __I uint32_t HcFmNumber; 00839 __IO uint32_t HcPeriodicStart; 00840 __IO uint32_t HcLSTreshold; 00841 __IO uint32_t HcRhDescriptorA; 00842 __IO uint32_t HcRhDescriptorB; 00843 __IO uint32_t HcRhStatus; 00844 __IO uint32_t HcRhPortStatus1; 00845 __IO uint32_t HcRhPortStatus2; 00846 uint32_t RESERVED0[40]; 00847 __I uint32_t Module_ID; 00848 00849 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ 00850 __IO uint32_t OTGIntEn; 00851 __O uint32_t OTGIntSet; 00852 __O uint32_t OTGIntClr; 00853 __IO uint32_t OTGStCtrl; 00854 __IO uint32_t OTGTmr; 00855 uint32_t RESERVED1[58]; 00856 00857 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ 00858 __IO uint32_t USBDevIntEn; 00859 __O uint32_t USBDevIntClr; 00860 __O uint32_t USBDevIntSet; 00861 00862 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ 00863 __I uint32_t USBCmdData; 00864 00865 __I uint32_t USBRxData; /* USB Device Transfer Registers */ 00866 __O uint32_t USBTxData; 00867 __I uint32_t USBRxPLen; 00868 __O uint32_t USBTxPLen; 00869 __IO uint32_t USBCtrl; 00870 __O uint32_t USBDevIntPri; 00871 00872 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ 00873 __IO uint32_t USBEpIntEn; 00874 __O uint32_t USBEpIntClr; 00875 __O uint32_t USBEpIntSet; 00876 __O uint32_t USBEpIntPri; 00877 00878 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ 00879 __O uint32_t USBEpInd; 00880 __IO uint32_t USBMaxPSize; 00881 00882 __I uint32_t USBDMARSt; /* USB Device DMA Registers */ 00883 __O uint32_t USBDMARClr; 00884 __O uint32_t USBDMARSet; 00885 uint32_t RESERVED2[9]; 00886 __IO uint32_t USBUDCAH; 00887 __I uint32_t USBEpDMASt; 00888 __O uint32_t USBEpDMAEn; 00889 __O uint32_t USBEpDMADis; 00890 __I uint32_t USBDMAIntSt; 00891 __IO uint32_t USBDMAIntEn; 00892 uint32_t RESERVED3[2]; 00893 __I uint32_t USBEoTIntSt; 00894 __O uint32_t USBEoTIntClr; 00895 __O uint32_t USBEoTIntSet; 00896 __I uint32_t USBNDDRIntSt; 00897 __O uint32_t USBNDDRIntClr; 00898 __O uint32_t USBNDDRIntSet; 00899 __I uint32_t USBSysErrIntSt; 00900 __O uint32_t USBSysErrIntClr; 00901 __O uint32_t USBSysErrIntSet; 00902 uint32_t RESERVED4[15]; 00903 00904 __I uint32_t I2C_RX; /* USB OTG I2C Registers */ 00905 __O uint32_t I2C_WO; 00906 __I uint32_t I2C_STS; 00907 __IO uint32_t I2C_CTL; 00908 __IO uint32_t I2C_CLKHI; 00909 __O uint32_t I2C_CLKLO; 00910 uint32_t RESERVED5[823]; 00911 00912 union { 00913 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ 00914 __IO uint32_t OTGClkCtrl; 00915 }; 00916 union { 00917 __I uint32_t USBClkSt; 00918 __I uint32_t OTGClkSt; 00919 }; 00920 } LPC_USB_TypeDef; 00921 00922 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ 00923 typedef struct 00924 { 00925 __IO uint32_t MAC1; /* MAC Registers */ 00926 __IO uint32_t MAC2; 00927 __IO uint32_t IPGT; 00928 __IO uint32_t IPGR; 00929 __IO uint32_t CLRT; 00930 __IO uint32_t MAXF; 00931 __IO uint32_t SUPP; 00932 __IO uint32_t TEST; 00933 __IO uint32_t MCFG; 00934 __IO uint32_t MCMD; 00935 __IO uint32_t MADR; 00936 __O uint32_t MWTD; 00937 __I uint32_t MRDD; 00938 __I uint32_t MIND; 00939 uint32_t RESERVED0[2]; 00940 __IO uint32_t SA0; 00941 __IO uint32_t SA1; 00942 __IO uint32_t SA2; 00943 uint32_t RESERVED1[45]; 00944 __IO uint32_t Command; /* Control Registers */ 00945 __I uint32_t Status; 00946 __IO uint32_t RxDescriptor; 00947 __IO uint32_t RxStatus; 00948 __IO uint32_t RxDescriptorNumber; 00949 __I uint32_t RxProduceIndex; 00950 __IO uint32_t RxConsumeIndex; 00951 __IO uint32_t TxDescriptor; 00952 __IO uint32_t TxStatus; 00953 __IO uint32_t TxDescriptorNumber; 00954 __IO uint32_t TxProduceIndex; 00955 __I uint32_t TxConsumeIndex; 00956 uint32_t RESERVED2[10]; 00957 __I uint32_t TSV0; 00958 __I uint32_t TSV1; 00959 __I uint32_t RSV; 00960 uint32_t RESERVED3[3]; 00961 __IO uint32_t FlowControlCounter; 00962 __I uint32_t FlowControlStatus; 00963 uint32_t RESERVED4[34]; 00964 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ 00965 __IO uint32_t RxFilterWoLStatus; 00966 __IO uint32_t RxFilterWoLClear; 00967 uint32_t RESERVED5; 00968 __IO uint32_t HashFilterL; 00969 __IO uint32_t HashFilterH; 00970 uint32_t RESERVED6[882]; 00971 __I uint32_t IntStatus; /* Module Control Registers */ 00972 __IO uint32_t IntEnable; 00973 __O uint32_t IntClear; 00974 __O uint32_t IntSet; 00975 uint32_t RESERVED7; 00976 __IO uint32_t PowerDown; 00977 uint32_t RESERVED8; 00978 __IO uint32_t Module_ID; 00979 } LPC_EMAC_TypeDef; 00980 00981 #pragma no_anon_unions 00982 00983 00984 /******************************************************************************/ 00985 /* Peripheral memory map */ 00986 /******************************************************************************/ 00987 /* Base addresses */ 00988 #define LPC_FLASH_BASE (0x00000000UL) 00989 #define LPC_RAM_BASE (0x10000000UL) 00990 #define LPC_GPIO_BASE (0x2009C000UL) 00991 #define LPC_APB0_BASE (0x40000000UL) 00992 #define LPC_APB1_BASE (0x40080000UL) 00993 #define LPC_AHB_BASE (0x50000000UL) 00994 #define LPC_CM3_BASE (0xE0000000UL) 00995 00996 /* APB0 peripherals */ 00997 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) 00998 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) 00999 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) 01000 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) 01001 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) 01002 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) 01003 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) 01004 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) 01005 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) 01006 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) 01007 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) 01008 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) 01009 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) 01010 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) 01011 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) 01012 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) 01013 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) 01014 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) 01015 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) 01016 01017 /* APB1 peripherals */ 01018 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) 01019 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) 01020 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) 01021 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) 01022 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) 01023 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) 01024 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) 01025 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) 01026 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) 01027 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) 01028 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) 01029 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) 01030 01031 /* AHB peripherals */ 01032 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) 01033 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) 01034 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) 01035 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) 01036 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) 01037 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) 01038 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) 01039 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) 01040 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) 01041 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) 01042 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) 01043 01044 /* GPIOs */ 01045 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) 01046 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) 01047 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) 01048 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) 01049 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) 01050 01051 01052 /******************************************************************************/ 01053 /* Peripheral declaration */ 01054 /******************************************************************************/ 01055 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) 01056 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) 01057 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) 01058 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) 01059 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) 01060 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) 01061 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) 01062 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) 01063 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) 01064 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) 01065 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) 01066 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) 01067 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) 01068 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) 01069 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) 01070 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) 01071 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) 01072 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) 01073 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) 01074 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) 01075 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) 01076 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) 01077 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) 01078 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) 01079 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) 01080 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) 01081 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) 01082 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) 01083 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) 01084 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) 01085 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) 01086 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) 01087 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) 01088 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) 01089 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) 01090 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) 01091 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) 01092 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) 01093 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) 01094 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) 01095 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) 01096 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) 01097 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) 01098 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) 01099 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) 01100 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) 01101 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) 01102 01103 #endif // __LPC17xx_H__
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