rik te winkel / mbed-dev

Forked mbed-dev as I use an 20 pins stm32F042 and not the 32 pins version

Dependents:   Numitron_clock

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC81X/spi_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include <math.h>
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 20 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 21 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 22 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 static const SWM_Map SWM_SPI_SSEL[] = {
<> 144:ef7eb2e8f9f7 25 {4, 16},
<> 144:ef7eb2e8f9f7 26 {5, 16},
<> 144:ef7eb2e8f9f7 27 };
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 static const SWM_Map SWM_SPI_SCLK[] = {
<> 144:ef7eb2e8f9f7 30 {3, 24},
<> 144:ef7eb2e8f9f7 31 {4, 24},
<> 144:ef7eb2e8f9f7 32 };
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 static const SWM_Map SWM_SPI_MOSI[] = {
<> 144:ef7eb2e8f9f7 35 {4, 0},
<> 144:ef7eb2e8f9f7 36 {5, 0},
<> 144:ef7eb2e8f9f7 37 };
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 static const SWM_Map SWM_SPI_MISO[] = {
<> 144:ef7eb2e8f9f7 40 {4, 8},
<> 144:ef7eb2e8f9f7 41 {5, 16},
<> 144:ef7eb2e8f9f7 42 };
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 // bit flags for used SPIs
<> 144:ef7eb2e8f9f7 45 static unsigned char spi_used = 0;
<> 144:ef7eb2e8f9f7 46 static int get_available_spi(void) {
<> 144:ef7eb2e8f9f7 47 int i;
<> 144:ef7eb2e8f9f7 48 for (i=0; i<2; i++) {
<> 144:ef7eb2e8f9f7 49 if ((spi_used & (1 << i)) == 0)
<> 144:ef7eb2e8f9f7 50 return i;
<> 144:ef7eb2e8f9f7 51 }
<> 144:ef7eb2e8f9f7 52 return -1;
<> 144:ef7eb2e8f9f7 53 }
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 static inline int ssp_disable(spi_t *obj);
<> 144:ef7eb2e8f9f7 56 static inline int ssp_enable(spi_t *obj);
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
<> 144:ef7eb2e8f9f7 59 int spi_n = get_available_spi();
<> 144:ef7eb2e8f9f7 60 if (spi_n == -1) {
<> 144:ef7eb2e8f9f7 61 error("No available SPI");
<> 144:ef7eb2e8f9f7 62 }
<> 144:ef7eb2e8f9f7 63 obj->spi_n = spi_n;
<> 144:ef7eb2e8f9f7 64 spi_used |= (1 << spi_n);
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE);
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 const SWM_Map *swm;
<> 144:ef7eb2e8f9f7 69 uint32_t regVal;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 swm = &SWM_SPI_SCLK[obj->spi_n];
<> 144:ef7eb2e8f9f7 72 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 73 LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 swm = &SWM_SPI_MOSI[obj->spi_n];
<> 144:ef7eb2e8f9f7 76 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 77 LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 swm = &SWM_SPI_MISO[obj->spi_n];
<> 144:ef7eb2e8f9f7 80 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 81 LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 swm = &SWM_SPI_SSEL[obj->spi_n];
<> 144:ef7eb2e8f9f7 84 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 85 LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 // clear interrupts
<> 144:ef7eb2e8f9f7 88 obj->spi->INTENCLR = 0x3f;
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 // enable power and clocking
<> 144:ef7eb2e8f9f7 91 switch (obj->spi_n) {
<> 144:ef7eb2e8f9f7 92 case 0:
<> 144:ef7eb2e8f9f7 93 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
<> 144:ef7eb2e8f9f7 94 LPC_SYSCON->PRESETCTRL &= ~(0x1<<0);
<> 144:ef7eb2e8f9f7 95 LPC_SYSCON->PRESETCTRL |= (0x1<<0);
<> 144:ef7eb2e8f9f7 96 break;
<> 144:ef7eb2e8f9f7 97 case 1:
<> 144:ef7eb2e8f9f7 98 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
<> 144:ef7eb2e8f9f7 99 LPC_SYSCON->PRESETCTRL &= ~(0x1<<1);
<> 144:ef7eb2e8f9f7 100 LPC_SYSCON->PRESETCTRL |= (0x1<<1);
<> 144:ef7eb2e8f9f7 101 break;
<> 144:ef7eb2e8f9f7 102 }
<> 144:ef7eb2e8f9f7 103 }
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 void spi_free(spi_t *obj) {}
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 void spi_format(spi_t *obj, int bits, int mode, int slave) {
<> 144:ef7eb2e8f9f7 108 MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
<> 144:ef7eb2e8f9f7 109 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 int polarity = (mode & 0x2) ? 1 : 0;
<> 144:ef7eb2e8f9f7 112 int phase = (mode & 0x1) ? 1 : 0;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 // set it up
<> 144:ef7eb2e8f9f7 115 int DSS = bits - 1; // DSS (data select size)
<> 144:ef7eb2e8f9f7 116 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
<> 144:ef7eb2e8f9f7 117 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 uint32_t tmp = obj->spi->CFG;
<> 144:ef7eb2e8f9f7 120 tmp &= ~((1 << 2) | (1 << 4) | (1 << 5));
<> 144:ef7eb2e8f9f7 121 tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2);
<> 144:ef7eb2e8f9f7 122 obj->spi->CFG = tmp;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 // select frame length
<> 144:ef7eb2e8f9f7 125 tmp = obj->spi->TXDATCTL;
<> 144:ef7eb2e8f9f7 126 tmp &= ~(0xf << 24);
<> 144:ef7eb2e8f9f7 127 tmp |= (DSS << 24);
<> 144:ef7eb2e8f9f7 128 obj->spi->TXDATCTL = tmp;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 void spi_frequency(spi_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 134 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 uint32_t PCLK = SystemCoreClock;
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 obj->spi->DIV = PCLK/hz - 1;
<> 144:ef7eb2e8f9f7 139 obj->spi->DLY = 0;
<> 144:ef7eb2e8f9f7 140 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 static inline int ssp_disable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 144 return obj->spi->CFG &= ~(1 << 0);
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 static inline int ssp_enable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 148 return obj->spi->CFG |= (1 << 0);
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 static inline int ssp_readable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 152 return obj->spi->STAT & (1 << 0);
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 static inline int ssp_writeable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 156 return obj->spi->STAT & (1 << 1);
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 static inline void ssp_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 160 while (!ssp_writeable(obj));
<> 144:ef7eb2e8f9f7 161 // end of transfer
<> 144:ef7eb2e8f9f7 162 obj->spi->TXDATCTL |= (1 << 20);
<> 144:ef7eb2e8f9f7 163 obj->spi->TXDAT = value;
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 static inline int ssp_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 167 while (!ssp_readable(obj));
<> 144:ef7eb2e8f9f7 168 return obj->spi->RXDAT;
<> 144:ef7eb2e8f9f7 169 }
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 static inline int ssp_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 172 // checking RXOV(Receiver Overrun interrupt flag)
<> 144:ef7eb2e8f9f7 173 return obj->spi->STAT & (1 << 2);
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 int spi_master_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 177 ssp_write(obj, value);
<> 144:ef7eb2e8f9f7 178 return ssp_read(obj);
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 int spi_slave_receive(spi_t *obj) {
<> 144:ef7eb2e8f9f7 182 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 int spi_slave_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 186 return obj->spi->RXDAT;
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 void spi_slave_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 190 while (ssp_writeable(obj) == 0) ;
<> 144:ef7eb2e8f9f7 191 obj->spi->TXDAT = value;
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 int spi_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 195 return ssp_busy(obj);
<> 144:ef7eb2e8f9f7 196 }