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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_pwr.h@106:ba1f97679dad, 2015-09-02 (annotated)

Committer:
Kojto
Date:
Wed Sep 02 14:17:43 2015 +0100
Revision:
106:ba1f97679dad
Parent:
99:dbbf35b96557
Child:
110:165afa46840b
Release 106  of the mbed library



Changes:

- new platform - Nucleo F446RE

- STM32F4 Cube driver update v2.3.2

- ST cmsis driver v2.3.2

- nordic bugfix gcc linker start address

- lpc11u68 - bugfix for serial ports

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_pwr.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
Kojto 106:ba1f97679dad 5 * @version V1.3.2
Kojto 106:ba1f97679dad 6 * @date 26-June-2015
bogdanm 92:4fc01daae5a5 7 * @brief Header file of PWR HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_PWR_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_PWR_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup PWR
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 58
Kojto 99:dbbf35b96557 59 /** @defgroup PWR_Exported_Types PWR Exported Types
Kojto 99:dbbf35b96557 60 * @{
Kojto 99:dbbf35b96557 61 */
Kojto 99:dbbf35b96557 62
bogdanm 92:4fc01daae5a5 63 /**
bogdanm 92:4fc01daae5a5 64 * @brief PWR PVD configuration structure definition
bogdanm 92:4fc01daae5a5 65 */
bogdanm 92:4fc01daae5a5 66 typedef struct
bogdanm 92:4fc01daae5a5 67 {
bogdanm 92:4fc01daae5a5 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
bogdanm 92:4fc01daae5a5 69 This parameter can be a value of @ref PWR_PVD_detection_level */
bogdanm 92:4fc01daae5a5 70
bogdanm 92:4fc01daae5a5 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
bogdanm 92:4fc01daae5a5 72 This parameter can be a value of @ref PWR_PVD_Mode */
bogdanm 92:4fc01daae5a5 73 }PWR_PVDTypeDef;
bogdanm 92:4fc01daae5a5 74
bogdanm 92:4fc01daae5a5 75 /**
bogdanm 92:4fc01daae5a5 76 * @}
bogdanm 92:4fc01daae5a5 77 */
bogdanm 92:4fc01daae5a5 78
Kojto 99:dbbf35b96557 79 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 80 /** @defgroup PWR_Exported_Constants PWR Exported Constants
Kojto 99:dbbf35b96557 81 * @{
Kojto 99:dbbf35b96557 82 */
Kojto 99:dbbf35b96557 83
Kojto 99:dbbf35b96557 84 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
Kojto 99:dbbf35b96557 85 * @{
Kojto 99:dbbf35b96557 86 */
Kojto 99:dbbf35b96557 87 #define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100)
Kojto 99:dbbf35b96557 88 #define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080)
Kojto 99:dbbf35b96557 89 /**
Kojto 99:dbbf35b96557 90 * @}
Kojto 99:dbbf35b96557 91 */
Kojto 99:dbbf35b96557 92
Kojto 99:dbbf35b96557 93 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
bogdanm 92:4fc01daae5a5 94 * @{
bogdanm 92:4fc01daae5a5 95 */
bogdanm 92:4fc01daae5a5 96 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
bogdanm 92:4fc01daae5a5 97 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
bogdanm 92:4fc01daae5a5 98 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
bogdanm 92:4fc01daae5a5 99 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
bogdanm 92:4fc01daae5a5 100 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
bogdanm 92:4fc01daae5a5 101 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
bogdanm 92:4fc01daae5a5 102 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
Kojto 99:dbbf35b96557 103 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
Kojto 99:dbbf35b96557 104 (Compare internally to VREFINT) */
bogdanm 92:4fc01daae5a5 105 /**
bogdanm 92:4fc01daae5a5 106 * @}
bogdanm 92:4fc01daae5a5 107 */
bogdanm 92:4fc01daae5a5 108
Kojto 99:dbbf35b96557 109 /** @defgroup PWR_PVD_Mode PWR PVD Mode
bogdanm 92:4fc01daae5a5 110 * @{
bogdanm 92:4fc01daae5a5 111 */
Kojto 99:dbbf35b96557 112 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
Kojto 99:dbbf35b96557 113 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
Kojto 99:dbbf35b96557 114 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
Kojto 99:dbbf35b96557 115 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
Kojto 99:dbbf35b96557 116 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
Kojto 99:dbbf35b96557 117 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
Kojto 99:dbbf35b96557 118 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
bogdanm 92:4fc01daae5a5 119 /**
bogdanm 92:4fc01daae5a5 120 * @}
Kojto 99:dbbf35b96557 121 */
bogdanm 92:4fc01daae5a5 122
Kojto 99:dbbf35b96557 123
Kojto 99:dbbf35b96557 124 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
bogdanm 92:4fc01daae5a5 125 * @{
bogdanm 92:4fc01daae5a5 126 */
bogdanm 92:4fc01daae5a5 127 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 128 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
bogdanm 92:4fc01daae5a5 129 /**
bogdanm 92:4fc01daae5a5 130 * @}
bogdanm 92:4fc01daae5a5 131 */
bogdanm 92:4fc01daae5a5 132
Kojto 99:dbbf35b96557 133 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
bogdanm 92:4fc01daae5a5 134 * @{
bogdanm 92:4fc01daae5a5 135 */
bogdanm 92:4fc01daae5a5 136 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
bogdanm 92:4fc01daae5a5 137 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
bogdanm 92:4fc01daae5a5 138 /**
bogdanm 92:4fc01daae5a5 139 * @}
bogdanm 92:4fc01daae5a5 140 */
bogdanm 92:4fc01daae5a5 141
Kojto 99:dbbf35b96557 142 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
bogdanm 92:4fc01daae5a5 143 * @{
bogdanm 92:4fc01daae5a5 144 */
bogdanm 92:4fc01daae5a5 145 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
bogdanm 92:4fc01daae5a5 146 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
bogdanm 92:4fc01daae5a5 147 /**
bogdanm 92:4fc01daae5a5 148 * @}
bogdanm 92:4fc01daae5a5 149 */
bogdanm 92:4fc01daae5a5 150
Kojto 99:dbbf35b96557 151 /** @defgroup PWR_Flag PWR Flag
bogdanm 92:4fc01daae5a5 152 * @{
bogdanm 92:4fc01daae5a5 153 */
bogdanm 92:4fc01daae5a5 154 #define PWR_FLAG_WU PWR_CSR_WUF
bogdanm 92:4fc01daae5a5 155 #define PWR_FLAG_SB PWR_CSR_SBF
bogdanm 92:4fc01daae5a5 156 #define PWR_FLAG_PVDO PWR_CSR_PVDO
bogdanm 92:4fc01daae5a5 157 #define PWR_FLAG_BRR PWR_CSR_BRR
bogdanm 92:4fc01daae5a5 158 #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
bogdanm 92:4fc01daae5a5 159 /**
bogdanm 92:4fc01daae5a5 160 * @}
bogdanm 92:4fc01daae5a5 161 */
bogdanm 92:4fc01daae5a5 162
bogdanm 92:4fc01daae5a5 163 /**
bogdanm 92:4fc01daae5a5 164 * @}
bogdanm 92:4fc01daae5a5 165 */
bogdanm 92:4fc01daae5a5 166
bogdanm 92:4fc01daae5a5 167 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 168 /** @defgroup PWR_Exported_Macro PWR Exported Macro
Kojto 99:dbbf35b96557 169 * @{
Kojto 99:dbbf35b96557 170 */
bogdanm 92:4fc01daae5a5 171
Kojto 106:ba1f97679dad 172 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 173 /** @brief macros configure the main internal regulator output voltage.
Kojto 99:dbbf35b96557 174 * @param __REGULATOR__: specifies the regulator output voltage to achieve
Kojto 99:dbbf35b96557 175 * a tradeoff between performance and power consumption when the device does
Kojto 99:dbbf35b96557 176 * not operate at the maximum frequency (refer to the datasheets for more details).
Kojto 99:dbbf35b96557 177 * This parameter can be one of the following values:
Kojto 99:dbbf35b96557 178 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
Kojto 99:dbbf35b96557 179 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
Kojto 99:dbbf35b96557 180 * @retval None
Kojto 99:dbbf35b96557 181 */
Kojto 99:dbbf35b96557 182 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
Kojto 99:dbbf35b96557 183 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 184 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
Kojto 99:dbbf35b96557 185 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 186 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
Kojto 99:dbbf35b96557 187 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 188 } while(0)
Kojto 99:dbbf35b96557 189 #else
bogdanm 92:4fc01daae5a5 190 /** @brief macros configure the main internal regulator output voltage.
bogdanm 92:4fc01daae5a5 191 * @param __REGULATOR__: specifies the regulator output voltage to achieve
bogdanm 92:4fc01daae5a5 192 * a tradeoff between performance and power consumption when the device does
bogdanm 92:4fc01daae5a5 193 * not operate at the maximum frequency (refer to the datasheets for more details).
bogdanm 92:4fc01daae5a5 194 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 195 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
bogdanm 92:4fc01daae5a5 196 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
bogdanm 92:4fc01daae5a5 197 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
bogdanm 92:4fc01daae5a5 198 * @retval None
bogdanm 92:4fc01daae5a5 199 */
Kojto 99:dbbf35b96557 200 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
Kojto 99:dbbf35b96557 201 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 202 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
Kojto 99:dbbf35b96557 203 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 204 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
Kojto 99:dbbf35b96557 205 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 206 } while(0)
Kojto 99:dbbf35b96557 207 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
bogdanm 92:4fc01daae5a5 208
bogdanm 92:4fc01daae5a5 209 /** @brief Check PWR flag is set or not.
bogdanm 92:4fc01daae5a5 210 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 211 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 212 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
bogdanm 92:4fc01daae5a5 213 * was received from the WKUP pin or from the RTC alarm (Alarm A
bogdanm 92:4fc01daae5a5 214 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
bogdanm 92:4fc01daae5a5 215 * An additional wakeup event is detected if the WKUP pin is enabled
bogdanm 92:4fc01daae5a5 216 * (by setting the EWUP bit) when the WKUP pin level is already high.
bogdanm 92:4fc01daae5a5 217 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
bogdanm 92:4fc01daae5a5 218 * resumed from StandBy mode.
bogdanm 92:4fc01daae5a5 219 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
bogdanm 92:4fc01daae5a5 220 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
bogdanm 92:4fc01daae5a5 221 * For this reason, this bit is equal to 0 after Standby or reset
bogdanm 92:4fc01daae5a5 222 * until the PVDE bit is set.
bogdanm 92:4fc01daae5a5 223 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
bogdanm 92:4fc01daae5a5 224 * when the device wakes up from Standby mode or by a system reset
bogdanm 92:4fc01daae5a5 225 * or power reset.
bogdanm 92:4fc01daae5a5 226 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
bogdanm 92:4fc01daae5a5 227 * scaling output selection is ready.
bogdanm 92:4fc01daae5a5 228 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 229 */
bogdanm 92:4fc01daae5a5 230 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 231
bogdanm 92:4fc01daae5a5 232 /** @brief Clear the PWR's pending flags.
bogdanm 92:4fc01daae5a5 233 * @param __FLAG__: specifies the flag to clear.
bogdanm 92:4fc01daae5a5 234 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 235 * @arg PWR_FLAG_WU: Wake Up flag
bogdanm 92:4fc01daae5a5 236 * @arg PWR_FLAG_SB: StandBy flag
bogdanm 92:4fc01daae5a5 237 */
bogdanm 92:4fc01daae5a5 238 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
bogdanm 92:4fc01daae5a5 239
Kojto 99:dbbf35b96557 240 /**
Kojto 99:dbbf35b96557 241 * @brief Enable the PVD Exti Line 16.
Kojto 99:dbbf35b96557 242 * @retval None.
Kojto 99:dbbf35b96557 243 */
Kojto 99:dbbf35b96557 244 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 245
Kojto 99:dbbf35b96557 246 /**
Kojto 99:dbbf35b96557 247 * @brief Disable the PVD EXTI Line 16.
Kojto 99:dbbf35b96557 248 * @retval None.
Kojto 99:dbbf35b96557 249 */
Kojto 99:dbbf35b96557 250 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 251
bogdanm 92:4fc01daae5a5 252 /**
Kojto 99:dbbf35b96557 253 * @brief Enable event on PVD Exti Line 16.
Kojto 99:dbbf35b96557 254 * @retval None.
Kojto 99:dbbf35b96557 255 */
Kojto 99:dbbf35b96557 256 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 257
Kojto 99:dbbf35b96557 258 /**
Kojto 99:dbbf35b96557 259 * @brief Disable event on PVD Exti Line 16.
Kojto 99:dbbf35b96557 260 * @retval None.
Kojto 99:dbbf35b96557 261 */
Kojto 99:dbbf35b96557 262 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 263
Kojto 99:dbbf35b96557 264 /**
Kojto 99:dbbf35b96557 265 * @brief Enable the PVD Extended Interrupt Rising Trigger.
bogdanm 92:4fc01daae5a5 266 * @retval None.
bogdanm 92:4fc01daae5a5 267 */
Kojto 99:dbbf35b96557 268 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 269
Kojto 99:dbbf35b96557 270 /**
Kojto 99:dbbf35b96557 271 * @brief Disable the PVD Extended Interrupt Rising Trigger.
Kojto 99:dbbf35b96557 272 * @retval None.
Kojto 99:dbbf35b96557 273 */
Kojto 99:dbbf35b96557 274 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 275
Kojto 99:dbbf35b96557 276 /**
Kojto 99:dbbf35b96557 277 * @brief Enable the PVD Extended Interrupt Falling Trigger.
Kojto 99:dbbf35b96557 278 * @retval None.
Kojto 99:dbbf35b96557 279 */
Kojto 99:dbbf35b96557 280 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 281
bogdanm 92:4fc01daae5a5 282
bogdanm 92:4fc01daae5a5 283 /**
Kojto 99:dbbf35b96557 284 * @brief Disable the PVD Extended Interrupt Falling Trigger.
bogdanm 92:4fc01daae5a5 285 * @retval None.
bogdanm 92:4fc01daae5a5 286 */
Kojto 99:dbbf35b96557 287 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 288
Kojto 99:dbbf35b96557 289
Kojto 99:dbbf35b96557 290 /**
Kojto 99:dbbf35b96557 291 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
Kojto 99:dbbf35b96557 292 * @retval None.
Kojto 99:dbbf35b96557 293 */
Kojto 99:dbbf35b96557 294 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
Kojto 99:dbbf35b96557 295
Kojto 99:dbbf35b96557 296 /**
Kojto 99:dbbf35b96557 297 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
Kojto 99:dbbf35b96557 298 * This parameter can be:
Kojto 99:dbbf35b96557 299 * @retval None.
Kojto 99:dbbf35b96557 300 */
Kojto 99:dbbf35b96557 301 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
bogdanm 92:4fc01daae5a5 302
bogdanm 92:4fc01daae5a5 303 /**
bogdanm 92:4fc01daae5a5 304 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
bogdanm 92:4fc01daae5a5 305 * @retval EXTI PVD Line Status.
bogdanm 92:4fc01daae5a5 306 */
Kojto 99:dbbf35b96557 307 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
bogdanm 92:4fc01daae5a5 308
bogdanm 92:4fc01daae5a5 309 /**
bogdanm 92:4fc01daae5a5 310 * @brief Clear the PVD Exti flag.
bogdanm 92:4fc01daae5a5 311 * @retval None.
bogdanm 92:4fc01daae5a5 312 */
Kojto 99:dbbf35b96557 313 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
bogdanm 92:4fc01daae5a5 314
bogdanm 92:4fc01daae5a5 315 /**
Kojto 99:dbbf35b96557 316 * @brief Generates a Software interrupt on PVD EXTI line.
bogdanm 92:4fc01daae5a5 317 * @retval None
bogdanm 92:4fc01daae5a5 318 */
Kojto 99:dbbf35b96557 319 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 320
Kojto 99:dbbf35b96557 321 /**
Kojto 99:dbbf35b96557 322 * @}
Kojto 99:dbbf35b96557 323 */
bogdanm 92:4fc01daae5a5 324
bogdanm 92:4fc01daae5a5 325 /* Include PWR HAL Extension module */
bogdanm 92:4fc01daae5a5 326 #include "stm32f4xx_hal_pwr_ex.h"
bogdanm 92:4fc01daae5a5 327
bogdanm 92:4fc01daae5a5 328 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 329 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
Kojto 99:dbbf35b96557 330 * @{
Kojto 99:dbbf35b96557 331 */
Kojto 99:dbbf35b96557 332
Kojto 99:dbbf35b96557 333 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 99:dbbf35b96557 334 * @{
Kojto 99:dbbf35b96557 335 */
bogdanm 92:4fc01daae5a5 336 /* Initialization and de-initialization functions *****************************/
bogdanm 92:4fc01daae5a5 337 void HAL_PWR_DeInit(void);
bogdanm 92:4fc01daae5a5 338 void HAL_PWR_EnableBkUpAccess(void);
bogdanm 92:4fc01daae5a5 339 void HAL_PWR_DisableBkUpAccess(void);
Kojto 99:dbbf35b96557 340 /**
Kojto 99:dbbf35b96557 341 * @}
Kojto 99:dbbf35b96557 342 */
bogdanm 92:4fc01daae5a5 343
Kojto 99:dbbf35b96557 344 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
Kojto 99:dbbf35b96557 345 * @{
Kojto 99:dbbf35b96557 346 */
bogdanm 92:4fc01daae5a5 347 /* Peripheral Control functions **********************************************/
bogdanm 92:4fc01daae5a5 348 /* PVD configuration */
Kojto 99:dbbf35b96557 349 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
bogdanm 92:4fc01daae5a5 350 void HAL_PWR_EnablePVD(void);
bogdanm 92:4fc01daae5a5 351 void HAL_PWR_DisablePVD(void);
bogdanm 92:4fc01daae5a5 352
bogdanm 92:4fc01daae5a5 353 /* WakeUp pins configuration */
bogdanm 92:4fc01daae5a5 354 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 92:4fc01daae5a5 355 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 92:4fc01daae5a5 356
bogdanm 92:4fc01daae5a5 357 /* Low Power modes entry */
bogdanm 92:4fc01daae5a5 358 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
bogdanm 92:4fc01daae5a5 359 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
bogdanm 92:4fc01daae5a5 360 void HAL_PWR_EnterSTANDBYMode(void);
bogdanm 92:4fc01daae5a5 361
Kojto 99:dbbf35b96557 362 /* Power PVD IRQ Handler */
bogdanm 92:4fc01daae5a5 363 void HAL_PWR_PVD_IRQHandler(void);
bogdanm 92:4fc01daae5a5 364 void HAL_PWR_PVDCallback(void);
bogdanm 92:4fc01daae5a5 365
Kojto 99:dbbf35b96557 366 /* Cortex System Control functions *******************************************/
Kojto 99:dbbf35b96557 367 void HAL_PWR_EnableSleepOnExit(void);
Kojto 99:dbbf35b96557 368 void HAL_PWR_DisableSleepOnExit(void);
Kojto 99:dbbf35b96557 369 void HAL_PWR_EnableSEVOnPend(void);
Kojto 99:dbbf35b96557 370 void HAL_PWR_DisableSEVOnPend(void);
Kojto 99:dbbf35b96557 371 /**
Kojto 99:dbbf35b96557 372 * @}
Kojto 99:dbbf35b96557 373 */
Kojto 99:dbbf35b96557 374
Kojto 99:dbbf35b96557 375 /**
Kojto 99:dbbf35b96557 376 * @}
Kojto 99:dbbf35b96557 377 */
Kojto 99:dbbf35b96557 378
Kojto 99:dbbf35b96557 379 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 380 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 381 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 382 /** @defgroup PWR_Private_Constants PWR Private Constants
Kojto 99:dbbf35b96557 383 * @{
Kojto 99:dbbf35b96557 384 */
Kojto 99:dbbf35b96557 385
Kojto 99:dbbf35b96557 386 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
Kojto 99:dbbf35b96557 387 * @{
Kojto 99:dbbf35b96557 388 */
Kojto 99:dbbf35b96557 389 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
Kojto 99:dbbf35b96557 390 /**
Kojto 99:dbbf35b96557 391 * @}
Kojto 99:dbbf35b96557 392 */
Kojto 99:dbbf35b96557 393
Kojto 99:dbbf35b96557 394 /** @defgroup PWR_register_alias_address PWR Register alias address
Kojto 99:dbbf35b96557 395 * @{
Kojto 99:dbbf35b96557 396 */
Kojto 99:dbbf35b96557 397 /* ------------- PWR registers bit address in the alias region ---------------*/
Kojto 99:dbbf35b96557 398 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
Kojto 99:dbbf35b96557 399 #define PWR_CR_OFFSET 0x00
Kojto 99:dbbf35b96557 400 #define PWR_CSR_OFFSET 0x04
Kojto 99:dbbf35b96557 401 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
Kojto 99:dbbf35b96557 402 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
Kojto 99:dbbf35b96557 403 /**
Kojto 99:dbbf35b96557 404 * @}
Kojto 99:dbbf35b96557 405 */
Kojto 99:dbbf35b96557 406
Kojto 99:dbbf35b96557 407 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
Kojto 99:dbbf35b96557 408 * @{
Kojto 99:dbbf35b96557 409 */
Kojto 99:dbbf35b96557 410 /* --- CR Register ---*/
Kojto 99:dbbf35b96557 411 /* Alias word address of DBP bit */
Kojto 99:dbbf35b96557 412 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
Kojto 99:dbbf35b96557 413 #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 414
Kojto 99:dbbf35b96557 415 /* Alias word address of PVDE bit */
Kojto 99:dbbf35b96557 416 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
Kojto 99:dbbf35b96557 417 #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 418
Kojto 99:dbbf35b96557 419 /* Alias word address of PMODE bit */
Kojto 99:dbbf35b96557 420 #define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
Kojto 99:dbbf35b96557 421 #define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PMODE_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 422 /**
Kojto 99:dbbf35b96557 423 * @}
Kojto 99:dbbf35b96557 424 */
Kojto 99:dbbf35b96557 425
Kojto 99:dbbf35b96557 426 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
Kojto 99:dbbf35b96557 427 * @{
Kojto 99:dbbf35b96557 428 */
Kojto 99:dbbf35b96557 429 /* --- CSR Register ---*/
Kojto 99:dbbf35b96557 430 /* Alias word address of EWUP bit */
Kojto 99:dbbf35b96557 431 #define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
Kojto 99:dbbf35b96557 432 #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (EWUP_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 433 /**
Kojto 99:dbbf35b96557 434 * @}
Kojto 99:dbbf35b96557 435 */
Kojto 99:dbbf35b96557 436
Kojto 99:dbbf35b96557 437 /**
Kojto 99:dbbf35b96557 438 * @}
Kojto 99:dbbf35b96557 439 */
Kojto 99:dbbf35b96557 440 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 441 /** @defgroup PWR_Private_Macros PWR Private Macros
Kojto 99:dbbf35b96557 442 * @{
Kojto 99:dbbf35b96557 443 */
Kojto 99:dbbf35b96557 444
Kojto 99:dbbf35b96557 445 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
Kojto 99:dbbf35b96557 446 * @{
Kojto 99:dbbf35b96557 447 */
Kojto 99:dbbf35b96557 448 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
Kojto 99:dbbf35b96557 449 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
Kojto 99:dbbf35b96557 450 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
Kojto 99:dbbf35b96557 451 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
Kojto 99:dbbf35b96557 452 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
Kojto 99:dbbf35b96557 453 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
Kojto 99:dbbf35b96557 454 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
Kojto 99:dbbf35b96557 455 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
Kojto 99:dbbf35b96557 456 ((MODE) == PWR_PVD_MODE_NORMAL))
Kojto 99:dbbf35b96557 457 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
Kojto 99:dbbf35b96557 458 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
Kojto 99:dbbf35b96557 459 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
Kojto 99:dbbf35b96557 460 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
Kojto 99:dbbf35b96557 461 /**
Kojto 99:dbbf35b96557 462 * @}
Kojto 99:dbbf35b96557 463 */
Kojto 99:dbbf35b96557 464
Kojto 99:dbbf35b96557 465 /**
Kojto 99:dbbf35b96557 466 * @}
Kojto 99:dbbf35b96557 467 */
bogdanm 92:4fc01daae5a5 468
bogdanm 92:4fc01daae5a5 469 /**
bogdanm 92:4fc01daae5a5 470 * @}
bogdanm 92:4fc01daae5a5 471 */
bogdanm 92:4fc01daae5a5 472
bogdanm 92:4fc01daae5a5 473 /**
bogdanm 92:4fc01daae5a5 474 * @}
bogdanm 92:4fc01daae5a5 475 */
bogdanm 92:4fc01daae5a5 476
bogdanm 92:4fc01daae5a5 477 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 478 }
bogdanm 92:4fc01daae5a5 479 #endif
bogdanm 92:4fc01daae5a5 480
bogdanm 92:4fc01daae5a5 481
bogdanm 92:4fc01daae5a5 482 #endif /* __STM32F4xx_HAL_PWR_H */
bogdanm 92:4fc01daae5a5 483
bogdanm 92:4fc01daae5a5 484 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/