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TARGET_RZ_A1H/spibsc_iodefine.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /*******************************************************************************
bogdanm 92:4fc01daae5a5 2 * DISCLAIMER
bogdanm 92:4fc01daae5a5 3 * This software is supplied by Renesas Electronics Corporation and is only
bogdanm 92:4fc01daae5a5 4 * intended for use with Renesas products. No other uses are authorized. This
bogdanm 92:4fc01daae5a5 5 * software is owned by Renesas Electronics Corporation and is protected under
bogdanm 92:4fc01daae5a5 6 * all applicable laws, including copyright laws.
bogdanm 92:4fc01daae5a5 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
bogdanm 92:4fc01daae5a5 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
bogdanm 92:4fc01daae5a5 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
bogdanm 92:4fc01daae5a5 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
bogdanm 92:4fc01daae5a5 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
bogdanm 92:4fc01daae5a5 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
bogdanm 92:4fc01daae5a5 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
bogdanm 92:4fc01daae5a5 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
bogdanm 92:4fc01daae5a5 16 * Renesas reserves the right, without notice, to make changes to this software
bogdanm 92:4fc01daae5a5 17 * and to discontinue the availability of this software. By using this software,
bogdanm 92:4fc01daae5a5 18 * you agree to the additional terms and conditions found by accessing the
bogdanm 92:4fc01daae5a5 19 * following link:
bogdanm 92:4fc01daae5a5 20 * http://www.renesas.com/disclaimer*
bogdanm 92:4fc01daae5a5 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
bogdanm 92:4fc01daae5a5 22 *******************************************************************************/
bogdanm 92:4fc01daae5a5 23 /*******************************************************************************
bogdanm 92:4fc01daae5a5 24 * File Name : spibsc_iodefine.h
bogdanm 92:4fc01daae5a5 25 * $Rev: $
bogdanm 92:4fc01daae5a5 26 * $Date:: $
bogdanm 92:4fc01daae5a5 27 * Description : Definition of I/O Register (V1.00a)
bogdanm 92:4fc01daae5a5 28 ******************************************************************************/
bogdanm 92:4fc01daae5a5 29 #ifndef SPIBSC_IODEFINE_H
bogdanm 92:4fc01daae5a5 30 #define SPIBSC_IODEFINE_H
bogdanm 92:4fc01daae5a5 31 /* ->SEC M1.10.1 : Not magic number */
bogdanm 92:4fc01daae5a5 32
bogdanm 92:4fc01daae5a5 33 struct st_spibsc
bogdanm 92:4fc01daae5a5 34 { /* SPIBSC */
bogdanm 92:4fc01daae5a5 35 volatile uint32_t CMNCR; /* CMNCR */
bogdanm 92:4fc01daae5a5 36 volatile uint32_t SSLDR; /* SSLDR */
bogdanm 92:4fc01daae5a5 37 volatile uint32_t SPBCR; /* SPBCR */
bogdanm 92:4fc01daae5a5 38 volatile uint32_t DRCR; /* DRCR */
bogdanm 92:4fc01daae5a5 39 volatile uint32_t DRCMR; /* DRCMR */
bogdanm 92:4fc01daae5a5 40 volatile uint32_t DREAR; /* DREAR */
bogdanm 92:4fc01daae5a5 41 volatile uint32_t DROPR; /* DROPR */
bogdanm 92:4fc01daae5a5 42 volatile uint32_t DRENR; /* DRENR */
bogdanm 92:4fc01daae5a5 43 volatile uint32_t SMCR; /* SMCR */
bogdanm 92:4fc01daae5a5 44 volatile uint32_t SMCMR; /* SMCMR */
bogdanm 92:4fc01daae5a5 45 volatile uint32_t SMADR; /* SMADR */
bogdanm 92:4fc01daae5a5 46 volatile uint32_t SMOPR; /* SMOPR */
bogdanm 92:4fc01daae5a5 47 volatile uint32_t SMENR; /* SMENR */
bogdanm 92:4fc01daae5a5 48 volatile uint8_t dummy1[4]; /* */
bogdanm 92:4fc01daae5a5 49 union iodefine_reg32_t SMRDR0; /* SMRDR0 */
bogdanm 92:4fc01daae5a5 50 union iodefine_reg32_t SMRDR1; /* SMRDR1 */
bogdanm 92:4fc01daae5a5 51 union iodefine_reg32_t SMWDR0; /* SMWDR0 */
bogdanm 92:4fc01daae5a5 52 union iodefine_reg32_t SMWDR1; /* SMWDR1 */
bogdanm 92:4fc01daae5a5 53
bogdanm 92:4fc01daae5a5 54 volatile uint32_t CMNSR; /* CMNSR */
bogdanm 92:4fc01daae5a5 55 volatile uint8_t dummy2[12]; /* */
bogdanm 92:4fc01daae5a5 56 volatile uint32_t DRDMCR; /* DRDMCR */
bogdanm 92:4fc01daae5a5 57 volatile uint32_t DRDRENR; /* DRDRENR */
bogdanm 92:4fc01daae5a5 58 volatile uint32_t SMDMCR; /* SMDMCR */
bogdanm 92:4fc01daae5a5 59 volatile uint32_t SMDRENR; /* SMDRENR */
bogdanm 92:4fc01daae5a5 60 };
bogdanm 92:4fc01daae5a5 61
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63 #define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
bogdanm 92:4fc01daae5a5 64 #define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
bogdanm 92:4fc01daae5a5 65
bogdanm 92:4fc01daae5a5 66
bogdanm 92:4fc01daae5a5 67 /* Start of channnel array defines of SPIBSC */
bogdanm 92:4fc01daae5a5 68
bogdanm 92:4fc01daae5a5 69 /* Channnel array defines of SPIBSC */
bogdanm 92:4fc01daae5a5 70 /*(Sample) value = SPIBSC[ channel ]->CMNCR; */
bogdanm 92:4fc01daae5a5 71 #define SPIBSC_COUNT 2
bogdanm 92:4fc01daae5a5 72 #define SPIBSC_ADDRESS_LIST \
bogdanm 92:4fc01daae5a5 73 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
bogdanm 92:4fc01daae5a5 74 &SPIBSC0, &SPIBSC1 \
bogdanm 92:4fc01daae5a5 75 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
bogdanm 92:4fc01daae5a5 76
bogdanm 92:4fc01daae5a5 77 /* End of channnel array defines of SPIBSC */
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 #define CMNCR_0 SPIBSC0.CMNCR
bogdanm 92:4fc01daae5a5 81 #define SSLDR_0 SPIBSC0.SSLDR
bogdanm 92:4fc01daae5a5 82 #define SPBCR_0 SPIBSC0.SPBCR
bogdanm 92:4fc01daae5a5 83 #define DRCR_0 SPIBSC0.DRCR
bogdanm 92:4fc01daae5a5 84 #define DRCMR_0 SPIBSC0.DRCMR
bogdanm 92:4fc01daae5a5 85 #define DREAR_0 SPIBSC0.DREAR
bogdanm 92:4fc01daae5a5 86 #define DROPR_0 SPIBSC0.DROPR
bogdanm 92:4fc01daae5a5 87 #define DRENR_0 SPIBSC0.DRENR
bogdanm 92:4fc01daae5a5 88 #define SMCR_0 SPIBSC0.SMCR
bogdanm 92:4fc01daae5a5 89 #define SMCMR_0 SPIBSC0.SMCMR
bogdanm 92:4fc01daae5a5 90 #define SMADR_0 SPIBSC0.SMADR
bogdanm 92:4fc01daae5a5 91 #define SMOPR_0 SPIBSC0.SMOPR
bogdanm 92:4fc01daae5a5 92 #define SMENR_0 SPIBSC0.SMENR
bogdanm 92:4fc01daae5a5 93 #define SMRDR0_0 SPIBSC0.SMRDR0.UINT32
bogdanm 92:4fc01daae5a5 94 #define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L]
bogdanm 92:4fc01daae5a5 95 #define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H]
bogdanm 92:4fc01daae5a5 96 #define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
bogdanm 92:4fc01daae5a5 97 #define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
bogdanm 92:4fc01daae5a5 98 #define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
bogdanm 92:4fc01daae5a5 99 #define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
bogdanm 92:4fc01daae5a5 100 #define SMRDR1_0 SPIBSC0.SMRDR1.UINT32
bogdanm 92:4fc01daae5a5 101 #define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L]
bogdanm 92:4fc01daae5a5 102 #define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H]
bogdanm 92:4fc01daae5a5 103 #define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
bogdanm 92:4fc01daae5a5 104 #define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
bogdanm 92:4fc01daae5a5 105 #define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
bogdanm 92:4fc01daae5a5 106 #define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
bogdanm 92:4fc01daae5a5 107 #define SMWDR0_0 SPIBSC0.SMWDR0.UINT32
bogdanm 92:4fc01daae5a5 108 #define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L]
bogdanm 92:4fc01daae5a5 109 #define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H]
bogdanm 92:4fc01daae5a5 110 #define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
bogdanm 92:4fc01daae5a5 111 #define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
bogdanm 92:4fc01daae5a5 112 #define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
bogdanm 92:4fc01daae5a5 113 #define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
bogdanm 92:4fc01daae5a5 114 #define SMWDR1_0 SPIBSC0.SMWDR1.UINT32
bogdanm 92:4fc01daae5a5 115 #define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L]
bogdanm 92:4fc01daae5a5 116 #define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H]
bogdanm 92:4fc01daae5a5 117 #define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
bogdanm 92:4fc01daae5a5 118 #define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
bogdanm 92:4fc01daae5a5 119 #define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
bogdanm 92:4fc01daae5a5 120 #define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
bogdanm 92:4fc01daae5a5 121 #define CMNSR_0 SPIBSC0.CMNSR
bogdanm 92:4fc01daae5a5 122 #define DRDMCR_0 SPIBSC0.DRDMCR
bogdanm 92:4fc01daae5a5 123 #define DRDRENR_0 SPIBSC0.DRDRENR
bogdanm 92:4fc01daae5a5 124 #define SMDMCR_0 SPIBSC0.SMDMCR
bogdanm 92:4fc01daae5a5 125 #define SMDRENR_0 SPIBSC0.SMDRENR
bogdanm 92:4fc01daae5a5 126 #define CMNCR_1 SPIBSC1.CMNCR
bogdanm 92:4fc01daae5a5 127 #define SSLDR_1 SPIBSC1.SSLDR
bogdanm 92:4fc01daae5a5 128 #define SPBCR_1 SPIBSC1.SPBCR
bogdanm 92:4fc01daae5a5 129 #define DRCR_1 SPIBSC1.DRCR
bogdanm 92:4fc01daae5a5 130 #define DRCMR_1 SPIBSC1.DRCMR
bogdanm 92:4fc01daae5a5 131 #define DREAR_1 SPIBSC1.DREAR
bogdanm 92:4fc01daae5a5 132 #define DROPR_1 SPIBSC1.DROPR
bogdanm 92:4fc01daae5a5 133 #define DRENR_1 SPIBSC1.DRENR
bogdanm 92:4fc01daae5a5 134 #define SMCR_1 SPIBSC1.SMCR
bogdanm 92:4fc01daae5a5 135 #define SMCMR_1 SPIBSC1.SMCMR
bogdanm 92:4fc01daae5a5 136 #define SMADR_1 SPIBSC1.SMADR
bogdanm 92:4fc01daae5a5 137 #define SMOPR_1 SPIBSC1.SMOPR
bogdanm 92:4fc01daae5a5 138 #define SMENR_1 SPIBSC1.SMENR
bogdanm 92:4fc01daae5a5 139 #define SMRDR0_1 SPIBSC1.SMRDR0.UINT32
bogdanm 92:4fc01daae5a5 140 #define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L]
bogdanm 92:4fc01daae5a5 141 #define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H]
bogdanm 92:4fc01daae5a5 142 #define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
bogdanm 92:4fc01daae5a5 143 #define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
bogdanm 92:4fc01daae5a5 144 #define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
bogdanm 92:4fc01daae5a5 145 #define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
bogdanm 92:4fc01daae5a5 146 #define SMRDR1_1 SPIBSC1.SMRDR1.UINT32
bogdanm 92:4fc01daae5a5 147 #define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L]
bogdanm 92:4fc01daae5a5 148 #define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H]
bogdanm 92:4fc01daae5a5 149 #define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
bogdanm 92:4fc01daae5a5 150 #define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
bogdanm 92:4fc01daae5a5 151 #define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
bogdanm 92:4fc01daae5a5 152 #define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
bogdanm 92:4fc01daae5a5 153 #define SMWDR0_1 SPIBSC1.SMWDR0.UINT32
bogdanm 92:4fc01daae5a5 154 #define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L]
bogdanm 92:4fc01daae5a5 155 #define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H]
bogdanm 92:4fc01daae5a5 156 #define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
bogdanm 92:4fc01daae5a5 157 #define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
bogdanm 92:4fc01daae5a5 158 #define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
bogdanm 92:4fc01daae5a5 159 #define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
bogdanm 92:4fc01daae5a5 160 #define SMWDR1_1 SPIBSC1.SMWDR1.UINT32
bogdanm 92:4fc01daae5a5 161 #define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L]
bogdanm 92:4fc01daae5a5 162 #define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H]
bogdanm 92:4fc01daae5a5 163 #define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
bogdanm 92:4fc01daae5a5 164 #define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
bogdanm 92:4fc01daae5a5 165 #define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
bogdanm 92:4fc01daae5a5 166 #define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
bogdanm 92:4fc01daae5a5 167 #define CMNSR_1 SPIBSC1.CMNSR
bogdanm 92:4fc01daae5a5 168 #define DRDMCR_1 SPIBSC1.DRDMCR
bogdanm 92:4fc01daae5a5 169 #define DRDRENR_1 SPIBSC1.DRDRENR
bogdanm 92:4fc01daae5a5 170 #define SMDMCR_1 SPIBSC1.SMDMCR
bogdanm 92:4fc01daae5a5 171 #define SMDRENR_1 SPIBSC1.SMDRENR
bogdanm 92:4fc01daae5a5 172 /* <-SEC M1.10.1 */
bogdanm 92:4fc01daae5a5 173 #endif