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TARGET_MTS_MDOT_F405RG/stm32f4xx_ll_fmc.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:: Kojto
Date:: Wed Nov 25 13:21:40 2015 +0000
Revision:: 110:165afa46840b
Parent:: 106:ba1f97679dad

Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	92:4fc01daae5a5	1	/**
bogdanm	92:4fc01daae5a5	2	******************************************************************************
bogdanm	92:4fc01daae5a5	3	* @file stm32f4xx_ll_fmc.h
bogdanm	92:4fc01daae5a5	4	* @author MCD Application Team
Kojto	110:165afa46840b	5	* @version V1.4.1
Kojto	110:165afa46840b	6	* @date 09-October-2015
bogdanm	92:4fc01daae5a5	7	* @brief Header file of FMC HAL module.
bogdanm	92:4fc01daae5a5	8	******************************************************************************
bogdanm	92:4fc01daae5a5	9	* @attention
bogdanm	92:4fc01daae5a5	10	*
Kojto	99:dbbf35b96557	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	92:4fc01daae5a5	12	*
bogdanm	92:4fc01daae5a5	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	92:4fc01daae5a5	14	* are permitted provided that the following conditions are met:
bogdanm	92:4fc01daae5a5	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	92:4fc01daae5a5	16	* this list of conditions and the following disclaimer.
bogdanm	92:4fc01daae5a5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	92:4fc01daae5a5	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	92:4fc01daae5a5	19	* and/or other materials provided with the distribution.
bogdanm	92:4fc01daae5a5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	92:4fc01daae5a5	21	* may be used to endorse or promote products derived from this software
bogdanm	92:4fc01daae5a5	22	* without specific prior written permission.
bogdanm	92:4fc01daae5a5	23	*
bogdanm	92:4fc01daae5a5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	92:4fc01daae5a5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	92:4fc01daae5a5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	92:4fc01daae5a5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	92:4fc01daae5a5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	92:4fc01daae5a5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	92:4fc01daae5a5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	92:4fc01daae5a5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	92:4fc01daae5a5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	92:4fc01daae5a5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	92:4fc01daae5a5	34	*
bogdanm	92:4fc01daae5a5	35	******************************************************************************
bogdanm	92:4fc01daae5a5	36	*/
bogdanm	92:4fc01daae5a5	37
bogdanm	92:4fc01daae5a5	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	92:4fc01daae5a5	39	#ifndef __STM32F4xx_LL_FMC_H
bogdanm	92:4fc01daae5a5	40	#define __STM32F4xx_LL_FMC_H
bogdanm	92:4fc01daae5a5	41
bogdanm	92:4fc01daae5a5	42	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	43	extern "C" {
bogdanm	92:4fc01daae5a5	44	#endif
bogdanm	92:4fc01daae5a5	45
bogdanm	92:4fc01daae5a5	46	/* Includes ------------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	47	#include "stm32f4xx_hal_def.h"
bogdanm	92:4fc01daae5a5	48
bogdanm	92:4fc01daae5a5	49	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	92:4fc01daae5a5	50	* @{
bogdanm	92:4fc01daae5a5	51	*/
Kojto	99:dbbf35b96557	52
Kojto	99:dbbf35b96557	53	/** @addtogroup FMC_LL
bogdanm	92:4fc01daae5a5	54	* @{
bogdanm	92:4fc01daae5a5	55	*/
Kojto	110:165afa46840b	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	57	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	58	/* Private types -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	59	/** @defgroup FMC_LL_Private_Types FMC Private Types
Kojto	99:dbbf35b96557	60	* @{
Kojto	99:dbbf35b96557	61	*/
bogdanm	92:4fc01daae5a5	62
bogdanm	92:4fc01daae5a5	63	/**
Kojto	99:dbbf35b96557	64	* @brief FMC NORSRAM Configuration Structure definition
bogdanm	92:4fc01daae5a5	65	*/
bogdanm	92:4fc01daae5a5	66	typedef struct
bogdanm	92:4fc01daae5a5	67	{
bogdanm	92:4fc01daae5a5	68	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm	92:4fc01daae5a5	69	This parameter can be a value of @ref FMC_NORSRAM_Bank */
bogdanm	92:4fc01daae5a5	70
bogdanm	92:4fc01daae5a5	71	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm	92:4fc01daae5a5	72	multiplexed on the data bus or not.
bogdanm	92:4fc01daae5a5	73	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
bogdanm	92:4fc01daae5a5	74
bogdanm	92:4fc01daae5a5	75	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm	92:4fc01daae5a5	76	the corresponding memory device.
bogdanm	92:4fc01daae5a5	77	This parameter can be a value of @ref FMC_Memory_Type */
bogdanm	92:4fc01daae5a5	78
bogdanm	92:4fc01daae5a5	79	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm	92:4fc01daae5a5	80	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
bogdanm	92:4fc01daae5a5	81
bogdanm	92:4fc01daae5a5	82	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm	92:4fc01daae5a5	83	valid only with synchronous burst Flash memories.
bogdanm	92:4fc01daae5a5	84	This parameter can be a value of @ref FMC_Burst_Access_Mode */
bogdanm	92:4fc01daae5a5	85
bogdanm	92:4fc01daae5a5	86	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm	92:4fc01daae5a5	87	the Flash memory in burst mode.
bogdanm	92:4fc01daae5a5	88	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
bogdanm	92:4fc01daae5a5	89
bogdanm	92:4fc01daae5a5	90	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm	92:4fc01daae5a5	91	memory, valid only when accessing Flash memories in burst mode.
Kojto	99:dbbf35b96557	92	This parameter can be a value of @ref FMC_Wrap_Mode
Kojto	110:165afa46840b	93	This mode is not available for the STM32F446/467/479xx devices */
bogdanm	92:4fc01daae5a5	94
bogdanm	92:4fc01daae5a5	95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm	92:4fc01daae5a5	96	clock cycle before the wait state or during the wait state,
bogdanm	92:4fc01daae5a5	97	valid only when accessing memories in burst mode.
bogdanm	92:4fc01daae5a5	98	This parameter can be a value of @ref FMC_Wait_Timing */
bogdanm	92:4fc01daae5a5	99
bogdanm	92:4fc01daae5a5	100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
bogdanm	92:4fc01daae5a5	101	This parameter can be a value of @ref FMC_Write_Operation */
bogdanm	92:4fc01daae5a5	102
bogdanm	92:4fc01daae5a5	103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm	92:4fc01daae5a5	104	signal, valid for Flash memory access in burst mode.
bogdanm	92:4fc01daae5a5	105	This parameter can be a value of @ref FMC_Wait_Signal */
bogdanm	92:4fc01daae5a5	106
bogdanm	92:4fc01daae5a5	107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm	92:4fc01daae5a5	108	This parameter can be a value of @ref FMC_Extended_Mode */
bogdanm	92:4fc01daae5a5	109
bogdanm	92:4fc01daae5a5	110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm	92:4fc01daae5a5	111	valid only with asynchronous Flash memories.
bogdanm	92:4fc01daae5a5	112	This parameter can be a value of @ref FMC_AsynchronousWait */
bogdanm	92:4fc01daae5a5	113
bogdanm	92:4fc01daae5a5	114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm	92:4fc01daae5a5	115	This parameter can be a value of @ref FMC_Write_Burst */
bogdanm	92:4fc01daae5a5	116
bogdanm	92:4fc01daae5a5	117	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
bogdanm	92:4fc01daae5a5	118	This parameter is only enabled through the FMC_BCR1 register, and don't care
bogdanm	92:4fc01daae5a5	119	through FMC_BCR2..4 registers.
bogdanm	92:4fc01daae5a5	120	This parameter can be a value of @ref FMC_Continous_Clock */
bogdanm	92:4fc01daae5a5	121
Kojto	99:dbbf35b96557	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto	99:dbbf35b96557	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	99:dbbf35b96557	124	through FMC_BCR2..4 registers.
Kojto	99:dbbf35b96557	125	This parameter can be a value of @ref FMC_Write_FIFO
Kojto	110:165afa46840b	126	This mode is available only for the STM32F446/469/479xx devices */
Kojto	99:dbbf35b96557	127
Kojto	99:dbbf35b96557	128	uint32_t PageSize; /*!< Specifies the memory page size.
Kojto	99:dbbf35b96557	129	This parameter can be a value of @ref FMC_Page_Size
Kojto	99:dbbf35b96557	130	This mode is available only for the STM32F446xx devices */
Kojto	99:dbbf35b96557	131
bogdanm	92:4fc01daae5a5	132	}FMC_NORSRAM_InitTypeDef;
bogdanm	92:4fc01daae5a5	133
bogdanm	92:4fc01daae5a5	134	/**
Kojto	99:dbbf35b96557	135	* @brief FMC NORSRAM Timing parameters structure definition
bogdanm	92:4fc01daae5a5	136	*/
bogdanm	92:4fc01daae5a5	137	typedef struct
bogdanm	92:4fc01daae5a5	138	{
bogdanm	92:4fc01daae5a5	139	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	92:4fc01daae5a5	140	the duration of the address setup time.
bogdanm	92:4fc01daae5a5	141	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	142	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	92:4fc01daae5a5	143
bogdanm	92:4fc01daae5a5	144	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	92:4fc01daae5a5	145	the duration of the address hold time.
bogdanm	92:4fc01daae5a5	146	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	147	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	92:4fc01daae5a5	148
bogdanm	92:4fc01daae5a5	149	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	92:4fc01daae5a5	150	the duration of the data setup time.
bogdanm	92:4fc01daae5a5	151	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm	92:4fc01daae5a5	152	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm	92:4fc01daae5a5	153	NOR Flash memories. */
bogdanm	92:4fc01daae5a5	154
bogdanm	92:4fc01daae5a5	155	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm	92:4fc01daae5a5	156	the duration of the bus turnaround.
bogdanm	92:4fc01daae5a5	157	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	158	@note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm	92:4fc01daae5a5	159
bogdanm	92:4fc01daae5a5	160	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm	92:4fc01daae5a5	161	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm	92:4fc01daae5a5	162	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm	92:4fc01daae5a5	163	accesses. */
bogdanm	92:4fc01daae5a5	164
bogdanm	92:4fc01daae5a5	165	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm	92:4fc01daae5a5	166	to the memory before getting the first data.
bogdanm	92:4fc01daae5a5	167	The parameter value depends on the memory type as shown below:
bogdanm	92:4fc01daae5a5	168	- It must be set to 0 in case of a CRAM
bogdanm	92:4fc01daae5a5	169	- It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm	92:4fc01daae5a5	170	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm	92:4fc01daae5a5	171	with synchronous burst mode enable */
bogdanm	92:4fc01daae5a5	172
bogdanm	92:4fc01daae5a5	173	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm	92:4fc01daae5a5	174	This parameter can be a value of @ref FMC_Access_Mode */
bogdanm	92:4fc01daae5a5	175	}FMC_NORSRAM_TimingTypeDef;
bogdanm	92:4fc01daae5a5	176
bogdanm	92:4fc01daae5a5	177	/**
Kojto	99:dbbf35b96557	178	* @brief FMC NAND Configuration Structure definition
bogdanm	92:4fc01daae5a5	179	*/
bogdanm	92:4fc01daae5a5	180	typedef struct
bogdanm	92:4fc01daae5a5	181	{
bogdanm	92:4fc01daae5a5	182	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm	92:4fc01daae5a5	183	This parameter can be a value of @ref FMC_NAND_Bank */
bogdanm	92:4fc01daae5a5	184
bogdanm	92:4fc01daae5a5	185	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm	92:4fc01daae5a5	186	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	92:4fc01daae5a5	187
bogdanm	92:4fc01daae5a5	188	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm	92:4fc01daae5a5	189	This parameter can be any value of @ref FMC_NAND_Data_Width */
bogdanm	92:4fc01daae5a5	190
bogdanm	92:4fc01daae5a5	191	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm	92:4fc01daae5a5	192	This parameter can be any value of @ref FMC_ECC */
bogdanm	92:4fc01daae5a5	193
bogdanm	92:4fc01daae5a5	194	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm	92:4fc01daae5a5	195	This parameter can be any value of @ref FMC_ECC_Page_Size */
bogdanm	92:4fc01daae5a5	196
bogdanm	92:4fc01daae5a5	197	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	92:4fc01daae5a5	198	delay between CLE low and RE low.
bogdanm	92:4fc01daae5a5	199	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	200
bogdanm	92:4fc01daae5a5	201	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	92:4fc01daae5a5	202	delay between ALE low and RE low.
bogdanm	92:4fc01daae5a5	203	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	204	}FMC_NAND_InitTypeDef;
bogdanm	92:4fc01daae5a5	205
bogdanm	92:4fc01daae5a5	206	/**
Kojto	99:dbbf35b96557	207	* @brief FMC NAND/PCCARD Timing parameters structure definition
bogdanm	92:4fc01daae5a5	208	*/
bogdanm	92:4fc01daae5a5	209	typedef struct
bogdanm	92:4fc01daae5a5	210	{
bogdanm	92:4fc01daae5a5	211	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm	92:4fc01daae5a5	212	the command assertion for NAND-Flash read or write access
bogdanm	92:4fc01daae5a5	213	to common/Attribute or I/O memory space (depending on
bogdanm	92:4fc01daae5a5	214	the memory space timing to be configured).
bogdanm	92:4fc01daae5a5	215	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	216
bogdanm	92:4fc01daae5a5	217	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm	92:4fc01daae5a5	218	command for NAND-Flash read or write access to
bogdanm	92:4fc01daae5a5	219	common/Attribute or I/O memory space (depending on the
bogdanm	92:4fc01daae5a5	220	memory space timing to be configured).
bogdanm	92:4fc01daae5a5	221	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	222
bogdanm	92:4fc01daae5a5	223	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm	92:4fc01daae5a5	224	(and data for write access) after the command de-assertion
bogdanm	92:4fc01daae5a5	225	for NAND-Flash read or write access to common/Attribute
bogdanm	92:4fc01daae5a5	226	or I/O memory space (depending on the memory space timing
bogdanm	92:4fc01daae5a5	227	to be configured).
bogdanm	92:4fc01daae5a5	228	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	229
bogdanm	92:4fc01daae5a5	230	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm	92:4fc01daae5a5	231	data bus is kept in HiZ after the start of a NAND-Flash
bogdanm	92:4fc01daae5a5	232	write access to common/Attribute or I/O memory space (depending
bogdanm	92:4fc01daae5a5	233	on the memory space timing to be configured).
bogdanm	92:4fc01daae5a5	234	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	235	}FMC_NAND_PCC_TimingTypeDef;
bogdanm	92:4fc01daae5a5	236
bogdanm	92:4fc01daae5a5	237	/**
Kojto	99:dbbf35b96557	238	* @brief FMC NAND Configuration Structure definition
bogdanm	92:4fc01daae5a5	239	*/
bogdanm	92:4fc01daae5a5	240	typedef struct
bogdanm	92:4fc01daae5a5	241	{
bogdanm	92:4fc01daae5a5	242	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm	92:4fc01daae5a5	243	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	92:4fc01daae5a5	244
bogdanm	92:4fc01daae5a5	245	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	92:4fc01daae5a5	246	delay between CLE low and RE low.
bogdanm	92:4fc01daae5a5	247	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	248
bogdanm	92:4fc01daae5a5	249	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	92:4fc01daae5a5	250	delay between ALE low and RE low.
bogdanm	92:4fc01daae5a5	251	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	252	}FMC_PCCARD_InitTypeDef;
bogdanm	92:4fc01daae5a5	253
bogdanm	92:4fc01daae5a5	254	/**
Kojto	99:dbbf35b96557	255	* @brief FMC SDRAM Configuration Structure definition
bogdanm	92:4fc01daae5a5	256	*/
bogdanm	92:4fc01daae5a5	257	typedef struct
bogdanm	92:4fc01daae5a5	258	{
bogdanm	92:4fc01daae5a5	259	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
bogdanm	92:4fc01daae5a5	260	This parameter can be a value of @ref FMC_SDRAM_Bank */
bogdanm	92:4fc01daae5a5	261
bogdanm	92:4fc01daae5a5	262	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
bogdanm	92:4fc01daae5a5	263	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
bogdanm	92:4fc01daae5a5	264
bogdanm	92:4fc01daae5a5	265	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
bogdanm	92:4fc01daae5a5	266	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
bogdanm	92:4fc01daae5a5	267
bogdanm	92:4fc01daae5a5	268	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
bogdanm	92:4fc01daae5a5	269	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
bogdanm	92:4fc01daae5a5	270
bogdanm	92:4fc01daae5a5	271	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
bogdanm	92:4fc01daae5a5	272	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
bogdanm	92:4fc01daae5a5	273
bogdanm	92:4fc01daae5a5	274	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	275	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
bogdanm	92:4fc01daae5a5	276
bogdanm	92:4fc01daae5a5	277	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
bogdanm	92:4fc01daae5a5	278	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
bogdanm	92:4fc01daae5a5	279
bogdanm	92:4fc01daae5a5	280	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
bogdanm	92:4fc01daae5a5	281	to disable the clock before changing frequency.
bogdanm	92:4fc01daae5a5	282	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
bogdanm	92:4fc01daae5a5	283
bogdanm	92:4fc01daae5a5	284	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
bogdanm	92:4fc01daae5a5	285	commands during the CAS latency and stores data in the Read FIFO.
bogdanm	92:4fc01daae5a5	286	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
bogdanm	92:4fc01daae5a5	287
bogdanm	92:4fc01daae5a5	288	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
bogdanm	92:4fc01daae5a5	289	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
bogdanm	92:4fc01daae5a5	290	}FMC_SDRAM_InitTypeDef;
bogdanm	92:4fc01daae5a5	291
bogdanm	92:4fc01daae5a5	292	/**
Kojto	99:dbbf35b96557	293	* @brief FMC SDRAM Timing parameters structure definition
bogdanm	92:4fc01daae5a5	294	*/
bogdanm	92:4fc01daae5a5	295	typedef struct
bogdanm	92:4fc01daae5a5	296	{
bogdanm	92:4fc01daae5a5	297	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
bogdanm	92:4fc01daae5a5	298	an active or Refresh command in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	299	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	300
bogdanm	92:4fc01daae5a5	301	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
bogdanm	92:4fc01daae5a5	302	issuing the Activate command in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	303	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	304
bogdanm	92:4fc01daae5a5	305	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
bogdanm	92:4fc01daae5a5	306	cycles.
bogdanm	92:4fc01daae5a5	307	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	308
bogdanm	92:4fc01daae5a5	309	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
bogdanm	92:4fc01daae5a5	310	and the delay between two consecutive Refresh commands in number of
bogdanm	92:4fc01daae5a5	311	memory clock cycles.
bogdanm	92:4fc01daae5a5	312	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	313
bogdanm	92:4fc01daae5a5	314	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	315	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	316
bogdanm	92:4fc01daae5a5	317	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
bogdanm	92:4fc01daae5a5	318	in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	319	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	320
bogdanm	92:4fc01daae5a5	321	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
bogdanm	92:4fc01daae5a5	322	command in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	323	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	324	}FMC_SDRAM_TimingTypeDef;
bogdanm	92:4fc01daae5a5	325
bogdanm	92:4fc01daae5a5	326	/**
Kojto	99:dbbf35b96557	327	* @brief SDRAM command parameters structure definition
bogdanm	92:4fc01daae5a5	328	*/
bogdanm	92:4fc01daae5a5	329	typedef struct
bogdanm	92:4fc01daae5a5	330	{
bogdanm	92:4fc01daae5a5	331	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
bogdanm	92:4fc01daae5a5	332	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
bogdanm	92:4fc01daae5a5	333
bogdanm	92:4fc01daae5a5	334	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
bogdanm	92:4fc01daae5a5	335	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
bogdanm	92:4fc01daae5a5	336
bogdanm	92:4fc01daae5a5	337	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
bogdanm	92:4fc01daae5a5	338	in auto refresh mode.
bogdanm	92:4fc01daae5a5	339	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	340	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
bogdanm	92:4fc01daae5a5	341	}FMC_SDRAM_CommandTypeDef;
Kojto	99:dbbf35b96557	342	/**
Kojto	99:dbbf35b96557	343	* @}
Kojto	99:dbbf35b96557	344	*/
bogdanm	92:4fc01daae5a5	345
Kojto	99:dbbf35b96557	346	/* Private constants ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	347	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
bogdanm	92:4fc01daae5a5	348	* @{
bogdanm	92:4fc01daae5a5	349	*/
bogdanm	92:4fc01daae5a5	350
Kojto	99:dbbf35b96557	351	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
Kojto	99:dbbf35b96557	352	* @{
Kojto	99:dbbf35b96557	353	*/
Kojto	99:dbbf35b96557	354	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
bogdanm	92:4fc01daae5a5	355	* @{
bogdanm	92:4fc01daae5a5	356	*/
bogdanm	92:4fc01daae5a5	357	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	358	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	359	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	360	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
bogdanm	92:4fc01daae5a5	361	/**
bogdanm	92:4fc01daae5a5	362	* @}
bogdanm	92:4fc01daae5a5	363	*/
bogdanm	92:4fc01daae5a5	364
Kojto	99:dbbf35b96557	365	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
bogdanm	92:4fc01daae5a5	366	* @{
bogdanm	92:4fc01daae5a5	367	*/
bogdanm	92:4fc01daae5a5	368	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	369	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	370	/**
bogdanm	92:4fc01daae5a5	371	* @}
bogdanm	92:4fc01daae5a5	372	*/
bogdanm	92:4fc01daae5a5	373
Kojto	99:dbbf35b96557	374	/** @defgroup FMC_Memory_Type FMC Memory Type
bogdanm	92:4fc01daae5a5	375	* @{
bogdanm	92:4fc01daae5a5	376	*/
bogdanm	92:4fc01daae5a5	377	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	378	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	379	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	380	/**
bogdanm	92:4fc01daae5a5	381	* @}
bogdanm	92:4fc01daae5a5	382	*/
bogdanm	92:4fc01daae5a5	383
Kojto	99:dbbf35b96557	384	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
bogdanm	92:4fc01daae5a5	385	* @{
bogdanm	92:4fc01daae5a5	386	*/
bogdanm	92:4fc01daae5a5	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	388	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	389	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	390	/**
bogdanm	92:4fc01daae5a5	391	* @}
bogdanm	92:4fc01daae5a5	392	*/
bogdanm	92:4fc01daae5a5	393
Kojto	99:dbbf35b96557	394	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
bogdanm	92:4fc01daae5a5	395	* @{
bogdanm	92:4fc01daae5a5	396	*/
bogdanm	92:4fc01daae5a5	397	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	398	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	399	/**
bogdanm	92:4fc01daae5a5	400	* @}
bogdanm	92:4fc01daae5a5	401	*/
bogdanm	92:4fc01daae5a5	402
Kojto	99:dbbf35b96557	403	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
bogdanm	92:4fc01daae5a5	404	* @{
bogdanm	92:4fc01daae5a5	405	*/
bogdanm	92:4fc01daae5a5	406	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	407	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
bogdanm	92:4fc01daae5a5	408	/**
bogdanm	92:4fc01daae5a5	409	* @}
bogdanm	92:4fc01daae5a5	410	*/
bogdanm	92:4fc01daae5a5	411
Kojto	99:dbbf35b96557	412	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
bogdanm	92:4fc01daae5a5	413	* @{
bogdanm	92:4fc01daae5a5	414	*/
bogdanm	92:4fc01daae5a5	415	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	416	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
bogdanm	92:4fc01daae5a5	417	/**
bogdanm	92:4fc01daae5a5	418	* @}
bogdanm	92:4fc01daae5a5	419	*/
bogdanm	92:4fc01daae5a5	420
Kojto	99:dbbf35b96557	421	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
bogdanm	92:4fc01daae5a5	422	* @{
bogdanm	92:4fc01daae5a5	423	*/
Kojto	110:165afa46840b	424	/** @note This mode is not available for the STM32F446/469/479xx devices
Kojto	99:dbbf35b96557	425	*/
Kojto	99:dbbf35b96557	426	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	427	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
bogdanm	92:4fc01daae5a5	428	/**
bogdanm	92:4fc01daae5a5	429	* @}
bogdanm	92:4fc01daae5a5	430	*/
bogdanm	92:4fc01daae5a5	431
Kojto	99:dbbf35b96557	432	/** @defgroup FMC_Wait_Timing FMC Wait Timing
Kojto	99:dbbf35b96557	433	* @{
Kojto	99:dbbf35b96557	434	*/
Kojto	99:dbbf35b96557	435	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	436	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
Kojto	99:dbbf35b96557	437	/**
Kojto	99:dbbf35b96557	438	* @}
Kojto	99:dbbf35b96557	439	*/
Kojto	99:dbbf35b96557	440
Kojto	99:dbbf35b96557	441	/** @defgroup FMC_Write_Operation FMC Write Operation
bogdanm	92:4fc01daae5a5	442	* @{
bogdanm	92:4fc01daae5a5	443	*/
bogdanm	92:4fc01daae5a5	444	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	445	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
bogdanm	92:4fc01daae5a5	446	/**
bogdanm	92:4fc01daae5a5	447	* @}
bogdanm	92:4fc01daae5a5	448	*/
bogdanm	92:4fc01daae5a5	449
Kojto	99:dbbf35b96557	450	/** @defgroup FMC_Wait_Signal FMC Wait Signal
bogdanm	92:4fc01daae5a5	451	* @{
bogdanm	92:4fc01daae5a5	452	*/
bogdanm	92:4fc01daae5a5	453	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	454	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
bogdanm	92:4fc01daae5a5	455	/**
bogdanm	92:4fc01daae5a5	456	* @}
bogdanm	92:4fc01daae5a5	457	*/
bogdanm	92:4fc01daae5a5	458
Kojto	99:dbbf35b96557	459	/** @defgroup FMC_Extended_Mode FMC Extended Mode
Kojto	99:dbbf35b96557	460	* @{
Kojto	99:dbbf35b96557	461	*/
Kojto	99:dbbf35b96557	462	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	463	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
Kojto	99:dbbf35b96557	464	/**
Kojto	99:dbbf35b96557	465	* @}
Kojto	99:dbbf35b96557	466	*/
Kojto	99:dbbf35b96557	467
Kojto	99:dbbf35b96557	468	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
bogdanm	92:4fc01daae5a5	469	* @{
bogdanm	92:4fc01daae5a5	470	*/
bogdanm	92:4fc01daae5a5	471	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	472	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
bogdanm	92:4fc01daae5a5	473	/**
bogdanm	92:4fc01daae5a5	474	* @}
bogdanm	92:4fc01daae5a5	475	*/
bogdanm	92:4fc01daae5a5	476
Kojto	99:dbbf35b96557	477	/** @defgroup FMC_Page_Size FMC Page Size
Kojto	110:165afa46840b	478	* @note These values are available only for the STM32F446/469/479xx devices.
Kojto	99:dbbf35b96557	479	* @{
Kojto	99:dbbf35b96557	480	*/
Kojto	99:dbbf35b96557	481	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	482	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
Kojto	99:dbbf35b96557	483	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
Kojto	99:dbbf35b96557	484	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
Kojto	99:dbbf35b96557	485	/**
Kojto	99:dbbf35b96557	486	* @}
Kojto	99:dbbf35b96557	487	*/
Kojto	99:dbbf35b96557	488
Kojto	99:dbbf35b96557	489	/** @defgroup FMC_Write_FIFO FMC Write FIFO
Kojto	110:165afa46840b	490	* @note These values are available only for the STM32F446/469/479xx devices.
Kojto	99:dbbf35b96557	491	* @{
Kojto	99:dbbf35b96557	492	*/
Kojto	99:dbbf35b96557	493	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	494	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
Kojto	99:dbbf35b96557	495	/**
Kojto	99:dbbf35b96557	496	* @}
Kojto	99:dbbf35b96557	497	*/
Kojto	99:dbbf35b96557	498
Kojto	99:dbbf35b96557	499	/** @defgroup FMC_Write_Burst FMC Write Burst
bogdanm	92:4fc01daae5a5	500	* @{
bogdanm	92:4fc01daae5a5	501	*/
bogdanm	92:4fc01daae5a5	502	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	503	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
bogdanm	92:4fc01daae5a5	504	/**
bogdanm	92:4fc01daae5a5	505	* @}
bogdanm	92:4fc01daae5a5	506	*/
bogdanm	92:4fc01daae5a5	507
Kojto	99:dbbf35b96557	508	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
bogdanm	92:4fc01daae5a5	509	* @{
bogdanm	92:4fc01daae5a5	510	*/
Kojto	99:dbbf35b96557	511	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	512	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
bogdanm	92:4fc01daae5a5	513	/**
bogdanm	92:4fc01daae5a5	514	* @}
bogdanm	92:4fc01daae5a5	515	*/
Kojto	99:dbbf35b96557	516
Kojto	99:dbbf35b96557	517	/** @defgroup FMC_Access_Mode FMC Access Mode
bogdanm	92:4fc01daae5a5	518	* @{
bogdanm	92:4fc01daae5a5	519	*/
bogdanm	92:4fc01daae5a5	520	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	521	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
bogdanm	92:4fc01daae5a5	522	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
bogdanm	92:4fc01daae5a5	523	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
bogdanm	92:4fc01daae5a5	524	/**
bogdanm	92:4fc01daae5a5	525	* @}
bogdanm	92:4fc01daae5a5	526	*/
bogdanm	92:4fc01daae5a5	527
bogdanm	92:4fc01daae5a5	528	/**
bogdanm	92:4fc01daae5a5	529	* @}
Kojto	99:dbbf35b96557	530	*/
bogdanm	92:4fc01daae5a5	531
Kojto	99:dbbf35b96557	532	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
bogdanm	92:4fc01daae5a5	533	* @{
bogdanm	92:4fc01daae5a5	534	*/
Kojto	99:dbbf35b96557	535	/** @defgroup FMC_NAND_Bank FMC NAND Bank
bogdanm	92:4fc01daae5a5	536	* @{
Kojto	99:dbbf35b96557	537	*/
bogdanm	92:4fc01daae5a5	538	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
Kojto	99:dbbf35b96557	539	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
bogdanm	92:4fc01daae5a5	540	/**
bogdanm	92:4fc01daae5a5	541	* @}
bogdanm	92:4fc01daae5a5	542	*/
bogdanm	92:4fc01daae5a5	543
Kojto	99:dbbf35b96557	544	/** @defgroup FMC_Wait_feature FMC Wait feature
bogdanm	92:4fc01daae5a5	545	* @{
bogdanm	92:4fc01daae5a5	546	*/
bogdanm	92:4fc01daae5a5	547	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	548	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	549	/**
bogdanm	92:4fc01daae5a5	550	* @}
bogdanm	92:4fc01daae5a5	551	*/
bogdanm	92:4fc01daae5a5	552
Kojto	99:dbbf35b96557	553	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
bogdanm	92:4fc01daae5a5	554	* @{
bogdanm	92:4fc01daae5a5	555	*/
bogdanm	92:4fc01daae5a5	556	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	557	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	558	/**
bogdanm	92:4fc01daae5a5	559	* @}
bogdanm	92:4fc01daae5a5	560	*/
bogdanm	92:4fc01daae5a5	561
Kojto	99:dbbf35b96557	562	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
bogdanm	92:4fc01daae5a5	563	* @{
bogdanm	92:4fc01daae5a5	564	*/
bogdanm	92:4fc01daae5a5	565	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	566	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	567	/**
bogdanm	92:4fc01daae5a5	568	* @}
bogdanm	92:4fc01daae5a5	569	*/
bogdanm	92:4fc01daae5a5	570
Kojto	99:dbbf35b96557	571	/** @defgroup FMC_ECC FMC ECC
bogdanm	92:4fc01daae5a5	572	* @{
bogdanm	92:4fc01daae5a5	573	*/
bogdanm	92:4fc01daae5a5	574	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	575	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	576	/**
bogdanm	92:4fc01daae5a5	577	* @}
bogdanm	92:4fc01daae5a5	578	*/
bogdanm	92:4fc01daae5a5	579
Kojto	99:dbbf35b96557	580	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
bogdanm	92:4fc01daae5a5	581	* @{
bogdanm	92:4fc01daae5a5	582	*/
bogdanm	92:4fc01daae5a5	583	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	584	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
bogdanm	92:4fc01daae5a5	585	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
bogdanm	92:4fc01daae5a5	586	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
bogdanm	92:4fc01daae5a5	587	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
bogdanm	92:4fc01daae5a5	588	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
bogdanm	92:4fc01daae5a5	589	/**
bogdanm	92:4fc01daae5a5	590	* @}
bogdanm	92:4fc01daae5a5	591	*/
Kojto	99:dbbf35b96557	592
bogdanm	92:4fc01daae5a5	593	/**
bogdanm	92:4fc01daae5a5	594	* @}
Kojto	99:dbbf35b96557	595	*/
bogdanm	92:4fc01daae5a5	596
Kojto	99:dbbf35b96557	597	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
bogdanm	92:4fc01daae5a5	598	* @{
bogdanm	92:4fc01daae5a5	599	*/
Kojto	99:dbbf35b96557	600	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
bogdanm	92:4fc01daae5a5	601	* @{
bogdanm	92:4fc01daae5a5	602	*/
Kojto	99:dbbf35b96557	603	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	604	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	605	/**
bogdanm	92:4fc01daae5a5	606	* @}
bogdanm	92:4fc01daae5a5	607	*/
bogdanm	92:4fc01daae5a5	608
Kojto	99:dbbf35b96557	609	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
bogdanm	92:4fc01daae5a5	610	* @{
bogdanm	92:4fc01daae5a5	611	*/
bogdanm	92:4fc01daae5a5	612	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	613	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	614	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	615	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
bogdanm	92:4fc01daae5a5	616	/**
bogdanm	92:4fc01daae5a5	617	* @}
bogdanm	92:4fc01daae5a5	618	*/
bogdanm	92:4fc01daae5a5	619
Kojto	99:dbbf35b96557	620	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
bogdanm	92:4fc01daae5a5	621	* @{
bogdanm	92:4fc01daae5a5	622	*/
bogdanm	92:4fc01daae5a5	623	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	624	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	625	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	626	/**
bogdanm	92:4fc01daae5a5	627	* @}
bogdanm	92:4fc01daae5a5	628	*/
bogdanm	92:4fc01daae5a5	629
Kojto	99:dbbf35b96557	630	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
bogdanm	92:4fc01daae5a5	631	* @{
bogdanm	92:4fc01daae5a5	632	*/
bogdanm	92:4fc01daae5a5	633	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	634	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	635	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	636	/**
bogdanm	92:4fc01daae5a5	637	* @}
bogdanm	92:4fc01daae5a5	638	*/
bogdanm	92:4fc01daae5a5	639
Kojto	99:dbbf35b96557	640	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
bogdanm	92:4fc01daae5a5	641	* @{
bogdanm	92:4fc01daae5a5	642	*/
bogdanm	92:4fc01daae5a5	643	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	644	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	645	/**
bogdanm	92:4fc01daae5a5	646	* @}
bogdanm	92:4fc01daae5a5	647	*/
bogdanm	92:4fc01daae5a5	648
Kojto	99:dbbf35b96557	649	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
bogdanm	92:4fc01daae5a5	650	* @{
bogdanm	92:4fc01daae5a5	651	*/
bogdanm	92:4fc01daae5a5	652	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
bogdanm	92:4fc01daae5a5	653	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
bogdanm	92:4fc01daae5a5	654	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
bogdanm	92:4fc01daae5a5	655	/**
bogdanm	92:4fc01daae5a5	656	* @}
bogdanm	92:4fc01daae5a5	657	*/
bogdanm	92:4fc01daae5a5	658
Kojto	99:dbbf35b96557	659	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
bogdanm	92:4fc01daae5a5	660	* @{
bogdanm	92:4fc01daae5a5	661	*/
bogdanm	92:4fc01daae5a5	662	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	663	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
bogdanm	92:4fc01daae5a5	664
bogdanm	92:4fc01daae5a5	665	/**
bogdanm	92:4fc01daae5a5	666	* @}
bogdanm	92:4fc01daae5a5	667	*/
bogdanm	92:4fc01daae5a5	668
Kojto	99:dbbf35b96557	669	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
bogdanm	92:4fc01daae5a5	670	* @{
bogdanm	92:4fc01daae5a5	671	*/
bogdanm	92:4fc01daae5a5	672	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	673	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
bogdanm	92:4fc01daae5a5	674	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
bogdanm	92:4fc01daae5a5	675	/**
bogdanm	92:4fc01daae5a5	676	* @}
bogdanm	92:4fc01daae5a5	677	*/
bogdanm	92:4fc01daae5a5	678
Kojto	99:dbbf35b96557	679	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
bogdanm	92:4fc01daae5a5	680	* @{
bogdanm	92:4fc01daae5a5	681	*/
bogdanm	92:4fc01daae5a5	682	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	683	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
bogdanm	92:4fc01daae5a5	684	/**
bogdanm	92:4fc01daae5a5	685	* @}
bogdanm	92:4fc01daae5a5	686	*/
bogdanm	92:4fc01daae5a5	687
Kojto	99:dbbf35b96557	688	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
bogdanm	92:4fc01daae5a5	689	* @{
bogdanm	92:4fc01daae5a5	690	*/
bogdanm	92:4fc01daae5a5	691	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	692	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
bogdanm	92:4fc01daae5a5	693	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
bogdanm	92:4fc01daae5a5	694	/**
bogdanm	92:4fc01daae5a5	695	* @}
bogdanm	92:4fc01daae5a5	696	*/
bogdanm	92:4fc01daae5a5	697
Kojto	99:dbbf35b96557	698	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
bogdanm	92:4fc01daae5a5	699	* @{
bogdanm	92:4fc01daae5a5	700	*/
bogdanm	92:4fc01daae5a5	701	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	702	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	703	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	704	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
bogdanm	92:4fc01daae5a5	705	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	706	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
bogdanm	92:4fc01daae5a5	707	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
bogdanm	92:4fc01daae5a5	708	/**
bogdanm	92:4fc01daae5a5	709	* @}
bogdanm	92:4fc01daae5a5	710	*/
bogdanm	92:4fc01daae5a5	711
Kojto	99:dbbf35b96557	712	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
bogdanm	92:4fc01daae5a5	713	* @{
bogdanm	92:4fc01daae5a5	714	*/
bogdanm	92:4fc01daae5a5	715	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
bogdanm	92:4fc01daae5a5	716	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
bogdanm	92:4fc01daae5a5	717	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
bogdanm	92:4fc01daae5a5	718	/**
bogdanm	92:4fc01daae5a5	719	* @}
bogdanm	92:4fc01daae5a5	720	*/
bogdanm	92:4fc01daae5a5	721
Kojto	99:dbbf35b96557	722	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
bogdanm	92:4fc01daae5a5	723	* @{
bogdanm	92:4fc01daae5a5	724	*/
bogdanm	92:4fc01daae5a5	725	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	726	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
bogdanm	92:4fc01daae5a5	727	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
bogdanm	92:4fc01daae5a5	728	/**
bogdanm	92:4fc01daae5a5	729	* @}
bogdanm	92:4fc01daae5a5	730	*/
Kojto	99:dbbf35b96557	731
bogdanm	92:4fc01daae5a5	732	/**
bogdanm	92:4fc01daae5a5	733	* @}
bogdanm	92:4fc01daae5a5	734	*/
bogdanm	92:4fc01daae5a5	735
Kojto	99:dbbf35b96557	736	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
bogdanm	92:4fc01daae5a5	737	* @{
bogdanm	92:4fc01daae5a5	738	*/
bogdanm	92:4fc01daae5a5	739	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	740	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	741	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	742	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
bogdanm	92:4fc01daae5a5	743	/**
bogdanm	92:4fc01daae5a5	744	* @}
bogdanm	92:4fc01daae5a5	745	*/
bogdanm	92:4fc01daae5a5	746
Kojto	99:dbbf35b96557	747	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
bogdanm	92:4fc01daae5a5	748	* @{
bogdanm	92:4fc01daae5a5	749	*/
bogdanm	92:4fc01daae5a5	750	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	751	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	752	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	753	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	754	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
bogdanm	92:4fc01daae5a5	755	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
bogdanm	92:4fc01daae5a5	756	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
bogdanm	92:4fc01daae5a5	757	/**
bogdanm	92:4fc01daae5a5	758	* @}
bogdanm	92:4fc01daae5a5	759	*/
bogdanm	92:4fc01daae5a5	760
Kojto	99:dbbf35b96557	761	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
Kojto	99:dbbf35b96557	762	* @{
Kojto	99:dbbf35b96557	763	*/
Kojto	110:165afa46840b	764	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	765	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
Kojto	99:dbbf35b96557	766	#else
Kojto	99:dbbf35b96557	767	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
Kojto	99:dbbf35b96557	768	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
Kojto	110:165afa46840b	769	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	770	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
Kojto	99:dbbf35b96557	771	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
Kojto	99:dbbf35b96557	772	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
Kojto	99:dbbf35b96557	773
bogdanm	92:4fc01daae5a5	774
Kojto	110:165afa46840b	775	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	776	#define FMC_NAND_DEVICE FMC_Bank3
Kojto	99:dbbf35b96557	777	#else
Kojto	99:dbbf35b96557	778	#define FMC_NAND_DEVICE FMC_Bank2_3
Kojto	99:dbbf35b96557	779	#define FMC_PCCARD_DEVICE FMC_Bank4
Kojto	110:165afa46840b	780	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	781	#define FMC_NORSRAM_DEVICE FMC_Bank1
Kojto	99:dbbf35b96557	782	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
Kojto	99:dbbf35b96557	783	#define FMC_SDRAM_DEVICE FMC_Bank5_6
Kojto	99:dbbf35b96557	784	/**
Kojto	99:dbbf35b96557	785	* @}
Kojto	99:dbbf35b96557	786	*/
Kojto	99:dbbf35b96557	787
Kojto	99:dbbf35b96557	788	/**
Kojto	99:dbbf35b96557	789	* @}
Kojto	99:dbbf35b96557	790	*/
Kojto	99:dbbf35b96557	791
Kojto	99:dbbf35b96557	792	/* Private macro -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	793	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
Kojto	99:dbbf35b96557	794	* @{
Kojto	99:dbbf35b96557	795	*/
Kojto	99:dbbf35b96557	796
Kojto	99:dbbf35b96557	797	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
bogdanm	92:4fc01daae5a5	798	* @brief macros to handle NOR device enable/disable and read/write operations
bogdanm	92:4fc01daae5a5	799	* @{
bogdanm	92:4fc01daae5a5	800	*/
bogdanm	92:4fc01daae5a5	801	/**
bogdanm	92:4fc01daae5a5	802	* @brief Enable the NORSRAM device access.
bogdanm	92:4fc01daae5a5	803	* @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm	92:4fc01daae5a5	804	* @param __BANK__: FMC_NORSRAM Bank
bogdanm	92:4fc01daae5a5	805	* @retval None
bogdanm	92:4fc01daae5a5	806	*/
bogdanm	92:4fc01daae5a5	807	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
bogdanm	92:4fc01daae5a5	808
bogdanm	92:4fc01daae5a5	809	/**
bogdanm	92:4fc01daae5a5	810	* @brief Disable the NORSRAM device access.
bogdanm	92:4fc01daae5a5	811	* @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm	92:4fc01daae5a5	812	* @param __BANK__: FMC_NORSRAM Bank
bogdanm	92:4fc01daae5a5	813	* @retval None
bogdanm	92:4fc01daae5a5	814	*/
bogdanm	92:4fc01daae5a5	815	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
bogdanm	92:4fc01daae5a5	816	/**
bogdanm	92:4fc01daae5a5	817	* @}
bogdanm	92:4fc01daae5a5	818	*/
bogdanm	92:4fc01daae5a5	819
Kojto	99:dbbf35b96557	820	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
bogdanm	92:4fc01daae5a5	821	* @brief macros to handle NAND device enable/disable
bogdanm	92:4fc01daae5a5	822	* @{
bogdanm	92:4fc01daae5a5	823	*/
Kojto	110:165afa46840b	824	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	825	/**
Kojto	99:dbbf35b96557	826	* @brief Enable the NAND device access.
Kojto	99:dbbf35b96557	827	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	828	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	829	* @retval None
Kojto	99:dbbf35b96557	830	*/
Kojto	99:dbbf35b96557	831	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
Kojto	99:dbbf35b96557	832
Kojto	99:dbbf35b96557	833	/**
Kojto	99:dbbf35b96557	834	* @brief Disable the NAND device access.
Kojto	99:dbbf35b96557	835	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	836	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	837	* @retval None
Kojto	99:dbbf35b96557	838	*/
Kojto	99:dbbf35b96557	839	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
Kojto	99:dbbf35b96557	840	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
bogdanm	92:4fc01daae5a5	841	/**
bogdanm	92:4fc01daae5a5	842	* @brief Enable the NAND device access.
bogdanm	92:4fc01daae5a5	843	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	92:4fc01daae5a5	844	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	845	* @retval None
bogdanm	92:4fc01daae5a5	846	*/
bogdanm	92:4fc01daae5a5	847	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
bogdanm	92:4fc01daae5a5	848	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
bogdanm	92:4fc01daae5a5	849
bogdanm	92:4fc01daae5a5	850	/**
bogdanm	92:4fc01daae5a5	851	* @brief Disable the NAND device access.
bogdanm	92:4fc01daae5a5	852	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	92:4fc01daae5a5	853	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	854	* @retval None
bogdanm	92:4fc01daae5a5	855	*/
bogdanm	92:4fc01daae5a5	856	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
bogdanm	92:4fc01daae5a5	857	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
Kojto	99:dbbf35b96557	858
Kojto	110:165afa46840b	859	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
bogdanm	92:4fc01daae5a5	860	/**
bogdanm	92:4fc01daae5a5	861	* @}
bogdanm	92:4fc01daae5a5	862	*/
Kojto	99:dbbf35b96557	863	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	864	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
bogdanm	92:4fc01daae5a5	865	* @brief macros to handle SRAM read/write operations
bogdanm	92:4fc01daae5a5	866	* @{
bogdanm	92:4fc01daae5a5	867	*/
bogdanm	92:4fc01daae5a5	868	/**
bogdanm	92:4fc01daae5a5	869	* @brief Enable the PCCARD device access.
bogdanm	92:4fc01daae5a5	870	* @param __INSTANCE__: FMC_PCCARD Instance
bogdanm	92:4fc01daae5a5	871	* @retval None
bogdanm	92:4fc01daae5a5	872	*/
bogdanm	92:4fc01daae5a5	873	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
bogdanm	92:4fc01daae5a5	874
bogdanm	92:4fc01daae5a5	875	/**
bogdanm	92:4fc01daae5a5	876	* @brief Disable the PCCARD device access.
bogdanm	92:4fc01daae5a5	877	* @param __INSTANCE__: FMC_PCCARD Instance
bogdanm	92:4fc01daae5a5	878	* @retval None
bogdanm	92:4fc01daae5a5	879	*/
bogdanm	92:4fc01daae5a5	880	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
bogdanm	92:4fc01daae5a5	881	/**
bogdanm	92:4fc01daae5a5	882	* @}
bogdanm	92:4fc01daae5a5	883	*/
Kojto	99:dbbf35b96557	884	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	99:dbbf35b96557	885
Kojto	99:dbbf35b96557	886	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
Kojto	99:dbbf35b96557	887	* @brief macros to handle FMC flags and interrupts
bogdanm	92:4fc01daae5a5	888	* @{
bogdanm	92:4fc01daae5a5	889	*/
Kojto	110:165afa46840b	890	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	891	/**
Kojto	99:dbbf35b96557	892	* @brief Enable the NAND device interrupt.
Kojto	99:dbbf35b96557	893	* @param __INSTANCE__: FMC_NAND instance
Kojto	99:dbbf35b96557	894	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	895	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	99:dbbf35b96557	896	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	897	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	99:dbbf35b96557	898	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	99:dbbf35b96557	899	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	99:dbbf35b96557	900	* @retval None
Kojto	99:dbbf35b96557	901	*/
Kojto	99:dbbf35b96557	902	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	903
bogdanm	92:4fc01daae5a5	904	/**
Kojto	99:dbbf35b96557	905	* @brief Disable the NAND device interrupt.
Kojto	99:dbbf35b96557	906	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	907	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	908	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	99:dbbf35b96557	909	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	910	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	99:dbbf35b96557	911	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	99:dbbf35b96557	912	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	99:dbbf35b96557	913	* @retval None
Kojto	99:dbbf35b96557	914	*/
Kojto	99:dbbf35b96557	915	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
Kojto	99:dbbf35b96557	916
Kojto	99:dbbf35b96557	917	/**
Kojto	99:dbbf35b96557	918	* @brief Get flag status of the NAND device.
Kojto	99:dbbf35b96557	919	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	920	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	921	* @param __FLAG__: FMC_NAND flag
Kojto	99:dbbf35b96557	922	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	923	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	99:dbbf35b96557	924	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	99:dbbf35b96557	925	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	99:dbbf35b96557	926	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	99:dbbf35b96557	927	* @retval The state of FLAG (SET or RESET).
Kojto	99:dbbf35b96557	928	*/
Kojto	99:dbbf35b96557	929	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
Kojto	99:dbbf35b96557	930	/**
Kojto	99:dbbf35b96557	931	* @brief Clear flag status of the NAND device.
Kojto	99:dbbf35b96557	932	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	933	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	934	* @param __FLAG__: FMC_NAND flag
Kojto	99:dbbf35b96557	935	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	936	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	99:dbbf35b96557	937	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	99:dbbf35b96557	938	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	99:dbbf35b96557	939	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	99:dbbf35b96557	940	* @retval None
Kojto	99:dbbf35b96557	941	*/
Kojto	99:dbbf35b96557	942	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
Kojto	99:dbbf35b96557	943	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	99:dbbf35b96557	944	/**
bogdanm	92:4fc01daae5a5	945	* @brief Enable the NAND device interrupt.
bogdanm	92:4fc01daae5a5	946	* @param __INSTANCE__: FMC_NAND instance
bogdanm	92:4fc01daae5a5	947	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	948	* @param __INTERRUPT__: FMC_NAND interrupt
bogdanm	92:4fc01daae5a5	949	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	950	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	92:4fc01daae5a5	951	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	92:4fc01daae5a5	952	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	92:4fc01daae5a5	953	* @retval None
bogdanm	92:4fc01daae5a5	954	*/
bogdanm	92:4fc01daae5a5	955	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
bogdanm	92:4fc01daae5a5	956	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
bogdanm	92:4fc01daae5a5	957
bogdanm	92:4fc01daae5a5	958	/**
bogdanm	92:4fc01daae5a5	959	* @brief Disable the NAND device interrupt.
Kojto	99:dbbf35b96557	960	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	92:4fc01daae5a5	961	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	962	* @param __INTERRUPT__: FMC_NAND interrupt
bogdanm	92:4fc01daae5a5	963	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	964	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	92:4fc01daae5a5	965	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	92:4fc01daae5a5	966	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	92:4fc01daae5a5	967	* @retval None
bogdanm	92:4fc01daae5a5	968	*/
bogdanm	92:4fc01daae5a5	969	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
bogdanm	92:4fc01daae5a5	970	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
bogdanm	92:4fc01daae5a5	971
bogdanm	92:4fc01daae5a5	972	/**
bogdanm	92:4fc01daae5a5	973	* @brief Get flag status of the NAND device.
Kojto	99:dbbf35b96557	974	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	92:4fc01daae5a5	975	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	976	* @param __FLAG__: FMC_NAND flag
bogdanm	92:4fc01daae5a5	977	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	978	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	92:4fc01daae5a5	979	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	92:4fc01daae5a5	980	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	92:4fc01daae5a5	981	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	92:4fc01daae5a5	982	* @retval The state of FLAG (SET or RESET).
bogdanm	92:4fc01daae5a5	983	*/
bogdanm	92:4fc01daae5a5	984	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
bogdanm	92:4fc01daae5a5	985	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
bogdanm	92:4fc01daae5a5	986	/**
bogdanm	92:4fc01daae5a5	987	* @brief Clear flag status of the NAND device.
Kojto	99:dbbf35b96557	988	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	92:4fc01daae5a5	989	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	990	* @param __FLAG__: FMC_NAND flag
bogdanm	92:4fc01daae5a5	991	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	992	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	92:4fc01daae5a5	993	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	92:4fc01daae5a5	994	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	92:4fc01daae5a5	995	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	92:4fc01daae5a5	996	* @retval None
bogdanm	92:4fc01daae5a5	997	*/
bogdanm	92:4fc01daae5a5	998	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto	99:dbbf35b96557	999	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto	110:165afa46840b	1000	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
Kojto	99:dbbf35b96557	1001
Kojto	99:dbbf35b96557	1002	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	1003	/**
bogdanm	92:4fc01daae5a5	1004	* @brief Enable the PCCARD device interrupt.
bogdanm	92:4fc01daae5a5	1005	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	92:4fc01daae5a5	1006	* @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm	92:4fc01daae5a5	1007	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1008	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	92:4fc01daae5a5	1009	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	92:4fc01daae5a5	1010	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	92:4fc01daae5a5	1011	* @retval None
bogdanm	92:4fc01daae5a5	1012	*/
bogdanm	92:4fc01daae5a5	1013	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1014
bogdanm	92:4fc01daae5a5	1015	/**
bogdanm	92:4fc01daae5a5	1016	* @brief Disable the PCCARD device interrupt.
bogdanm	92:4fc01daae5a5	1017	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	92:4fc01daae5a5	1018	* @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm	92:4fc01daae5a5	1019	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1020	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	92:4fc01daae5a5	1021	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	92:4fc01daae5a5	1022	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	92:4fc01daae5a5	1023	* @retval None
bogdanm	92:4fc01daae5a5	1024	*/
bogdanm	92:4fc01daae5a5	1025	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1026
bogdanm	92:4fc01daae5a5	1027	/**
bogdanm	92:4fc01daae5a5	1028	* @brief Get flag status of the PCCARD device.
bogdanm	92:4fc01daae5a5	1029	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	92:4fc01daae5a5	1030	* @param __FLAG__: FMC_PCCARD flag
bogdanm	92:4fc01daae5a5	1031	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1032	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	92:4fc01daae5a5	1033	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	92:4fc01daae5a5	1034	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	92:4fc01daae5a5	1035	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	92:4fc01daae5a5	1036	* @retval The state of FLAG (SET or RESET).
bogdanm	92:4fc01daae5a5	1037	*/
bogdanm	92:4fc01daae5a5	1038	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
bogdanm	92:4fc01daae5a5	1039
bogdanm	92:4fc01daae5a5	1040	/**
bogdanm	92:4fc01daae5a5	1041	* @brief Clear flag status of the PCCARD device.
bogdanm	92:4fc01daae5a5	1042	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	92:4fc01daae5a5	1043	* @param __FLAG__: FMC_PCCARD flag
bogdanm	92:4fc01daae5a5	1044	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1045	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	92:4fc01daae5a5	1046	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	92:4fc01daae5a5	1047	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	92:4fc01daae5a5	1048	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	92:4fc01daae5a5	1049	* @retval None
bogdanm	92:4fc01daae5a5	1050	*/
bogdanm	92:4fc01daae5a5	1051	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto	99:dbbf35b96557	1052	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	99:dbbf35b96557	1053
bogdanm	92:4fc01daae5a5	1054	/**
bogdanm	92:4fc01daae5a5	1055	* @brief Enable the SDRAM device interrupt.
bogdanm	92:4fc01daae5a5	1056	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	92:4fc01daae5a5	1057	* @param __INTERRUPT__: FMC_SDRAM interrupt
bogdanm	92:4fc01daae5a5	1058	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1059	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
bogdanm	92:4fc01daae5a5	1060	* @retval None
bogdanm	92:4fc01daae5a5	1061	*/
bogdanm	92:4fc01daae5a5	1062	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1063
bogdanm	92:4fc01daae5a5	1064	/**
bogdanm	92:4fc01daae5a5	1065	* @brief Disable the SDRAM device interrupt.
bogdanm	92:4fc01daae5a5	1066	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	92:4fc01daae5a5	1067	* @param __INTERRUPT__: FMC_SDRAM interrupt
bogdanm	92:4fc01daae5a5	1068	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1069	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
bogdanm	92:4fc01daae5a5	1070	* @retval None
bogdanm	92:4fc01daae5a5	1071	*/
bogdanm	92:4fc01daae5a5	1072	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1073
bogdanm	92:4fc01daae5a5	1074	/**
bogdanm	92:4fc01daae5a5	1075	* @brief Get flag status of the SDRAM device.
bogdanm	92:4fc01daae5a5	1076	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	92:4fc01daae5a5	1077	* @param __FLAG__: FMC_SDRAM flag
bogdanm	92:4fc01daae5a5	1078	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1079	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
bogdanm	92:4fc01daae5a5	1080	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
bogdanm	92:4fc01daae5a5	1081	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
bogdanm	92:4fc01daae5a5	1082	* @retval The state of FLAG (SET or RESET).
bogdanm	92:4fc01daae5a5	1083	*/
bogdanm	92:4fc01daae5a5	1084	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
bogdanm	92:4fc01daae5a5	1085
bogdanm	92:4fc01daae5a5	1086	/**
bogdanm	92:4fc01daae5a5	1087	* @brief Clear flag status of the SDRAM device.
bogdanm	92:4fc01daae5a5	1088	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	92:4fc01daae5a5	1089	* @param __FLAG__: FMC_SDRAM flag
bogdanm	92:4fc01daae5a5	1090	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1091	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
bogdanm	92:4fc01daae5a5	1092	* @retval None
bogdanm	92:4fc01daae5a5	1093	*/
bogdanm	92:4fc01daae5a5	1094	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
bogdanm	92:4fc01daae5a5	1095	/**
bogdanm	92:4fc01daae5a5	1096	* @}
Kojto	99:dbbf35b96557	1097	*/
Kojto	99:dbbf35b96557	1098
Kojto	99:dbbf35b96557	1099	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto	99:dbbf35b96557	1100	* @{
Kojto	99:dbbf35b96557	1101	*/
Kojto	99:dbbf35b96557	1102	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
Kojto	99:dbbf35b96557	1103	((BANK) == FMC_NORSRAM_BANK2) \|\| \
Kojto	99:dbbf35b96557	1104	((BANK) == FMC_NORSRAM_BANK3) \|\| \
Kojto	99:dbbf35b96557	1105	((BANK) == FMC_NORSRAM_BANK4))
Kojto	99:dbbf35b96557	1106
Kojto	99:dbbf35b96557	1107	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1108	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
Kojto	99:dbbf35b96557	1109
Kojto	99:dbbf35b96557	1110	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
Kojto	99:dbbf35b96557	1111	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
Kojto	99:dbbf35b96557	1112	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
Kojto	99:dbbf35b96557	1113
Kojto	99:dbbf35b96557	1114	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	99:dbbf35b96557	1115	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	99:dbbf35b96557	1116	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto	99:dbbf35b96557	1117
Kojto	99:dbbf35b96557	1118	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
Kojto	99:dbbf35b96557	1119	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
Kojto	99:dbbf35b96557	1120	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
Kojto	99:dbbf35b96557	1121	((__MODE__) == FMC_ACCESS_MODE_D))
Kojto	99:dbbf35b96557	1122
Kojto	99:dbbf35b96557	1123	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
Kojto	99:dbbf35b96557	1124	((BANK) == FMC_NAND_BANK3))
Kojto	99:dbbf35b96557	1125
Kojto	99:dbbf35b96557	1126	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1127	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto	99:dbbf35b96557	1128
Kojto	99:dbbf35b96557	1129	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
Kojto	99:dbbf35b96557	1130	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto	99:dbbf35b96557	1131
Kojto	99:dbbf35b96557	1132	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1133	((STATE) == FMC_NAND_ECC_ENABLE))
Kojto	99:dbbf35b96557	1134
Kojto	99:dbbf35b96557	1135	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
Kojto	99:dbbf35b96557	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
Kojto	99:dbbf35b96557	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
Kojto	99:dbbf35b96557	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
Kojto	99:dbbf35b96557	1139	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
Kojto	99:dbbf35b96557	1140	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto	99:dbbf35b96557	1141
Kojto	99:dbbf35b96557	1142	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1143
Kojto	99:dbbf35b96557	1144	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1145
Kojto	99:dbbf35b96557	1146	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1147
Kojto	99:dbbf35b96557	1148	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1149
Kojto	99:dbbf35b96557	1150	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1151
Kojto	99:dbbf35b96557	1152	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1153
Kojto	99:dbbf35b96557	1154	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
Kojto	99:dbbf35b96557	1155
Kojto	99:dbbf35b96557	1156	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
Kojto	99:dbbf35b96557	1157
Kojto	99:dbbf35b96557	1158	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
Kojto	99:dbbf35b96557	1159
Kojto	99:dbbf35b96557	1160	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
Kojto	99:dbbf35b96557	1161
Kojto	99:dbbf35b96557	1162	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1163	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
Kojto	99:dbbf35b96557	1164
Kojto	99:dbbf35b96557	1165	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
Kojto	99:dbbf35b96557	1166	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto	99:dbbf35b96557	1167
Kojto	110:165afa46840b	1168	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	1169	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
Kojto	110:165afa46840b	1170	((__MODE__) == FMC_WRAP_MODE_ENABLE))
Kojto	110:165afa46840b	1171	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	1172
Kojto	99:dbbf35b96557	1173	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
Kojto	99:dbbf35b96557	1174	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
Kojto	99:dbbf35b96557	1175
Kojto	99:dbbf35b96557	1176	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1177	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
Kojto	99:dbbf35b96557	1178
Kojto	99:dbbf35b96557	1179	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1180	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
Kojto	99:dbbf35b96557	1181
Kojto	99:dbbf35b96557	1182	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1183	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
Kojto	99:dbbf35b96557	1184
Kojto	99:dbbf35b96557	1185	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1186	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto	99:dbbf35b96557	1187
Kojto	99:dbbf35b96557	1188	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1189	((__BURST__) == FMC_WRITE_BURST_ENABLE))
Kojto	99:dbbf35b96557	1190
Kojto	99:dbbf35b96557	1191	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
Kojto	99:dbbf35b96557	1192	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto	99:dbbf35b96557	1193
Kojto	99:dbbf35b96557	1194	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
Kojto	99:dbbf35b96557	1195
Kojto	99:dbbf35b96557	1196	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
Kojto	99:dbbf35b96557	1197
Kojto	99:dbbf35b96557	1198	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
Kojto	99:dbbf35b96557	1199
Kojto	99:dbbf35b96557	1200	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
Kojto	99:dbbf35b96557	1201
Kojto	99:dbbf35b96557	1202	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
Kojto	99:dbbf35b96557	1203
Kojto	99:dbbf35b96557	1204	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
Kojto	99:dbbf35b96557	1205
Kojto	99:dbbf35b96557	1206	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
Kojto	99:dbbf35b96557	1207	((BANK) == FMC_SDRAM_BANK2))
Kojto	99:dbbf35b96557	1208
Kojto	99:dbbf35b96557	1209	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
Kojto	99:dbbf35b96557	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
Kojto	99:dbbf35b96557	1211	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
Kojto	99:dbbf35b96557	1212	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
Kojto	99:dbbf35b96557	1213
Kojto	99:dbbf35b96557	1214	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
Kojto	99:dbbf35b96557	1215	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
Kojto	99:dbbf35b96557	1216	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
Kojto	99:dbbf35b96557	1217
Kojto	99:dbbf35b96557	1218	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	99:dbbf35b96557	1219	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	99:dbbf35b96557	1220	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
Kojto	99:dbbf35b96557	1221
Kojto	99:dbbf35b96557	1222	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
Kojto	99:dbbf35b96557	1223	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
Kojto	99:dbbf35b96557	1224
Kojto	99:dbbf35b96557	1225
Kojto	99:dbbf35b96557	1226	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
Kojto	99:dbbf35b96557	1227	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
Kojto	99:dbbf35b96557	1228	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
Kojto	99:dbbf35b96557	1229
Kojto	99:dbbf35b96557	1230	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1231	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
Kojto	99:dbbf35b96557	1232	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
Kojto	99:dbbf35b96557	1233
Kojto	99:dbbf35b96557	1234	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1235	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
Kojto	99:dbbf35b96557	1236
Kojto	99:dbbf35b96557	1237
Kojto	99:dbbf35b96557	1238	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
Kojto	99:dbbf35b96557	1239	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
Kojto	99:dbbf35b96557	1240	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
Kojto	99:dbbf35b96557	1241
Kojto	99:dbbf35b96557	1242	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	99:dbbf35b96557	1243
Kojto	99:dbbf35b96557	1244	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	99:dbbf35b96557	1245
Kojto	99:dbbf35b96557	1246	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto	99:dbbf35b96557	1247
Kojto	99:dbbf35b96557	1248	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	99:dbbf35b96557	1249
Kojto	99:dbbf35b96557	1250	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto	99:dbbf35b96557	1251
Kojto	99:dbbf35b96557	1252	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	99:dbbf35b96557	1253
Kojto	99:dbbf35b96557	1254	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	99:dbbf35b96557	1255
Kojto	99:dbbf35b96557	1256	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
Kojto	99:dbbf35b96557	1257	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
Kojto	99:dbbf35b96557	1258	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
Kojto	99:dbbf35b96557	1259	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
Kojto	99:dbbf35b96557	1260	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
Kojto	99:dbbf35b96557	1261	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
Kojto	99:dbbf35b96557	1262	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
Kojto	99:dbbf35b96557	1263
Kojto	99:dbbf35b96557	1264	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
Kojto	99:dbbf35b96557	1265	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
Kojto	99:dbbf35b96557	1266	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
Kojto	99:dbbf35b96557	1267
Kojto	99:dbbf35b96557	1268	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
Kojto	99:dbbf35b96557	1269
Kojto	99:dbbf35b96557	1270	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
Kojto	99:dbbf35b96557	1271
Kojto	99:dbbf35b96557	1272	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
Kojto	99:dbbf35b96557	1273
Kojto	99:dbbf35b96557	1274	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
Kojto	99:dbbf35b96557	1275
Kojto	99:dbbf35b96557	1276	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1277	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
Kojto	99:dbbf35b96557	1278
Kojto	110:165afa46840b	1279	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1280	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
Kojto	99:dbbf35b96557	1281	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
Kojto	99:dbbf35b96557	1282	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
Kojto	99:dbbf35b96557	1283	((SIZE) == FMC_PAGE_SIZE_1024))
Kojto	99:dbbf35b96557	1284
Kojto	99:dbbf35b96557	1285	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1286	((FIFO) == FMC_WRITE_FIFO_ENABLE))
Kojto	110:165afa46840b	1287	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	1288
Kojto	99:dbbf35b96557	1289	/**
Kojto	99:dbbf35b96557	1290	* @}
Kojto	99:dbbf35b96557	1291	*/
Kojto	99:dbbf35b96557	1292
Kojto	99:dbbf35b96557	1293	/**
Kojto	99:dbbf35b96557	1294	* @}
bogdanm	92:4fc01daae5a5	1295	*/
bogdanm	92:4fc01daae5a5	1296
Kojto	99:dbbf35b96557	1297	/* Private functions ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	1298	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
Kojto	99:dbbf35b96557	1299	* @{
Kojto	99:dbbf35b96557	1300	*/
bogdanm	92:4fc01daae5a5	1301
Kojto	99:dbbf35b96557	1302	/** @defgroup FMC_LL_NORSRAM NOR SRAM
Kojto	99:dbbf35b96557	1303	* @{
Kojto	99:dbbf35b96557	1304	*/
Kojto	99:dbbf35b96557	1305	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1306	* @{
Kojto	99:dbbf35b96557	1307	*/
bogdanm	92:4fc01daae5a5	1308	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
bogdanm	92:4fc01daae5a5	1309	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1310	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
bogdanm	92:4fc01daae5a5	1311	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
Kojto	99:dbbf35b96557	1312	/**
Kojto	99:dbbf35b96557	1313	* @}
Kojto	99:dbbf35b96557	1314	*/
bogdanm	92:4fc01daae5a5	1315
Kojto	99:dbbf35b96557	1316	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto	99:dbbf35b96557	1317	* @{
Kojto	99:dbbf35b96557	1318	*/
bogdanm	92:4fc01daae5a5	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1320	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	99:dbbf35b96557	1321	/**
Kojto	99:dbbf35b96557	1322	* @}
Kojto	99:dbbf35b96557	1323	*/
Kojto	99:dbbf35b96557	1324	/**
Kojto	99:dbbf35b96557	1325	* @}
Kojto	99:dbbf35b96557	1326	*/
bogdanm	92:4fc01daae5a5	1327
Kojto	99:dbbf35b96557	1328	/** @defgroup FMC_LL_NAND NAND
Kojto	99:dbbf35b96557	1329	* @{
Kojto	99:dbbf35b96557	1330	*/
Kojto	99:dbbf35b96557	1331	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1332	* @{
Kojto	99:dbbf35b96557	1333	*/
bogdanm	92:4fc01daae5a5	1334	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
bogdanm	92:4fc01daae5a5	1335	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1336	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1337	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	99:dbbf35b96557	1338	/**
Kojto	99:dbbf35b96557	1339	* @}
Kojto	99:dbbf35b96557	1340	*/
bogdanm	92:4fc01daae5a5	1341
Kojto	99:dbbf35b96557	1342	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto	99:dbbf35b96557	1343	* @{
Kojto	99:dbbf35b96557	1344	*/
bogdanm	92:4fc01daae5a5	1345	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1346	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1347	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
bogdanm	92:4fc01daae5a5	1348
Kojto	99:dbbf35b96557	1349	/**
Kojto	99:dbbf35b96557	1350	* @}
Kojto	99:dbbf35b96557	1351	*/
Kojto	99:dbbf35b96557	1352	/**
Kojto	99:dbbf35b96557	1353	* @}
Kojto	99:dbbf35b96557	1354	*/
Kojto	99:dbbf35b96557	1355	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	1356	/** @defgroup FMC_LL_PCCARD PCCARD
Kojto	99:dbbf35b96557	1357	* @{
Kojto	99:dbbf35b96557	1358	*/
Kojto	99:dbbf35b96557	1359	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1360	* @{
Kojto	99:dbbf35b96557	1361	*/
bogdanm	92:4fc01daae5a5	1362	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
bogdanm	92:4fc01daae5a5	1363	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	92:4fc01daae5a5	1364	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	92:4fc01daae5a5	1365	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	92:4fc01daae5a5	1366	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
Kojto	99:dbbf35b96557	1367	/**
Kojto	99:dbbf35b96557	1368	* @}
Kojto	99:dbbf35b96557	1369	*/
Kojto	99:dbbf35b96557	1370	/**
Kojto	99:dbbf35b96557	1371	* @}
Kojto	99:dbbf35b96557	1372	*/
Kojto	99:dbbf35b96557	1373	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	1374
Kojto	99:dbbf35b96557	1375	/** @defgroup FMC_LL_SDRAM SDRAM
Kojto	99:dbbf35b96557	1376	* @{
Kojto	99:dbbf35b96557	1377	*/
Kojto	99:dbbf35b96557	1378	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1379	* @{
Kojto	99:dbbf35b96557	1380	*/
bogdanm	92:4fc01daae5a5	1381	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
bogdanm	92:4fc01daae5a5	1382	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1383	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	99:dbbf35b96557	1384	/**
Kojto	99:dbbf35b96557	1385	* @}
Kojto	99:dbbf35b96557	1386	*/
bogdanm	92:4fc01daae5a5	1387
Kojto	99:dbbf35b96557	1388	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
Kojto	99:dbbf35b96557	1389	* @{
Kojto	99:dbbf35b96557	1390	*/
bogdanm	92:4fc01daae5a5	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1392	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1393	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
bogdanm	92:4fc01daae5a5	1394	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
bogdanm	92:4fc01daae5a5	1395	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
bogdanm	92:4fc01daae5a5	1396	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1397	/**
bogdanm	92:4fc01daae5a5	1398	* @}
Kojto	99:dbbf35b96557	1399	*/
Kojto	99:dbbf35b96557	1400	/**
Kojto	99:dbbf35b96557	1401	* @}
Kojto	99:dbbf35b96557	1402	*/
bogdanm	92:4fc01daae5a5	1403
bogdanm	92:4fc01daae5a5	1404	/**
bogdanm	92:4fc01daae5a5	1405	* @}
bogdanm	92:4fc01daae5a5	1406	*/
Kojto	99:dbbf35b96557	1407
Kojto	110:165afa46840b	1408	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	1409	/**
Kojto	99:dbbf35b96557	1410	* @}
Kojto	99:dbbf35b96557	1411	*/
Kojto	99:dbbf35b96557	1412
Kojto	99:dbbf35b96557	1413	/**
Kojto	99:dbbf35b96557	1414	* @}
Kojto	99:dbbf35b96557	1415	*/
bogdanm	92:4fc01daae5a5	1416	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	1417	}
bogdanm	92:4fc01daae5a5	1418	#endif
bogdanm	92:4fc01daae5a5	1419
bogdanm	92:4fc01daae5a5	1420	#endif /* __STM32F4xx_LL_FMC_H */
bogdanm	92:4fc01daae5a5	1421
bogdanm	92:4fc01daae5a5	1422	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Apr 2016
Imports:	0
Forks:	0
Commits:	119
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TARGET_MTS_MDOT_F405RG/stm32f4xx_ll_fmc.h@110:165afa46840b, 2015-11-25 (annotated)

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